From patchwork Wed Jun 14 08:23:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105467 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp180048qgd; Wed, 14 Jun 2017 01:24:24 -0700 (PDT) X-Received: by 10.99.99.134 with SMTP id x128mr3162688pgb.81.1497428664838; Wed, 14 Jun 2017 01:24:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497428664; cv=none; d=google.com; s=arc-20160816; b=vMWjwqD3Ylb24ainJjifkRvhUUlMwNjxOxVTmCcL9FWrfOolsn/iTLW6LYELwAGFLb hDKyxd7ou44iqcLhlnEq6tpR/fqu4pGeGxTChn6o0/ERKpvPFmfKcZF7iOJq6/y7MKyA 6xl5GSNHLAJsJsQmYcGHGpoEvbYYr4YHkj7mb2uYt/GdshpD106I/JWb80AhW3Bry3G1 eStm/GrQSu/hsjGyNdjWfS8kCypR6i83iOONG+cZ3L83mCRCkZSpEY5mgXrY6h8dKeNv tSL6Rawk4J4R+PCk/WHu0TmticSvaBpToiygtqZE756Ti8GxvY2Q5E5Qv/9bNRjmnXw+ 7wtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=xmMM2WJG38NPfhr/SWKW/L8WVq/lGxJnRa8pzOOVc78=; b=FKdJxhsErW7ywL3bikHHZOIR3mCJFWSrMcOKQ4u4Jw3kTdyf2E5VInJhJUMlhWHqB6 SxGYEZVAp3gjbiTQUejui1RTrwMUBfdSwJNodqKlJnNR5nwnjM8RbRDXW1ad2hY52Vge LLxUuukO3Aa5Ais72aAAZOoCyI304zNNzgXUA/9huwFyQabk7X4YgknOKyv6Wa4ssVQ8 4fxpvKfqEOsTI625GU9r9IKd1QAd62l04ut+tbXcxcpX4W/6PXLI3bf7T+02gOZHVwrT s9Ucn8jowY/enjo7RcmH/hwR1qASrWJSEL43vRwgIiIBg+2tNtgVBIYDvgfjW5tkCS7i exiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=J6vvHgRx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q12si165859pgr.237.2017.06.14.01.24.24; Wed, 14 Jun 2017 01:24:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=J6vvHgRx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754544AbdFNIYI (ORCPT + 25 others); Wed, 14 Jun 2017 04:24:08 -0400 Received: from mail-pf0-f171.google.com ([209.85.192.171]:35894 "EHLO mail-pf0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754268AbdFNIYE (ORCPT ); Wed, 14 Jun 2017 04:24:04 -0400 Received: by mail-pf0-f171.google.com with SMTP id x63so80790634pff.3 for ; Wed, 14 Jun 2017 01:23:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xmMM2WJG38NPfhr/SWKW/L8WVq/lGxJnRa8pzOOVc78=; b=J6vvHgRx3IlTpaI9fTV0qnxsF2PYD5J154sul8OPgmaff4jAbX9+w860Nik9PSWnxy QrDvSCp/oBIjiTWwc6TcD40PmBCBr2iLqGjYhte7vltP2BMqQVsN+LOeHtH6QjBl34va EIUQTLRlziG1+FbmCFvNqQOKpisKFZHlBMPQU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xmMM2WJG38NPfhr/SWKW/L8WVq/lGxJnRa8pzOOVc78=; b=duqY4tBWf6iM5lBGi71XmflBRO4Pksec5j2fWWTujn1LCtdRH/4eM21yUF7gUcW/9X 0pv5DoRQc1ozpHqDL/LyES1h+Tz+YndcfeRAERiP/FZRPJoZdHF9Pnj/SPtakWTELECF pCHpJTdEu5epcTF+JBM4wNzpECM/gwKu9h/VaHZ+tAAtBM2DaRiRT1QrkVcO5X6PdV0b vykgIVK3q9XAD787hojT0L6G8CipsOsJ40E4s2Pb0vVrApQ/2/EncbhJwl7gfqAI7rn1 kNm3WkMFkbg/ZRpSXTSlLqOxhNOUZHdmt0fmaACauGzP8sUHTXq3iY2nV2BSmmB7NsdM vOrw== X-Gm-Message-State: AKS2vOz1/JXpmybgIdEPAE6V1CF91dQUaTaanYo4VLL6a+g6yR9Jj5XA I+/B8/hnZ2PZ8vY4 X-Received: by 10.84.160.204 with SMTP id v12mr3614951plg.91.1497428638714; Wed, 14 Jun 2017 01:23:58 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.23.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:23:58 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Guodong Xu Subject: [PATCH v3 01/21] dt-bindings: arm: hisilicon: add bindings for HiKey960 board Date: Wed, 14 Jun 2017 16:23:18 +0800 Message-Id: <20170614082338.15673-2-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings for HiKey960 Board. Signed-off-by: Guodong Xu Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.10.2 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 2e73215..7111fbc8 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -4,6 +4,10 @@ Hi3660 SoC Required root node properties: - compatible = "hisilicon,hi3660"; +HiKey960 Board +Required root node properties: + - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; + Hi3798cv200 SoC Required root node properties: - compatible = "hisilicon,hi3798cv200"; From patchwork Wed Jun 14 08:23:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105490 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp207560qgd; Wed, 14 Jun 2017 02:55:08 -0700 (PDT) X-Received: by 10.99.169.26 with SMTP id u26mr3597982pge.177.1497434107919; Wed, 14 Jun 2017 02:55:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497434107; cv=none; d=google.com; s=arc-20160816; b=ndYoyaHFdh8uOLbSr9ZdfCwRuqVB41ambn7RsI+YRWd2HJ+i5QJp9YiT6rIcIAtcIt zIclHA55E4Cf85qQec4erUgWtLekbkYg8FTOTYFH/YMRD0gviByH5QRsAbOG/xNK+e1d g5zH2JV5PTfp+DhL+FR2seS5c9hPQNPYTBPwbpDZjpcl7CnaXSsxNmDxuGjcBLLSucym tcaW37tIn/bJyLT5P1wayjRpHIhIKqrHVGwZOK209LVyrZXFzvPRYrzjt5+nifDB/QWi uPtPk5r3yvei4zFZsNY55u7Jbkz92ccaRc+IbcNz9XjFC3KNwKwWa3GWzrExBD+bXsyV CSrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=k2rEOj59VAxOOTppfiW15cc433btNtSPCWjUihdJ1nk=; b=A7P11feBWo17M61u7AIAn5J2QjvCB+5eAaG2NBrw9ic1E2Qfju7G7teqlr3XGzPdCR O64dl92vhx6wEHWAorKEGKwLZA136MGV4X0uOpJ1DGadUbohofqjSFr7ncTXOdkBor+m Xy8qeI0ug9OHSEhyoMu8IRmydafNQw1PIxTD9boxpLIOtxoaa0QegK24ZGz+rQmHvosU YUzGXy88dNRQw0pX70oDzNdpekCHHZFVSkQWVN88moudp3XvzcaGqd0Jpy2+UsZlgXWJ Q8sC/YgeFdir+2RTHNvsxBWiobLgeViRdAHcKLhztZAzFQpEjpcjQvdqw+EBoV3y2DCi GMbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=kDxP0RPD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 62si328735plb.111.2017.06.14.02.55.07; Wed, 14 Jun 2017 02:55:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=kDxP0RPD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752389AbdFNJzF (ORCPT + 25 others); Wed, 14 Jun 2017 05:55:05 -0400 Received: from mail-pf0-f173.google.com ([209.85.192.173]:33101 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754547AbdFNIYM (ORCPT ); Wed, 14 Jun 2017 04:24:12 -0400 Received: by mail-pf0-f173.google.com with SMTP id 83so80771738pfr.0 for ; Wed, 14 Jun 2017 01:24:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k2rEOj59VAxOOTppfiW15cc433btNtSPCWjUihdJ1nk=; b=kDxP0RPDNnR7gJlhqm06X0OwkiMyVlYJXNnbg3lHnB/ZhjIS39nUqa2X01sqi/xZTi 1j8XcoLr+WFkisdF0fG+rEA2nGJRatL551snSRwLFa8Phz+gtybyeM+W9BNcAi1N0N3L L6wlAttAdyKZF4Ze6mD5EaRPpoo4jKOWq4q4I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k2rEOj59VAxOOTppfiW15cc433btNtSPCWjUihdJ1nk=; b=VLu4XI3cQDxOZBmwOkeMe6S/Xgqi4wNPzv5IAt3pjjIoNn9RLQLLlK8hNBkIuapEfP PwYWu3an6pLbgVez5W3GRJJe3wGOMPc7WkPJrCGpvC20sjd/Zg7nanQymdYdoJ3+C8uU i3amkfAJ6/12AkoGKghh50lNu3HjRW/zZD7GbNb60MwlCrzVZ2LNokqkszi0d4FTEuU7 FWGrab4gqZ2p6oN+IjoC9N6dYrmo4r9mzTuQvoXtsaeaGC7WiTGU9cf7JfpTl4MjQt1c z96c/lRtOHMVF2jIuEP4PgFi4TLNoXRcYWkVQwHlLlhCGIUdHi8VJtD90MmhD1ly48sS UMtQ== X-Gm-Message-State: AKS2vOwevadkr9qw07I1ej6yBcJM4IqW8E/eSO9OgRibxlysRrlvBbuq t08V9orcSKDZzQi6 X-Received: by 10.98.9.16 with SMTP id e16mr2987494pfd.57.1497428651677; Wed, 14 Jun 2017 01:24:11 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.24.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:24:11 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Wang Xiaoyin , Chen Jun , Guodong Xu Subject: [PATCH v3 03/21] arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig Date: Wed, 14 Jun 2017 16:23:20 +0800 Message-Id: <20170614082338.15673-4-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wang Xiaoyin This commit adds more pinmux and pinctrl information for devices on HiKey960, including i2c, spi, cam, uart, ufs, pcie, csi, pwr_key, isp, sd/sdio, i2s, and usb. Signed-off-by: Wang Xiaoyin Signed-off-by: Chen Jun Signed-off-by: Guodong Xu Acked-by: Rob Herring --- .../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 778 +++++++++++++++++++-- 1 file changed, 715 insertions(+), 63 deletions(-) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi index 719c4bc..7e542d2 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi @@ -24,6 +24,27 @@ &range 0 7 0 &range 8 116 0>; + pmu_pmx_func: pmu_pmx_func { + pinctrl-single,pins = < + 0x008 MUX_M1 /* PMU1_SSI */ + 0x00c MUX_M1 /* PMU2_SSI */ + 0x010 MUX_M1 /* PMU_CLKOUT */ + 0x100 MUX_M1 /* PMU_HKADC_SSI */ + >; + }; + + csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x044 MUX_M0 /* CSI0_PWD_N */ + >; + }; + + csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x04c MUX_M0 /* CSI1_PWD_N */ + >; + }; + isp0_pmx_func: isp0_pmx_func { pinctrl-single,pins = < 0x058 MUX_M1 /* ISP_CLK0 */ @@ -40,6 +61,12 @@ >; }; + pwr_key_pmx_func: pwr_key_pmx_func { + pinctrl-single,pins = < + 0x080 MUX_M0 /* GPIO_034 */ + >; + }; + i2c3_pmx_func: i2c3_pmx_func { pinctrl-single,pins = < 0x02c MUX_M1 /* I2C3_SCL */ @@ -67,21 +94,10 @@ >; }; - spi1_pmx_func: spi1_pmx_func { - pinctrl-single,pins = < - 0x034 MUX_M1 /* SPI1_CLK */ - 0x038 MUX_M1 /* SPI1_DI */ - 0x03c MUX_M1 /* SPI1_DO */ - 0x040 MUX_M1 /* SPI1_CS_N */ - >; - }; - uart0_pmx_func: uart0_pmx_func { pinctrl-single,pins = < 0x0cc MUX_M2 /* UART0_RXD */ 0x0d0 MUX_M2 /* UART0_TXD */ - 0x0d4 MUX_M2 /* UART0_RXD_M */ - 0x0d8 MUX_M2 /* UART0_TXD_M */ >; }; @@ -138,6 +154,18 @@ 0x0d8 MUX_M1 /* UART6_TXD */ >; }; + + cam0_rst_pmx_func: cam0_rst_pmx_func { + pinctrl-single,pins = < + 0x0c8 MUX_M0 /* CAM0_RST */ + >; + }; + + cam1_rst_pmx_func: cam1_rst_pmx_func { + pinctrl-single,pins = < + 0x124 MUX_M0 /* CAM1_RST */ + >; + }; }; /* [IOMG_MMC0_000, IOMG_MMC0_005] */ @@ -174,6 +202,13 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 12 0>; + ufs_pmx_func: ufs_pmx_func { + pinctrl-single,pins = < + 0x000 MUX_M1 /* UFS_REF_CLK */ + 0x004 MUX_M1 /* UFS_RST_N */ + >; + }; + spi3_pmx_func: spi3_pmx_func { pinctrl-single,pins = < 0x008 MUX_M1 /* SPI3_CLK */ @@ -248,17 +283,17 @@ >; }; - i2c2_pmx_func: i2c2_pmx_func { + i2c7_pmx_func: i2c7_pmx_func { pinctrl-single,pins = < - 0x024 MUX_M1 /* I2C2_SCL */ - 0x028 MUX_M1 /* I2C2_SDA */ + 0x024 MUX_M3 /* I2C7_SCL */ + 0x028 MUX_M3 /* I2C7_SDA */ >; }; - i2c7_pmx_func: i2c7_pmx_func { + pcie_pmx_func: pcie_pmx_func { pinctrl-single,pins = < - 0x024 MUX_M3 /* I2C7_SCL */ - 0x028 MUX_M3 /* I2C7_SDA */ + 0x084 MUX_M1 /* PCIE_CLKREQ_N */ + 0x088 MUX_M1 /* PCIE_WAKE_N */ >; }; @@ -271,15 +306,6 @@ >; }; - spi4_pmx_func: spi4_pmx_func { - pinctrl-single,pins = < - 0x08c MUX_M4 /* SPI4_CLK */ - 0x090 MUX_M4 /* SPI4_DI */ - 0x094 MUX_M4 /* SPI4_DO */ - 0x098 MUX_M4 /* SPI4_CS0_N */ - >; - }; - i2s0_pmx_func: i2s0_pmx_func { pinctrl-single,pins = < 0x034 MUX_M1 /* I2S0_DI */ @@ -290,17 +316,18 @@ }; }; - pmx5: pinmux@ff3fd800 { + pmx5: pinmux@e896c800 { compatible = "pinconf-single"; - reg = <0x0 0xff3fd800 0x0 0x18>; + reg = <0x0 0xe896c800 0x0 0x200>; #pinctrl-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-single,register-width = <32>; + pinctrl-single,register-width = <0x20>; - sdio_clk_cfg_func: sdio_clk_cfg_func { + pmu_cfg_func: pmu_cfg_func { pinctrl-single,pins = < - 0x000 0x0 /* SDIO_CLK */ + 0x010 0x0 /* PMU1_SSI */ + 0x014 0x0 /* PMU2_SSI */ + 0x018 0x0 /* PMU_CLKOUT */ + 0x10c 0x0 /* PMU_HKADC_SSI */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -315,18 +342,35 @@ PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK + DRIVE7_06MA DRIVE6_MASK >; }; - sdio_cfg_func: sdio_cfg_func { + i2c3_cfg_func: i2c3_cfg_func { pinctrl-single,pins = < - 0x004 0x0 /* SDIO_CMD */ - 0x008 0x0 /* SDIO_DATA0 */ - 0x00c 0x0 /* SDIO_DATA1 */ - 0x010 0x0 /* SDIO_DATA2 */ - 0x014 0x0 /* SDIO_DATA3 */ + 0x038 0x0 /* I2C3_SCL */ + 0x03c 0x0 /* I2C3_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x050 0x0 /* CSI0_PWD_N */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -335,29 +379,64 @@ PULL_DOWN >; pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x058 0x0 /* CSI1_PWD_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK + DRIVE7_04MA DRIVE6_MASK >; }; - }; - pmx6: pinmux@ff37e800 { - compatible = "pinconf-single"; - reg = <0x0 0xff37e800 0x0 0x18>; - #pinctrl-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-single,register-width = <32>; + isp0_cfg_func: isp0_cfg_func { + pinctrl-single,pins = < + 0x064 0x0 /* ISP_CLK0 */ + 0x070 0x0 /* ISP_SCL0 */ + 0x074 0x0 /* ISP_SDA0 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK>; + }; - sd_clk_cfg_func: sd_clk_cfg_func { + isp1_cfg_func: isp1_cfg_func { pinctrl-single,pins = < - 0x000 0x0 /* SD_CLK */ + 0x068 0x0 /* ISP_CLK1 */ + 0x078 0x0 /* ISP_SCL1 */ + 0x07c 0x0 /* ISP_SDA1 */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -372,18 +451,37 @@ PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK + DRIVE7_04MA DRIVE6_MASK >; }; - sd_cfg_func: sd_cfg_func { + pwr_key_cfg_func: pwr_key_cfg_func { pinctrl-single,pins = < - 0x004 0x0 /* SD_CMD */ - 0x008 0x0 /* SD_DATA0 */ - 0x00c 0x0 /* SD_DATA1 */ - 0x010 0x0 /* SD_DATA2 */ - 0x014 0x0 /* SD_DATA3 */ + 0x08c 0x0 /* GPIO_034 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart1_cfg_func: uart1_cfg_func { + pinctrl-single,pins = < + 0x0b4 0x0 /* UART1_RXD */ + 0x0b8 0x0 /* UART1_TXD */ + 0x0bc 0x0 /* UART1_CTS_N */ + 0x0c0 0x0 /* UART1_RTS_N */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -392,14 +490,568 @@ PULL_DOWN >; pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart2_cfg_func: uart2_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* UART2_CTS_N */ + 0x0cc 0x0 /* UART2_RTS_N */ + 0x0d0 0x0 /* UART2_TXD */ + 0x0d4 0x0 /* UART2_RXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart5_cfg_func: uart5_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* UART5_RXD */ + 0x0cc 0x0 /* UART5_TXD */ + 0x0d0 0x0 /* UART5_CTS_N */ + 0x0d4 0x0 /* UART5_RTS_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + cam0_rst_cfg_func: cam0_rst_cfg_func { + pinctrl-single,pins = < + 0x0d4 0x0 /* CAM0_RST */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart0_cfg_func: uart0_cfg_func { + pinctrl-single,pins = < + 0x0d8 0x0 /* UART0_RXD */ + 0x0dc 0x0 /* UART0_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart6_cfg_func: uart6_cfg_func { + pinctrl-single,pins = < + 0x0d8 0x0 /* UART6_CTS_N */ + 0x0dc 0x0 /* UART6_RTS_N */ + 0x0e0 0x0 /* UART6_RXD */ + 0x0e4 0x0 /* UART6_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x0e8 0x0 /* UART3_CTS_N */ + 0x0ec 0x0 /* UART3_RTS_N */ + 0x0f0 0x0 /* UART3_RXD */ + 0x0f4 0x0 /* UART3_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x0f8 0x0 /* UART4_CTS_N */ + 0x0fc 0x0 /* UART4_RTS_N */ + 0x100 0x0 /* UART4_RXD */ + 0x104 0x0 /* UART4_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + cam1_rst_cfg_func: cam1_rst_cfg_func { + pinctrl-single,pins = < + 0x130 0x0 /* CAM1_RST */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + }; + + pmx6: pinmux@ff3b6800 { + compatible = "pinconf-single"; + reg = <0x0 0xff3b6800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + ufs_cfg_func: ufs_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* UFS_REF_CLK */ + 0x004 0x0 /* UFS_RST_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_08MA DRIVE6_MASK + >; + }; + + spi3_cfg_func: spi3_cfg_func { + pinctrl-single,pins = < + 0x008 0x0 /* SPI3_CLK */ + 0x0 /* SPI3_DI */ + 0x010 0x0 /* SPI3_DO */ + 0x014 0x0 /* SPI3_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + }; + + pmx7: pinmux@ff3fd800 { + compatible = "pinconf-single"; + reg = <0x0 0xff3fd800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + sdio_clk_cfg_func: sdio_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SDIO_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA DRIVE6_MASK + >; + }; + + sdio_cfg_func: sdio_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SDIO_CMD */ + 0x008 0x0 /* SDIO_DATA0 */ + 0x00c 0x0 /* SDIO_DATA1 */ + 0x010 0x0 /* SDIO_DATA2 */ + 0x014 0x0 /* SDIO_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA DRIVE6_MASK + >; + }; + }; + + pmx8: pinmux@ff37e800 { + compatible = "pinconf-single"; + reg = <0x0 0xff37e800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + sd_clk_cfg_func: sd_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SD_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA + DRIVE6_MASK + >; + }; + + sd_cfg_func: sd_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SD_CMD */ + 0x008 0x0 /* SD_DATA0 */ + 0x00c 0x0 /* SD_DATA1 */ + 0x010 0x0 /* SD_DATA2 */ + 0x014 0x0 /* SD_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA + DRIVE6_MASK + >; + }; + }; + + pmx9: pinmux@fff11800 { + compatible = "pinconf-single"; + reg = <0x0 0xfff11800 0x0 0xbc>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0x01c 0x0 /* I2C0_SCL */ + 0x020 0x0 /* I2C0_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0x024 0x0 /* I2C1_SCL */ + 0x028 0x0 /* I2C1_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2c7_cfg_func: i2c7_cfg_func { + pinctrl-single,pins = < + 0x02c 0x0 /* I2C7_SCL */ + 0x030 0x0 /* I2C7_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + slimbus_cfg_func: slimbus_cfg_func { + pinctrl-single,pins = < + 0x034 0x0 /* SLIMBUS_CLK */ + 0x038 0x0 /* SLIMBUS_DATA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2s0_cfg_func: i2s0_cfg_func { + pinctrl-single,pins = < + 0x040 0x0 /* I2S0_DI */ + 0x044 0x0 /* I2S0_DO */ + 0x048 0x0 /* I2S0_XCLK */ + 0x04c 0x0 /* I2S0_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2s2_cfg_func: i2s2_cfg_func { + pinctrl-single,pins = < + 0x050 0x0 /* I2S2_DI */ + 0x054 0x0 /* I2S2_DO */ + 0x058 0x0 /* I2S2_XCLK */ + 0x05c 0x0 /* I2S2_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + pcie_cfg_func: pcie_cfg_func { + pinctrl-single,pins = < + 0x094 0x0 /* PCIE_CLKREQ_N */ + 0x098 0x0 /* PCIE_WAKE_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + spi2_cfg_func: spi2_cfg_func { + pinctrl-single,pins = < + 0x09c 0x0 /* SPI2_CLK */ + 0x0a0 0x0 /* SPI2_DI */ + 0x0a4 0x0 /* SPI2_DO */ + 0x0a8 0x0 /* SPI2_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + usb_cfg_func: usb_cfg_func { + pinctrl-single,pins = < + 0x0ac 0x0 /* GPIO_219 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK >; }; }; From patchwork Wed Jun 14 08:23:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105469 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp180213qgd; Wed, 14 Jun 2017 01:25:01 -0700 (PDT) X-Received: by 10.99.104.136 with SMTP id d130mr3206678pgc.236.1497428701581; Wed, 14 Jun 2017 01:25:01 -0700 (PDT) ARC-Seal: i=1; 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Wed, 14 Jun 2017 01:24:17 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.24.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:24:17 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 04/21] arm64: dts: hi3660: add resources for clock and reset Date: Wed, 14 Jun 2017 16:23:21 +0800 Message-Id: <20170614082338.15673-5-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhangfei Gao Add some resource nodes for clock and reset Signed-off-by: Zhangfei Gao Acked-by: Rob Herring --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 53 +++++++++++++++++++++++++++---- 1 file changed, 46 insertions(+), 7 deletions(-) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3983086..f55710a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -5,6 +5,7 @@ */ #include +#include / { compatible = "hisilicon,hi3660"; @@ -141,18 +142,56 @@ #size-cells = <2>; ranges; - fixed_uart5: fixed_19_2M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "fixed:uart5"; + crg_ctrl: crg_ctrl@fff35000 { + compatible = "hisilicon,hi3660-crgctrl", "syscon"; + reg = <0x0 0xfff35000 0x0 0x1000>; + #clock-cells = <1>; }; - uart5: uart@fdf05000 { + crg_rst: crg_rst_controller { + compatible = "hisilicon,hi3660-reset"; + #reset-cells = <2>; + hisi,rst-syscon = <&crg_ctrl>; + }; + + + pctrl: pctrl@e8a09000 { + compatible = "hisilicon,hi3660-pctrl", "syscon"; + reg = <0x0 0xe8a09000 0x0 0x2000>; + #clock-cells = <1>; + }; + + pmuctrl: crg_ctrl@fff34000 { + compatible = "hisilicon,hi3660-pmuctrl", "syscon"; + reg = <0x0 0xfff34000 0x0 0x1000>; + #clock-cells = <1>; + }; + + sctrl: sctrl@fff0a000 { + compatible = "hisilicon,hi3660-sctrl", "syscon"; + reg = <0x0 0xfff0a000 0x0 0x1000>; + #clock-cells = <1>; + }; + + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3660-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + #clock-cells = <1>; + + }; + + iomcu_rst: reset { + compatible = "hisilicon,hi3660-reset"; + hisi,rst-syscon = <&iomcu>; + #reset-cells = <2>; + }; + + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; interrupts = ; - clocks = <&fixed_uart5 &fixed_uart5>; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, + <&crg_ctrl HI3660_CLK_GATE_UART5>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; From patchwork Wed Jun 14 08:23:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105489 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp207552qgd; Wed, 14 Jun 2017 02:55:06 -0700 (PDT) X-Received: by 10.98.111.194 with SMTP id k185mr3232071pfc.13.1497434106719; Wed, 14 Jun 2017 02:55:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497434106; cv=none; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id 62si328735plb.111.2017.06.14.02.55.06; Wed, 14 Jun 2017 02:55:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=XfozYQ7y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752346AbdFNJyo (ORCPT + 25 others); Wed, 14 Jun 2017 05:54:44 -0400 Received: from mail-pf0-f179.google.com ([209.85.192.179]:34284 "EHLO mail-pf0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754569AbdFNIYY (ORCPT ); Wed, 14 Jun 2017 04:24:24 -0400 Received: by mail-pf0-f179.google.com with SMTP id s66so12692700pfs.1 for ; Wed, 14 Jun 2017 01:24:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jXFtgFIjDk5tb4iZZTJ1ZCyrIT65KjYJF6ztgq0q2pk=; b=XfozYQ7yeP4NrYRIY0pwKYvq4KPXF7Kng8xObqOhSMHWT4WgmmKFrCFmts57R4REor EtrcmwgNd098zbHUCXwAY2Te61EmqO6OPpjmEQRHJ1wFx/a36cyxSgjKOYz2vsPBTrib d7VhBnGLGCxPw+ioYn60TntiCWEQ2GghJW5ss= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jXFtgFIjDk5tb4iZZTJ1ZCyrIT65KjYJF6ztgq0q2pk=; b=nJkrYHl6mj+Km5giWab5nMPAKEJXny37I0lCPihhcWBeR1X1/Knyay3Fy53lRNS3Zy cLxl8C9VuMqCOyqeTh7kEyjY4LV5DZkqOkOQO3eEufiWojfiP2+VFaWD+Y8UU87XDopI h2BUzzCq62V4iPxTQXxCG0F3sG8BX3VTBxcKJ4LLN/lk9bGWeWSMfrmIq1Hy/xWIXTav ApCdn5XXtYY3Rs2sbScvNzjOr81rN1grbvZk3vrvbqSIVPPJ0CguSjl3vwz/BkX6baY8 Tqa7tGe8FPX8dPhQ1XinWkcMlTSFt9N5/ep+yuZrIWmoV8nrivatBf1FgmaoJ8y44RCf fZ5Q== X-Gm-Message-State: AKS2vOwy4XHg5dDCxbOIbr+pBRHGUz24GDN+KCfTnxakB2iD1KLzc9rj dH9DbHRuHPSRFYPb X-Received: by 10.99.107.136 with SMTP id g130mr3307761pgc.3.1497428663873; Wed, 14 Jun 2017 01:24:23 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.24.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:24:23 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Jarkko Nikula , Guodong Xu Subject: [PATCH v3 05/21] arm64: dts: Add I2C nodes for Hi3660 Date: Wed, 14 Jun 2017 16:23:22 +0800 Message-Id: <20170614082338.15673-6-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhangfei Gao Add I2C nodes for Hi3660-hikey960. On HiKey960, I2C0, I2C7 are connected to Low Speed Expansion Connector. I2C1 is connected to ADV7535. I2C3 is connected to USB5734. Cc: Jarkko Nikula Signed-off-by: Zhangfei Gao Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 22 +++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 56 +++++++++++++++++++++++ 2 files changed, 78 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 64875a5..1a4d6c5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -29,6 +29,28 @@ }; }; +&i2c0 { + /* On Low speed expansion */ + label = "LS-I2C0"; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + adv7533: adv7533@39 { + status = "ok"; + compatible = "adi,adv7533"; + reg = <0x39>; + }; +}; + +&i2c7 { + /* On Low speed expansion */ + label = "LS-I2C1"; + status = "okay"; +}; + &uart5 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index f55710a..9abe84e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -186,6 +186,62 @@ #reset-cells = <2>; }; + i2c0: i2c@ffd71000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd71000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; + resets = <&iomcu_rst 0x20 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@ffd72000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd72000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; + resets = <&iomcu_rst 0x20 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c3: i2c@fdf0c000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0c000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; + resets = <&crg_rst 0x78 7>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; + status = "disabled"; + }; + + i2c7: i2c@fdf0b000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0b000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; + resets = <&crg_rst 0x60 14>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; + status = "disabled"; + }; + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; From patchwork Wed Jun 14 08:23:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105470 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp180225qgd; Wed, 14 Jun 2017 01:25:02 -0700 (PDT) X-Received: by 10.84.192.3 with SMTP id b3mr3826000pld.76.1497428702754; Wed, 14 Jun 2017 01:25:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497428702; cv=none; d=google.com; s=arc-20160816; b=UUDPF1MhlCKFJaUitAtSWtMfXPJs+LRNxHlC9akXj4mT6/a5q6iEFr4Yz6z0xKPHQA JgTf648Jc3LMVOrkItzW/6MmG8ZqtDtwLu1huLfpR46vhZQ7bS0UPoj4DVvUV/6blolC hd2tO564oTLe9VYfGAKGnrbHuoXNUACazeE3pmjwWLzVY8m2+ntWTytRDnb2TU++tiHd ScjSWD7S8wGccBzdNRvZU9TsMO5Uvdi3GpKQQ/kT0zhoWUnVWHx5bq7ET7kraVBb3VM4 pyL4NLPatIPWANlHcyp5/ZyoMU2QiPnyksfkUqXgwqwhrv1dDXRtBaN06KYr4gK8cznr XhFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=SKle1N3Cdi0bgyCL3EILNiJD5thnQRze5cZRg4jGxMc=; b=L++CxF7QyurLDy0G/b8qweKv8EsPnTjtNxpjdEjvDUvseEieWHiQ7v1O6xI720qa/T 8v0MrTEoYxfK9D8gQ+c5iXh5gJBi5OJWoGU1Fm8wDZeJpMRpogMb6lZOTkbMEbi7OcQD QFHHMeddzUTj4I7uhwt1cAZiYbPDLY1f8lz7c8YR3i0WF1ZDk4tgK+/8G/79EUdFE35c Jp+BlqmVboYTqw87O9bVmrlxPNmJNMwIlnKySOdAJlKZtEVKvAsry2HIsoI7QE9L4PG+ p2oqZxIlPNWUbosrfZjzzi6+3XbMeGKbiMWTCWxXKmGvRUFaOFMQHKLtXM4/eqZAS8NJ tQtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=bO75yvmU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b74si170544pfc.93.2017.06.14.01.25.02; Wed, 14 Jun 2017 01:25:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=bO75yvmU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754613AbdFNIYj (ORCPT + 25 others); Wed, 14 Jun 2017 04:24:39 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:34313 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754343AbdFNIYf (ORCPT ); Wed, 14 Jun 2017 04:24:35 -0400 Received: by mail-pf0-f182.google.com with SMTP id s66so12694019pfs.1 for ; Wed, 14 Jun 2017 01:24:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SKle1N3Cdi0bgyCL3EILNiJD5thnQRze5cZRg4jGxMc=; b=bO75yvmU72eI+eh5V4F2lnnXmsrmKAMO/iWGQgmK2LCsK9qNDZmOkjA2DPDElwc5zB 1ihc20v0InVWwonqT9pc2n7BLVPLUqmXiyftzI4ZZQq/VmfQSRIMwZhKX1fsSblZs5yL W06D950osbO2D70yWlSoNhgdsztfkK8jZ+CTk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SKle1N3Cdi0bgyCL3EILNiJD5thnQRze5cZRg4jGxMc=; b=Nnmo29Yco+8uBh1gChqPg2Eg9BKe0ftLMpX6mn4Iye2n7ErXuFiwPnfUWMWck/S7Iu 7K5QCzeZ2k8wGyoiinE4sSZIDoTreR3OEZFgXw2/SYtHNBQfoDc6YACiFdz+ewsQHbSn 53BXJOAjQCAqKCB/aPSGiT4uvCciqyje4d5aZX9qgoXQKnfD8hiki7MSpI/Z9wt7JS4C WiZq8NWJeKHux76sncdCq6qdUYNOnNtmidkIK3qudcsnEzTziTnHQf+5SlxhWU4kKEcs ip1l/qlhjbk/hU/yKxVH4pY/eqtfxLevXG0ZKDBRf8ZcBru1dgibvCRLx+kTm527NFP+ r8NA== X-Gm-Message-State: AKS2vOziRu2/r+umcV52KvK5ijpJwlod62iLio8F5nC/MrolTjeFgkYl +sOQsf7LKLRMqQYx X-Received: by 10.99.109.141 with SMTP id i135mr3310478pgc.103.1497428669990; Wed, 14 Jun 2017 01:24:29 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.24.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:24:29 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Wang Xiaoyin Subject: [PATCH v3 06/21] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC Date: Wed, 14 Jun 2017 16:23:23 +0800 Message-Id: <20170614082338.15673-7-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wang Xiaoyin This patch adds pl061 device nodes for Hi3660 SoC. Signed-off-by: Wang Xiaoyin --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 380 ++++++++++++++++++++++++++++++ 1 file changed, 380 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 9abe84e..b03be4d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -251,5 +251,385 @@ clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; + + gpio0: gpio@e8a0b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0b000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 1 0 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@e8a0c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0c000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 1 7 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@e8a0d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0d000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 14 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; + clock-names = "apb_pclk"; + }; + + gpio3: gpio@e8a0e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0e000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 22 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; + clock-names = "apb_pclk"; + }; + + gpio4: gpio@e8a0f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0f000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 30 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; + clock-names = "apb_pclk"; + }; + + gpio5: gpio@e8a10000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a10000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 38 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; + clock-names = "apb_pclk"; + }; + + gpio6: gpio@e8a11000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a11000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 46 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; + clock-names = "apb_pclk"; + }; + + gpio7: gpio@e8a12000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a12000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 54 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; + clock-names = "apb_pclk"; + }; + + gpio8: gpio@e8a13000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a13000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 62 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; + clock-names = "apb_pclk"; + }; + + gpio9: gpio@e8a14000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a14000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 70 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; + clock-names = "apb_pclk"; + }; + + gpio10: gpio@e8a15000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a15000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 78 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; + clock-names = "apb_pclk"; + }; + + gpio11: gpio@e8a16000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a16000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 86 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; + clock-names = "apb_pclk"; + }; + + gpio12: gpio@e8a17000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a17000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; + clock-names = "apb_pclk"; + }; + + gpio13: gpio@e8a18000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a18000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 102 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; + clock-names = "apb_pclk"; + }; + + gpio14: gpio@e8a19000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a19000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 110 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; + clock-names = "apb_pclk"; + }; + + gpio15: gpio@e8a1a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1a000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 118 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; + clock-names = "apb_pclk"; + }; + + gpio16: gpio@e8a1b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1b000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; + clock-names = "apb_pclk"; + }; + + gpio17: gpio@e8a1c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1c000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; + clock-names = "apb_pclk"; + }; + + gpio18: gpio@ff3b4000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xff3b4000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx2 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; + clock-names = "apb_pclk"; + }; + + gpio19: gpio@ff3b5000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xff3b5000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx2 0 8 4>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; + clock-names = "apb_pclk"; + }; + + gpio20: gpio@e8a1f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1f000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx1 0 0 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; + clock-names = "apb_pclk"; + }; + + gpio21: gpio@e8a20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a20000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pmx3 0 0 6>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; + clock-names = "apb_pclk"; + }; + + gpio22: gpio@fff0b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0b000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO176 */ + gpio-ranges = <&pmx4 2 0 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; + clock-names = "apb_pclk"; + }; + + gpio23: gpio@fff0c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0c000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO184 */ + gpio-ranges = <&pmx4 0 6 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; + clock-names = "apb_pclk"; + }; + + gpio24: gpio@fff0d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0d000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO192 */ + gpio-ranges = <&pmx4 0 13 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; + clock-names = "apb_pclk"; + }; + + gpio25: gpio@fff0e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0e000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO200 */ + gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; + clock-names = "apb_pclk"; + }; + + gpio26: gpio@fff0f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0f000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO208 */ + gpio-ranges = <&pmx4 0 28 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; + clock-names = "apb_pclk"; + }; + + gpio27: gpio@fff10000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff10000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO216 */ + gpio-ranges = <&pmx4 0 36 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; + clock-names = "apb_pclk"; + }; + + gpio28: gpio@fff1d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff1d000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; + clock-names = "apb_pclk"; + }; }; }; From patchwork Wed Jun 14 08:23:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105478 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp180381qgd; Wed, 14 Jun 2017 01:25:34 -0700 (PDT) X-Received: by 10.99.2.70 with SMTP id 67mr3321537pgc.61.1497428734501; Wed, 14 Jun 2017 01:25:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497428734; cv=none; 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[209.132.180.67]) by mx.google.com with ESMTP id 33si168406plk.159.2017.06.14.01.25.34; Wed, 14 Jun 2017 01:25:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=Ndv+51Fp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932093AbdFNIZX (ORCPT + 25 others); Wed, 14 Jun 2017 04:25:23 -0400 Received: from mail-pf0-f174.google.com ([209.85.192.174]:34967 "EHLO mail-pf0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754683AbdFNIZM (ORCPT ); Wed, 14 Jun 2017 04:25:12 -0400 Received: by mail-pf0-f174.google.com with SMTP id l89so80806803pfi.2 for ; Wed, 14 Jun 2017 01:25:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W4L2d8u22c6yygXQJRk+Sqhtqu9yLqxVCuULdrLlfyQ=; b=Ndv+51FpyOPZ4V3+rExQ2HrAesm8ryU7kFGAbaow/uIX0HFe0FYgWkzmzN0+amJOcJ zWQLPlATiPCp9FEO1fRPth+RIT6SL/+oP4aZQx2QoAPVVklIWI/+gnD4cWOKfLejiD7S 91RB64o+7SEa7f88q88ASfmjiGhyVf16erT3M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W4L2d8u22c6yygXQJRk+Sqhtqu9yLqxVCuULdrLlfyQ=; b=qwrI1exN3pZmMNPUdnARDFkywIYIJ9mVyC/z2TzoujhGzBQ1wAsjN+FS4yKP7u6kWT oSrCJ93do4sRC+y02fBnycaoRvIis7FJkJomkz8HRrp0aQSZp/q6iFri6Jtj/C7TF0AH q/6WIrKpDDCh/umxBpeKF/TJ4mI4kotU+S0FcJHr3INgNuCS6MA/MnDTlgh787OLGzqU DXTfeSwKxKqMVBss+TN906dc+jywRp18+boGM0TQhgewAnTjo68f5XQTn7P+OH8Sx5lB dOnR0vO5IgdhD8n6Dg0x8Lq3vn/W4TKcxX4GbGqbFXg0L7khQ3pSdEYL0F02Xsi0HMNE YhBQ== X-Gm-Message-State: AKS2vOyurgCR9XP95g0oPPKvIK2WRexI7wiX2zPY5UUWGHSp6hfxi8w2 k6hcIsyCnd+whpx5 X-Received: by 10.99.173.75 with SMTP id y11mr3192959pgo.108.1497428707095; Wed, 14 Jun 2017 01:25:07 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.25.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:25:06 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Wang Xiaoyin , Guodong Xu Subject: [PATCH v3 12/21] arm64: dts: hi3660: add spi device nodes Date: Wed, 14 Jun 2017 16:23:29 +0800 Message-Id: <20170614082338.15673-13-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wang Xiaoyin Add spi2 and spi3 device nodes for hi3660, and enable them for hikey960. On HiKey960: - SPI2 is wired out through low speed expansion connector. - SPI3 is wired out through high speed expansion connector. Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 12 +++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 30 +++++++++++++++++++++++ 2 files changed, 42 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 9ecf6c6..ca448f0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -142,3 +142,15 @@ label = "LS-UART1"; status = "okay"; }; + +&spi2 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; +}; + +&spi3 { + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3b2a3a7..a6b91f1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -713,5 +713,35 @@ clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; clock-names = "apb_pclk"; }; + + spi2: spi@ffd68000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xffd68000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio27 2 0>; + status = "disabled"; + }; + + spi3: spi@ff3b3000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xff3b3000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio18 5 0>; + status = "disabled"; + }; }; }; From patchwork Wed Jun 14 08:23:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105476 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp180376qgd; Wed, 14 Jun 2017 01:25:33 -0700 (PDT) X-Received: by 10.84.200.200 with SMTP id u8mr3615718plh.63.1497428733770; Wed, 14 Jun 2017 01:25:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497428733; cv=none; d=google.com; s=arc-20160816; b=u6KjJBO3IQB7p3QM/BVjvklew0fEh9sZ0p07F291qtkvHaGS9QORF6aoXaX6eepZ8J TwBGKlLUgxDTgOPQPyOqfxz7WzxOs5QhGt2/1DFXJz0IkXfDTndpcpDttDN0PjWPQd4F kGHVsBZMDtiyiBfxVKl5GLkR3DFxF46agXDRValtV3Yroqk55ZWtAs8C1wPp1Y8jTKXh XboAwTe2LH7zfLj9PrCTMnJxXy8Eg6PnUuJWqXMXFiYJb+j2YvlJbYT5hs+dPYFHp0Am GetnUzkKmqRKsC2sBu1tsn3fwlJtDk+0V0TnKbOU+FLIgitkUJBNInceYEdCdNPrS1PM J8uA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=uF2+UHz5Zo6cE9UhxZbr+4/2CvK/opumC474b2CdIm0jbtm2yDqSN4fycup82eHYnt VIkufA/2iO4ZOL5FQhGHgMyjfH7roEzeU8J9zzuNmvRNN+qhfOXldGvyCM69uGKyq5R3 N93j5L5r5iTme6mVvt93ElRWf7Whc+kxaGa3aTJUC5AMUdRw8Y5dHwqyuzeRj5jLIoQ3 ZYPE6DvD9QUi4GyfSwmHKq4jRhcCsfSWwxowElC+2GFb/DHQQhRDUCuODQ2YypPWIkdl L9XL4pUn4XKj24/sBf/B5Q1quEBQA6M1p36kfYVYT/dJmWZ5gjCgalNnRIx8orGmMuFo 98+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=c6k8/+VW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 33si168406plk.159.2017.06.14.01.25.33; Wed, 14 Jun 2017 01:25:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=c6k8/+VW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754716AbdFNIZV (ORCPT + 25 others); Wed, 14 Jun 2017 04:25:21 -0400 Received: from mail-pg0-f52.google.com ([74.125.83.52]:36488 "EHLO mail-pg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754431AbdFNIZN (ORCPT ); Wed, 14 Jun 2017 04:25:13 -0400 Received: by mail-pg0-f52.google.com with SMTP id a70so72554787pge.3 for ; Wed, 14 Jun 2017 01:25:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=c6k8/+VWrAMsAAaJTC+ki/2mZKyFh7JHSglprk24oHsZDDMvDcjuYpWLNhFRtzlKRC 1CERX4wK7VNiYmAUZO/33VQNSTCS2JREyMW019SknfpPhkunDL6ol27TWiBCfYGWYdCi W/L/kTuhzegou/d0MJmnw+ZbslLdV34jjzZuA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=oSPt0HB11PPUlsfZj+UCAa4jQWss6/5qgsVltvUgBIBruW0Ghftv/eEySGIBUKZBcd 8DbiA4uJdgqxVujt6D7y0Gs7EZzDwAAD1JQX/XxfXlyOjT59b4mlBQc8NXoLmSWty3mo LUKXoXt2vCy6MvB8H4pv0J6w+KVDkklWYEv90MODBWqwcutvgooleWcOUm6d2VCQLx+E RAMo44Zy6NYfqWWlbO7qaGXsiOOCf0iUYKbG+v/bAvi7YaGZ8rhOyn9HZG/038wWf5zf FFgE/nHc5NHiGDPuJDJuQ7dIOKe8O85OJVOVKKMnw1csEj6xuk2j1D+srxKG5TGUQsqH KeuA== X-Gm-Message-State: AKS2vOwCKtB4n5h8cFW5Io0Y3G3rhWvnTmkwx+iSIFofoR9bYpC9v+DY wvib9oQvFAfuv1OH X-Received: by 10.98.50.129 with SMTP id y123mr3000516pfy.53.1497428713240; Wed, 14 Jun 2017 01:25:13 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.25.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:25:12 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Leo Yan Subject: [PATCH v3 13/21] arm64: dts: hi3660: add sp804 timer node Date: Wed, 14 Jun 2017 16:23:30 +0800 Message-Id: <20170614082338.15673-14-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Leo Yan The Hi3660 SoC comes with the sp804 timer in addition to the architecture timers. These ones are shutdown when reaching a deep idle states and a backup timer is needed. The sp804 belongs to another power domain and can fulfill the purpose of replacing temporarily an architecture timer when the CPU is idle. Describe it in the device tree, so it can be enabled at boot time. Suggested-by: Daniel Lezcano Acked-by: Daniel Lezcano Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index a6b91f1..e138973 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -186,6 +186,17 @@ #reset-cells = <2>; }; + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = , + ; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + i2c0: i2c@ffd71000 { compatible = "snps,designware-i2c"; reg = <0x0 0xffd71000 0x0 0x1000>; From patchwork Wed Jun 14 08:23:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105479 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp180388qgd; Wed, 14 Jun 2017 01:25:35 -0700 (PDT) X-Received: by 10.99.123.94 with SMTP id k30mr3328959pgn.123.1497428735596; Wed, 14 Jun 2017 01:25:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497428735; cv=none; d=google.com; s=arc-20160816; b=lOp32/a7xxfYPuo3KbCmztwTdRqApcapBXGpUQX39wD918vEzWBAW/Lndj/g3hJEMj s2Q2vuely0LQZDmuMbms+XSXgGTJLezjSWjxIJLWHb/ANFpF5+FvfjE3gseuMLFQrbO2 VzjPkdycO9KwQEfKqbdUoMZ4vs9lkntwd8w412gZh9xKn5hwaoWS8KKEB/dDkXe+5MDd LSD7g4fBXYgy0cjnX7lt04zgpQS7abckEu0O90DWjRhYmKDrBQAey9D9bVKi6XOUG55d ePXgbu+9bplNll86Cv6ozrT2q5oO4uuSComv3AWtefPULvRgs/YDKMok1tsRBU//4RN2 YAiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=l8HEG60ACS51qmx+5dpnRvo8Cd2RySFdr2XUItZtdDs=; b=Ih/6ZyFqzkEZ+cEh0KNVWh4DdIrPR2JfPCcYi27AJavzzzhgtU4rHN0BejR2cbmq0o NeuJ8Ta+WAfZxp8s80MILyo7H3fLZFV+JFrkiyS4r4Ri8UxS72Y8Tsk/2aZoKF4xX4k6 lAVDfFZ5QQkn4p4BXQhL9RBphJgQz6RsqgkaUtIK4CAJGDDmR3S22renf6imU3QMtEeg ofhxsiAESleE6XH8y3WKKaIKRa1QT8kcjdbNQLwCgCYLlEIH1LcKQ0asU+RFDx7FnIVB mpJxZGYmXQ4roXa2cmcpIKIo/8RH97wk9JBXGGi7JBNBHuAmJezxbbOe0tZ0HriVfwDA 7COQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=fuETlLuM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 33si168406plk.159.2017.06.14.01.25.35; Wed, 14 Jun 2017 01:25:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=fuETlLuM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754727AbdFNIZa (ORCPT + 25 others); Wed, 14 Jun 2017 04:25:30 -0400 Received: from mail-pg0-f51.google.com ([74.125.83.51]:33104 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932095AbdFNIZ0 (ORCPT ); Wed, 14 Jun 2017 04:25:26 -0400 Received: by mail-pg0-f51.google.com with SMTP id f185so72602336pgc.0 for ; Wed, 14 Jun 2017 01:25:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l8HEG60ACS51qmx+5dpnRvo8Cd2RySFdr2XUItZtdDs=; b=fuETlLuMkRqb+WvKK38oCTdw21HcTloU22Nyp2SEsd9NjVxkeljQtYZyqIgr9Y2qAW LJmYIARp4trqqPyCl5O6aWtCRrIGUcPWmJeIkRL8+WlJ+m8JoQF1nyenQu/E0ofN4u61 S34tro9r5aOidmReod8EbjqkFyiu/wsi39OTs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l8HEG60ACS51qmx+5dpnRvo8Cd2RySFdr2XUItZtdDs=; b=ZkpWrRO0XwhRK0Oyf1gYlO8MycHlIrM9EX3MUDnRMXBpCOHNIcbTN8jGPOZzMd89yN gtRlm99HJ1FqlXhuM2i2KUZ9oSr8Mmm9b3OuxV5WtwPpkcluoKpC2O5s0oorgNNTMBFl qopOMTeZIzyLUp83dy16hKp9M5gLVwXjMpdMLlhL9qXNAU0GUtG9PaZndY/CQ+FA3Tu+ 6dC4NOUci6cw6KwcJrla5M7l3AWEoRMvGqBQInckvtlwZU7eSGiOExgivRUIYkl/kS4X JyJDa59ebtglWoBcxTISZ5wkjq/rvSB2C57MxQatWbeyn6VICFesc9R20H+Z3EPEFDms GUoQ== X-Gm-Message-State: AKS2vOxkHBwS+HBT/ecHl/qsc9zmICoOTL8BAX7abmrEAmVMuZsaryW1 9vmVfPbB9PfapVkw X-Received: by 10.98.39.2 with SMTP id n2mr3036103pfn.182.1497428726071; Wed, 14 Jun 2017 01:25:26 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.25.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:25:25 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Xiaowei Song Subject: [PATCH v3 15/21] dt-bindings: PCI: hisi: Add document for PCIe of Kirin SoCs Date: Wed, 14 Jun 2017 16:23:32 +0800 Message-Id: <20170614082338.15673-16-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaowei Song This patch adds document for PCIe of Kirin SoC series. Signed-off-by: Xiaowei Song Acked-by: Rob Herring --- .../devicetree/bindings/pci/kirin-pcie.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt -- 2.10.2 diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt new file mode 100644 index 0000000..68ffa0f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt @@ -0,0 +1,50 @@ +HiSilicon Kirin SoCs PCIe host DT description + +Kirin PCIe host controller is based on Designware PCI core. +It shares common functions with PCIe Designware core driver +and inherits common properties defined in +Documentation/devicetree/bindings/pci/designware-pci.txt. + +Additional properties are described here: + +Required properties +- compatible: + "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC +- reg: Should contain rc_dbi, apb, phy, config registers location and length. +- reg-names: Must include the following entries: + "dbi": controller configuration registers; + "apb": apb Ctrl register defined by Kirin; + "phy": apb PHY register defined by Kirin; + "config": PCIe configuration space registers. +- reset-gpios: The gpio to generate PCIe perst assert and deassert signal. + +Optional properties: + +Example based on kirin960: + + pcie@f4000000 { + compatible = "hisilicon,kirin-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; + reg-names = "dbi","apb","phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, + <0x0 0 0 2 &gic 0 0 0 283 4>, + <0x0 0 0 3 &gic 0 0 0 284 4>, + <0x0 0 0 4 &gic 0 0 0 285 4>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + }; From patchwork Wed Jun 14 08:23:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105482 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp180490qgd; Wed, 14 Jun 2017 01:25:57 -0700 (PDT) X-Received: by 10.98.106.66 with SMTP id f63mr3023889pfc.169.1497428757425; Wed, 14 Jun 2017 01:25:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497428757; cv=none; d=google.com; s=arc-20160816; b=BG1/L0S/dVv7+NTv8EPTZDkiTYf+5z2AKXbawf6ubqPoE0rS3dzpLPpPOumc7SFYma f92w7AxkPTUjMU8G3ibixLTmzEOTd5h4txSC4NjkC8Odh78ZXawJtOZNA2B/rPPbyzyr IiJJZQhQYTNXW6/hfJC6DW+Z3GSkwxbyMNZOGOEMf0bTnZ67WWpm5hmK9j3MuENRpfen 7ayZffbmDOvLDR04vT7JGBdklQ9WqKucXV8ZjXfWkZgFlrt5p0NV+XOc+Wa/bnAYHiPi mmGWqnuC9oUw5+Bk5g7BjqmJGUy+G3k6tCUhDU53+mpCK/WJP9FCI2nvGpSwrZCZSnOZ 6kbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=8PV3QUvE4/KsHx+LrJUzAofvvlExf85kZV20f2X9des=; b=z5Pn7NuLnVTJrS9IvbZNPlNJayQ6kDmG+8AZ2hpO3N9HGOUQKgUMeFpcreVAgDz3VQ v+A4lwfqf9aafyYh2L4IrKPFLnZarXkZhoBfwPHyHQ1EhR3gxFKh7LtUhGvTBwa9BGzn +fGwMWBVEsylFbh7TccSxqszLMEXecrscsEShOhxGe3wpx6gQZpS8ZLJIY92UPxqeQ8G qLiPneIpK/UkCQPPZTc74b1wr+zc/Ph6U5aGa8anrmy9RVMYNOoEhitXjh/TuRCaMC4l 0UMVRugb3+/5vraHIc6j+vmkhuGVS5/LJHvtRvyQSca0ZwtSkIFDyr3DvpB4aag9N+gQ fl3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=anAbZoeX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 14 Jun 2017 01:25:44 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.25.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:25:44 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Wang Xiaoyin , Guodong Xu Subject: [PATCH v3 18/21] arm64: dts: hikey960: add device node for pmic and regulators Date: Wed, 14 Jun 2017 16:23:35 +0800 Message-Id: <20170614082338.15673-19-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wang Xiaoyin add device node for hi6421 pmic core and hi6421v530 voltage regulator,include LDO(1,3,9,11,15,16) Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 46 +++++++++++++++++++++++ 1 file changed, 46 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index ca448f0..e579333 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -97,6 +97,52 @@ default-state = "off"; }; }; + + pmic: pmic@fff34000 { + compatible = "hisilicon,hi6421v530-pmic"; + reg = <0x0 0xfff34000 0x0 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + ldo3: LDO3 { /* HDMI */ + regulator-name = "VOUT3_1V85"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo9: LDO9 { /* SDCARD I/O */ + regulator-name = "VOUT9_1V8_2V95"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <240>; + }; + + ldo11: LDO11 { /* Low Speed Connector */ + regulator-name = "VOUT11_1V8_2V95"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <240>; + }; + + ldo15: LDO15 { /* UFS VCC */ + regulator-name = "VOUT15_3V0"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + regulator-enable-ramp-delay = <120>; + }; + + ldo16: LDO16 { /* SD VDD */ + regulator-name = "VOUT16_2V95"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <360>; + }; + }; + }; }; &i2c0 { From patchwork Wed Jun 14 08:23:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105484 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp180582qgd; Wed, 14 Jun 2017 01:26:16 -0700 (PDT) X-Received: by 10.99.104.69 with SMTP id d66mr3286153pgc.12.1497428776205; Wed, 14 Jun 2017 01:26:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497428776; cv=none; d=google.com; s=arc-20160816; b=a/LNqQxs9tM5C3Xq0lv9+7GK92GYbFvhxEuw6XG7PLLC2YqoQcFpCB4TsGmOjxg2jd Z/7SFrkjZYq46Gq8chA0WaWK0EqrOlylfv61QRZhI8mrFoajkSmO+JF5LudzupPwYBm7 D4gDaEg/gCZkRti980IMIoWZ/TpMEmZJmC06vCRIzfSGFMBfXVZKtlaRrnupnAv8cwK8 6/ifHjJn4pX16hZtvCLC3SLRVi28eQ803AjTMAa5RDgdYHvs7di2IRliOIXQwGGGRh+H XbbWUBwQOWeHSoOxyZsgmhoiH/TKaABsn25KpDQVBHobh58HgPHV4sXppqldmk+6MLNu sBDg== ARC-Message-Signature: i=1; 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Wed, 14 Jun 2017 01:25:57 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.25.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:25:57 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Li Wei , Chen Jun Subject: [PATCH v3 20/21] arm64: dts: hi3660: add sd/sdio device nodes Date: Wed, 14 Jun 2017 16:23:37 +0800 Message-Id: <20170614082338.15673-21-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Li Wei Add sd/sdio device nodes for hi3660 soc Signed-off-by: Li Wei Signed-off-by: Chen Jun --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 8 ++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 58 +++++++++++++++++++++++ 2 files changed, 66 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index e579333..cec0b60 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -18,6 +18,8 @@ compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; aliases { + mshc1 = &dwmmc1; + mshc2 = &dwmmc2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -200,3 +202,9 @@ label = "HS-SPI1"; status = "okay"; }; + +&dwmmc1 { + vmmc-supply = <&ldo16>; + vqmmc-supply = <&ldo9>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index bdfdf27..e102b95 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -849,5 +849,63 @@ reset-gpios = <&gpio11 1 0 >; status = "ok"; }; + + /* SD */ + dwmmc1: dwmmc1@ff37f000 { + #address-cells = <1>; + #size-cells = <0>; + cd-inverted; + compatible = "hisilicon,hi3660-dw-mshc"; + num-slots = <1>; + bus-width = <0x4>; + disable-wp; + cap-sd-highspeed; + supports-highspeed; + card-detect-delay = <200>; + reg = <0x0 0xff37f000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, + <&crg_ctrl HI3660_HCLK_GATE_SD>; + clock-names = "ciu", "biu"; + clock-frequency = <3200000>; + resets = <&crg_rst 0x94 18>; + cd-gpios = <&gpio25 3 0>; + hisilicon,peripheral-syscon = <&sctrl>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pmx_func + &sd_clk_cfg_func + &sd_cfg_func>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "disabled"; + + slot@0 { + reg = <0x0>; + bus-width = <4>; + disable-wp; + }; + }; + + /* SDIO */ + dwmmc2: dwmmc2@ff3ff000 { + compatible = "hisilicon,hi3660-dw-mshc"; + reg = <0x0 0xff3ff000 0x0 0x1000>; + interrupts = ; + num-slots = <1>; + clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, + <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; + clock-names = "ciu", "biu"; + resets = <&crg_rst 0x94 20>; + card-detect-delay = <200>; + supports-highspeed; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pmx_func + &sdio_clk_cfg_func + &sdio_cfg_func>; + status = "disabled"; + }; }; };