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Thu, 16 May 2024 18:19:10 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay05.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJ8I913566572 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:10 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 372DF5806F; Thu, 16 May 2024 18:19:08 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EA9545807E; Thu, 16 May 2024 18:19:07 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:07 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 02/40] fsi: Move slave definitions to fsi-slave.h Date: Thu, 16 May 2024 13:18:29 -0500 Message-Id: <20240516181907.3468796-3-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 9ahhNrsrXLPZwHiaLLpIZK0eSJdPoh2d X-Proofpoint-ORIG-GUID: 9ahhNrsrXLPZwHiaLLpIZK0eSJdPoh2d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 Master drivers may need access to the slave definitions. Signed-off-by: Eddie James --- drivers/fsi/fsi-core.c | 35 ----------------- drivers/fsi/fsi-slave.h | 84 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+), 35 deletions(-) diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 097d5a780264c..7bf0c96fc0172 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -45,41 +45,6 @@ static const int engine_page_size = 0x400; -#define FSI_SLAVE_BASE 0x800 - -/* - * FSI slave engine control register offsets - */ -#define FSI_SMODE 0x0 /* R/W: Mode register */ -#define FSI_SISC 0x8 /* R/W: Interrupt condition */ -#define FSI_SSTAT 0x14 /* R : Slave status */ -#define FSI_SLBUS 0x30 /* W : LBUS Ownership */ -#define FSI_LLMODE 0x100 /* R/W: Link layer mode register */ - -/* - * SMODE fields - */ -#define FSI_SMODE_WSC 0x80000000 /* Warm start done */ -#define FSI_SMODE_ECRC 0x20000000 /* Hw CRC check */ -#define FSI_SMODE_SID_SHIFT 24 /* ID shift */ -#define FSI_SMODE_SID_MASK 3 /* ID Mask */ -#define FSI_SMODE_ED_SHIFT 20 /* Echo delay shift */ -#define FSI_SMODE_ED_MASK 0xf /* Echo delay mask */ -#define FSI_SMODE_SD_SHIFT 16 /* Send delay shift */ -#define FSI_SMODE_SD_MASK 0xf /* Send delay mask */ -#define FSI_SMODE_LBCRR_SHIFT 8 /* Clk ratio shift */ -#define FSI_SMODE_LBCRR_MASK 0xf /* Clk ratio mask */ - -/* - * SLBUS fields - */ -#define FSI_SLBUS_FORCE 0x80000000 /* Force LBUS ownership */ - -/* - * LLMODE fields - */ -#define FSI_LLMODE_ASYNC 0x1 - #define FSI_SLAVE_SIZE_23b 0x800000 static DEFINE_IDA(master_ida); diff --git a/drivers/fsi/fsi-slave.h b/drivers/fsi/fsi-slave.h index 1d63a585829dd..dba65bd4e083f 100644 --- a/drivers/fsi/fsi-slave.h +++ b/drivers/fsi/fsi-slave.h @@ -7,6 +7,90 @@ #include #include +#define FSI_SLAVE_BASE 0x800 + +/* + * FSI slave engine control register offsets + */ +#define FSI_SMODE 0x0 /* R/W: Mode register */ +#define FSI_SISC 0x8 /* R : Interrupt condition */ +#define FSI_SCISC 0x8 /* C : Clear interrupt condition */ +#define FSI_SISM 0xc /* R/W: Interrupt mask */ +#define FSI_SISS 0x10 /* R : Interrupt status */ +#define FSI_SSISM 0x10 /* S : Set interrupt mask */ +#define FSI_SCISM 0x14 /* C : Clear interrupt mask */ +#define FSI_SSTAT 0x14 /* R : Slave status */ +#define FSI_SI1S 0x1c /* R : Slave interrupt 1 status */ +#define FSI_SSI1M 0x1c /* S : Set slave interrupt 1 mask */ +#define FSI_SCI1M 0x20 /* C : Clear slave interrupt 1 mask */ +#define FSI_SLBUS 0x30 /* W : LBUS Ownership */ +#define FSI_SRSIC0 0x68 /* C : Clear remote interrupt condition */ +#define FSI_SRSIC4 0x6c /* C : Clear remote interrupt condition */ +#define FSI_SRSIM0 0x70 /* R/W: Remote interrupt mask */ +#define FSI_SRSIM4 0x74 /* R/W: Remote interrupt mask */ +#define FSI_SRSIS0 0x78 /* R : Remote interrupt status */ +#define FSI_SRSIS4 0x7c /* R : Remote interrupt status */ +#define FSI_LLMODE 0x100 /* R/W: Link layer mode register */ + +/* + * SMODE fields + */ +#define FSI_SMODE_WSC 0x80000000 /* Warm start done */ +#define FSI_SMODE_ECRC 0x20000000 /* Hw CRC check */ +#define FSI_SMODE_SID_SHIFT 24 /* ID shift */ +#define FSI_SMODE_SID_MASK 3 /* ID Mask */ +#define FSI_SMODE_ED_SHIFT 20 /* Echo delay shift */ +#define FSI_SMODE_ED_MASK 0xf /* Echo delay mask */ +#define FSI_SMODE_SD_SHIFT 16 /* Send delay shift */ +#define FSI_SMODE_SD_MASK 0xf /* Send delay mask */ +#define FSI_SMODE_LBCRR_SHIFT 8 /* Clk ratio shift */ +#define FSI_SMODE_LBCRR_MASK 0xf /* Clk ratio mask */ + +/* + * SISS fields + */ +#define FSI_SISS_CRC_ERROR BIT(31) +#define FSI_SISS_PROTO_ERROR BIT(30) +#define FSI_SISS_LBUS_PARITY_ERROR BIT(29) +#define FSI_SISS_LBUS_PROTO_ERROR BIT(28) +#define FSI_SISS_ACCESS_ERROR BIT(27) +#define FSI_SISS_LBUS_OWNERSHIP_ERROR BIT(26) +#define FSI_SISS_LBUS_OWNERSHIP_CHANGE BIT(25) +#define FSI_SISS_ASYNC_MODE_ERROR BIT(14) +#define FSI_SISS_OPB_ACCESS_ERROR BIT(13) +#define FSI_SISS_OPB_FENCED BIT(12) +#define FSI_SISS_OPB_PARITY_ERROR BIT(11) +#define FSI_SISS_OPB_PROTO_ERROR BIT(10) +#define FSI_SISS_OPB_TIMEOUT BIT(9) +#define FSI_SISS_OPB_ERROR_ACK BIT(8) +#define FSI_SISS_MFSI_MASTER_ERROR BIT(3) +#define FSI_SISS_MFSI_PORT_ERROR BIT(2) +#define FSI_SISS_MFSI_HP BIT(1) +#define FSI_SISS_MFSI_CR_PARITY_ERROR BIT(0) +#define FSI_SISS_ALL 0xfe007f00 + +/* + * SI1S fields + */ +#define FSI_SI1S_SLAVE_BIT 31 +#define FSI_SI1S_SHIFT_BIT 30 +#define FSI_SI1S_SCOM_BIT 29 +#define FSI_SI1S_SCRATCH_BIT 28 +#define FSI_SI1S_I2C_BIT 27 +#define FSI_SI1S_SPI_BIT 26 +#define FSI_SI1S_SBEFIFO_BIT 25 +#define FSI_SI1S_MBOX_BIT 24 + +/* + * SLBUS fields + */ +#define FSI_SLBUS_FORCE 0x80000000 /* Force LBUS ownership */ + +/* + * LLMODE fields + */ +#define FSI_LLMODE_ASYNC 0x1 + struct fsi_master; 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Thu, 16 May 2024 18:19:12 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay05.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJASx21496554 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:12 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 777A35807D; Thu, 16 May 2024 18:19:08 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3FBB558071; Thu, 16 May 2024 18:19:08 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:08 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 03/40] fsi: Fix slave addressing after break command Date: Thu, 16 May 2024 13:18:30 -0500 Message-Id: <20240516181907.3468796-4-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: CklOn_OLANOO577Ilyz59g5tq9McdkVA X-Proofpoint-GUID: CklOn_OLANOO577Ilyz59g5tq9McdkVA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 clxscore=1015 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 After a break command, the slave ID is set to 0x3, which means the FSI driver should use that ID when communicating with the slave, until SMODE is programmed with the new ID (forced to 0 for 23 bit addressing in the current implementation). This worked previously due to a feature of newer FSI slaves that don't enforce this requirement. Since hub masters cannot address non-zero slave IDs, disable this behavior for slaves off hub masters. Fixes: 2b545cd8e1b2 ("drivers/fsi: Implement slave initialisation") Signed-off-by: Eddie James --- drivers/fsi/fsi-core.c | 20 ++++++++++---------- drivers/fsi/fsi-master-hub.c | 1 + drivers/fsi/fsi-master.h | 1 + drivers/fsi/fsi-slave.h | 1 + 4 files changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 7bf0c96fc0172..e8dbf5e95c234 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -217,7 +217,7 @@ static uint32_t fsi_slave_smode(int id, u8 t_senddly, u8 t_echodly) | fsi_smode_lbcrr(0x8); } -static int fsi_slave_set_smode(struct fsi_slave *slave) +static int fsi_slave_set_smode(struct fsi_slave *slave, uint8_t id) { uint32_t smode; __be32 data; @@ -228,8 +228,7 @@ static int fsi_slave_set_smode(struct fsi_slave *slave) smode = fsi_slave_smode(slave->id, slave->t_send_delay, slave->t_echo_delay); data = cpu_to_be32(smode); - return fsi_master_write(slave->master, slave->link, slave->id, - FSI_SLAVE_BASE + FSI_SMODE, + return fsi_master_write(slave->master, slave->link, id, FSI_SLAVE_BASE + FSI_SMODE, &data, sizeof(data)); } @@ -281,7 +280,7 @@ static int fsi_slave_handle_error(struct fsi_slave *slave, bool write, slave->t_send_delay = send_delay; slave->t_echo_delay = echo_delay; - rc = fsi_slave_set_smode(slave); + rc = fsi_slave_set_smode(slave, FSI_SMODE_SID_BREAK); if (rc) return rc; @@ -773,7 +772,7 @@ static ssize_t slave_send_echo_store(struct device *dev, slave->t_send_delay = val; slave->t_echo_delay = val; - rc = fsi_slave_set_smode(slave); + rc = fsi_slave_set_smode(slave, slave->id); if (rc < 0) return rc; if (master->link_config) @@ -945,6 +944,8 @@ EXPORT_SYMBOL_GPL(fsi_free_minor); static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id) { + const uint8_t break_id = (master->flags & FSI_MASTER_FLAG_NO_BREAK_SID) ? 0 : + FSI_SMODE_SID_BREAK; uint32_t cfam_id; struct fsi_slave *slave; uint8_t crc; @@ -957,7 +958,7 @@ static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id) if (id != 0) return -EINVAL; - rc = fsi_master_read(master, link, id, 0, &data, sizeof(data)); + rc = fsi_master_read(master, link, break_id, 0, &data, sizeof(data)); if (rc) { dev_dbg(&master->dev, "can't read slave %02x:%02x %d\n", link, id, rc); @@ -981,9 +982,8 @@ static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id) */ if (master->flags & FSI_MASTER_FLAG_SWCLOCK) { llmode = cpu_to_be32(FSI_LLMODE_ASYNC); - rc = fsi_master_write(master, link, id, - FSI_SLAVE_BASE + FSI_LLMODE, - &llmode, sizeof(llmode)); + rc = fsi_master_write(master, link, break_id, FSI_SLAVE_BASE + FSI_LLMODE, &llmode, + sizeof(llmode)); if (rc) dev_warn(&master->dev, "can't set llmode on slave:%02x:%02x %d\n", @@ -1028,7 +1028,7 @@ static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id) "can't set slbus on slave:%02x:%02x %d\n", link, id, rc); - rc = fsi_slave_set_smode(slave); + rc = fsi_slave_set_smode(slave, break_id); if (rc) { dev_warn(&master->dev, "can't set smode on slave:%02x:%02x %d\n", diff --git a/drivers/fsi/fsi-master-hub.c b/drivers/fsi/fsi-master-hub.c index 36da643b32018..eea8649fee74d 100644 --- a/drivers/fsi/fsi-master-hub.c +++ b/drivers/fsi/fsi-master-hub.c @@ -232,6 +232,7 @@ static int hub_master_probe(struct device *dev) hub->master.idx = fsi_dev->slave->link + 1; hub->master.n_links = links; + hub->master.flags = FSI_MASTER_FLAG_NO_BREAK_SID; hub->master.read = hub_master_read; hub->master.write = hub_master_write; hub->master.send_break = hub_master_break; diff --git a/drivers/fsi/fsi-master.h b/drivers/fsi/fsi-master.h index 967622c1cabf7..a0d7ad0f0f7cc 100644 --- a/drivers/fsi/fsi-master.h +++ b/drivers/fsi/fsi-master.h @@ -111,6 +111,7 @@ /* fsi-master definition and flags */ #define FSI_MASTER_FLAG_SWCLOCK 0x1 +#define FSI_MASTER_FLAG_NO_BREAK_SID 0x2 /* * Structures and function prototypes diff --git a/drivers/fsi/fsi-slave.h b/drivers/fsi/fsi-slave.h index dba65bd4e083f..f6cca04131a92 100644 --- a/drivers/fsi/fsi-slave.h +++ b/drivers/fsi/fsi-slave.h @@ -39,6 +39,7 @@ #define FSI_SMODE_ECRC 0x20000000 /* Hw CRC check */ #define FSI_SMODE_SID_SHIFT 24 /* ID shift */ #define FSI_SMODE_SID_MASK 3 /* ID Mask */ +#define FSI_SMODE_SID_BREAK 3 /* ID after break command */ #define FSI_SMODE_ED_SHIFT 20 /* Echo delay shift */ #define FSI_SMODE_ED_MASK 0xf /* Echo delay mask */ #define FSI_SMODE_SD_SHIFT 16 /* Send delay shift */ From patchwork Thu May 16 18:18:33 2024 Content-Type: text/plain; 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Thu, 16 May 2024 18:19:11 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay06.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJ9If28574388 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:11 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6503B58087; Thu, 16 May 2024 18:19:09 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2500D58065; Thu, 16 May 2024 18:19:09 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:09 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 06/40] fsi: core: Improve master read/write/error traces Date: Thu, 16 May 2024 13:18:33 -0500 Message-Id: <20240516181907.3468796-7-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 7nyjdNlNVNj31MUGPHseawf0FtNyXecb X-Proofpoint-ORIG-GUID: 7nyjdNlNVNj31MUGPHseawf0FtNyXecb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 phishscore=0 suspectscore=0 mlxlogscore=881 adultscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 Consolidate the master read and write traces into one trace and change the result trace into an error trace for less spam. Signed-off-by: Eddie James --- drivers/fsi/fsi-core.c | 26 +++++---- include/trace/events/fsi.h | 112 ++++++++++++------------------------- 2 files changed, 51 insertions(+), 87 deletions(-) diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 44875f2350b04..b3029f9c05e4a 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -1116,14 +1116,15 @@ static int fsi_master_read(struct fsi_master *master, int link, { int rc; - trace_fsi_master_read(master, link, slave_id, addr, size); - rc = fsi_check_access(addr, size); - if (!rc) + if (!rc) { rc = master->read(master, link, slave_id, addr, val, size); - - trace_fsi_master_rw_result(master, link, slave_id, addr, size, - false, val, rc); + if (rc) + trace_fsi_master_error(master->idx, link, slave_id, addr, size, val, rc, + true); + else + trace_fsi_master_xfer(master->idx, link, slave_id, addr, size, val, true); + } return rc; } @@ -1133,14 +1134,15 @@ static int fsi_master_write(struct fsi_master *master, int link, { int rc; - trace_fsi_master_write(master, link, slave_id, addr, size, val); - rc = fsi_check_access(addr, size); - if (!rc) + if (!rc) { rc = master->write(master, link, slave_id, addr, val, size); - - trace_fsi_master_rw_result(master, link, slave_id, addr, size, - true, val, rc); + if (rc) + trace_fsi_master_error(master->idx, link, slave_id, addr, size, val, rc, + false); + else + trace_fsi_master_xfer(master->idx, link, slave_id, addr, size, val, false); + } return rc; } diff --git a/include/trace/events/fsi.h b/include/trace/events/fsi.h index 5ff15126ad9d5..fed8835f438e5 100644 --- a/include/trace/events/fsi.h +++ b/include/trace/events/fsi.h @@ -8,101 +8,63 @@ #include -TRACE_EVENT(fsi_master_read, - TP_PROTO(const struct fsi_master *master, int link, int id, - uint32_t addr, size_t size), - TP_ARGS(master, link, id, addr, size), +TRACE_EVENT(fsi_master_xfer, + TP_PROTO(int master_idx, int link, int id, uint32_t addr, size_t size, const void *data, + bool read), + TP_ARGS(master_idx, link, id, addr, size, data, read), TP_STRUCT__entry( - __field(int, master_idx) - __field(int, link) - __field(int, id) - __field(__u32, addr) - __field(size_t, size) + __field(int, master_idx) + __field(int, link) + __field(int, id) + __field(uint32_t, addr) + __field(int, size) + __field(uint32_t, data) + __field(bool, read) ), TP_fast_assign( - __entry->master_idx = master->idx; + __entry->master_idx = master_idx; __entry->link = link; __entry->id = id; __entry->addr = addr; - __entry->size = size; - ), - TP_printk("fsi%d:%02d:%02d %08x[%zu]", - __entry->master_idx, - __entry->link, - __entry->id, - __entry->addr, - __entry->size - ) -); - -TRACE_EVENT(fsi_master_write, - TP_PROTO(const struct fsi_master *master, int link, int id, - uint32_t addr, size_t size, const void *data), - TP_ARGS(master, link, id, addr, size, data), - TP_STRUCT__entry( - __field(int, master_idx) - __field(int, link) - __field(int, id) - __field(__u32, addr) - __field(size_t, size) - __field(__u32, data) - ), - TP_fast_assign( - __entry->master_idx = master->idx; - __entry->link = link; - __entry->id = id; - __entry->addr = addr; - __entry->size = size; + __entry->size = (int)size; __entry->data = 0; memcpy(&__entry->data, data, size); + __entry->read = read; ), - TP_printk("fsi%d:%02d:%02d %08x[%zu] <= {%*ph}", - __entry->master_idx, - __entry->link, - __entry->id, - __entry->addr, - __entry->size, - (int)__entry->size, &__entry->data - ) + TP_printk("fsi%d:%02d:%02d %s %08x {%*ph}", __entry->master_idx, __entry->link, + __entry->id, __entry->read ? "read" : "write", __entry->addr, __entry->size, + &__entry->data) ); -TRACE_EVENT(fsi_master_rw_result, - TP_PROTO(const struct fsi_master *master, int link, int id, - uint32_t addr, size_t size, - bool write, const void *data, int ret), - TP_ARGS(master, link, id, addr, size, write, data, ret), +TRACE_EVENT(fsi_master_error, + TP_PROTO(int master_idx, int link, int id, uint32_t addr, size_t size, const void *data, + int ret, bool read), + TP_ARGS(master_idx, link, id, addr, size, data, ret, read), TP_STRUCT__entry( - __field(int, master_idx) - __field(int, link) - __field(int, id) - __field(__u32, addr) - __field(size_t, size) - __field(bool, write) - __field(__u32, data) - __field(int, ret) + __field(int, master_idx) + __field(int, link) + __field(int, id) + __field(uint32_t, addr) + __field(int, size) + __field(uint32_t, data) + __field(int, ret) + __field(bool, read) ), TP_fast_assign( - __entry->master_idx = master->idx; + __entry->master_idx = master_idx; __entry->link = link; __entry->id = id; __entry->addr = addr; - __entry->size = size; - __entry->write = write; + __entry->size = (int)size; __entry->data = 0; - __entry->ret = ret; - if (__entry->write || !__entry->ret) + if (!read) memcpy(&__entry->data, data, size); + __entry->ret = ret; + __entry->read = read; ), - TP_printk("fsi%d:%02d:%02d %08x[%zu] %s {%*ph} ret %d", - __entry->master_idx, - __entry->link, - __entry->id, - __entry->addr, - __entry->size, - __entry->write ? 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Thu, 16 May 2024 18:19:15 GMT Received: from smtprelay03.wdc07v.mail.ibm.com ([172.16.1.70]) by ppma13.dal12v.mail.ibm.com (PPS) with ESMTPS id 3y2n7m34m4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 May 2024 18:19:15 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay03.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJC4I10289720 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:14 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9274A58067; Thu, 16 May 2024 18:19:10 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 52E4E58069; Thu, 16 May 2024 18:19:10 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:10 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 10/40] fsi: core: Add slave spinlock Date: Thu, 16 May 2024 13:18:37 -0500 Message-Id: <20240516181907.3468796-11-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: jIaNXquNEVynCey3evKIVRnjE3zyk2gu X-Proofpoint-ORIG-GUID: jIaNXquNEVynCey3evKIVRnjE3zyk2gu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 suspectscore=0 mlxscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 phishscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 FSI slave operations were not locked, meaning that during slave error recovery operations, other slave accesses may take place, resulting in incorrect recovery and additional errors. Make the slave access and error recovery atomic with a spinlock. Don't use a mutex for future interrupt handling support. Signed-off-by: Eddie James --- drivers/fsi/fsi-core.c | 7 +++++++ drivers/fsi/fsi-slave.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index ce9762d1bd8b0..660f89b743235 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -304,6 +304,7 @@ static int fsi_slave_handle_error(struct fsi_slave *slave, bool write, int fsi_slave_read(struct fsi_slave *slave, uint32_t addr, void *val, size_t size) { + unsigned long flags; uint8_t id = slave->id; int rc, err_rc, i; @@ -311,6 +312,7 @@ int fsi_slave_read(struct fsi_slave *slave, uint32_t addr, if (rc) return rc; + spin_lock_irqsave(&slave->lock, flags); for (i = 0; i < slave_retries; i++) { rc = fsi_master_read(slave->master, slave->link, id, addr, val, size); @@ -321,6 +323,7 @@ int fsi_slave_read(struct fsi_slave *slave, uint32_t addr, if (err_rc) break; } + spin_unlock_irqrestore(&slave->lock, flags); return rc; } @@ -329,6 +332,7 @@ EXPORT_SYMBOL_GPL(fsi_slave_read); int fsi_slave_write(struct fsi_slave *slave, uint32_t addr, const void *val, size_t size) { + unsigned long flags; uint8_t id = slave->id; int rc, err_rc, i; @@ -336,6 +340,7 @@ int fsi_slave_write(struct fsi_slave *slave, uint32_t addr, if (rc) return rc; + spin_lock_irqsave(&slave->lock, flags); for (i = 0; i < slave_retries; i++) { rc = fsi_master_write(slave->master, slave->link, id, addr, val, size); @@ -346,6 +351,7 @@ int fsi_slave_write(struct fsi_slave *slave, uint32_t addr, if (err_rc) break; } + spin_unlock_irqrestore(&slave->lock, flags); return rc; } @@ -1007,6 +1013,7 @@ static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id) if (!slave) return -ENOMEM; + spin_lock_init(&slave->lock); dev_set_name(&slave->dev, "slave@%02x:%02x", link, id); slave->dev.type = &cfam_type; slave->dev.parent = &master->dev; diff --git a/drivers/fsi/fsi-slave.h b/drivers/fsi/fsi-slave.h index e9fd4be6f3760..0468ec1c60db2 100644 --- a/drivers/fsi/fsi-slave.h +++ b/drivers/fsi/fsi-slave.h @@ -6,6 +6,7 @@ #include #include +#include #define FSI_SLAVE_BASE 0x800 @@ -107,6 +108,7 @@ struct fsi_slave { struct device dev; struct fsi_master *master; struct cdev cdev; + spinlock_t lock; /* atomic access and error recovery */ int cdev_idx; int id; /* FSI address */ int link; /* FSI link# */ From patchwork Thu May 16 18:18:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797447 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3410915ECC6; Thu, 16 May 2024 18:19:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.158.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715883587; cv=none; b=l6kENBnn8wsW5qZJxeIfHC77Evf1eWqtdxb2nVq/ld9OkpQBlDAMGGY4vgTOZO2BjsOZBQigZpRFp6SdROGDvg8xbtRPskZXUcUcppXIQOn1rw9ArQojtKA1zc0Vte4GjlqLBxVmH4F437x7woAdm0zP/uzUUqAsn14gW2gDlgE= ARC-Message-Signature: i=1; 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Thu, 16 May 2024 18:19:13 GMT Received: from smtprelay04.wdc07v.mail.ibm.com ([172.16.1.71]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3y2mgmud2x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 May 2024 18:19:13 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay04.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJB1k57213288 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:13 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 369345808D; Thu, 16 May 2024 18:19:11 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E3EED58069; Thu, 16 May 2024 18:19:10 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:10 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 12/40] fsi: core: Add common regmap master functions Date: Thu, 16 May 2024 13:18:39 -0500 Message-Id: <20240516181907.3468796-13-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Jlr-WwbmGT8S9WoBXaDQDVCLCIiud5Hn X-Proofpoint-ORIG-GUID: Jlr-WwbmGT8S9WoBXaDQDVCLCIiud5Hn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 adultscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 For hardware FSI masters (Aspeed and hub at the moment), the initialization, link enable, and error recovery procedures are common. Add a regmap pointer to the master structure so that master drivers can let the common code handle these procedures. Signed-off-by: Eddie James --- Changes since v2: - Zero the regmap_config structure in the common FSI initialization function drivers/fsi/Kconfig | 2 + drivers/fsi/fsi-core.c | 162 ++++++++++++++++++++++++++++++++++++- drivers/fsi/fsi-master.h | 16 ++++ include/trace/events/fsi.h | 17 ++++ 4 files changed, 195 insertions(+), 2 deletions(-) diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig index 79a31593618a6..a6760870538d3 100644 --- a/drivers/fsi/Kconfig +++ b/drivers/fsi/Kconfig @@ -7,6 +7,7 @@ menuconfig FSI tristate "FSI support" depends on OF select CRC4 + select REGMAP help FSI - the FRU Support Interface - is a simple bus for low-level access to POWER-based hardware. @@ -37,6 +38,7 @@ config FSI_MASTER_GPIO config FSI_MASTER_HUB tristate "FSI hub master" + select REGMAP_FSI help This option enables a FSI hub master driver. Hub is a type of FSI master that is connected to the upstream master via a slave. Hubs diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 36e31eafad3d0..bfb147de90efc 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -1155,18 +1156,50 @@ static int fsi_master_write(struct fsi_master *master, int link, return rc; } +int fsi_master_link_enable(struct fsi_master *master, int link, bool enable) +{ + u32 msiep = 0x80000000 >> (4 * (link % 8)); + u32 menp = 0x80000000 >> (link % 32); + int enable_idx = 4 * (link / 32); + int irq_idx = 4 * (link / 8); + int rc; + + if (enable) { + rc = regmap_write(master->map, FSI_MSENP0 + enable_idx, menp); + if (rc) + return rc; + + mdelay(FSI_LINK_ENABLE_SETUP_TIME); + + rc = regmap_write(master->map, FSI_MSSIEP0 + irq_idx, msiep); + } else { + rc = regmap_write(master->map, FSI_MCSIEP0 + irq_idx, msiep); + if (rc) + return rc; + + rc = regmap_write(master->map, FSI_MCENP0 + enable_idx, menp); + } + + return rc; +} +EXPORT_SYMBOL_GPL(fsi_master_link_enable); + static int fsi_master_link_disable(struct fsi_master *master, int link) { if (master->link_enable) return master->link_enable(master, link, false); + else if (master->map) + return fsi_master_link_enable(master, link, false); return 0; } -static int fsi_master_link_enable(struct fsi_master *master, int link) +static int _fsi_master_link_enable(struct fsi_master *master, int link) { if (master->link_enable) return master->link_enable(master, link, true); + else if (master->map) + return fsi_master_link_enable(master, link, true); return 0; } @@ -1194,7 +1227,7 @@ static int fsi_master_scan(struct fsi_master *master) trace_fsi_master_scan(master, true); for (link = 0; link < master->n_links; link++) { - rc = fsi_master_link_enable(master, link); + rc = _fsi_master_link_enable(master, link); if (rc) { dev_dbg(&master->dev, "enable link %d failed: %d\n", link, rc); @@ -1291,6 +1324,131 @@ static struct class fsi_master_class = { .dev_groups = master_groups, }; +void fsi_master_error(struct fsi_master *master, int link) +{ + u32 bits = FSI_MMODE_EIP | FSI_MMODE_RELA; + bool mmode = master->mmode & bits; + + if (trace_fsi_master_error_regs_enabled()) { + unsigned int mesrb = 0xffffffff; + unsigned int mstap = 0xffffffff; + + regmap_read(master->map, FSI_MESRB0, &mesrb); + regmap_read(master->map, FSI_MSTAP0 + (link * 4), &mstap); + + trace_fsi_master_error_regs(master->idx, mesrb, mstap); + } + + if (mmode) + regmap_write(master->map, FSI_MMODE, master->mmode & ~bits); + + regmap_write(master->map, FSI_MRESP0, FSI_MRESP_RST_ALL_MASTER); + + if (mmode) + regmap_write(master->map, FSI_MMODE, master->mmode); +} +EXPORT_SYMBOL_GPL(fsi_master_error); + +static inline u32 fsi_mmode_crs0(u32 x) +{ + return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT; +} + +static inline u32 fsi_mmode_crs1(u32 x) +{ + return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT; +} + +int fsi_master_init(struct fsi_master *master, unsigned long parent_clock_frequency) +{ + unsigned int mlevp; + unsigned int maeb; + int div = 1; + int rc; + + if (parent_clock_frequency) { + u32 clock_frequency; + + if (device_property_read_u32(&master->dev, "clock-frequency", &clock_frequency) || + !clock_frequency) + clock_frequency = parent_clock_frequency; + + div = DIV_ROUND_UP(parent_clock_frequency, clock_frequency); + master->clock_frequency = parent_clock_frequency / div; + } + + rc = regmap_write(master->map, FSI_MRESP0, FSI_MRESP_RST_ALL_MASTER | + FSI_MRESP_RST_ALL_LINK | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); + if (rc) + return rc; + + rc = regmap_write(master->map, FSI_MECTRL, FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM); + if (rc) + return rc; + + master->mmode = FSI_MMODE_ECRC | FSI_MMODE_EPC | fsi_mmode_crs0(div) | + fsi_mmode_crs1(div) | FSI_MMODE_P8_TO_LSB; + rc = regmap_write(master->map, FSI_MMODE, master->mmode); + if (rc) + return rc; + + rc = regmap_write(master->map, FSI_MDLYR, 0xffff0000); + if (rc) + return rc; + + rc = regmap_write(master->map, FSI_MSENP0, 0xffffffff); + if (rc) + return rc; + + mdelay(FSI_LINK_ENABLE_SETUP_TIME); + + rc = regmap_write(master->map, FSI_MCENP0, 0xffffffff); + if (rc) + return rc; + + rc = regmap_read(master->map, FSI_MAEB, &maeb); + if (rc) + return rc; + + rc = regmap_write(master->map, FSI_MRESP0, FSI_MRESP_RST_ALL_MASTER | + FSI_MRESP_RST_ALL_LINK); + if (rc) + return rc; + + rc = regmap_read(master->map, FSI_MLEVP0, &mlevp); + if (rc) + return rc; + + rc = regmap_write(master->map, FSI_MRESB0, FSI_MRESB_RST_GEN); + if (rc) + return rc; + + rc = regmap_write(master->map, FSI_MRESB0, FSI_MRESB_RST_ERR); + if (rc) + return rc; + + if (master->flags & FSI_MASTER_FLAG_INTERRUPT) + master->mmode |= FSI_MMODE_EIP; + if (master->flags & FSI_MASTER_FLAG_RELA) + master->mmode |= FSI_MMODE_RELA; + return regmap_write(master->map, FSI_MMODE, master->mmode); +} +EXPORT_SYMBOL_GPL(fsi_master_init); + +void fsi_master_regmap_config(struct regmap_config *config) +{ + memset(config, 0, sizeof(*config)); + + config->reg_bits = 32; + config->val_bits = 32; + config->disable_locking = true; // master driver will lock + config->fast_io = true; + config->cache_type = REGCACHE_NONE; + config->val_format_endian = REGMAP_ENDIAN_NATIVE; + config->can_sleep = false; +} +EXPORT_SYMBOL_GPL(fsi_master_regmap_config); + int fsi_master_register(struct fsi_master *master) { int rc; diff --git a/drivers/fsi/fsi-master.h b/drivers/fsi/fsi-master.h index ff23983ea84c8..8ea2f69ec4922 100644 --- a/drivers/fsi/fsi-master.h +++ b/drivers/fsi/fsi-master.h @@ -27,6 +27,9 @@ #define FSI_MLEVP0 0x18 /* R: plug detect */ #define FSI_MSENP0 0x18 /* S: Set enable */ #define FSI_MCENP0 0x20 /* C: Clear enable */ +#define FSI_MSIEP0 0x30 /* R/W: interrupt enable */ +#define FSI_MSSIEP0 0x50 /* S: Set interrupt enable */ +#define FSI_MCSIEP0 0x70 /* C: Clear interrupt enable */ #define FSI_MAEB 0x70 /* R: Error address */ #define FSI_MVER 0x74 /* R: master version/type */ #define FSI_MSTAP0 0xd0 /* R: Port status */ @@ -108,10 +111,16 @@ /* Misc */ #define FSI_CRC_SIZE 4 +#define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */ /* fsi-master definition and flags */ #define FSI_MASTER_FLAG_SWCLOCK 0x1 #define FSI_MASTER_FLAG_NO_BREAK_SID 0x2 +#define FSI_MASTER_FLAG_INTERRUPT 0x4 +#define FSI_MASTER_FLAG_RELA 0x8 + +struct regmap; +struct regmap_config; /* * Structures and function prototypes @@ -121,6 +130,8 @@ struct fsi_master { struct device dev; + struct regmap *map; + u32 mmode; unsigned long clock_frequency; int idx; int n_links; @@ -140,6 +151,11 @@ struct fsi_master { #define to_fsi_master(d) container_of(d, struct fsi_master, dev) +void fsi_master_error(struct fsi_master *master, int link); +int fsi_master_init(struct fsi_master *master, unsigned long parent_clock_frequency); +int fsi_master_link_enable(struct fsi_master *master, int link, bool enable); +void fsi_master_regmap_config(struct regmap_config *config); + /** * fsi_master registration & lifetime: the fsi_master_register() and * fsi_master_unregister() functions will take ownership of the master, and diff --git a/include/trace/events/fsi.h b/include/trace/events/fsi.h index 5509afc98ee8b..da977d59e163e 100644 --- a/include/trace/events/fsi.h +++ b/include/trace/events/fsi.h @@ -67,6 +67,23 @@ TRACE_EVENT(fsi_master_error, &__entry->data, __entry->ret) ); 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Thu, 16 May 2024 18:19:11 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 14/40] fsi: hub: Use common initialization and link enable Date: Thu, 16 May 2024 13:18:41 -0500 Message-Id: <20240516181907.3468796-15-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: PERxO3mfmi5SQtAcViUm7s-hG3sfF54E X-Proofpoint-ORIG-GUID: PERxO3mfmi5SQtAcViUm7s-hG3sfF54E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 malwarescore=0 phishscore=0 clxscore=1015 mlxlogscore=904 priorityscore=1501 adultscore=0 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 Set up an FSI regmap for the hub master to use the new common master initialization and link enable procedures. Signed-off-by: Eddie James --- drivers/fsi/fsi-master-hub.c | 142 ++++++----------------------------- 1 file changed, 23 insertions(+), 119 deletions(-) diff --git a/drivers/fsi/fsi-master-hub.c b/drivers/fsi/fsi-master-hub.c index eea8649fee74d..91ad6b7728fa2 100644 --- a/drivers/fsi/fsi-master-hub.c +++ b/drivers/fsi/fsi-master-hub.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "fsi-master.h" @@ -16,8 +17,6 @@ #define FSI_ENGID_HUB_MASTER 0x1c -#define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */ - /* * FSI hub master support * @@ -78,134 +77,33 @@ static int hub_master_break(struct fsi_master *master, int link) return hub_master_write(master, link, 0, addr, &cmd, sizeof(cmd)); } -static int hub_master_link_enable(struct fsi_master *master, int link, - bool enable) -{ - struct fsi_master_hub *hub = to_fsi_master_hub(master); - int idx, bit; - __be32 reg; - int rc; - - idx = link / 32; - bit = link % 32; - - reg = cpu_to_be32(0x80000000 >> bit); - - if (!enable) - return fsi_device_write(hub->upstream, FSI_MCENP0 + (4 * idx), - ®, 4); - - rc = fsi_device_write(hub->upstream, FSI_MSENP0 + (4 * idx), ®, 4); - if (rc) - return rc; - - mdelay(FSI_LINK_ENABLE_SETUP_TIME); - - return 0; -} - static void hub_master_release(struct device *dev) { struct fsi_master_hub *hub = to_fsi_master_hub(to_fsi_master(dev)); + regmap_exit(hub->master.map); kfree(hub); } -/* mmode encoders */ -static inline u32 fsi_mmode_crs0(u32 x) -{ - return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT; -} - -static inline u32 fsi_mmode_crs1(u32 x) -{ - return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT; -} - -static int hub_master_init(struct fsi_master_hub *hub) -{ - struct fsi_device *dev = hub->upstream; - __be32 reg; - int rc; - - reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK - | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); - rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg)); - if (rc) - return rc; - - /* Initialize the MFSI (hub master) engine */ - reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK - | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); - rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg)); - if (rc) - return rc; - - reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM); - rc = fsi_device_write(dev, FSI_MECTRL, ®, sizeof(reg)); - if (rc) - return rc; - - reg = cpu_to_be32(FSI_MMODE_EIP | FSI_MMODE_ECRC | FSI_MMODE_EPC - | fsi_mmode_crs0(1) | fsi_mmode_crs1(1) - | FSI_MMODE_P8_TO_LSB); - rc = fsi_device_write(dev, FSI_MMODE, ®, sizeof(reg)); - if (rc) - return rc; - - reg = cpu_to_be32(0xffff0000); - rc = fsi_device_write(dev, FSI_MDLYR, ®, sizeof(reg)); - if (rc) - return rc; - - reg = cpu_to_be32(~0); - rc = fsi_device_write(dev, FSI_MSENP0, ®, sizeof(reg)); - if (rc) - return rc; - - /* Leave enabled long enough for master logic to set up */ - mdelay(FSI_LINK_ENABLE_SETUP_TIME); - - rc = fsi_device_write(dev, FSI_MCENP0, ®, sizeof(reg)); - if (rc) - return rc; - - rc = fsi_device_read(dev, FSI_MAEB, ®, sizeof(reg)); - if (rc) - return rc; - - reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK); - rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg)); - if (rc) - return rc; - - rc = fsi_device_read(dev, FSI_MLEVP0, ®, sizeof(reg)); - if (rc) - return rc; - - /* Reset the master bridge */ - reg = cpu_to_be32(FSI_MRESB_RST_GEN); - rc = fsi_device_write(dev, FSI_MRESB0, ®, sizeof(reg)); - if (rc) - return rc; - - reg = cpu_to_be32(FSI_MRESB_RST_ERR); - return fsi_device_write(dev, FSI_MRESB0, ®, sizeof(reg)); -} - static int hub_master_probe(struct device *dev) { + struct regmap_config hub_master_regmap_config; struct fsi_device *fsi_dev = to_fsi_dev(dev); struct fsi_master_hub *hub; + struct regmap *map; uint32_t reg, links; - __be32 __reg; int rc; - rc = fsi_device_read(fsi_dev, FSI_MVER, &__reg, sizeof(__reg)); + fsi_master_regmap_config(&hub_master_regmap_config); + hub_master_regmap_config.reg_base = fsi_dev->addr; + map = regmap_init_fsi(fsi_dev, &hub_master_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + + rc = regmap_read(map, FSI_MVER, ®); if (rc) - return rc; + goto err_regmap; - reg = be32_to_cpu(__reg); links = (reg >> 8) & 0xff; dev_dbg(dev, "hub version %08x (%d links)\n", reg, links); @@ -213,7 +111,7 @@ static int hub_master_probe(struct device *dev) FSI_HUB_LINK_SIZE * links); if (rc) { dev_err(dev, "can't claim slave address range for links"); - return rc; + goto err_regmap; } hub = kzalloc(sizeof(*hub), GFP_KERNEL); @@ -229,22 +127,24 @@ static int hub_master_probe(struct device *dev) hub->master.dev.parent = dev; hub->master.dev.release = hub_master_release; hub->master.dev.of_node = of_node_get(dev_of_node(dev)); + hub->master.map = map; hub->master.idx = fsi_dev->slave->link + 1; hub->master.n_links = links; - hub->master.flags = FSI_MASTER_FLAG_NO_BREAK_SID; + hub->master.flags = FSI_MASTER_FLAG_NO_BREAK_SID | FSI_MASTER_FLAG_INTERRUPT; hub->master.read = hub_master_read; hub->master.write = hub_master_write; hub->master.send_break = hub_master_break; - hub->master.link_enable = hub_master_link_enable; dev_set_drvdata(dev, hub); - hub_master_init(hub); + rc = fsi_master_init(&hub->master, fsi_dev->slave->master->clock_frequency); + if (rc) + goto err_free; rc = fsi_master_register(&hub->master); if (rc) - goto err_release; + goto err_free; /* At this point, fsi_master_register performs the device_initialize(), * and holds the sole reference on master.dev. This means the device @@ -256,9 +156,13 @@ static int hub_master_probe(struct device *dev) get_device(&hub->master.dev); return 0; +err_free: + kfree(hub); err_release: fsi_slave_release_range(fsi_dev->slave, FSI_HUB_LINK_OFFSET, FSI_HUB_LINK_SIZE * links); +err_regmap: + regmap_exit(map); return rc; } From patchwork Thu May 16 18:18:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797443 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B0FC15747C; Thu, 16 May 2024 18:20:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.158.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715883606; cv=none; b=gfG5OWvzZVxXqK6r5r9oNYH0ZWXoox3DiGt61sGTCS4NO6WOVaqu/AdC1cIYJdAjOR5F7fWlvTH5rjdpxoqxV2jUp9OcVGBW0AyYCGdzHdX7kjId++iAzEMZoufhpk4IejWNHROmn6CXzpvv4X4/gPUZjYUMs0CPZQy/cwzSkJ4= ARC-Message-Signature: i=1; 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Thu, 16 May 2024 18:19:17 GMT Received: from smtprelay05.wdc07v.mail.ibm.com ([172.16.1.72]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3y2mgmud35-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 May 2024 18:19:17 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay05.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJE8426411654 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:17 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AE6B95807A; Thu, 16 May 2024 18:19:12 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6FB245806B; Thu, 16 May 2024 18:19:12 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:12 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 17/40] fsi: aspeed: Refactor trace functions Date: Thu, 16 May 2024 13:18:44 -0500 Message-Id: <20240516181907.3468796-18-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: SJUFraF2MmaFOkX6y36r_0vh4Mt_xvBo X-Proofpoint-ORIG-GUID: SJUFraF2MmaFOkX6y36r_0vh4Mt_xvBo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 malwarescore=0 phishscore=0 clxscore=1015 mlxlogscore=889 priorityscore=1501 adultscore=0 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 Remove the opb error trace, add a timeout trace, and combine the read/write traces. Signed-off-by: Eddie James --- drivers/fsi/fsi-master-aspeed.c | 29 +++------ include/trace/events/fsi_master_aspeed.h | 80 ++++++++---------------- 2 files changed, 34 insertions(+), 75 deletions(-) diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c index 29932037c9866..04aa5cb9b6fad 100644 --- a/drivers/fsi/fsi-master-aspeed.c +++ b/drivers/fsi/fsi-master-aspeed.c @@ -122,16 +122,17 @@ static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr, status = readl(base + OPB0_STATUS); - trace_fsi_master_aspeed_opb_write(addr, val, transfer_size, status, reg); - /* Return error when poll timed out */ - if (ret) + if (ret) { + trace_fsi_master_aspeed_timeout(reg, status, false); return ret; + } /* Command failed, master will reset */ if (status & STATUS_ERR_ACK) return -EIO; + trace_fsi_master_aspeed_opb_xfer(addr, transfer_size + 1, val, false); return 0; } @@ -175,13 +176,11 @@ static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr, result = readl(base + OPB0_FSI_DATA_R); - trace_fsi_master_aspeed_opb_read(addr, transfer_size, result, - readl(base + OPB0_STATUS), - reg); - /* Return error when poll timed out */ - if (ret) + if (ret) { + trace_fsi_master_aspeed_timeout(reg, status, true); return ret; + } /* Command failed, master will reset */ if (status & STATUS_ERR_ACK) @@ -204,6 +203,7 @@ static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr, } + trace_fsi_master_aspeed_opb_xfer(addr, transfer_size + 1, result, true); return 0; } @@ -226,19 +226,6 @@ static int check_errors(struct fsi_master_aspeed *aspeed, int err) { int ret; - if (trace_fsi_master_aspeed_opb_error_enabled()) { - __be32 mresp0, mstap0, mesrb0; - - opb_readl(aspeed, ctrl_base + FSI_MRESP0, &mresp0); - opb_readl(aspeed, ctrl_base + FSI_MSTAP0, &mstap0); - opb_readl(aspeed, ctrl_base + FSI_MESRB0, &mesrb0); - - trace_fsi_master_aspeed_opb_error( - be32_to_cpu(mresp0), - be32_to_cpu(mstap0), - be32_to_cpu(mesrb0)); - } - if (err == -EIO) { /* Check MAEB (0x70) ? */ diff --git a/include/trace/events/fsi_master_aspeed.h b/include/trace/events/fsi_master_aspeed.h index 0fff873775f19..7eeecbfec7f09 100644 --- a/include/trace/events/fsi_master_aspeed.h +++ b/include/trace/events/fsi_master_aspeed.h @@ -8,69 +8,41 @@ #include -TRACE_EVENT(fsi_master_aspeed_opb_read, - TP_PROTO(uint32_t addr, size_t size, uint32_t result, uint32_t status, uint32_t irq_status), - TP_ARGS(addr, size, result, status, irq_status), +TRACE_EVENT(fsi_master_aspeed_opb_xfer, + TP_PROTO(uint32_t addr, uint32_t size, uint32_t data, bool read), + TP_ARGS(addr, size, data, read), TP_STRUCT__entry( - __field(uint32_t, addr) - __field(size_t, size) - __field(uint32_t, result) - __field(uint32_t, status) - __field(uint32_t, irq_status) - ), + __field(uint32_t, addr) + __field(uint32_t, size) + __field(uint32_t, data) + __field(bool, read) + ), TP_fast_assign( __entry->addr = addr; __entry->size = size; - __entry->result = result; - __entry->status = status; - __entry->irq_status = irq_status; - ), - TP_printk("addr %08x size %zu: result %08x sts: %08x irq_sts: %08x", - __entry->addr, __entry->size, __entry->result, - __entry->status, __entry->irq_status - ) + __entry->data = data; + __entry->read = read; + ), + TP_printk("%s addr %08x size %u data %08x", __entry->read ? "read" : "write", + __entry->addr, __entry->size, __entry->data) ); -TRACE_EVENT(fsi_master_aspeed_opb_write, - TP_PROTO(uint32_t addr, uint32_t val, size_t size, uint32_t status, uint32_t irq_status), - TP_ARGS(addr, val, size, status, irq_status), +TRACE_EVENT(fsi_master_aspeed_timeout, + TP_PROTO(uint32_t irq, uint32_t status, bool read), + TP_ARGS(irq, status, read), TP_STRUCT__entry( - __field(uint32_t, addr) - __field(uint32_t, val) - __field(size_t, size) - __field(uint32_t, status) - __field(uint32_t, irq_status) - ), + __field(uint32_t, irq) + __field(uint32_t, status) + __field(bool, read) + ), TP_fast_assign( - __entry->addr = addr; - __entry->val = val; - __entry->size = size; + __entry->irq = irq; __entry->status = status; - __entry->irq_status = irq_status; - ), - TP_printk("addr %08x val %08x size %zu status: %08x irq_sts: %08x", - __entry->addr, __entry->val, __entry->size, - __entry->status, __entry->irq_status - ) - ); - -TRACE_EVENT(fsi_master_aspeed_opb_error, - TP_PROTO(uint32_t mresp0, uint32_t mstap0, uint32_t mesrb0), - TP_ARGS(mresp0, mstap0, mesrb0), - TP_STRUCT__entry( - __field(uint32_t, mresp0) - __field(uint32_t, mstap0) - __field(uint32_t, mesrb0) - ), - TP_fast_assign( - __entry->mresp0 = mresp0; - __entry->mstap0 = mstap0; - __entry->mesrb0 = mesrb0; - ), - TP_printk("mresp0 %08x mstap0 %08x mesrb0 %08x", - __entry->mresp0, __entry->mstap0, __entry->mesrb0 - ) - ); + __entry->read = read; + ), + TP_printk("%s irq %08x status %08x", __entry->read ? "read" : "write", __entry->irq, + __entry->status) +); TRACE_EVENT(fsi_master_aspeed_cfam_reset, TP_PROTO(bool start), From patchwork Thu May 16 18:18:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797459 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8B00156F5F; Thu, 16 May 2024 18:19:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.158.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715883573; cv=none; b=ChIfhuulAzyyD4oRnAemLomYj+l97qf6O8XLX47nGx/Eax1YboO443EaOkP/x6zL0nN6SYkKx/zzJBKP+FtmAl2J1wf0glwDudU/ca0ypZvG1DKpO1FKlgWBC9Zhd035ePsbsxy9hTtgMOTSt7nGrgwXjHROEWIaZwUsr2d9dPc= ARC-Message-Signature: i=1; a=rsa-sha256; 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Thu, 16 May 2024 18:19:15 GMT Received: from smtprelay06.wdc07v.mail.ibm.com ([172.16.1.73]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3y2m0pkfuj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 May 2024 18:19:15 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay06.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJD7D19202620 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:15 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0082D58056; Thu, 16 May 2024 18:19:13 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B649058052; Thu, 16 May 2024 18:19:12 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:12 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 18/40] fsi: aspeed: Don't clear all IRQs during OPB transfers Date: Thu, 16 May 2024 13:18:45 -0500 Message-Id: <20240516181907.3468796-19-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: u2pDWQQhoxsFKEfFhDC_C6Oq6MKpP5WB X-Proofpoint-GUID: u2pDWQQhoxsFKEfFhDC_C6Oq6MKpP5WB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 clxscore=1015 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 In order to support FSI interrupts, the OPB transfer functions should not clear all the IRQs pending. Instead, just write the OPB ACK bit to the IRQ status register. As commented, this register invisibly masks the interrupt once the interrupt condition is cleared. Fix this by writing 0 before each OPB transfer. Signed-off-by: Eddie James --- drivers/fsi/fsi-master-aspeed.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c index 04aa5cb9b6fad..f840c7c4a56b9 100644 --- a/drivers/fsi/fsi-master-aspeed.c +++ b/drivers/fsi/fsi-master-aspeed.c @@ -47,6 +47,11 @@ static const u32 fsi_base = 0xa0000000; #define OPB_CLK_SYNC 0x3c #define OPB_IRQ_CLEAR 0x40 #define OPB_IRQ_MASK 0x44 +/* + * This register does NOT behave in the expected manner. It is expected that writing 1b would clear + * the corresponding interrupt condition. However it also invisibly masks the interrupt! Writing 0b + * unmasks again. + */ #define OPB_IRQ_STATUS 0x48 #define OPB0_SELECT 0x10 @@ -113,13 +118,14 @@ static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr, writel_relaxed(transfer_size, base + OPB0_XFER_SIZE); writel_relaxed(addr, base + OPB0_FSI_ADDR); writel_relaxed(val, base + OPB0_FSI_DATA_W); - writel_relaxed(0x1, base + OPB_IRQ_CLEAR); + writel_relaxed(0, base + OPB_IRQ_STATUS); writel(0x1, base + OPB_TRIGGER); ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, (reg & OPB0_XFER_ACK_EN) != 0, 0, OPB_POLL_TIMEOUT); + writel(OPB0_XFER_ACK_EN, base + OPB_IRQ_STATUS); status = readl(base + OPB0_STATUS); /* Return error when poll timed out */ @@ -165,13 +171,14 @@ static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr, writel_relaxed(CMD_READ, base + OPB0_RW); writel_relaxed(transfer_size, base + OPB0_XFER_SIZE); writel_relaxed(addr, base + OPB0_FSI_ADDR); - writel_relaxed(0x1, base + OPB_IRQ_CLEAR); + writel_relaxed(0, aspeed->base + OPB_IRQ_STATUS); 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Thu, 16 May 2024 18:19:12 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 19/40] fsi: aspeed: Only read result register for successful read Date: Thu, 16 May 2024 13:18:46 -0500 Message-Id: <20240516181907.3468796-20-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: dseMJk1nsvCJkqP5Ol27olpILNqvAdTi X-Proofpoint-GUID: dseMJk1nsvCJkqP5Ol27olpILNqvAdTi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 clxscore=1015 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 No reason to read the result in the error path, and remove the null pointer check on the output, as it should never be null. Signed-off-by: Eddie James --- drivers/fsi/fsi-master-aspeed.c | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c index f840c7c4a56b9..10ca23cf58c2e 100644 --- a/drivers/fsi/fsi-master-aspeed.c +++ b/drivers/fsi/fsi-master-aspeed.c @@ -181,8 +181,6 @@ static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr, writel(OPB0_XFER_ACK_EN, base + OPB_IRQ_STATUS); status = readl(base + OPB0_STATUS); - result = readl(base + OPB0_FSI_DATA_R); - /* Return error when poll timed out */ if (ret) { trace_fsi_master_aspeed_timeout(reg, status, true); @@ -193,21 +191,20 @@ static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr, if (status & STATUS_ERR_ACK) return -EIO; - if (out) { - switch (transfer_size) { - case XFER_BYTE: - *(u8 *)out = result; - break; - case XFER_HALFWORD: - *(u16 *)out = result; - break; - case XFER_FULLWORD: - *(u32 *)out = result; - break; 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Thu, 16 May 2024 18:19:13 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 22/40] fsi: aspeed: Use common master error handler Date: Thu, 16 May 2024 13:18:49 -0500 Message-Id: <20240516181907.3468796-23-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: mNQb2WIZQn7bcU-F0x82aAhQb5jhTRBU X-Proofpoint-ORIG-GUID: mNQb2WIZQn7bcU-F0x82aAhQb5jhTRBU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 adultscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 This will do the correct mmode manipulation to do the master reset. Signed-off-by: Eddie James --- drivers/fsi/fsi-master-aspeed.c | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c index c9f6d84e1a372..eecd64bc29512 100644 --- a/drivers/fsi/fsi-master-aspeed.c +++ b/drivers/fsi/fsi-master-aspeed.c @@ -226,27 +226,6 @@ static int opb_readb(struct fsi_master_aspeed *aspeed, uint32_t addr, u8 *out) return __opb_read(aspeed, addr, XFER_BYTE, (void *)out); } -static int check_errors(struct fsi_master_aspeed *aspeed, int err) -{ - int ret; - - if (err == -EIO) { - /* Check MAEB (0x70) ? */ - - /* Then clear errors in master */ - ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0, - cpu_to_be32(FSI_MRESP_RST_ALL_MASTER)); - if (ret) { - /* TODO: log? return different code? */ - return ret; - } - /* TODO: confirm that 0x70 was okay */ - } - - /* This will pass through timeout errors */ - return err; -} - static int aspeed_master_read(struct fsi_master *master, int link, uint8_t id, uint32_t addr, void *val, size_t size) { @@ -277,7 +256,8 @@ static int aspeed_master_read(struct fsi_master *master, int link, goto done; } - ret = check_errors(aspeed, ret); + if (ret == -EIO) + fsi_master_error(&aspeed->master, link); done: spin_unlock_irqrestore(&aspeed->lock, flags); return ret; @@ -313,7 +293,8 @@ static int aspeed_master_write(struct fsi_master *master, int link, goto done; } - ret = check_errors(aspeed, ret); + if (ret == -EIO) + fsi_master_error(&aspeed->master, link); done: spin_unlock_irqrestore(&aspeed->lock, flags); return ret; From patchwork Thu May 16 18:18:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797456 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBDEC157492; Thu, 16 May 2024 18:19:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.156.1 ARC-Seal: i=1; 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Thu, 16 May 2024 18:19:14 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 23/40] fsi: core: Add interrupt support Date: Thu, 16 May 2024 13:18:50 -0500 Message-Id: <20240516181907.3468796-24-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: B0drdVEIYzFF3eT6Qfqye_spNtgHk3t_ X-Proofpoint-ORIG-GUID: B0drdVEIYzFF3eT6Qfqye_spNtgHk3t_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 bulkscore=0 adultscore=0 malwarescore=0 spamscore=0 phishscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 Add an irq chip to the FSI master structure to control slave interrupt masking. Add a function to request an IRQ from the FSI device. The FSI master IRQ mapping is based on the FSI device engine type and slave link. Signed-off-by: Eddie James --- Changes since v2: - Remove slave interrupt handler since it's not used yet drivers/fsi/fsi-core.c | 159 +++++++++++++++++++++++++++++++++++++ drivers/fsi/fsi-master.h | 9 +++ include/linux/fsi.h | 2 + include/trace/events/fsi.h | 60 ++++++++++++++ 4 files changed, 230 insertions(+) diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 8b402149acbe9..ae65d87d4b13e 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -14,10 +14,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -109,6 +111,67 @@ int fsi_device_peek(struct fsi_device *dev, void *val) return fsi_slave_read(dev->slave, addr, val, sizeof(uint32_t)); } +EXPORT_SYMBOL_GPL(fsi_device_peek); + +static int fsi_request_irq(struct fsi_slave *slave, irq_handler_t handler, void *data, + unsigned int engine_irq, struct device *dev) +{ + struct device_node *parent = of_node_get(slave->master->dev.of_node); + struct irq_fwspec fwspec; + unsigned int irq; + + /* + * FSI devices can only report interrupts to their own master, so if the master + * isn't an interrupt controller, don't try and map an irq. + */ + if (!of_get_property(parent, "#interrupt-cells", NULL)) { + of_node_put(parent); + return -EINVAL; + } + + fwspec.fwnode = of_node_to_fwnode(parent); + fwspec.param_count = 1; + fwspec.param[0] = engine_irq + (slave->link * FSI_IRQ_COUNT); + irq = irq_create_fwspec_mapping(&fwspec); + if (!irq) + return -EINVAL; + + return devm_request_irq(dev, irq, handler, 0, dev_name(dev), data); +} + +int fsi_device_request_irq(struct fsi_device *dev, irq_handler_t handler, void *data) +{ + unsigned int engine_irq; + + switch (dev->engine_type) { + case 0x4: // shift + engine_irq = 1; + break; + case 0x5: // scom + engine_irq = 2; + break; + case 0x6: // scratchpad + engine_irq = 3; + break; + case 0x7: // i2cm + engine_irq = 4; + break; + case 0x20: // mbox + engine_irq = 7; + break; + case 0x22: // sbefifo + engine_irq = 6; + break; + case 0x23: // spim + engine_irq = 5; + break; + default: + return -EINVAL; + } + + return fsi_request_irq(dev->slave, handler, data, engine_irq, &dev->dev); +} +EXPORT_SYMBOL_GPL(fsi_device_request_irq); unsigned long fsi_device_local_bus_frequency(struct fsi_device *dev) { @@ -1467,6 +1530,99 @@ void fsi_master_regmap_config(struct regmap_config *config) } EXPORT_SYMBOL_GPL(fsi_master_regmap_config); +int fsi_master_irq(struct fsi_master *master, struct irq_domain *irq_domain, unsigned int link) +{ + struct irq_desc *downstream = irq_resolve_mapping(irq_domain, (link * FSI_IRQ_COUNT) + 8); + unsigned long size = FSI_SI1S_SLAVE_BIT + 1; + unsigned long bit = FSI_SI1S_MBOX_BIT; + unsigned long srsis0 = 0; + unsigned long srsis4 = 0; + unsigned long si1s; + __be32 reg; + int rc; + + rc = fsi_master_read(master, link, 0, FSI_SLAVE_BASE + FSI_SI1S, ®, sizeof(reg)); + if (rc) + return rc; + + si1s = (unsigned long)be32_to_cpu(reg); + for_each_set_bit_from(bit, &si1s, size) + generic_handle_domain_irq(irq_domain, (link * FSI_IRQ_COUNT) + (31 - bit)); + + if (downstream) { + int i; + + master->remote_interrupt_status = 0; + + rc = fsi_master_read(master, link, 0, FSI_SLAVE_BASE + FSI_SRSIS0, ®, + sizeof(reg)); + if (rc) + return rc; + + srsis0 = (unsigned long)be32_to_cpu(reg); + for (i = 0; i < 4; ++i) { + if (srsis0 & (0xff000000 >> (8 * i))) + master->remote_interrupt_status |= (1 << i); + } + + rc = fsi_master_read(master, link, 0, FSI_SLAVE_BASE + FSI_SRSIS4, ®, + sizeof(reg)); + if (rc) + return rc; + + srsis4 = (unsigned long)be32_to_cpu(reg); + for (i = 0; i < 4; ++i) { + if (srsis4 & (0xff000000 >> (8 * i))) + master->remote_interrupt_status |= (16 << i); + } + + if (master->remote_interrupt_status) { + handle_irq_desc(downstream); + + reg = cpu_to_be32(0xffffffff); + if (master->remote_interrupt_status & 0xf) + fsi_master_write(master, link, 0, FSI_SLAVE_BASE + FSI_SRSIC0, + ®, sizeof(reg)); + + if (master->remote_interrupt_status & 0xf0) + fsi_master_write(master, link, 0, FSI_SLAVE_BASE + FSI_SRSIC4, + ®, sizeof(reg)); + } + } + + trace_fsi_master_irq(master, link, si1s, srsis0, srsis4); + return 0; +} +EXPORT_SYMBOL_GPL(fsi_master_irq); + +static void fsi_master_irq_mask(struct irq_data *data) +{ + unsigned int bit = 31 - (data->hwirq % FSI_IRQ_COUNT); + + if (bit >= FSI_SI1S_MBOX_BIT) { + struct fsi_master *master = irq_data_get_irq_chip_data(data); + int link = data->hwirq / FSI_IRQ_COUNT; + __be32 mask = cpu_to_be32(BIT(bit)); + + trace_fsi_master_irq_mask(master, link, data->hwirq % FSI_IRQ_COUNT, true); + fsi_master_write(master, link, 0, FSI_SLAVE_BASE + FSI_SCI1M, &mask, sizeof(mask)); + } +} + +static void fsi_master_irq_unmask(struct irq_data *data) +{ + unsigned int bit = 31 - (data->hwirq % FSI_IRQ_COUNT); + + if (bit >= FSI_SI1S_MBOX_BIT) { + struct fsi_master *master = irq_data_get_irq_chip_data(data); + int link = data->hwirq / FSI_IRQ_COUNT; + __be32 mask = cpu_to_be32(BIT(bit)); + + trace_fsi_master_irq_mask(master, link, data->hwirq % FSI_IRQ_COUNT, false); + fsi_master_write(master, link, 0, FSI_SLAVE_BASE + FSI_SSI1M, &mask, sizeof(mask)); + } +} + int fsi_master_register(struct fsi_master *master) { int rc; @@ -1491,6 +1647,9 @@ int fsi_master_register(struct fsi_master *master) if (master->flags & FSI_MASTER_FLAG_SWCLOCK) master->clock_frequency = 100000000; // POWER reference clock + master->irq_chip.name = dev_name(&master->dev); + master->irq_chip.irq_mask = fsi_master_irq_mask; + master->irq_chip.irq_unmask = fsi_master_irq_unmask; master->dev.class = &fsi_master_class; mutex_lock(&master->scan_lock); diff --git a/drivers/fsi/fsi-master.h b/drivers/fsi/fsi-master.h index 8ea2f69ec4922..2104902091e05 100644 --- a/drivers/fsi/fsi-master.h +++ b/drivers/fsi/fsi-master.h @@ -10,6 +10,7 @@ #define DRIVERS_FSI_MASTER_H #include +#include #include /* @@ -112,6 +113,7 @@ /* Misc */ #define FSI_CRC_SIZE 4 #define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */ +#define FSI_IRQ_COUNT 9 /* fsi-master definition and flags */ #define FSI_MASTER_FLAG_SWCLOCK 0x1 @@ -137,6 +139,7 @@ struct fsi_master { int n_links; int flags; struct mutex scan_lock; + struct irq_chip irq_chip; int (*read)(struct fsi_master *, int link, uint8_t id, uint32_t addr, void *val, size_t size); int (*write)(struct fsi_master *, int link, uint8_t id, @@ -147,6 +150,7 @@ struct fsi_master { bool enable); int (*link_config)(struct fsi_master *, int link, u8 t_send_delay, u8 t_echo_delay); + u8 remote_interrupt_status; }; #define to_fsi_master(d) container_of(d, struct fsi_master, dev) @@ -176,4 +180,9 @@ extern void fsi_master_unregister(struct fsi_master *master); extern int fsi_master_rescan(struct fsi_master *master); +struct irq_domain; + +extern int fsi_master_irq(struct fsi_master *master, struct irq_domain *irq_domain, + unsigned int link); + #endif /* DRIVERS_FSI_MASTER_H */ diff --git a/include/linux/fsi.h b/include/linux/fsi.h index e0309bf0ae072..c249a95b7ff84 100644 --- a/include/linux/fsi.h +++ b/include/linux/fsi.h @@ -8,6 +8,7 @@ #define LINUX_FSI_H #include +#include struct fsi_device { struct device dev; @@ -25,6 +26,7 @@ extern int fsi_device_write(struct fsi_device *dev, uint32_t addr, const void *val, size_t size); extern int fsi_device_peek(struct fsi_device *dev, void *val); extern unsigned long fsi_device_local_bus_frequency(struct fsi_device *dev); +extern int fsi_device_request_irq(struct fsi_device *dev, irq_handler_t handler, void *data); struct fsi_device_id { u8 engine_type; diff --git a/include/trace/events/fsi.h b/include/trace/events/fsi.h index da977d59e163e..0e4d717ee0adb 100644 --- a/include/trace/events/fsi.h +++ b/include/trace/events/fsi.h @@ -8,6 +8,47 @@ #include +TRACE_EVENT(fsi_master_irq, + TP_PROTO(const struct fsi_master *master, unsigned int link, uint32_t si1s, + uint32_t srsis0, uint32_t srsis4), + TP_ARGS(master, link, si1s, srsis0, srsis4), + TP_STRUCT__entry( + __field(int, master_idx) + __field(unsigned int, link) + __field(uint32_t, si1s) + __field(uint32_t, srsis0) + __field(uint32_t, srsis4) + ), + TP_fast_assign( + __entry->master_idx = master->idx; + __entry->link = link; + __entry->si1s = si1s; + __entry->srsis0 = srsis0; + __entry->srsis4 = srsis4; + ), + TP_printk("fsi%d:%02d si1s:%08x srsis0:%08x srsis4:%08x", __entry->master_idx, + __entry->link, __entry->si1s, __entry->srsis0, __entry->srsis4) +); + +TRACE_EVENT(fsi_master_irq_mask, + TP_PROTO(const struct fsi_master *master, unsigned int link, unsigned int bit, bool mask), + TP_ARGS(master, link, bit, mask), + TP_STRUCT__entry( + __field(int, master_idx) + __field(unsigned int, link) + __field(unsigned int, bit) + __field(bool, mask) + ), + TP_fast_assign( + __entry->master_idx = master->idx; + __entry->link = link; + __entry->bit = bit; + __entry->mask = mask; + ), + TP_printk("fsi%d:%02d %s bit:%d", __entry->master_idx, __entry->link, + __entry->mask ? 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Signed-off-by: Eddie James --- drivers/fsi/fsi-master-aspeed.c | 106 ++++++++++++++++++++++- include/trace/events/fsi_master_aspeed.h | 12 +++ 2 files changed, 115 insertions(+), 3 deletions(-) diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c index eecd64bc29512..34f4c9e00e43d 100644 --- a/drivers/fsi/fsi-master-aspeed.c +++ b/drivers/fsi/fsi-master-aspeed.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include #include #include @@ -25,11 +27,13 @@ struct fsi_master_aspeed_data { struct fsi_master_aspeed { struct fsi_master master; spinlock_t lock; /* protect HW access */ + struct irq_domain *irq_domain; struct device *dev; void __iomem *base; void __iomem *ctrl; struct clk *clk; struct gpio_desc *cfam_reset_gpio; + u32 irq_mask; }; #define to_fsi_master_aspeed(m) \ @@ -79,6 +83,11 @@ static const u32 fsi_base = 0xa0000000; #define STATUS_TIMEOUT BIT(4) /* OPB_IRQ_MASK */ +#define FSI_MASTER_ERROR_IRQ BIT(28) +#define FSI_PORT_ERROR_IRQ BIT(27) +#define FSI_HOTPLUG_IRQ BIT(26) +#define FSI_REMOTE_SLV_IRQ(l) (BIT(FSI_REMOTE_SLV_IRQ_BIT) << (l)) +#define FSI_REMOTE_SLV_IRQ_BIT 18 #define OPB1_XFER_ACK_EN BIT(17) #define OPB0_XFER_ACK_EN BIT(16) @@ -96,7 +105,7 @@ static const u32 fsi_base = 0xa0000000; #define OPB_RC_CTRL_OPB BIT(18) /* Access controller over OPB, not AHB (AST27xx+) */ #define OPB_RC_XFER_ACK_EN BIT(16) /* Enable OPBx xfer ack bit without mask */ #define OPB_RC_COUNT GENMASK(15, 0) /* Number of retries */ -#define OPB_RC_DEFAULT 0x10 +#define OPB_RC_DEFAULT (OPB_RC_XFER_ACK_EN | 0x10) #define CREATE_TRACE_POINTS #include @@ -322,11 +331,76 @@ static int aspeed_master_break(struct fsi_master *master, int link) return aspeed_master_write(master, link, 0, addr, &cmd, 4); } +static int aspeed_master_link_enable(struct fsi_master *master, int link, bool enable) +{ + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); + unsigned long flags; + int rc; + + spin_lock_irqsave(&aspeed->lock, flags); + if (enable) { + rc = fsi_master_link_enable(master, link, enable); + if (rc) + goto done; + + aspeed->irq_mask |= FSI_REMOTE_SLV_IRQ(link); + writel(aspeed->irq_mask, aspeed->base + OPB_IRQ_MASK); + } else { + aspeed->irq_mask &= ~FSI_REMOTE_SLV_IRQ(link); + writel(aspeed->irq_mask, aspeed->base + OPB_IRQ_MASK); + + rc = fsi_master_link_enable(master, link, enable); + } + +done: + spin_unlock_irqrestore(&aspeed->lock, flags); + return rc; +} + +static irqreturn_t aspeed_master_irq(int irq, void *data) +{ + struct fsi_master_aspeed *aspeed = data; + unsigned long size = FSI_REMOTE_SLV_IRQ_BIT + aspeed->master.n_links; + unsigned long bit = FSI_REMOTE_SLV_IRQ_BIT; + unsigned long status; + + status = readl(aspeed->base + OPB_IRQ_STATUS); + writel(0, aspeed->base + OPB_IRQ_MASK); + + for_each_set_bit_from(bit, &status, size) + fsi_master_irq(&aspeed->master, aspeed->irq_domain, bit - FSI_REMOTE_SLV_IRQ_BIT); + + writel(status, aspeed->base + OPB_IRQ_STATUS); + writel(0, aspeed->base + OPB_IRQ_STATUS); + writel(aspeed->irq_mask, aspeed->base + OPB_IRQ_MASK); + + trace_fsi_master_aspeed_irq(status); + return IRQ_HANDLED; +} + +static int aspeed_master_irqd_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct fsi_master_aspeed *aspeed = domain->host_data; + + irq_set_chip_and_handler(irq, &aspeed->master.irq_chip, handle_simple_irq); + irq_set_chip_data(irq, &aspeed->master); + + return 0; +} + +static const struct irq_domain_ops aspeed_master_irq_domain_ops = { + .map = aspeed_master_irqd_map, +}; + static void aspeed_master_release(struct device *dev) { struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(to_fsi_master(dev)); + if (aspeed->irq_domain) + irq_domain_remove(aspeed->irq_domain); + regmap_exit(aspeed->master.map); kfree(aspeed); } @@ -477,6 +551,7 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev) struct resource *res; unsigned int reg; int rc, links; + int irq; rc = tacoma_cabled_fsi_fixup(&pdev->dev); if (rc) { @@ -567,11 +642,12 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev) aspeed->master.dev.of_node = of_node_get(dev_of_node(&pdev->dev)); aspeed->master.n_links = links; - aspeed->master.flags = FSI_MASTER_FLAG_RELA; + aspeed->master.flags = FSI_MASTER_FLAG_INTERRUPT | FSI_MASTER_FLAG_RELA; aspeed->master.read = aspeed_master_read; aspeed->master.write = aspeed_master_write; aspeed->master.send_break = aspeed_master_break; aspeed->master.term = aspeed_master_term; + aspeed->master.link_enable = aspeed_master_link_enable; dev_set_drvdata(&pdev->dev, aspeed); @@ -579,9 +655,30 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev) if (rc) goto err_regmap; + irq = platform_get_irq(pdev, 0); + if (irq > 0) { + unsigned int size = links * FSI_IRQ_COUNT; + + aspeed->irq_domain = irq_domain_add_linear(aspeed->dev->of_node, size, + &aspeed_master_irq_domain_ops, aspeed); + if (aspeed->irq_domain) { + rc = devm_request_irq(aspeed->dev, irq, aspeed_master_irq, 0, + dev_name(aspeed->dev), aspeed); + if (rc) { + dev_warn(aspeed->dev, "failed to request irq:%d\n", irq); + irq_domain_remove(aspeed->irq_domain); + aspeed->irq_domain = NULL; + } else { + dev_info(aspeed->dev, "enabling interrupts irq:%d\n", irq); + } + } else { + dev_warn(aspeed->dev, "failed to create irq domain\n"); + } + } + rc = fsi_master_register(&aspeed->master); if (rc) - goto err_regmap; + goto err_irq; /* At this point, fsi_master_register performs the device_initialize(), * and holds the sole reference on master.dev. This means the device @@ -593,6 +690,9 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev) get_device(&aspeed->master.dev); return 0; +err_irq: + if (aspeed->irq_domain) + irq_domain_remove(aspeed->irq_domain); err_regmap: regmap_exit(aspeed->master.map); err_release: diff --git a/include/trace/events/fsi_master_aspeed.h b/include/trace/events/fsi_master_aspeed.h index 7eeecbfec7f09..dba1776334a0e 100644 --- a/include/trace/events/fsi_master_aspeed.h +++ b/include/trace/events/fsi_master_aspeed.h @@ -8,6 +8,18 @@ #include +TRACE_EVENT(fsi_master_aspeed_irq, + TP_PROTO(uint32_t status), + TP_ARGS(status), + TP_STRUCT__entry( + __field(uint32_t, status) + ), + TP_fast_assign( + __entry->status = status; + ), + TP_printk("status %08x", __entry->status) +); + TRACE_EVENT(fsi_master_aspeed_opb_xfer, TP_PROTO(uint32_t addr, uint32_t size, uint32_t data, bool read), TP_ARGS(addr, size, data, read), From patchwork Thu May 16 18:18:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797444 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3935161302; 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Thu, 16 May 2024 18:19:14 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 25/40] fsi: hub: Add interrupt support Date: Thu, 16 May 2024 13:18:52 -0500 Message-Id: <20240516181907.3468796-26-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Xxr-s5lPq7S7aX6RkbSaXYiYCaLde0WE X-Proofpoint-ORIG-GUID: Xxr-s5lPq7S7aX6RkbSaXYiYCaLde0WE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=796 phishscore=0 adultscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 The hub master receives it's interrupts from the local slave register space, which is handled in the FSI core. Therefore, just route the remote slave interrupts to the hub link device interrupts. Signed-off-by: Eddie James --- drivers/fsi/fsi-master-hub.c | 119 ++++++++++++++++++++++++++++++++++- 1 file changed, 116 insertions(+), 3 deletions(-) diff --git a/drivers/fsi/fsi-master-hub.c b/drivers/fsi/fsi-master-hub.c index 91ad6b7728fa2..4dbc542500bbd 100644 --- a/drivers/fsi/fsi-master-hub.c +++ b/drivers/fsi/fsi-master-hub.c @@ -7,8 +7,10 @@ #include #include +#include #include #include +#include #include #include @@ -35,9 +37,10 @@ */ struct fsi_master_hub { struct fsi_master master; + struct irq_domain *irq_domain; struct fsi_device *upstream; - uint32_t addr, size; /* slave-relative addr of */ - /* master address space */ + uint32_t addr; + uint32_t size; }; #define to_fsi_master_hub(m) container_of(m, struct fsi_master_hub, master) @@ -77,10 +80,81 @@ static int hub_master_break(struct fsi_master *master, int link) return hub_master_write(master, link, 0, addr, &cmd, sizeof(cmd)); } +static int hub_master_link_enable(struct fsi_master *master, int link, + bool enable) +{ + struct fsi_master_hub *hub = to_fsi_master_hub(master); + u32 srsim = 0xff000000 >> (8 * (link % 4)); + int slave_idx = 4 * (link / 4); + __be32 srsim_be; + int ret; + + ret = fsi_slave_read(hub->upstream->slave, FSI_SLAVE_BASE + FSI_SRSIM0 + slave_idx, + &srsim_be, sizeof(srsim_be)); + if (ret) + return ret; + + if (enable) { + ret = fsi_master_link_enable(master, link, enable); + if (ret) + return ret; + + srsim |= be32_to_cpu(srsim_be); + srsim_be = cpu_to_be32(srsim); + ret = fsi_slave_write(hub->upstream->slave, + FSI_SLAVE_BASE + FSI_SRSIM0 + slave_idx, &srsim_be, + sizeof(srsim_be)); + } else { + srsim = be32_to_cpu(srsim_be) & ~srsim; + srsim_be = cpu_to_be32(srsim); + ret = fsi_slave_write(hub->upstream->slave, + FSI_SLAVE_BASE + FSI_SRSIM0 + slave_idx, &srsim_be, + sizeof(srsim_be)); + if (ret) + return ret; + + ret = fsi_master_link_enable(master, link, enable); + } + + return ret; +} + +static irqreturn_t hub_master_irq(int irq, void *data) +{ + struct fsi_master_hub *hub = data; + struct fsi_master *parent = hub->upstream->slave->master; + unsigned int link = 0; + + for (; link < FSI_HUB_MASTER_MAX_LINKS; ++link) { + if (parent->remote_interrupt_status & (1 << link)) + fsi_master_irq(&hub->master, hub->irq_domain, link); + } + + return IRQ_HANDLED; +} + +static int hub_master_irqd_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct fsi_master_hub *hub = domain->host_data; + + irq_set_chip_and_handler(irq, &hub->master.irq_chip, handle_simple_irq); + irq_set_chip_data(irq, &hub->master); + + return 0; +} + +static const struct irq_domain_ops hub_master_irq_domain_ops = { + .map = hub_master_irqd_map, +}; + static void hub_master_release(struct device *dev) { struct fsi_master_hub *hub = to_fsi_master_hub(to_fsi_master(dev)); + if (hub->irq_domain) + irq_domain_remove(hub->irq_domain); + regmap_exit(hub->master.map); kfree(hub); } @@ -135,6 +209,7 @@ static int hub_master_probe(struct device *dev) hub->master.read = hub_master_read; hub->master.write = hub_master_write; hub->master.send_break = hub_master_break; + hub->master.link_enable = hub_master_link_enable; dev_set_drvdata(dev, hub); @@ -142,9 +217,44 @@ static int hub_master_probe(struct device *dev) if (rc) goto err_free; + if (of_property_read_bool(dev->of_node, "interrupt-controller")) { + struct device_node *parent = of_irq_find_parent(dev->of_node); + + if (parent) { + struct irq_fwspec fwspec; + unsigned int irq; + + fwspec.fwnode = of_node_to_fwnode(parent); + fwspec.param_count = 1; + fwspec.param[0] = (fsi_dev->slave->link * FSI_IRQ_COUNT) + 8; + irq = irq_create_fwspec_mapping(&fwspec); + if (irq) { + unsigned int size = links * FSI_IRQ_COUNT; + + hub->irq_domain = irq_domain_add_linear(dev->of_node, size, + &hub_master_irq_domain_ops, + hub); + + if (hub->irq_domain) { + rc = devm_request_irq(dev, irq, hub_master_irq, 0, + dev_name(dev), hub); + if (rc) { + dev_warn(dev, "failed to request irq:%u\n", irq); + irq_domain_remove(hub->irq_domain); + hub->irq_domain = NULL; + } else { + dev_info(dev, "enabling interrupts irq:%u\n", irq); + } + } else { + dev_warn(dev, "failed to create irq domain\n"); + } + } + } + } + rc = fsi_master_register(&hub->master); if (rc) - goto err_free; + goto err_irq; /* At this point, fsi_master_register performs the device_initialize(), * and holds the sole reference on master.dev. This means the device @@ -156,6 +266,9 @@ static int hub_master_probe(struct device *dev) get_device(&hub->master.dev); return 0; +err_irq: + if (hub->irq_domain) + irq_domain_remove(hub->irq_domain); err_free: kfree(hub); err_release: From patchwork Thu May 16 18:18:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797458 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68936157488; Thu, 16 May 2024 18:19:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715883574; cv=none; b=D06XNKHEctug7xfBjhocgWer64nlU/lac06vrMbeRfqE5AoYdGcqjt65iO/EsDKSfHsXdqe/rfNM1ZjAxCzHnizqcPMWxeqHjdriIecQWbNd9RXOBRcodcnacJj5+k1zIpUtTCzahEpdTpAKeVdwpoaFbrTa2Iv3aLu+g77ZXU8= ARC-Message-Signature: i=1; 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Thu, 16 May 2024 18:19:19 GMT Received: from smtprelay07.dal12v.mail.ibm.com ([172.16.1.9]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3y2mgmud39-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 May 2024 18:19:19 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay07.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJGA542140022 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:18 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C90C858078; Thu, 16 May 2024 18:19:16 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8AD6858080; Thu, 16 May 2024 18:19:16 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:16 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 31/40] i2c: fsi: Add boolean for skip stop command on abort Date: Thu, 16 May 2024 13:18:58 -0500 Message-Id: <20240516181907.3468796-32-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: HC54uwD7Go1XxXnYpXpr9t0lMi06jJCP X-Proofpoint-ORIG-GUID: HC54uwD7Go1XxXnYpXpr9t0lMi06jJCP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 In preparation for interrupt support, store whether to skip the final stop command during the abort procedure instead of checking the previously read status register in the abort function. Signed-off-by: Eddie James --- drivers/i2c/busses/i2c-fsi.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/busses/i2c-fsi.c b/drivers/i2c/busses/i2c-fsi.c index 022f1287aa0e3..614d830419bb8 100644 --- a/drivers/i2c/busses/i2c-fsi.c +++ b/drivers/i2c/busses/i2c-fsi.c @@ -116,6 +116,9 @@ #define I2C_STAT_ANY_RESP (I2C_STAT_ERR | \ I2C_STAT_DAT_REQ | \ I2C_STAT_CMD_COMP) +#define I2C_STAT_SKIP_STOP (I2C_STAT_PARITY | \ + I2C_STAT_LOST_ARB | \ + I2C_STAT_STOP_ERR) /* extended status register */ #define I2C_ESTAT_FIFO_SZ GENMASK(31, 24) @@ -150,6 +153,7 @@ struct fsi_i2c_master { struct mutex lock; u32 clock_div; u8 fifo_size; + bool skip_stop; }; struct fsi_i2c_port { @@ -459,31 +463,30 @@ static int fsi_i2c_reset_engine(struct fsi_i2c_master *i2c, u16 port) return 0; } -static int fsi_i2c_abort(struct fsi_i2c_port *port, u32 status) +static int fsi_i2c_abort(struct fsi_i2c_port *port) { struct fsi_i2c_master *i2c = port->master; u32 cmd = I2C_CMD_WITH_STOP; unsigned long start; - u32 stat; + u32 status; int rc; rc = fsi_i2c_reset_engine(i2c, port->port); if (rc) return rc; - rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &stat); + rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &status); if (rc) return rc; /* if sda is low, peform full bus reset */ - if (!(stat & I2C_STAT_SDA_IN)) { + if (!(status & I2C_STAT_SDA_IN)) { rc = fsi_i2c_reset_bus(i2c, port); if (rc) return rc; } - /* skip final stop command for these errors */ - if (status & (I2C_STAT_PARITY | I2C_STAT_LOST_ARB | I2C_STAT_STOP_ERR)) + if (i2c->skip_stop) return 0; /* write stop command */ @@ -534,7 +537,8 @@ static int fsi_i2c_handle_status(struct fsi_i2c_port *port, int rc; if (status & I2C_STAT_ERR) { - rc = fsi_i2c_abort(port, status); + port->master->skip_stop = status & I2C_STAT_SKIP_STOP; + rc = fsi_i2c_abort(port); if (rc) return rc; From patchwork Thu May 16 18:18:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797450 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA86F158A18; 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Thu, 16 May 2024 18:19:16 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 32/40] i2c: fsi: Add interrupt support Date: Thu, 16 May 2024 13:18:59 -0500 Message-Id: <20240516181907.3468796-33-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: e3iekewMegtYRprZq0GSTS1xnVyEoHSL X-Proofpoint-GUID: e3iekewMegtYRprZq0GSTS1xnVyEoHSL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 Optionally support interrupts from the I2C controller so that the driver can wait rather than poll the status register. Signed-off-by: Eddie James --- drivers/i2c/busses/i2c-fsi.c | 215 ++++++++++++++++++++++++++++++--- include/trace/events/i2c_fsi.h | 45 +++++++ 2 files changed, 245 insertions(+), 15 deletions(-) create mode 100644 include/trace/events/i2c_fsi.h diff --git a/drivers/i2c/busses/i2c-fsi.c b/drivers/i2c/busses/i2c-fsi.c index 614d830419bb8..f8d9bc178ef5b 100644 --- a/drivers/i2c/busses/i2c-fsi.c +++ b/drivers/i2c/busses/i2c-fsi.c @@ -23,6 +23,7 @@ #include #include #include +#include #define FSI_ENGID_I2C 0x7 @@ -87,6 +88,7 @@ #define I2C_INT_STOP_ERR BIT(7) #define I2C_INT_BUSY BIT(6) #define I2C_INT_IDLE BIT(5) +#define I2C_INT_ANY GENMASK(15, 7) /* status register */ #define I2C_STAT_INV_CMD BIT(31) @@ -148,21 +150,35 @@ /* choose timeout length from legacy driver; it's well tested */ #define I2C_ABORT_TIMEOUT msecs_to_jiffies(100) +struct fsi_i2c_port; + struct fsi_i2c_master { struct fsi_device *fsi; + struct fsi_i2c_port *port; struct mutex lock; + wait_queue_head_t wait; u32 clock_div; u8 fifo_size; + bool interrupts; bool skip_stop; + bool abort; }; struct fsi_i2c_port { struct i2c_adapter adapter; struct fsi_i2c_master *master; + struct i2c_msg *msgs; + int nmsgs; + int rc; + int i; u16 port; u16 xfrd; + bool wake; }; +#define CREATE_TRACE_POINTS +#include + static int fsi_i2c_read_reg(struct fsi_device *fsi, unsigned int reg, u32 *data) { @@ -192,7 +208,7 @@ static int fsi_i2c_dev_init(struct fsi_i2c_master *i2c) u32 watermark; int rc; - /* since we use polling, disable interrupts */ + /* start with interrupts disabled */ rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, 0); if (rc) return rc; @@ -236,22 +252,24 @@ static int fsi_i2c_set_port(struct fsi_i2c_port *port) return fsi_i2c_write_reg(fsi, I2C_FSI_RESET_ERR, 0); } -static int fsi_i2c_start(struct fsi_i2c_port *port, struct i2c_msg *msg, - bool stop) +static int fsi_i2c_start(struct fsi_i2c_port *port) { u32 cmd = I2C_CMD_WITH_START | I2C_CMD_WITH_ADDR; + struct i2c_msg *msg = &port->msgs[port->i]; port->xfrd = 0; if (msg->flags & I2C_M_RD) cmd |= I2C_CMD_READ; - if (stop || msg->flags & I2C_M_STOP) + if ((port->i == (port->nmsgs - 1)) || (msg->flags & I2C_M_STOP)) cmd |= I2C_CMD_WITH_STOP; cmd |= FIELD_PREP(I2C_CMD_ADDR, msg->addr); cmd |= FIELD_PREP(I2C_CMD_LEN, msg->len); + trace_i2c_fsi_start(port, cmd); + return fsi_i2c_write_reg(port->master->fsi, I2C_FSI_CMD, cmd); } @@ -489,11 +507,38 @@ static int fsi_i2c_abort(struct fsi_i2c_port *port) if (i2c->skip_stop) return 0; + if (i2c->interrupts) { + i2c->abort = true; + port->wake = false; + + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, I2C_INT_ANY); + if (rc) + return rc; + } + /* write stop command */ rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_CMD, cmd); if (rc) return rc; + if (i2c->interrupts) { + rc = wait_event_interruptible_timeout(i2c->wait, port->wake, I2C_ABORT_TIMEOUT); + if (rc > 0) + return port->rc; + + fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, 0); + + if (!rc) { + rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &status); + if (!rc && (status & I2C_STAT_CMD_COMP)) + rc = 0; + else + rc = -ETIMEDOUT; + } + + return rc; + } + /* wait until we see command complete in the master */ start = jiffies; do { @@ -564,8 +609,59 @@ static int fsi_i2c_handle_status(struct fsi_i2c_port *port, return 0; } -static int fsi_i2c_wait(struct fsi_i2c_port *port, struct i2c_msg *msg, - unsigned long timeout) +static int fsi_i2c_wait_irq(struct fsi_i2c_port *port, unsigned long timeout) +{ + int rc; + + port->wake = false; + + rc = fsi_i2c_write_reg(port->master->fsi, I2C_FSI_INT_MASK, I2C_INT_ANY); + if (rc) + return rc; + + rc = wait_event_interruptible_timeout(port->master->wait, port->wake, timeout); + if (rc > 0) { + rc = port->rc; + + if (port->master->abort) { + int rc2 = fsi_i2c_abort(port); + + if (rc2) + return rc2; + } + + return rc; + } + + /* + * The interrupt handler should turn off interrupts once it's done, but in this + * case we timed out or were interrupted, so mask them off here. + */ + fsi_i2c_write_reg(port->master->fsi, I2C_FSI_INT_MASK, 0); + + if (!rc) { + u32 status; + + rc = fsi_i2c_read_reg(port->master->fsi, I2C_FSI_STAT, &status); + if (!rc && (status & I2C_STAT_ANY_RESP)) { + rc = fsi_i2c_handle_status(port, &port->msgs[port->i], status); + if (rc < 0) + return rc; + + /* cmd complete and all data xfrd */ + if (rc == port->msgs[port->i].len) + return 0; + + rc = -ETIMEDOUT; + } else { + rc = -ETIMEDOUT; + } + } + + return rc; +} + +static int fsi_i2c_wait_poll(struct fsi_i2c_port *port, unsigned long timeout) { unsigned long start = jiffies; u32 status; @@ -578,12 +674,12 @@ static int fsi_i2c_wait(struct fsi_i2c_port *port, struct i2c_msg *msg, return rc; if (status & I2C_STAT_ANY_RESP) { - rc = fsi_i2c_handle_status(port, msg, status); + rc = fsi_i2c_handle_status(port, &port->msgs[port->i], status); if (rc < 0) return rc; /* cmd complete and all data xfrd */ - if (rc == msg->len) + if (rc == port->msgs[port->i].len) return 0; /* need to xfr more data, but maybe don't need wait */ @@ -601,9 +697,7 @@ static int fsi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, { struct fsi_i2c_port *port = i2c_get_adapdata(adap); unsigned long start_time; - struct i2c_msg *msg; int rc; - int i; mutex_lock(&port->master->lock); @@ -611,21 +705,28 @@ static int fsi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, if (rc) goto unlock; - for (i = 0; i < num; i++) { - msg = msgs + i; + port->master->port = port; + port->master->abort = false; + port->msgs = msgs; + port->nmsgs = num; + for (port->i = 0; port->i < num; ++port->i) { start_time = jiffies; - rc = fsi_i2c_start(port, msg, i == num - 1); + rc = fsi_i2c_start(port); if (rc) goto unlock; - rc = fsi_i2c_wait(port, msg, - adap->timeout - (jiffies - start_time)); + if (port->master->interrupts) + rc = fsi_i2c_wait_irq(port, adap->timeout - (jiffies - start_time)); + else + rc = fsi_i2c_wait_poll(port, adap->timeout - (jiffies - start_time)); if (rc) goto unlock; } unlock: + port->msgs = NULL; + port->master->port = NULL; mutex_unlock(&port->master->lock); return rc ? : num; } @@ -636,6 +737,85 @@ static u32 fsi_i2c_functionality(struct i2c_adapter *adap) I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; } +static irqreturn_t fsi_i2c_irq(int irq, void *data) +{ + struct fsi_i2c_master *i2c = data; + struct fsi_i2c_port *port; + struct i2c_msg *msg; + u32 status; + int rc; + + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, 0); + if (rc) + return IRQ_NONE; + + if (!i2c->port) + return IRQ_HANDLED; + + port = i2c->port; + rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &status); + if (rc) + goto wake; + + trace_i2c_fsi_irq(port, status); + + if (i2c->abort) { + if (status & I2C_STAT_CMD_COMP) { + port->wake = true; + goto done; + } else { + rc = fsi_i2c_error_status_to_rc(status); + goto wake; + } + } + + if (status & I2C_STAT_ERR) { + i2c->abort = true; + i2c->skip_stop = status & I2C_STAT_SKIP_STOP; + rc = fsi_i2c_error_status_to_rc(status); + goto wake; + } + + if (!port->msgs || port->i >= port->nmsgs) { + rc = -ENODEV; + goto wake; + } + + msg = &port->msgs[port->i]; + if (status & I2C_STAT_DAT_REQ) { + u8 fifo_count = FIELD_GET(I2C_STAT_FIFO_COUNT, status); + + if (msg->flags & I2C_M_RD) + rc = fsi_i2c_read_fifo(port, msg, fifo_count); + else + rc = fsi_i2c_write_fifo(port, msg, fifo_count); + } else if (status & I2C_STAT_CMD_COMP) { + if (port->xfrd < msg->len) { + rc = -ENODATA; + } else { + ++port->i; + if (port->i < port->nmsgs) { + rc = fsi_i2c_start(port); + } else { + port->wake = true; + goto done; + } + } + } + + if (!rc) + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, I2C_INT_ANY); + +wake: + if (rc) + port->wake = true; +done: + port->rc = rc; + if (port->wake) + wake_up_interruptible_all(&i2c->wait); + return IRQ_HANDLED; +} + static struct i2c_bus_recovery_info fsi_i2c_bus_recovery_info = { .recover_bus = i2c_generic_scl_recovery, .get_scl = fsi_i2c_get_scl, @@ -683,6 +863,7 @@ static int fsi_i2c_probe(struct device *dev) return -ENOMEM; mutex_init(&i2c->lock); + init_waitqueue_head(&i2c->wait); i2c->fsi = to_fsi_dev(dev); i2c->clock_div = I2C_DEFAULT_CLK_DIV; @@ -706,6 +887,10 @@ static int fsi_i2c_probe(struct device *dev) if (rc) return rc; + rc = fsi_device_request_irq(i2c->fsi, fsi_i2c_irq, i2c); + if (!rc) + i2c->interrupts = true; + ports = FIELD_GET(I2C_STAT_MAX_PORT, stat) + 1; dev_dbg(dev, "I2C master has %d ports\n", ports); diff --git a/include/trace/events/i2c_fsi.h b/include/trace/events/i2c_fsi.h new file mode 100644 index 0000000000000..ac49ae9be356b --- /dev/null +++ b/include/trace/events/i2c_fsi.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM i2c_fsi + +#if !defined(_TRACE_I2C_FSI_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_I2C_FSI_H + +#include + +TRACE_EVENT(i2c_fsi_irq, + TP_PROTO(const struct fsi_i2c_port *port, uint32_t status), + TP_ARGS(port, status), + TP_STRUCT__entry( + __field(int, bus) + __field(int, msg_idx) + __field(uint32_t, status) + ), + TP_fast_assign( + __entry->bus = port->adapter.nr; + __entry->msg_idx = port->i; + __entry->status = status; + ), + TP_printk("i2c-%d [%d] status:%08x", __entry->bus, __entry->msg_idx, __entry->status) +); + +TRACE_EVENT(i2c_fsi_start, + TP_PROTO(const struct fsi_i2c_port *port, uint32_t command), + TP_ARGS(port, command), + TP_STRUCT__entry( + __field(int, bus) + __field(int, msg_idx) + __field(uint32_t, command) + ), + TP_fast_assign( + __entry->bus = port->adapter.nr; + __entry->msg_idx = port->i; + __entry->command = command; + ), + TP_printk("i2c-%d [%d] command:%08x", __entry->bus, __entry->msg_idx, __entry->command) +); + +#endif + +#include From patchwork Thu May 16 18:19:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797445 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4E3515F41F; Thu, 16 May 2024 18:19:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.158.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715883593; cv=none; b=gTU2b5Z1iqg0875QzynK4GASL3BoMOKc9RDHmL4Zj50YP+raUamN5JRMPPprLx0oijG/eTUtTPhGcFHizen0qmYojVsrH9wzBEDx5epfetykASrH/8fvoxCvaDpgZzrzQyG81AYWsgcN5fAefTePPyfMWHTuxVQ04e0ELqy1tP0= ARC-Message-Signature: i=1; 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Thu, 16 May 2024 18:19:20 GMT Received: from smtprelay01.wdc07v.mail.ibm.com ([172.16.1.68]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3y2m0pkfus-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 May 2024 18:19:20 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay01.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJHn539846334 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:19 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 66EB15806F; Thu, 16 May 2024 18:19:17 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 28F375806A; Thu, 16 May 2024 18:19:17 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:17 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 33/40] fsi: hub master: Reset hub master after errors Date: Thu, 16 May 2024 13:19:00 -0500 Message-Id: <20240516181907.3468796-34-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 7q38jETbYYQUbopbcmLQUqSA_hw5T1g_ X-Proofpoint-ORIG-GUID: 7q38jETbYYQUbopbcmLQUqSA_hw5T1g_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 adultscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 The hub master driver wasn't clearing errors after accessing remote slaves. Perform the standard master reset procedure to clear errors to fully recover. Signed-off-by: Eddie James --- drivers/fsi/fsi-master-hub.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/fsi/fsi-master-hub.c b/drivers/fsi/fsi-master-hub.c index 4dbc542500bbd..1bd53b1e52a91 100644 --- a/drivers/fsi/fsi-master-hub.c +++ b/drivers/fsi/fsi-master-hub.c @@ -49,24 +49,34 @@ static int hub_master_read(struct fsi_master *master, int link, uint8_t id, uint32_t addr, void *val, size_t size) { struct fsi_master_hub *hub = to_fsi_master_hub(master); + int rc; if (id != 0) return -EINVAL; addr += hub->addr + (link * FSI_HUB_LINK_SIZE); - return fsi_slave_read(hub->upstream->slave, addr, val, size); + rc = fsi_slave_read(hub->upstream->slave, addr, val, size); + if (rc) + fsi_master_error(master, link); + + return rc; } static int hub_master_write(struct fsi_master *master, int link, uint8_t id, uint32_t addr, const void *val, size_t size) { struct fsi_master_hub *hub = to_fsi_master_hub(master); + int rc; if (id != 0) return -EINVAL; addr += hub->addr + (link * FSI_HUB_LINK_SIZE); - return fsi_slave_write(hub->upstream->slave, addr, val, size); + rc = fsi_slave_write(hub->upstream->slave, addr, val, size); + if (rc) + fsi_master_error(master, link); + + return rc; } static int hub_master_break(struct fsi_master *master, int link) From patchwork Thu May 16 18:19:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797452 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD8B6158847; Thu, 16 May 2024 18:19:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715883577; cv=none; b=oK3lXqWC0kERL1OuFAubueDY5eVpzslANmz87UWiQp6fBuNbuIIRW/MkX4lGSWD2UaeJH6kIC50rqn37JmLZlua7tjQ5XcKjZ1xXUOBLDRXS7xJNdGojjGkCQDmcVeNhudyMvPFreP9BblOrbZBkye58NIuIIV4uff4i/eFtsWc= ARC-Message-Signature: i=1; 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Thu, 16 May 2024 18:19:20 GMT Received: from smtprelay01.wdc07v.mail.ibm.com ([172.16.1.68]) by ppma13.dal12v.mail.ibm.com (PPS) with ESMTPS id 3y2n7m34mg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 May 2024 18:19:20 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay01.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJHj544630574 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:20 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id ACB5F58073; Thu, 16 May 2024 18:19:17 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6E88558071; Thu, 16 May 2024 18:19:17 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:17 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 34/40] fsi: core: Add master register read-only sysfs Date: Thu, 16 May 2024 13:19:01 -0500 Message-Id: <20240516181907.3468796-35-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: pR0lzxHYKRZTL71aAOXDWwxAvFP9QeCG X-Proofpoint-ORIG-GUID: pR0lzxHYKRZTL71aAOXDWwxAvFP9QeCG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 The master registers are commonly used for debugging or diagnosis so provide them in sysfs files. Signed-off-by: Eddie James --- drivers/fsi/fsi-core.c | 144 +++++++++++++++++++++++++++++++++++++++ drivers/fsi/fsi-master.h | 6 ++ 2 files changed, 150 insertions(+) diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index ae65d87d4b13e..096b26c6421f2 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -1392,6 +1392,141 @@ static ssize_t master_break_store(struct device *dev, static DEVICE_ATTR(break, 0200, NULL, master_break_store); +struct fsi_master_attribute { + struct device_attribute attr; + int reg; +}; + +static ssize_t master_reg_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct fsi_master_attribute *fattr = container_of(attr, struct fsi_master_attribute, attr); + struct fsi_master *master = to_fsi_master(dev); + unsigned int reg; + int rc; + + rc = regmap_read(master->map, fattr->reg, ®); + if (rc) + return rc; + + return sysfs_emit(buf, "%08x\n", reg); +} + +static ssize_t master_reg_1bpp_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct fsi_master_attribute *fattr = container_of(attr, struct fsi_master_attribute, attr); + struct fsi_master *master = to_fsi_master(dev); + unsigned int count = (master->n_links + 31) / 32; + unsigned int reg; + unsigned int i; + int len = 0; + int rc; + + for (i = 0; i < count; ++i) { + rc = regmap_read(master->map, fattr->reg + (i * 4), ®); + if (rc) + return rc; + + len += sysfs_emit_at(buf, len, "%08x\n", reg); + } + + return len; +} + +static ssize_t master_reg_4bpp_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct fsi_master_attribute *fattr = container_of(attr, struct fsi_master_attribute, attr); + struct fsi_master *master = to_fsi_master(dev); + unsigned int count = (master->n_links + 7) / 8; + unsigned int reg; + unsigned int i; + int len = 0; + int rc; + + for (i = 0; i < count; ++i) { + rc = regmap_read(master->map, fattr->reg + (i * 4), ®); + if (rc) + return rc; + + len += sysfs_emit_at(buf, len, "%08x\n", reg); + } + + return len; +} + +static ssize_t master_reg_32bpp_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct fsi_master_attribute *fattr = container_of(attr, struct fsi_master_attribute, attr); + struct fsi_master *master = to_fsi_master(dev); + unsigned int reg; + int len = 0; + int rc; + int i; + + for (i = 0; i < master->n_links; ++i) { + rc = regmap_read(master->map, fattr->reg + (i * 4), ®); + if (rc) + return rc; + + len += sysfs_emit_at(buf, len, "%08x\n", reg); + } + + return len; +} + +#define FSI_MASTER_ATTR(name, reg) \ + struct fsi_master_attribute dev_attr_##name = { __ATTR(name, 0444, master_reg_show, NULL), reg } +#define FSI_MASTER_ATTR_1BPP(name, reg) \ + struct fsi_master_attribute dev_attr_##name = { __ATTR(name, 0444, master_reg_1bpp_show, NULL), reg } +#define FSI_MASTER_ATTR_4BPP(name, reg) \ + struct fsi_master_attribute dev_attr_##name = { __ATTR(name, 0444, master_reg_4bpp_show, NULL), reg } +#define FSI_MASTER_ATTR_32BPP(name, reg) \ + struct fsi_master_attribute dev_attr_##name = { __ATTR(name, 0444, master_reg_32bpp_show, NULL), reg } + +static FSI_MASTER_ATTR(mmode, FSI_MMODE); +static FSI_MASTER_ATTR(mdlyr, FSI_MDLYR); +static FSI_MASTER_ATTR_1BPP(mcrsp, FSI_MCRSP); +static FSI_MASTER_ATTR_1BPP(menp, FSI_MENP0); +static FSI_MASTER_ATTR_1BPP(mlevp, FSI_MLEVP0); +static FSI_MASTER_ATTR_1BPP(mrefp, FSI_MREFP0); +static FSI_MASTER_ATTR_1BPP(mhpmp, FSI_MHPMP0); +static FSI_MASTER_ATTR_4BPP(msiep, FSI_MSIEP0); +static FSI_MASTER_ATTR_1BPP(maesp, FSI_MAESP0); +static FSI_MASTER_ATTR(maeb, FSI_MAEB); +static FSI_MASTER_ATTR(mver, FSI_MVER); +static FSI_MASTER_ATTR_1BPP(mbsyp, FSI_MBSYP0); +static FSI_MASTER_ATTR_32BPP(mstap, FSI_MSTAP0); +static FSI_MASTER_ATTR(mesrb, FSI_MESRB0); +static FSI_MASTER_ATTR(mscsb, FSI_MSCSB0); +static FSI_MASTER_ATTR(matrb, FSI_MATRB0); +static FSI_MASTER_ATTR(mdtrb, FSI_MDTRB0); +static FSI_MASTER_ATTR(mectrl, FSI_MECTRL); + +static struct attribute *master_mapped_attrs[] = { + &dev_attr_mmode.attr.attr, + &dev_attr_mdlyr.attr.attr, + &dev_attr_mcrsp.attr.attr, + &dev_attr_menp.attr.attr, + &dev_attr_mlevp.attr.attr, + &dev_attr_mrefp.attr.attr, + &dev_attr_mhpmp.attr.attr, + &dev_attr_msiep.attr.attr, + &dev_attr_maesp.attr.attr, + &dev_attr_maeb.attr.attr, + &dev_attr_mver.attr.attr, + &dev_attr_mbsyp.attr.attr, + &dev_attr_mstap.attr.attr, + &dev_attr_mesrb.attr.attr, + &dev_attr_mscsb.attr.attr, + &dev_attr_matrb.attr.attr, + &dev_attr_mdtrb.attr.attr, + &dev_attr_mectrl.attr.attr, + NULL +}; + +static const struct attribute_group master_mapped_group = { + .attrs = master_mapped_attrs, +}; + static struct attribute *master_attrs[] = { &dev_attr_break.attr, &dev_attr_rescan.attr, @@ -1665,6 +1800,12 @@ int fsi_master_register(struct fsi_master *master) } out: mutex_unlock(&master->scan_lock); + + if (!rc && master->map) { + if (!sysfs_create_group(&master->dev.kobj, &master_mapped_group)) + master->groups = true; + } + return rc; } EXPORT_SYMBOL_GPL(fsi_master_register); @@ -1675,6 +1816,9 @@ void fsi_master_unregister(struct fsi_master *master) trace_fsi_master_unregister(master); + if (master->groups) + sysfs_remove_group(&master->dev.kobj, &master_mapped_group); + mutex_lock(&master->scan_lock); fsi_master_unscan(master); master->n_links = 0; diff --git a/drivers/fsi/fsi-master.h b/drivers/fsi/fsi-master.h index 2104902091e05..1fa101a477899 100644 --- a/drivers/fsi/fsi-master.h +++ b/drivers/fsi/fsi-master.h @@ -12,6 +12,7 @@ #include #include #include +#include /* * Master registers @@ -27,12 +28,16 @@ #define FSI_MENP0 0x10 /* R/W: enable */ #define FSI_MLEVP0 0x18 /* R: plug detect */ #define FSI_MSENP0 0x18 /* S: Set enable */ +#define FSI_MREFP0 0x20 /* R: Plug reference */ #define FSI_MCENP0 0x20 /* C: Clear enable */ +#define FSI_MHPMP0 0x28 /* R: Plug monitor */ #define FSI_MSIEP0 0x30 /* R/W: interrupt enable */ +#define FSI_MAESP0 0x50 /* R: Any error port */ #define FSI_MSSIEP0 0x50 /* S: Set interrupt enable */ #define FSI_MCSIEP0 0x70 /* C: Clear interrupt enable */ #define FSI_MAEB 0x70 /* R: Error address */ #define FSI_MVER 0x74 /* R: master version/type */ +#define FSI_MBSYP0 0x78 /* R: Port busy */ #define FSI_MSTAP0 0xd0 /* R: Port status */ #define FSI_MRESP0 0xd0 /* W: Port reset */ #define FSI_MESRB0 0x1d0 /* R: Master error status */ @@ -151,6 +156,7 @@ struct fsi_master { int (*link_config)(struct fsi_master *, int link, u8 t_send_delay, u8 t_echo_delay); u8 remote_interrupt_status; + bool groups; }; #define to_fsi_master(d) container_of(d, struct fsi_master, dev) From patchwork Thu May 16 18:19:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797451 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E93EB158A25; Thu, 16 May 2024 18:19:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.158.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715883578; cv=none; b=DO60FzmozK8oOjYo3QtrhA4GPUb5b+EqrefzDl7SduAk6eSFcgLHhRF8P4EJo+q8JR/wJBqgBC4rEsWwks/lI3dIW60/6kRXaVKNRikjev3cgIliIpbcoyMNy8xIeBzEKPzyFsxdDZlLtbIvskUyFXmBH4DG8KSretvF6ZqXZ+g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 16 May 2024 18:19:21 GMT Received: from smtprelay02.wdc07v.mail.ibm.com ([172.16.1.69]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3y2mgmud3h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 May 2024 18:19:21 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay02.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJI1G18678322 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:21 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9F4D85806B; Thu, 16 May 2024 18:19:18 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 60A1C58069; Thu, 16 May 2024 18:19:18 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:18 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 37/40] fsi: core: Add different types of CFAM Date: Thu, 16 May 2024 13:19:04 -0500 Message-Id: <20240516181907.3468796-38-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: BvFygxNzDn5UiTwaxCXe-fb5nnUBLwAP X-Proofpoint-GUID: BvFygxNzDn5UiTwaxCXe-fb5nnUBLwAP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 clxscore=1015 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 Detect the CFAM type based on the chip id and set up the device type based on the CFAM type. Signed-off-by: Eddie James --- drivers/fsi/fsi-core.c | 84 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 83 insertions(+), 1 deletion(-) diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 3d2bedb3ad51b..2785812a7d4ad 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -1028,6 +1028,37 @@ static struct attribute *cfam_attrs[] = { ATTRIBUTE_GROUPS(cfam); +static struct attribute *cfam_s_attrs[] = { + &dev_attr_send_echo_delays.attr, + &dev_attr_chip_id.attr, + &dev_attr_cfam_id.attr, + &dev_attr_send_term.attr, + &dev_attr_config_table.attr, + &dev_attr_smode.attr.attr, + &dev_attr_sdma.attr.attr, + &dev_attr_sisc.attr.attr, + &dev_attr_sism.attr.attr, + &dev_attr_siss.attr.attr, + &dev_attr_sstat.attr.attr, + &dev_attr_si1m.attr.attr, + &dev_attr_si1s.attr.attr, + &dev_attr_sic.attr.attr, + &dev_attr_si2m.attr.attr, + &dev_attr_si2s.attr.attr, + &dev_attr_scmdt.attr.attr, + &dev_attr_sdata.attr.attr, + &dev_attr_slastd.attr.attr, + &dev_attr_smbl.attr.attr, + &dev_attr_soml.attr.attr, + &dev_attr_snml.attr.attr, + &dev_attr_smbr.attr.attr, + &dev_attr_somr.attr.attr, + &dev_attr_snmr.attr.attr, + NULL, +}; + +ATTRIBUTE_GROUPS(cfam_s); + static char *cfam_devnode(const struct device *dev, umode_t *mode, kuid_t *uid, kgid_t *gid) { @@ -1046,6 +1077,57 @@ static const struct device_type cfam_type = { .groups = cfam_groups }; +static char *cfam_ody_devnode(const struct device *dev, umode_t *mode, kuid_t *uid, kgid_t *gid) +{ + const struct fsi_slave *slave = to_fsi_slave(dev); + +#ifdef CONFIG_FSI_NEW_DEV_NODE + return kasprintf(GFP_KERNEL, "fsi/ody%d", slave->cdev_idx); +#else + return kasprintf(GFP_KERNEL, "ody%d", slave->cdev_idx); +#endif +} + +static const struct device_type cfam_ody_type = { + .name = "ody", + .devnode = cfam_ody_devnode +}; + +static char *cfam_s_devnode(const struct device *dev, umode_t *mode, kuid_t *uid, kgid_t *gid) +{ + const struct fsi_slave *slave = to_fsi_slave(dev); + +#ifdef CONFIG_FSI_NEW_DEV_NODE + return kasprintf(GFP_KERNEL, "fsi/cfam-s%d", slave->cdev_idx); +#else + return kasprintf(GFP_KERNEL, "cfam-s%d", slave->cdev_idx); +#endif +} + +static const struct device_type cfam_s_type = { + .name = "cfam-s", + .devnode = cfam_s_devnode, + .groups = cfam_s_groups, +}; + +const struct device_type *fsi_get_cfam_type(u32 id) +{ + u32 major = (id & 0xf00) >> 8; + u32 minor = (id & 0xf0) >> 4; + + switch (major) { + case 0x9: + return &cfam_s_type; + case 0xc: + if (minor == 0) + return &cfam_ody_type; + fallthrough; + case 0xd: + default: + return &cfam_type; + } +} + static char *fsi_cdev_devnode(const struct device *dev, umode_t *mode, kuid_t *uid, kgid_t *gid) { @@ -1202,7 +1284,7 @@ static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id) spin_lock_init(&slave->lock); dev_set_name(&slave->dev, "slave@%02x:%02x", link, id); - slave->dev.type = &cfam_type; + slave->dev.type = fsi_get_cfam_type(cfam_id); slave->dev.parent = &master->dev; slave->dev.of_node = fsi_slave_find_of_node(master, link, id); slave->dev.release = fsi_slave_release; From patchwork Thu May 16 18:19:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797453 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3DF315821A; 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Thu, 16 May 2024 18:19:18 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 38/40] spi: fsi: Calculate clock divider from local bus frequency Date: Thu, 16 May 2024 13:19:05 -0500 Message-Id: <20240516181907.3468796-39-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: t6GYCQt_X6uhjL6KkshgjWQhVkW4aZkY X-Proofpoint-ORIG-GUID: t6GYCQt_X6uhjL6KkshgjWQhVkW4aZkY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 clxscore=1015 impostorscore=0 mlxscore=0 malwarescore=0 mlxlogscore=844 spamscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 Use the new FSI device local bus clock to calculate the proper SPI clock divider. Signed-off-by: Eddie James --- drivers/spi/spi-fsi.c | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-fsi.c b/drivers/spi/spi-fsi.c index fc9e33be1e0e7..e762690f1a390 100644 --- a/drivers/spi/spi-fsi.c +++ b/drivers/spi/spi-fsi.c @@ -40,6 +40,7 @@ #define SPI_FSI_CLOCK_CFG_SCK_RECV_DEL GENMASK_ULL(51, 44) #define SPI_FSI_CLOCK_CFG_SCK_NO_DEL BIT_ULL(51) #define SPI_FSI_CLOCK_CFG_SCK_DIV GENMASK_ULL(63, 52) +#define SPI_FSI_CLOCK_CFG_SCK_DIV_MIN 0x4 #define SPI_FSI_MMAP 0x4 #define SPI_FSI_DATA_TX 0x5 #define SPI_FSI_DATA_RX 0x6 @@ -70,6 +71,7 @@ struct fsi2spi { struct fsi_device *fsi; /* FSI2SPI CFAM engine device */ struct mutex lock; /* lock access to the device */ + u32 lbus_freq; }; struct fsi_spi { @@ -359,7 +361,7 @@ static int fsi_spi_transfer_data(struct fsi_spi *ctx, return 0; } -static int fsi_spi_transfer_init(struct fsi_spi *ctx) +static int fsi_spi_transfer_init(struct fsi_spi *ctx, u32 clock_div) { int loops = 0; int rc; @@ -370,7 +372,7 @@ static int fsi_spi_transfer_init(struct fsi_spi *ctx) u64 status = 0ULL; u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE | SPI_FSI_CLOCK_CFG_SCK_NO_DEL | - FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19); + FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, clock_div); end = jiffies + msecs_to_jiffies(SPI_FSI_TIMEOUT_MS); do { @@ -421,6 +423,24 @@ static int fsi_spi_transfer_init(struct fsi_spi *ctx) return rc; } +static u32 fsi_spi_calculate_clock_div(struct fsi2spi *bridge, struct spi_device *dev, + struct spi_transfer *transfer) +{ + u32 div = 19; + + if (bridge->lbus_freq) { + u32 desired_speed_hz = transfer->speed_hz ?: dev->max_speed_hz; + + div = DIV_ROUND_UP(bridge->lbus_freq, desired_speed_hz); + if (div < SPI_FSI_CLOCK_CFG_SCK_DIV_MIN) + div = SPI_FSI_CLOCK_CFG_SCK_DIV_MIN; + + transfer->effective_speed_hz = bridge->lbus_freq / div; + } + + return div; +} + static int fsi_spi_transfer_one_message(struct spi_controller *ctlr, struct spi_message *mesg) { @@ -429,6 +449,7 @@ static int fsi_spi_transfer_one_message(struct spi_controller *ctlr, unsigned int len; struct spi_transfer *transfer; struct fsi_spi *ctx = spi_controller_get_devdata(ctlr); + u32 div; rc = fsi_spi_check_mux(ctx->bridge->fsi, ctx->dev); if (rc) @@ -446,7 +467,8 @@ static int fsi_spi_transfer_one_message(struct spi_controller *ctlr, dev_dbg(ctx->dev, "Start tx of %d bytes.\n", transfer->len); - rc = fsi_spi_transfer_init(ctx); + div = fsi_spi_calculate_clock_div(ctx->bridge, mesg->spi, transfer); + rc = fsi_spi_transfer_init(ctx, div); if (rc < 0) goto error; @@ -533,6 +555,7 @@ static int fsi_spi_probe(struct device *dev) bridge->fsi = fsi; mutex_init(&bridge->lock); + bridge->lbus_freq = fsi_device_local_bus_frequency(fsi); for_each_available_child_of_node(dev->of_node, np) { u32 base; @@ -550,6 +573,10 @@ static int fsi_spi_probe(struct device *dev) ctlr->dev.of_node = np; ctlr->num_chipselect = of_get_available_child_count(np) ?: 1; + if (bridge->lbus_freq) { + ctlr->min_speed_hz = DIV_ROUND_UP(bridge->lbus_freq, 0xfff); + ctlr->max_speed_hz = bridge->lbus_freq / SPI_FSI_CLOCK_CFG_SCK_DIV_MIN; + } ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX; ctlr->max_transfer_size = fsi_spi_max_transfer_size; ctlr->transfer_one_message = fsi_spi_transfer_one_message;