From patchwork Mon Oct 21 10:35:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 177043 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3223799ill; Mon, 21 Oct 2019 03:35:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqyZlV3nBCdHndGTFfsb7qv1a5xCWCgGUJ+MA316xDngmTZRr8CNfo6PozyKE2g9L96QfEbM X-Received: by 2002:a05:6402:2c5:: with SMTP id b5mr1221037edx.157.1571654151685; Mon, 21 Oct 2019 03:35:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571654151; cv=none; d=google.com; s=arc-20160816; b=x6JAz0TLsx2LQHNfq4a9TuGksc1A4teyANqpB6lIDquU5nOVMI3ma7jT4YqenJf0DF TmYeWXVQQAPYAtvFzDsVYAC1naVx7ZkcMLg4RH4U55BTwsWmSk0w1P5xN0EUrDyYNorH h/3bfw5NhWNlwLSEvsfGMLqmUf2pNwb8fXDfQnDxQz31YJsSmf7FjeUz8mmxjAtQD6ln lY1YSo9YzZANgymLAI23TS+DLcVrJ2ByyzYRwvaZ2rdUESuhBqpyOtLR8E6YKQy09++J NfJDDArt1rBUFi4+t2mde7cupzFu6v4B7xFJvTbD3ELlsWBSXvtGGHJ6xRezlMVJZBk3 m/KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=ByQuSAprS9jXkayR9k8WNXgC0XRVOmuonTQ+tfTnFgQ=; b=IM45/wO/35cCaoykYzpqdd61j7MyYyvfpbeIkVImc8uMGwtkk+uI89Fvp3hZNpEef5 LvBPRJPnzPUn7bdus1ux4LmR5GDIEYC8q14gelP4xOsuTTgRRcqbObheDL8E+fsJZTrF /x0xH7+dDKYZDE6oowGrRAjmVL8T/ELgbbExUAF1LN2AFEyiwi4Hr00nyyV5KiET3D45 +4HnRS4WUPl9FH1DC33twyj70xVOaStMeL7lnVapVSyD87H0hjIXZ8GWCXfQnddMnaQa dMLTonDGypnlQjwbAZqgYH+KUkbr+ig3M9SPo0J9cTsw4oFMSUBkB5ZI4nozZEhah7Xr SpEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F20sjx0y; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b44si9634713ede.451.2019.10.21.03.35.51; Mon, 21 Oct 2019 03:35:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F20sjx0y; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728227AbfJUKfu (ORCPT + 10 others); Mon, 21 Oct 2019 06:35:50 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:44371 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728197AbfJUKfu (ORCPT ); Mon, 21 Oct 2019 06:35:50 -0400 Received: by mail-pf1-f195.google.com with SMTP id q21so8154206pfn.11 for ; Mon, 21 Oct 2019 03:35:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=ByQuSAprS9jXkayR9k8WNXgC0XRVOmuonTQ+tfTnFgQ=; b=F20sjx0yS3J6Y1j5JsXZ2Gpm20YNzlBp1Q9Sh/pFUqGmdiaOG2MjLbZMFn+mL+S7py 7Djb+E855QkNZOggjigBXw87iY0cOhXI27sUJwGAlVjCuJi1TaE+qHGoc98Ek08e3cpu 4vMffBQ+hcVwtddGYa1fPuYCu5mq2MYAL0l/iCEvWK+KdjIORO4pLVmaUmJjBpl8cJp3 VaDydgsopnGKZJzZ82yjCH4xJNyw//AaQLkLHFubBpHqrwF0IouKcslwojVBzUtI2uaQ 6r2SqNedzxv7HvJVJ0W+2OjkO81BdXDQfyVuPQoYVOccXuAZLQUY1J6qJhPiQWHpzpj0 +dmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=ByQuSAprS9jXkayR9k8WNXgC0XRVOmuonTQ+tfTnFgQ=; b=CFnTtq7ttzQ0MOAW1FcNR5FbTd6m1gb30/2MVY2P87Wu/Q3r6NJZGId2yQbrhcSEKR TS1vv/QgjilkFWmmuu6jgaVBkJnUOWtFe5dOzdbtEQkGfIqAoVyILjsi40m6K6QJTw/q erdOeR8gnALeDoOMC621qQw7lSnp14KUMVZKRnD3HNolvWO1F95nKki2sKZDmnwKFve5 LJ53gi3mCdu2z1V/BP4xasjC4TirXkC+QRqRvaxXr317meilZIq2bN/kVpLZSCyVf7es zrXwY5cDHtFYJ24EWw2cHwWILeix88l2bVrqYc6aUrUP2uRpHqaUPlNGc7nFFhWvZWXX OOUA== X-Gm-Message-State: APjAAAWZS+R9VmmhwlFaiEnxst8Y8KkvR9a/wN64KXknwERXE5uNqCEO uKKeybMHSNMpxg/TDQxEyjds1w== X-Received: by 2002:a17:90a:b304:: with SMTP id d4mr28610421pjr.27.1571654149379; Mon, 21 Oct 2019 03:35:49 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id k6sm20516678pfg.162.2019.10.21.03.35.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:35:48 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v6 02/15] drivers: thermal: tsens: Simplify code flow in tsens_probe Date: Mon, 21 Oct 2019 16:05:21 +0530 Message-Id: <184422dcc1c12553e71a58c62e01425fd7d1172a.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Move platform_set_drvdata up to avoid an extra 'if (ret)' check after the call to tsens_register. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd Reviewed-by: Daniel Lezcano --- drivers/thermal/qcom/tsens.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 6ed687a6e53cd..542a7f8c3d962 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -149,6 +149,8 @@ static int tsens_probe(struct platform_device *pdev) priv->feat = data->feat; priv->fields = data->fields; + platform_set_drvdata(pdev, priv); + if (!priv->ops || !priv->ops->init || !priv->ops->get_temp) return -EINVAL; @@ -167,11 +169,7 @@ static int tsens_probe(struct platform_device *pdev) } } - ret = tsens_register(priv); - - platform_set_drvdata(pdev, priv); - - return ret; + return tsens_register(priv); } static int tsens_remove(struct platform_device *pdev) From patchwork Mon Oct 21 10:35:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 177045 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3223946ill; Mon, 21 Oct 2019 03:35:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqzdsdC1/zijfmeNcXHsgoIXDxCEr2JLhTVJyvmSH2EQTYGig7b6Q4KMNkiAzzrzrSZHFRpF X-Received: by 2002:a17:907:10d3:: with SMTP id rv19mr20497488ejb.301.1571654159639; Mon, 21 Oct 2019 03:35:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571654159; cv=none; d=google.com; s=arc-20160816; b=PDb7B95gkPKn+ZPp7JzvgiIRO2gMdzKanJGZY8E1qA1UV5X0pZv4G4ekU1NMTrg9dJ SPNiVx31shyFcynTOsS3eqZy2hkgMueLXASRgyW/9dcqNNVhuDmxWUW0IcnNKTcI5MwG qUdZKlBJVGKskrsnsijpWAoIjz0Wf6XYI8NK/fCwnpy+lyJqdy++GfM38XN4DPD9hNzy rdazFeB4BJYinyuUXgX0LGhB7Ov1Jvjaqky6BLD5RAnD1QlqTVnfziogw0+JboAXGGvA A1Mq4uGlFuZCbnQ8Jc/biZYolqOtImvCplJgQlMPbeBnTgx2UAyHCZDzkZ7GMuYzpXlv QeiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=vKvS2rESDoy6PQiz2SnKaFwj6LTgApvN5b42XLtJTXo=; b=qdDj1FDmO5OgrVG/pMIZLIsS7uLsumS9HZCeM2EgYBeN6oYhma1665ZJ7noZvtSOdi Wr09HokTiQj322D72tMTezku5bBTcKPvVQ3qQRgHD/e5rY9WAfQ0tDp58r+9KID5Mp9O FNm/Ga1meqoGk0JKwxZGJzC3JWmOwnaGhmvR2hBcXW0wzjMTA5wWD0c5lt6MY4CnlNCV BzIk5FrW88TELrIaI/W2Erb+uHDC7uVkS+mvYQNa3QJdvQt7nwFzqz6MkqvGYQKfUZM/ Lh9T143/Nb7fQWPGSZ0KzyOLEFyM7kIA+p6HqnpSHGzdHlrbpvjXl8/Ubpx4laWWVWPa ANIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vRxWMzYJ; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d17si8759892edv.76.2019.10.21.03.35.59; Mon, 21 Oct 2019 03:35:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vRxWMzYJ; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728262AbfJUKf6 (ORCPT + 10 others); Mon, 21 Oct 2019 06:35:58 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:47081 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728260AbfJUKf5 (ORCPT ); Mon, 21 Oct 2019 06:35:57 -0400 Received: by mail-pl1-f194.google.com with SMTP id q24so6399287plr.13 for ; Mon, 21 Oct 2019 03:35:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=vKvS2rESDoy6PQiz2SnKaFwj6LTgApvN5b42XLtJTXo=; b=vRxWMzYJfmSP5fBSVSoLcZ1X39pHCGWkElQMy6zu8HkFuokcu0mfeAJ/UUtKqLyv+V YZS6CRMM59EUmmX2V0BrStC4nWZHeW9Jo6JQlByfl/Oda7KvXo3Z3ROpxef2xOG1RBYo fKkeckIsDBRNSC4aZCFpCxfMh55Le5ijR8n4Yq7Cv/VqgEm3SmLY+CqRpQK1K8QVBIEb UXpqXO4N/bRCQhOetk0X2G3u4G29dKtvvfvnH7Wi4SIHwyqEEoP29fXGknmf/wTaSDZ/ CJwuOAQKDUnnNw/iCvNTftcPgzQZiwDOTNgQuOmduE2smAjWcnF1Jhe9S/EqgGTzXyFK XPmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=vKvS2rESDoy6PQiz2SnKaFwj6LTgApvN5b42XLtJTXo=; b=eObJxCJYloupeQhfSiiMdXjETAh6AQuROvW42+rNU5iXbl684JQuqzZklilcuMcNVQ N+/t+LpWDlL7uuACFVdEL1ZcKyHGDELpDFPp25D1iOb7bzMbOpPvQ/48dyD5L5HFb1xT VzjdJY42ht33QIuoZzht/5QwgUdG37SepBqXREphMMgiM9+wqp7cjgwH7gjlnG8dhvzs rUz6w65S41ZBREcpTzX9kUkGcth2azMq65FdlSpUNEQ2JfZLFtRUMSQcjcCwtfFNWQmm YRx1yYdg4Ofq5a7jqusE9Xp/+3C7ZELoYM8TfDF9+UNGVAHaqSIJQjucywwc55OPR2x8 7hEQ== X-Gm-Message-State: APjAAAUPYLqP9+gcUpKo4QcSTACuX0LFPdFkiUv0WoPxtqCqiLleo1JZ gxBbZ8MKIt21TJKQvgrA1cSIlg== X-Received: by 2002:a17:902:aa91:: with SMTP id d17mr23259072plr.69.1571654156571; Mon, 21 Oct 2019 03:35:56 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id w25sm14423643pfi.60.2019.10.21.03.35.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:35:56 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v6 04/15] drivers: thermal: tsens: Add debugfs support Date: Mon, 21 Oct 2019 16:05:23 +0530 Message-Id: <16e39c1bbfc18b5cf6274620cd72cc63205f53a5.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Dump some basic version info and sensor details into debugfs. Example from qcs404 below: --(/sys/kernel/debug) $ ls tsens/ 4a9000.thermal-sensor version --(/sys/kernel/debug) $ cat tsens/version 1.4.0 --(/sys/kernel/debug) $ cat tsens/4a9000.thermal-sensor/sensors max: 11 num: 10 id slope offset ------------------------ 0 3200 404000 1 3200 404000 2 3200 404000 3 3200 404000 4 3200 404000 5 3200 404000 6 3200 404000 7 3200 404000 8 3200 404000 9 3200 404000 Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd --- drivers/thermal/qcom/tsens-common.c | 83 +++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 2 + drivers/thermal/qcom/tsens.h | 6 +++ 3 files changed, 91 insertions(+) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 7437bfe196e50..ea2c46cc6a66a 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -139,6 +140,77 @@ int get_temp_common(struct tsens_sensor *s, int *temp) return 0; } +#ifdef CONFIG_DEBUG_FS +static int dbg_sensors_show(struct seq_file *s, void *data) +{ + struct platform_device *pdev = s->private; + struct tsens_priv *priv = platform_get_drvdata(pdev); + int i; + + seq_printf(s, "max: %2d\nnum: %2d\n\n", + priv->feat->max_sensors, priv->num_sensors); + + seq_puts(s, " id slope offset\n--------------------------\n"); + for (i = 0; i < priv->num_sensors; i++) { + seq_printf(s, "%8d %8d %8d\n", priv->sensor[i].hw_id, + priv->sensor[i].slope, priv->sensor[i].offset); + } + + return 0; +} + +static int dbg_version_show(struct seq_file *s, void *data) +{ + struct platform_device *pdev = s->private; + struct tsens_priv *priv = platform_get_drvdata(pdev); + u32 maj_ver, min_ver, step_ver; + int ret; + + if (tsens_ver(priv) > VER_0_1) { + ret = regmap_field_read(priv->rf[VER_MAJOR], &maj_ver); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[VER_MINOR], &min_ver); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[VER_STEP], &step_ver); + if (ret) + return ret; + seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver); + } else { + seq_puts(s, "0.1.0\n"); + } + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(dbg_version); +DEFINE_SHOW_ATTRIBUTE(dbg_sensors); + +static void tsens_debug_init(struct platform_device *pdev) +{ + struct tsens_priv *priv = platform_get_drvdata(pdev); + struct dentry *root, *file; + + root = debugfs_lookup("tsens", NULL); + if (!root) + priv->debug_root = debugfs_create_dir("tsens", NULL); + else + priv->debug_root = root; + + file = debugfs_lookup("version", priv->debug_root); + if (!file) + debugfs_create_file("version", 0444, priv->debug_root, + pdev, &dbg_version_fops); + + /* A directory for each instance of the TSENS IP */ + priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root); + debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops); +} +#else +static inline void tsens_debug_init(struct platform_device *pdev) {} +#endif + static const struct regmap_config tsens_config = { .name = "tm", .reg_bits = 32, @@ -199,6 +271,15 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } + if (tsens_ver(priv) > VER_0_1) { + for (i = VER_MAJOR; i <= VER_STEP; i++) { + priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[i]); + if (IS_ERR(priv->rf[i])) + return PTR_ERR(priv->rf[i]); + } + } + priv->rf[TSENS_EN] = devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_EN]); if (IS_ERR(priv->rf[TSENS_EN])) { @@ -238,6 +319,8 @@ int __init init_common(struct tsens_priv *priv) } } + tsens_debug_init(op); + return 0; err_put_device: diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 06c6bbd69a1a7..772aa76b50e12 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -176,6 +177,7 @@ static int tsens_remove(struct platform_device *pdev) { struct tsens_priv *priv = platform_get_drvdata(pdev); + debugfs_remove_recursive(priv->debug_root); if (priv->ops->disable) priv->ops->disable(priv); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 84e5447c56860..00899c17e848c 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -293,6 +293,8 @@ struct tsens_context { * @feat: features of the IP * @fields: bitfield locations * @ops: pointer to list of callbacks supported by this device + * @debug_root: pointer to debugfs dentry for all tsens + * @debug: pointer to debugfs dentry for tsens controller * @sensor: list of sensors attached to this device */ struct tsens_priv { @@ -306,6 +308,10 @@ struct tsens_priv { const struct tsens_features *feat; const struct reg_field *fields; const struct tsens_ops *ops; + + struct dentry *debug_root; + struct dentry *debug; + struct tsens_sensor sensor[0]; }; From patchwork Mon Oct 21 10:35:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 177056 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3224674ill; Mon, 21 Oct 2019 03:36:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqyiWeU8W8Z+2RfYAUpZBz9+4n+GsSA2ZsKyNhHDHhrthvvst9ZEvm60GRNyiZA1Dipno6XR X-Received: by 2002:a17:906:19cf:: with SMTP id h15mr22046732ejd.184.1571654200075; Mon, 21 Oct 2019 03:36:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571654200; cv=none; d=google.com; s=arc-20160816; b=vFJE5+h2/RZZqCAjgUmjmCfyJMrOHHjTKU8JQDsNTb4Zs9C1OrUSz2ZI+MmNeWeyaM ezdZTytiFedpBmgP//gq03CKdUVvF2cfcnfDxZTW6aUl68my35qBIbnPJiPFFA5bSt7r fnV29mV1sK6ckbuCDPRjnkZ5jc5cXoW+4PEuzMFC4MPlby88UITwbIy18erSqFqG9JPB QPsWfnymuFcglTA5eDCSZDMcNNSml6tmlLjdG7SA2zS67A4OVdwGg6n04A1Use/JOvJt p+hfrRaryR7jVK2CXDM1SuE9eOzX/O1mStgLW6G0b2JXHWeXSLQgTW4tHB4ngTEARHrP mIsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=lM0jdHw3/iMJOlz39xOMNJ1CbpOVydSXDUYI87GWPVM=; b=BxqfHxuteTh8gjPASvTzPdpcYf2r92SK3D/b9v2WIrD5Fy+RPt+T8k0p41CuPUSeR9 HP3g7nDZ2dJczi7rIfRs0KFYqVRPHmu3XE954upeTF6PfrkmlabO6C5OMFJUAOnkPzB3 70lWd8HPOBxEbsicZot5fDUohmtjBc14OlO8ahTNd0y0ffw0pPTikJKXJEQK3g8ur6tm 6qSjCi8I04jfP3eIa2QMXqR1D6I/dDIPF7wd3+d5sl0wbCsNSFCmK6Y9nlGRitbJnGwW PkkoHV46lF7Auxa+dTr2LZdWSZ97U66moHxs8MgcJlSKdj8kcItk2q7ex4jvcIfCJ3qE 9RdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lphZzpU5; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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We only add support for upper and lower threshold interrupts for now. TSENSv2 has an irq [status|clear|mask] bit tuple for each sensor while earlier versions only have a single bit per sensor to denote status and clear. These differences are handled transparently by the interrupt handler. At each interrupt, we reprogram the new upper and lower threshold in the .set_trip callback. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd --- drivers/thermal/qcom/tsens-common.c | 377 ++++++++++++++++++++++++++-- drivers/thermal/qcom/tsens-v0_1.c | 11 + drivers/thermal/qcom/tsens-v1.c | 29 +++ drivers/thermal/qcom/tsens-v2.c | 13 + drivers/thermal/qcom/tsens.c | 32 ++- drivers/thermal/qcom/tsens.h | 270 ++++++++++++++++---- 6 files changed, 669 insertions(+), 63 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index c34a1a26ce298..03bf1b8133eac 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -13,6 +13,31 @@ #include #include "tsens.h" +/** + * struct tsens_irq_data - IRQ status and temperature violations + * @up_viol: upper threshold violated + * @up_thresh: upper threshold temperature value + * @up_irq_mask: mask register for upper threshold irqs + * @up_irq_clear: clear register for uppper threshold irqs + * @low_viol: lower threshold violated + * @low_thresh: lower threshold temperature value + * @low_irq_mask: mask register for lower threshold irqs + * @low_irq_clear: clear register for lower threshold irqs + * + * Structure containing data about temperature threshold settings and + * irq status if they were violated. + */ +struct tsens_irq_data { + u32 up_viol; + int up_thresh; + u32 up_irq_mask; + u32 up_irq_clear; + u32 low_viol; + int low_thresh; + u32 low_irq_mask; + u32 low_irq_clear; +}; + char *qfprom_read(struct device *dev, const char *cname) { struct nvmem_cell *cell; @@ -65,6 +90,14 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, } } +static inline u32 degc_to_code(int degc, const struct tsens_sensor *s) +{ + u64 code = (degc * s->slope + s->offset) / SLOPE_FACTOR; + + pr_debug("%s: raw_code: 0x%llx, degc:%d\n", __func__, code, degc); + return clamp_val(code, THRESHOLD_MIN_ADC_CODE, THRESHOLD_MAX_ADC_CODE); +} + static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) { int degc, num, den; @@ -117,6 +150,313 @@ static int tsens_hw_to_mC(struct tsens_sensor *s, int field) return sign_extend32(temp, resolution) * 100; } +/** + * tsens_mC_to_hw - Convert temperature to hardware register value + * @s: Pointer to sensor struct + * @temp: temperature in milliCelsius to be programmed to hardware + * + * This function outputs the value to be written to hardware in ADC code + * or deciCelsius depending on IP version. + * + * Return: ADC code or temperature in deciCelsius. + */ +static int tsens_mC_to_hw(struct tsens_sensor *s, int temp) +{ + struct tsens_priv *priv = s->priv; + + /* milliC to adc code */ + if (priv->feat->adc) + return degc_to_code(temp / 1000, s); + + /* milliC to deciC */ + return temp / 100; +} + +static inline enum tsens_ver tsens_version(struct tsens_priv *priv) +{ + return priv->feat->ver_major; +} + +static void tsens_set_interrupt_v1(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + u32 index; + + switch (irq_type) { + case UPPER: + index = UP_INT_CLEAR_0 + hw_id; + break; + case LOWER: + index = LOW_INT_CLEAR_0 + hw_id; + break; + } + regmap_field_write(priv->rf[index], enable ? 0 : 1); +} + +static void tsens_set_interrupt_v2(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + u32 index_mask, index_clear; + + /* + * To enable the interrupt flag for a sensor: + * - clear the mask bit + * To disable the interrupt flag for a sensor: + * - Mask further interrupts for this sensor + * - Write 1 followed by 0 to clear the interrupt + */ + switch (irq_type) { + case UPPER: + index_mask = UP_INT_MASK_0 + hw_id; + index_clear = UP_INT_CLEAR_0 + hw_id; + break; + case LOWER: + index_mask = LOW_INT_MASK_0 + hw_id; + index_clear = LOW_INT_CLEAR_0 + hw_id; + break; + } + + if (enable) { + regmap_field_write(priv->rf[index_mask], 0); + } else { + regmap_field_write(priv->rf[index_mask], 1); + regmap_field_write(priv->rf[index_clear], 1); + regmap_field_write(priv->rf[index_clear], 0); + } +} + +/** + * tsens_set_interrupt - Set state of an interrupt + * @priv: Pointer to tsens controller private data + * @hw_id: Hardware ID aka. sensor number + * @irq_type: irq_type from enum tsens_irq_type + * @enable: false = disable, true = enable + * + * Call IP-specific function to set state of an interrupt + * + * Return: void + */ +static void tsens_set_interrupt(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + dev_dbg(priv->dev, "[%u] %s: %s -> %s\n", hw_id, __func__, + irq_type ? ((irq_type == 1) ? "UP" : "CRITICAL") : "LOW", + enable ? "en" : "dis"); + if (tsens_version(priv) > VER_1_X) + tsens_set_interrupt_v2(priv, hw_id, irq_type, enable); + else + tsens_set_interrupt_v1(priv, hw_id, irq_type, enable); +} + +/** + * tsens_threshold_violated - Check if a sensor temperature violated a preset threshold + * @priv: Pointer to tsens controller private data + * @hw_id: Hardware ID aka. sensor number + * @d: Pointer to irq state data + * + * Return: 0 if threshold was not violated, 1 if it was violated and negative + * errno in case of errors + */ +static int tsens_threshold_violated(struct tsens_priv *priv, u32 hw_id, + struct tsens_irq_data *d) +{ + int ret; + + ret = regmap_field_read(priv->rf[UPPER_STATUS_0 + hw_id], &d->up_viol); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOWER_STATUS_0 + hw_id], &d->low_viol); + if (ret) + return ret; + if (d->up_viol || d->low_viol) + return 1; + + return 0; +} + +static int tsens_read_irq_state(struct tsens_priv *priv, u32 hw_id, + struct tsens_sensor *s, struct tsens_irq_data *d) +{ + int ret; + + ret = regmap_field_read(priv->rf[UP_INT_CLEAR_0 + hw_id], &d->up_irq_clear); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOW_INT_CLEAR_0 + hw_id], &d->low_irq_clear); + if (ret) + return ret; + if (tsens_version(priv) > VER_1_X) { + ret = regmap_field_read(priv->rf[UP_INT_MASK_0 + hw_id], &d->up_irq_mask); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask); + if (ret) + return ret; + } else { + /* No mask register on older TSENS */ + d->up_irq_mask = 0; + d->low_irq_mask = 0; + } + + d->up_thresh = tsens_hw_to_mC(s, UP_THRESH_0 + hw_id); + d->low_thresh = tsens_hw_to_mC(s, LOW_THRESH_0 + hw_id); + + dev_dbg(priv->dev, "[%u] %s%s: status(%u|%u) | clr(%u|%u) | mask(%u|%u)\n", + hw_id, __func__, (d->up_viol || d->low_viol) ? "(V)" : "", + d->low_viol, d->up_viol, d->low_irq_clear, d->up_irq_clear, + d->low_irq_mask, d->up_irq_mask); + dev_dbg(priv->dev, "[%u] %s%s: thresh: (%d:%d)\n", hw_id, __func__, + (d->up_viol || d->low_viol) ? "(violation)" : "", + d->low_thresh, d->up_thresh); + + return 0; +} + +static inline u32 masked_irq(u32 hw_id, u32 mask, enum tsens_ver ver) +{ + if (ver > VER_1_X) + return mask & (1 << hw_id); + + /* v1, v0.1 don't have a irq mask register */ + return 0; +} + +/** + * tsens_irq_thread - Threaded interrupt handler for uplow interrupts + * @irq: irq number + * @data: tsens controller private data + * + * Check all sensors to find ones that violated their threshold limits. If the + * temperature is still outside the limits, call thermal_zone_device_update() to + * update the thresholds, else re-enable the interrupts. + * + * The level-triggered interrupt might deassert if the temperature returned to + * within the threshold limits by the time the handler got scheduled. We + * consider the irq to have been handled in that case. + * + * Return: IRQ_HANDLED + */ +irqreturn_t tsens_irq_thread(int irq, void *data) +{ + struct tsens_priv *priv = data; + struct tsens_irq_data d; + bool enable = true, disable = false; + unsigned long flags; + int temp, ret, i; + + for (i = 0; i < priv->num_sensors; i++) { + bool trigger = false; + struct tsens_sensor *s = &priv->sensor[i]; + u32 hw_id = s->hw_id; + + if (IS_ERR(priv->sensor[i].tzd)) + continue; + if (!tsens_threshold_violated(priv, hw_id, &d)) + continue; + ret = get_temp_tsens_valid(s, &temp); + if (ret) { + dev_err(priv->dev, "[%u] %s: error reading sensor\n", hw_id, __func__); + continue; + } + + spin_lock_irqsave(&priv->ul_lock, flags); + + tsens_read_irq_state(priv, hw_id, s, &d); + + if (d.up_viol && + !masked_irq(hw_id, d.up_irq_mask, tsens_version(priv))) { + tsens_set_interrupt(priv, hw_id, UPPER, disable); + if (d.up_thresh > temp) { + dev_dbg(priv->dev, "[%u] %s: re-arm upper\n", + priv->sensor[i].hw_id, __func__); + tsens_set_interrupt(priv, hw_id, UPPER, enable); + } else { + trigger = true; + /* Keep irq masked */ + } + } else if (d.low_viol && + !masked_irq(hw_id, d.low_irq_mask, tsens_version(priv))) { + tsens_set_interrupt(priv, hw_id, LOWER, disable); + if (d.low_thresh < temp) { + dev_dbg(priv->dev, "[%u] %s: re-arm low\n", + priv->sensor[i].hw_id, __func__); + tsens_set_interrupt(priv, hw_id, LOWER, enable); + } else { + trigger = true; + /* Keep irq masked */ + } + } + + spin_unlock_irqrestore(&priv->ul_lock, flags); + + if (trigger) { + dev_dbg(priv->dev, "[%u] %s: TZ update trigger (%d mC)\n", + hw_id, __func__, temp); + thermal_zone_device_update(priv->sensor[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + } else { + dev_dbg(priv->dev, "[%u] %s: no violation: %d\n", + hw_id, __func__, temp); + } + } + + return IRQ_HANDLED; +} + +int tsens_set_trips(void *_sensor, int low, int high) +{ + struct tsens_sensor *s = _sensor; + struct tsens_priv *priv = s->priv; + struct device *dev = priv->dev; + struct tsens_irq_data d; + unsigned long flags; + int high_val, low_val, cl_high, cl_low; + u32 hw_id = s->hw_id; + + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", + hw_id, __func__, low, high); + + cl_high = clamp_val(high, -40000, 120000); + cl_low = clamp_val(low, -40000, 120000); + + high_val = tsens_mC_to_hw(s, cl_high); + low_val = tsens_mC_to_hw(s, cl_low); + + spin_lock_irqsave(&priv->ul_lock, flags); + + tsens_read_irq_state(priv, hw_id, s, &d); + + /* Write the new thresholds and clear the status */ + regmap_field_write(priv->rf[LOW_THRESH_0 + hw_id], low_val); + regmap_field_write(priv->rf[UP_THRESH_0 + hw_id], high_val); + tsens_set_interrupt(priv, hw_id, LOWER, true); + tsens_set_interrupt(priv, hw_id, UPPER, true); + + spin_unlock_irqrestore(&priv->ul_lock, flags); + + dev_dbg(dev, "[%u] %s: (%d:%d)->(%d:%d)\n", + s->hw_id, __func__, d.low_thresh, d.up_thresh, cl_low, cl_high); + + return 0; +} + +int tsens_enable_irq(struct tsens_priv *priv) +{ + int ret; + int val = tsens_version(priv) > VER_1_X ? 7 : 1; + + ret = regmap_field_write(priv->rf[INT_EN], val); + if (ret < 0) + dev_err(priv->dev, "%s: failed to enable interrupts\n", __func__); + + return ret; +} + +void tsens_disable_irq(struct tsens_priv *priv) +{ + regmap_field_write(priv->rf[INT_EN], 0); +} + int get_temp_tsens_valid(struct tsens_sensor *s, int *temp) { struct tsens_priv *priv = s->priv; @@ -187,7 +527,7 @@ static int dbg_version_show(struct seq_file *s, void *data) u32 maj_ver, min_ver, step_ver; int ret; - if (tsens_ver(priv) > VER_0_1) { + if (tsens_version(priv) > VER_0_1) { ret = regmap_field_read(priv->rf[VER_MAJOR], &maj_ver); if (ret) return ret; @@ -292,7 +632,7 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } - if (tsens_ver(priv) > VER_0_1) { + if (tsens_version(priv) > VER_0_1) { for (i = VER_MAJOR; i <= VER_STEP; i++) { priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[i]); @@ -322,24 +662,29 @@ int __init init_common(struct tsens_priv *priv) ret = PTR_ERR(priv->rf[SENSOR_EN]); goto err_put_device; } - /* now alloc regmap_fields in tm_map */ - for (i = 0, j = LAST_TEMP_0; i < priv->feat->max_sensors; i++, j++) { - priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map, - priv->fields[j]); - if (IS_ERR(priv->rf[j])) { - ret = PTR_ERR(priv->rf[j]); - goto err_put_device; - } + priv->rf[INT_EN] = devm_regmap_field_alloc(dev, priv->tm_map, + priv->fields[INT_EN]); + if (IS_ERR(priv->rf[INT_EN])) { + ret = PTR_ERR(priv->rf[INT_EN]); + goto err_put_device; } - for (i = 0, j = VALID_0; i < priv->feat->max_sensors; i++, j++) { - priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map, - priv->fields[j]); - if (IS_ERR(priv->rf[j])) { - ret = PTR_ERR(priv->rf[j]); - goto err_put_device; + + /* This loop might need changes if enum regfield_ids is reordered */ + for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) { + for (i = 0; i < priv->feat->max_sensors; i++) { + int idx = j + i; + + priv->rf[idx] = devm_regmap_field_alloc(dev, priv->tm_map, + priv->fields[idx]); + if (IS_ERR(priv->rf[idx])) { + ret = PTR_ERR(priv->rf[idx]); + goto err_put_device; + } } } + spin_lock_init(&priv->ul_lock); + tsens_enable_irq(priv); tsens_debug_init(op); return 0; diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 055647bcee67d..4b8dd6de02ce4 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -347,9 +347,20 @@ static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { /* INTERRUPT ENABLE */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), + /* UPPER/LOWER TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), + REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), + + /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20), + REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21), + + /* NO CRITICAL INTERRUPT SUPPORT on v0.1 */ + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), /* No VALID field on v0.1 */ + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 870f502f2cb6c..7d33a0c8cd3ec 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -17,6 +17,8 @@ #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004 #define TM_Sn_STATUS_OFF 0x0044 #define TM_TRDY_OFF 0x0084 +#define TM_HIGH_LOW_INT_STATUS_OFF 0x0088 +#define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090 /* eeprom layout data for qcs404/405 (v1) */ #define BASE0_MASK 0x000007f8 @@ -168,9 +170,36 @@ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { /* INTERRUPT ENABLE */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), + /* UPPER/LOWER TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), + REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), + + /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20), + REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21), + [LOW_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 0, 0), + [LOW_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 1, 1), + [LOW_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 2, 2), + [LOW_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 3, 3), + [LOW_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 4, 4), + [LOW_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 5, 5), + [LOW_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 6, 6), + [LOW_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 7, 7), + [UP_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 8, 8), + [UP_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 9, 9), + [UP_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 10, 10), + [UP_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 11, 11), + [UP_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 12, 12), + [UP_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 13, 13), + [UP_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 14, 14), + [UP_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 15, 15), + + /* NO CRITICAL INTERRUPT SUPPORT on v1 */ + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14), + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 0a4f2b8fcab6c..a4d15e1abfddd 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -50,9 +50,22 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* v2 has separate enables for UPPER/LOWER/CRITICAL interrupts */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 2), + /* TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR16(LOW_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 0, 11), + REG_FIELD_FOR_EACH_SENSOR16(UP_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 12, 23), + + /* INTERRUPTS [CLEAR/STATUS/MASK] */ + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF), + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF), + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF), + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 11), REG_FIELD_FOR_EACH_SENSOR16(VALID, TM_Sn_STATUS_OFF, 21, 21), + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR16(MIN_STATUS, TM_Sn_STATUS_OFF, 16, 16), REG_FIELD_FOR_EACH_SENSOR16(LOWER_STATUS, TM_Sn_STATUS_OFF, 17, 17), REG_FIELD_FOR_EACH_SENSOR16(UPPER_STATUS, TM_Sn_STATUS_OFF, 18, 18), diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 772aa76b50e12..7d317660211e1 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -78,12 +79,14 @@ MODULE_DEVICE_TABLE(of, tsens_table); static const struct thermal_zone_of_device_ops tsens_of_ops = { .get_temp = tsens_get_temp, .get_trend = tsens_get_trend, + .set_trips = tsens_set_trips, }; static int tsens_register(struct tsens_priv *priv) { - int i; + int i, ret, irq; struct thermal_zone_device *tzd; + struct platform_device *pdev; for (i = 0; i < priv->num_sensors; i++) { priv->sensor[i].priv = priv; @@ -96,7 +99,31 @@ static int tsens_register(struct tsens_priv *priv) if (priv->ops->enable) priv->ops->enable(priv, i); } - return 0; + + pdev = of_find_device_by_node(priv->dev->of_node); + if (!pdev) + return -ENODEV; + + irq = platform_get_irq_byname(pdev, "uplow"); + if (irq < 0) { + ret = irq; + goto err_put_device; + } + + ret = devm_request_threaded_irq(&pdev->dev, irq, + NULL, tsens_irq_thread, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + dev_name(&pdev->dev), priv); + if (ret) { + dev_err(&pdev->dev, "%s: failed to get irq\n", __func__); + goto err_put_device; + } + + enable_irq_wake(irq); + +err_put_device: + put_device(&pdev->dev); + return ret; } static int tsens_probe(struct platform_device *pdev) @@ -178,6 +205,7 @@ static int tsens_remove(struct platform_device *pdev) struct tsens_priv *priv = platform_get_drvdata(pdev); debugfs_remove_recursive(priv->debug_root); + tsens_disable_irq(priv); if (priv->ops->disable) priv->ops->disable(priv); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 00899c17e848c..8b20f28c5c512 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -13,8 +13,10 @@ #define CAL_DEGC_PT2 120 #define SLOPE_FACTOR 1000 #define SLOPE_DEFAULT 3200 +#define THRESHOLD_MAX_ADC_CODE 0x3ff +#define THRESHOLD_MIN_ADC_CODE 0x0 - +#include #include #include #include @@ -27,6 +29,11 @@ enum tsens_ver { VER_2_X, }; +enum tsens_irq_type { + LOWER, + UPPER, +}; + /** * struct tsens_sensor - data for each sensor connected to the tsens device * @priv: tsens device instance that this sensor is connected to @@ -100,22 +107,66 @@ struct tsens_ops { [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \ [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit) -/* reg_field IDs to use as an index into an array */ +#define REG_FIELD_SPLIT_BITS_0_15(_name, _offset) \ + [_name##_##0] = REG_FIELD(_offset, 0, 0), \ + [_name##_##1] = REG_FIELD(_offset, 1, 1), \ + [_name##_##2] = REG_FIELD(_offset, 2, 2), \ + [_name##_##3] = REG_FIELD(_offset, 3, 3), \ + [_name##_##4] = REG_FIELD(_offset, 4, 4), \ + [_name##_##5] = REG_FIELD(_offset, 5, 5), \ + [_name##_##6] = REG_FIELD(_offset, 6, 6), \ + [_name##_##7] = REG_FIELD(_offset, 7, 7), \ + [_name##_##8] = REG_FIELD(_offset, 8, 8), \ + [_name##_##9] = REG_FIELD(_offset, 9, 9), \ + [_name##_##10] = REG_FIELD(_offset, 10, 10), \ + [_name##_##11] = REG_FIELD(_offset, 11, 11), \ + [_name##_##12] = REG_FIELD(_offset, 12, 12), \ + [_name##_##13] = REG_FIELD(_offset, 13, 13), \ + [_name##_##14] = REG_FIELD(_offset, 14, 14), \ + [_name##_##15] = REG_FIELD(_offset, 15, 15) + +#define REG_FIELD_SPLIT_BITS_16_31(_name, _offset) \ + [_name##_##0] = REG_FIELD(_offset, 16, 16), \ + [_name##_##1] = REG_FIELD(_offset, 17, 17), \ + [_name##_##2] = REG_FIELD(_offset, 18, 18), \ + [_name##_##3] = REG_FIELD(_offset, 19, 19), \ + [_name##_##4] = REG_FIELD(_offset, 20, 20), \ + [_name##_##5] = REG_FIELD(_offset, 21, 21), \ + [_name##_##6] = REG_FIELD(_offset, 22, 22), \ + [_name##_##7] = REG_FIELD(_offset, 23, 23), \ + [_name##_##8] = REG_FIELD(_offset, 24, 24), \ + [_name##_##9] = REG_FIELD(_offset, 25, 25), \ + [_name##_##10] = REG_FIELD(_offset, 26, 26), \ + [_name##_##11] = REG_FIELD(_offset, 27, 27), \ + [_name##_##12] = REG_FIELD(_offset, 28, 28), \ + [_name##_##13] = REG_FIELD(_offset, 29, 29), \ + [_name##_##14] = REG_FIELD(_offset, 30, 30), \ + [_name##_##15] = REG_FIELD(_offset, 31, 31) + +/* + * reg_field IDs to use as an index into an array + * If you change the order of the entries, check the devm_regmap_field_alloc() + * calls in init_common() + */ enum regfield_ids { /* ----- SROT ------ */ /* HW_VER */ - VER_MAJOR = 0, + VER_MAJOR, VER_MINOR, VER_STEP, /* CTRL_OFFSET */ - TSENS_EN = 3, + TSENS_EN, TSENS_SW_RST, SENSOR_EN, CODE_OR_TEMP, /* ----- TM ------ */ + /* TRDY */ + TRDY, + /* INTERRUPT ENABLE */ + INT_EN, /* v2+ has separate enables for crit, upper and lower irq */ /* STATUS */ - LAST_TEMP_0 = 7, /* Last temperature reading */ + LAST_TEMP_0, /* Last temperature reading */ LAST_TEMP_1, LAST_TEMP_2, LAST_TEMP_3, @@ -131,7 +182,7 @@ enum regfield_ids { LAST_TEMP_13, LAST_TEMP_14, LAST_TEMP_15, - VALID_0 = 23, /* VALID reading or not */ + VALID_0, /* VALID reading or not */ VALID_1, VALID_2, VALID_3, @@ -147,38 +198,6 @@ enum regfield_ids { VALID_13, VALID_14, VALID_15, - MIN_STATUS_0, /* MIN threshold violated */ - MIN_STATUS_1, - MIN_STATUS_2, - MIN_STATUS_3, - MIN_STATUS_4, - MIN_STATUS_5, - MIN_STATUS_6, - MIN_STATUS_7, - MIN_STATUS_8, - MIN_STATUS_9, - MIN_STATUS_10, - MIN_STATUS_11, - MIN_STATUS_12, - MIN_STATUS_13, - MIN_STATUS_14, - MIN_STATUS_15, - MAX_STATUS_0, /* MAX threshold violated */ - MAX_STATUS_1, - MAX_STATUS_2, - MAX_STATUS_3, - MAX_STATUS_4, - MAX_STATUS_5, - MAX_STATUS_6, - MAX_STATUS_7, - MAX_STATUS_8, - MAX_STATUS_9, - MAX_STATUS_10, - MAX_STATUS_11, - MAX_STATUS_12, - MAX_STATUS_13, - MAX_STATUS_14, - MAX_STATUS_15, LOWER_STATUS_0, /* LOWER threshold violated */ LOWER_STATUS_1, LOWER_STATUS_2, @@ -195,6 +214,70 @@ enum regfield_ids { LOWER_STATUS_13, LOWER_STATUS_14, LOWER_STATUS_15, + LOW_INT_STATUS_0, /* LOWER interrupt status */ + LOW_INT_STATUS_1, + LOW_INT_STATUS_2, + LOW_INT_STATUS_3, + LOW_INT_STATUS_4, + LOW_INT_STATUS_5, + LOW_INT_STATUS_6, + LOW_INT_STATUS_7, + LOW_INT_STATUS_8, + LOW_INT_STATUS_9, + LOW_INT_STATUS_10, + LOW_INT_STATUS_11, + LOW_INT_STATUS_12, + LOW_INT_STATUS_13, + LOW_INT_STATUS_14, + LOW_INT_STATUS_15, + LOW_INT_CLEAR_0, /* LOWER interrupt clear */ + LOW_INT_CLEAR_1, + LOW_INT_CLEAR_2, + LOW_INT_CLEAR_3, + LOW_INT_CLEAR_4, + LOW_INT_CLEAR_5, + LOW_INT_CLEAR_6, + LOW_INT_CLEAR_7, + LOW_INT_CLEAR_8, + LOW_INT_CLEAR_9, + LOW_INT_CLEAR_10, + LOW_INT_CLEAR_11, + LOW_INT_CLEAR_12, + LOW_INT_CLEAR_13, + LOW_INT_CLEAR_14, + LOW_INT_CLEAR_15, + LOW_INT_MASK_0, /* LOWER interrupt mask */ + LOW_INT_MASK_1, + LOW_INT_MASK_2, + LOW_INT_MASK_3, + LOW_INT_MASK_4, + LOW_INT_MASK_5, + LOW_INT_MASK_6, + LOW_INT_MASK_7, + LOW_INT_MASK_8, + LOW_INT_MASK_9, + LOW_INT_MASK_10, + LOW_INT_MASK_11, + LOW_INT_MASK_12, + LOW_INT_MASK_13, + LOW_INT_MASK_14, + LOW_INT_MASK_15, + LOW_THRESH_0, /* LOWER threshold values */ + LOW_THRESH_1, + LOW_THRESH_2, + LOW_THRESH_3, + LOW_THRESH_4, + LOW_THRESH_5, + LOW_THRESH_6, + LOW_THRESH_7, + LOW_THRESH_8, + LOW_THRESH_9, + LOW_THRESH_10, + LOW_THRESH_11, + LOW_THRESH_12, + LOW_THRESH_13, + LOW_THRESH_14, + LOW_THRESH_15, UPPER_STATUS_0, /* UPPER threshold violated */ UPPER_STATUS_1, UPPER_STATUS_2, @@ -211,6 +294,70 @@ enum regfield_ids { UPPER_STATUS_13, UPPER_STATUS_14, UPPER_STATUS_15, + UP_INT_STATUS_0, /* UPPER interrupt status */ + UP_INT_STATUS_1, + UP_INT_STATUS_2, + UP_INT_STATUS_3, + UP_INT_STATUS_4, + UP_INT_STATUS_5, + UP_INT_STATUS_6, + UP_INT_STATUS_7, + UP_INT_STATUS_8, + UP_INT_STATUS_9, + UP_INT_STATUS_10, + UP_INT_STATUS_11, + UP_INT_STATUS_12, + UP_INT_STATUS_13, + UP_INT_STATUS_14, + UP_INT_STATUS_15, + UP_INT_CLEAR_0, /* UPPER interrupt clear */ + UP_INT_CLEAR_1, + UP_INT_CLEAR_2, + UP_INT_CLEAR_3, + UP_INT_CLEAR_4, + UP_INT_CLEAR_5, + UP_INT_CLEAR_6, + UP_INT_CLEAR_7, + UP_INT_CLEAR_8, + UP_INT_CLEAR_9, + UP_INT_CLEAR_10, + UP_INT_CLEAR_11, + UP_INT_CLEAR_12, + UP_INT_CLEAR_13, + UP_INT_CLEAR_14, + UP_INT_CLEAR_15, + UP_INT_MASK_0, /* UPPER interrupt mask */ + UP_INT_MASK_1, + UP_INT_MASK_2, + UP_INT_MASK_3, + UP_INT_MASK_4, + UP_INT_MASK_5, + UP_INT_MASK_6, + UP_INT_MASK_7, + UP_INT_MASK_8, + UP_INT_MASK_9, + UP_INT_MASK_10, + UP_INT_MASK_11, + UP_INT_MASK_12, + UP_INT_MASK_13, + UP_INT_MASK_14, + UP_INT_MASK_15, + UP_THRESH_0, /* UPPER threshold values */ + UP_THRESH_1, + UP_THRESH_2, + UP_THRESH_3, + UP_THRESH_4, + UP_THRESH_5, + UP_THRESH_6, + UP_THRESH_7, + UP_THRESH_8, + UP_THRESH_9, + UP_THRESH_10, + UP_THRESH_11, + UP_THRESH_12, + UP_THRESH_13, + UP_THRESH_14, + UP_THRESH_15, CRITICAL_STATUS_0, /* CRITICAL threshold violated */ CRITICAL_STATUS_1, CRITICAL_STATUS_2, @@ -227,13 +374,38 @@ enum regfield_ids { CRITICAL_STATUS_13, CRITICAL_STATUS_14, CRITICAL_STATUS_15, - /* TRDY */ - TRDY, - /* INTERRUPT ENABLE */ - INT_EN, /* Pre-V1, V1.x */ - LOW_INT_EN, /* V2.x */ - UP_INT_EN, /* V2.x */ - CRIT_INT_EN, /* V2.x */ + MIN_STATUS_0, /* MIN threshold violated */ + MIN_STATUS_1, + MIN_STATUS_2, + MIN_STATUS_3, + MIN_STATUS_4, + MIN_STATUS_5, + MIN_STATUS_6, + MIN_STATUS_7, + MIN_STATUS_8, + MIN_STATUS_9, + MIN_STATUS_10, + MIN_STATUS_11, + MIN_STATUS_12, + MIN_STATUS_13, + MIN_STATUS_14, + MIN_STATUS_15, + MAX_STATUS_0, /* MAX threshold violated */ + MAX_STATUS_1, + MAX_STATUS_2, + MAX_STATUS_3, + MAX_STATUS_4, + MAX_STATUS_5, + MAX_STATUS_6, + MAX_STATUS_7, + MAX_STATUS_8, + MAX_STATUS_9, + MAX_STATUS_10, + MAX_STATUS_11, + MAX_STATUS_12, + MAX_STATUS_13, + MAX_STATUS_14, + MAX_STATUS_15, /* Keep last */ MAX_REGFIELDS @@ -303,6 +475,10 @@ struct tsens_priv { struct regmap *tm_map; struct regmap *srot_map; u32 tm_offset; + + /* lock for upper/lower threshold interrupts */ + spinlock_t ul_lock; + struct regmap_field *rf[MAX_REGFIELDS]; struct tsens_context ctx; const struct tsens_features *feat; @@ -320,6 +496,10 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mo int init_common(struct tsens_priv *priv); int get_temp_tsens_valid(struct tsens_sensor *s, int *temp); int get_temp_common(struct tsens_sensor *s, int *temp); +int tsens_enable_irq(struct tsens_priv *priv); +void tsens_disable_irq(struct tsens_priv *priv); +int tsens_set_trips(void *_sensor, int low, int high); +irqreturn_t tsens_irq_thread(int irq, void *data); /* TSENS target */ extern const struct tsens_plat_data data_8960;