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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c254a76729sm4826265a91.0.2024.06.05.20.29.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 20:29:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, alex.bennee@linaro.org Subject: [PATCH v2 1/9] tcg: Introduce INDEX_op_plugin_pc Date: Wed, 5 Jun 2024 20:29:18 -0700 Message-Id: <20240606032926.83599-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606032926.83599-1-richard.henderson@linaro.org> References: <20240606032926.83599-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add an opcode to find a code address within the current insn, for later use with unwinding. Generate the code generically using tcg_reg_alloc_do_movi. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- include/tcg/tcg-op-common.h | 1 + include/tcg/tcg-opc.h | 1 + tcg/tcg-op.c | 5 +++++ tcg/tcg.c | 10 ++++++++++ 4 files changed, 17 insertions(+) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 009e2778c5..a32c88a182 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -76,6 +76,7 @@ void tcg_gen_lookup_and_goto_ptr(void); void tcg_gen_plugin_cb(unsigned from); void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminfo); +void tcg_gen_plugin_pc(TCGv_ptr); /* 32 bit ops */ diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 546eb49c11..087d1b82da 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -199,6 +199,7 @@ DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT) DEF(plugin_mem_cb, 0, 1, 1, TCG_OPF_NOT_PRESENT) +DEF(plugin_pc, 1, 0, 0, TCG_OPF_NOT_PRESENT) /* Replicate ld/st ops for 32 and 64-bit guest addresses. */ DEF(qemu_ld_a32_i32, 1, 1, 1, diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index eff3728622..b8ca78cbe4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -322,6 +322,11 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminfo) tcg_gen_op2(INDEX_op_plugin_mem_cb, tcgv_i64_arg(addr), meminfo); } +void tcg_gen_plugin_pc(TCGv_ptr arg) +{ + tcg_gen_op1(INDEX_op_plugin_pc, tcgv_ptr_arg(arg)); +} + /* 32 bit ops */ void tcg_gen_discard_i32(TCGv_i32 arg) diff --git a/tcg/tcg.c b/tcg/tcg.c index 34e3056380..b7c28d92a6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -4689,6 +4689,13 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) } } +static void tcg_reg_alloc_plugin_pc(TCGContext *s, const TCGOp *op) +{ + tcg_reg_alloc_do_movi(s, arg_temp(op->args[0]), + (uintptr_t)tcg_splitwx_to_rx(s->code_ptr), + op->life, output_pref(op, 0)); +} + /* * Specialized code generation for INDEX_op_dup_vec. */ @@ -6196,6 +6203,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) case INDEX_op_mov_vec: tcg_reg_alloc_mov(s, op); break; + case INDEX_op_plugin_pc: + tcg_reg_alloc_plugin_pc(s, op); + break; case INDEX_op_dup_vec: tcg_reg_alloc_dup(s, op); break; From patchwork Thu Jun 6 03:29:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801976 Delivered-To: patch@linaro.org Received: by 2002:adf:f147:0:b0:35b:5a80:51b4 with SMTP id y7csp96535wro; Wed, 5 Jun 2024 20:31:03 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW7Ch9KrNqWdTvtvwdUxFhAJx/wX+w8kofFnJxVaHQRENjBYvfoZFy+0LStPou1PmineGI7IR65LVRPrVLoRzGy X-Google-Smtp-Source: AGHT+IG/Hr/B7VrotKwZsuzk+pMRvT0lHxe/IMBmePHR9Fqsdro7lSWGE0OqlT2fcCqz99LPCfG4 X-Received: by 2002:a25:b192:0:b0:df7:8e6f:b0fc with SMTP id 3f1490d57ef6-dfacad27254mr4538690276.63.1717644662651; Wed, 05 Jun 2024 20:31:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717644662; cv=none; d=google.com; s=arc-20160816; b=ZA7qHNeEGyJYIP65lpLHzPDjxM8gDoC0sj1reS9DHLrGsjezKcUyyjPVbvrVkHLwd1 UZbABdv3aoaOpNrmmIRmWIdX3lDJI8hI9Q2CqZ+K3UF3PaWwlC8k5H485vxYPSdxZykz +9/lxbUM18liX/puh3dSxdlsFZM3kIQbYZAUwRWwSrXRnc+tzJSD0pSqXebv2seNfabT b+3VAHYCFpBmfIPoqIK9gqMfI8ey90ACT60GSaqM01OirxuKHU7r4+NvenV9puoAr3TL l21sroPh5t4CmTgi5dUdzaRjHvXBdUCWZUMiq6SVaW3q66gEQsLIjNbNEDnqQRKLfebV bf+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7X+3P14YSYVXNQMiOZZLhD74NHSTkNTZimCmiwm+qG4=; fh=DfUxOGz7MnM49MBgqH5VPROGi+97fYtPWhcEZCG1Y5Q=; b=IzP6/hkvsmXjhEnWS7mT8b4xP1cFgiyo1B881MUqaGTQjhbHEGbtUMXU8qqNyEWmsa ZkF2ZpCDavXspsE43caE8PmWEQiXANpZ6NOUddC+x3Oo5eYw7OipnawLyyNd2pXZjO+0 W4fcVBUXlFd9Z6ebM79YmGfCukdUbzu/4s0puH/p0rV1vqE1SSKy/xxTirGfASNPdQRB V8yHLztpOiIH/IKTnMK9777kt/NNalgIw1CDtZrogTHxur+S2Rrj0G/7nQ7HhXWi1E4Y oQOMFt+xZgY3ZoNTC7IK57SccydXQLyem/usslkNmazv69HBTI8h8KlqXW7foeaRXn3q pM3w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vfv9bDgt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c254a76729sm4826265a91.0.2024.06.05.20.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 20:29:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, alex.bennee@linaro.org Subject: [PATCH v2 2/9] accel/tcg: Set CPUState.plugin_ra before all plugin callbacks Date: Wed, 5 Jun 2024 20:29:19 -0700 Message-Id: <20240606032926.83599-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606032926.83599-1-richard.henderson@linaro.org> References: <20240606032926.83599-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Store a host code address to use with the tcg unwinder when called from a plugin. Generate one such store per guest insn that uses a plugin callback. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- include/hw/core/cpu.h | 4 +--- accel/tcg/plugin-gen.c | 49 +++++++++++++++++++++++++++++++++++++----- 2 files changed, 45 insertions(+), 8 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index a2c8536943..19b7fcc9f3 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -354,9 +354,7 @@ typedef union IcountDecr { typedef struct CPUNegativeOffsetState { CPUTLB tlb; #ifdef CONFIG_PLUGIN - /* - * The callback pointer are accessed via TCG (see gen_empty_mem_helper). - */ + uintptr_t plugin_ra; GArray *plugin_mem_cbs; #endif IcountDecr icount_decr; diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index cc1634e7a6..650e3810e6 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -37,6 +37,12 @@ enum plugin_gen_from { PLUGIN_GEN_AFTER_TB, }; +enum plugin_gen_ra { + GEN_RA_DONE, + GEN_RA_FROM_TB, + GEN_RA_FROM_INSN, +}; + /* called before finishing a TB with exit_tb, goto_tb or goto_ptr */ void plugin_gen_disable_mem_helpers(void) { @@ -213,11 +219,37 @@ static void gen_mem_cb(struct qemu_plugin_regular_cb *cb, tcg_temp_free_i32(cpu_index); } -static void inject_cb(struct qemu_plugin_dyn_cb *cb) +static void inject_ra(enum plugin_gen_ra *gen_ra) +{ + TCGv_ptr ra; + switch (*gen_ra) { + case GEN_RA_DONE: + return; + case GEN_RA_FROM_TB: + ra = tcg_constant_ptr(NULL); + break; + case GEN_RA_FROM_INSN: + ra = tcg_temp_ebb_new_ptr(); + tcg_gen_plugin_pc(ra); + break; + default: + g_assert_not_reached(); + } + + tcg_gen_st_ptr(ra, tcg_env, + offsetof(CPUState, neg.plugin_ra) - + offsetof(ArchCPU, env)); + tcg_temp_free_ptr(ra); + *gen_ra = GEN_RA_DONE; +} + +static void inject_cb(struct qemu_plugin_dyn_cb *cb, + enum plugin_gen_ra *gen_ra) { switch (cb->type) { case PLUGIN_CB_REGULAR: + inject_ra(gen_ra); gen_udata_cb(&cb->regular); break; case PLUGIN_CB_COND: @@ -235,19 +267,21 @@ static void inject_cb(struct qemu_plugin_dyn_cb *cb) } static void inject_mem_cb(struct qemu_plugin_dyn_cb *cb, + enum plugin_gen_ra *gen_ra, enum qemu_plugin_mem_rw rw, qemu_plugin_meminfo_t meminfo, TCGv_i64 addr) { switch (cb->type) { case PLUGIN_CB_MEM_REGULAR: if (rw && cb->regular.rw) { + inject_ra(gen_ra); gen_mem_cb(&cb->regular, meminfo, addr); } break; case PLUGIN_CB_INLINE_ADD_U64: case PLUGIN_CB_INLINE_STORE_U64: if (rw && cb->inline_insn.rw) { - inject_cb(cb); + inject_cb(cb, gen_ra); } break; default: @@ -260,6 +294,7 @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb) { TCGOp *op, *next; int insn_idx = -1; + enum plugin_gen_ra gen_ra; if (unlikely(qemu_loglevel_mask(LOG_TB_OP_PLUGIN) && qemu_log_in_addr_range(tcg_ctx->plugin_db->pc_first))) { @@ -279,10 +314,12 @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb) */ memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps)); + gen_ra = GEN_RA_FROM_TB; QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) { switch (op->opc) { case INDEX_op_insn_start: insn_idx++; + gen_ra = GEN_RA_FROM_INSN; break; case INDEX_op_plugin_cb: @@ -318,7 +355,8 @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb) cbs = plugin_tb->cbs; for (i = 0, n = (cbs ? cbs->len : 0); i < n; i++) { inject_cb( - &g_array_index(cbs, struct qemu_plugin_dyn_cb, i)); + &g_array_index(cbs, struct qemu_plugin_dyn_cb, i), + &gen_ra); } break; @@ -330,7 +368,8 @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb) cbs = insn->insn_cbs; for (i = 0, n = (cbs ? cbs->len : 0); i < n; i++) { inject_cb( - &g_array_index(cbs, struct qemu_plugin_dyn_cb, i)); + &g_array_index(cbs, struct qemu_plugin_dyn_cb, i), + &gen_ra); } break; @@ -362,7 +401,7 @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb) cbs = insn->mem_cbs; for (i = 0, n = (cbs ? cbs->len : 0); i < n; i++) { inject_mem_cb(&g_array_index(cbs, struct qemu_plugin_dyn_cb, i), - rw, meminfo, addr); + &gen_ra, rw, meminfo, addr); } tcg_ctx->emit_before_op = NULL; From patchwork Thu Jun 6 03:29:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801973 Delivered-To: patch@linaro.org Received: by 2002:adf:f147:0:b0:35b:5a80:51b4 with SMTP id y7csp96392wro; Wed, 5 Jun 2024 20:30:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU1KslOj0OsRSpgZaTvbrWT+x68ySKTMayr2w0nsf6DEUCe7VtxoTkuw5qdbWr01FuRLxfVcnGA+lquiuzziK06 X-Google-Smtp-Source: AGHT+IFp//X72BteBJQgHLaDB88fN2zYaYOhMBMrMQzDrZLnRE4TWwxJGRjrG28C7bpBRYgJBAw9 X-Received: by 2002:a05:622a:30b:b0:43d:f44e:8271 with SMTP id d75a77b69052e-4402b5de52fmr47771841cf.40.1717644629362; Wed, 05 Jun 2024 20:30:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717644629; cv=none; d=google.com; s=arc-20160816; b=CySxFPCgGUbE7b5QvaqL7Hg9Gjdt0ddbAtWkKBhGAh/mc3NfALLF84Nc5p0u/UX9hf oM92hDCZaid6Bp66nL+kH/RSgt7LomPgNFTmI+eYtXtJdmqd7jv7WCm53AFu/t7Nvdf0 pDekH5jTmPLPdfFAzSYJbO4h1yKRHObeT2CwQRVvE/ueIBtK4PiO/veYZC5nA+rRxPXC 3GUTpjCVrAtd8RCUHW+2YoRRZc1PB4mqQBzD+qm+jvuX6Mmrb05OFof333aTeMS3x+dA WtgqUSQ8MH3rRuFwXD3fuH2j2geZFsfy6jcQPtU0Kgy7JldnWj6NxuaKwg8KT3gluKiY RCpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=24NTC+fN8JzFiuW9KudaNDXejfk5/YoKTwKq+1qKbsQ=; fh=DfUxOGz7MnM49MBgqH5VPROGi+97fYtPWhcEZCG1Y5Q=; b=kXCXALLYM/aRkRaXl3dED3GLqeSEDzFvp1LedTsSI9UFVSTtY3OgFSYqInkuktq+qU pDsV5DRXc4dM2I24fWa7r4GFcTQLJa2t0L4sB54cWfimKZdSQUkTcaxY/Q+Wfc1YDmkj qOTTk+YZr0sRPBXICZzIs/mcea2z0aaSBIQ13iraeaxwa7uAJ8kGUh+hQBWRt0B3zW/o LvgqMgRGx1aDbYX0j/3/ncDzdzsUJX3Uz64ASJgjC+DBfmVRSdauM72wI2wthDJUNwp5 HT14ZOxJkfPWCueyjyd3e91L2cyV4iR2uNd+EtWon4oUS/O53SBISessK91PZCSxCLm6 lWXQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GPePFfqN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c254a76729sm4826265a91.0.2024.06.05.20.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 20:29:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, alex.bennee@linaro.org Subject: [PATCH v2 3/9] accel/tcg: Return the TranslationBlock from cpu_unwind_state_data Date: Wed, 5 Jun 2024 20:29:20 -0700 Message-Id: <20240606032926.83599-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606032926.83599-1-richard.henderson@linaro.org> References: <20240606032926.83599-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Adjust the i386 get_memio_eip function to use tb->cflags instead of tcg_cflags_has, which is technically more correct. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- include/exec/cpu-common.h | 9 +++++---- accel/tcg/translate-all.c | 9 +++++---- target/i386/helper.c | 6 ++++-- 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 815342d043..c1887462e6 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -189,12 +189,13 @@ uint32_t curr_cflags(CPUState *cpu); * @host_pc: the host pc within the translation * @data: output data * - * Attempt to load the the unwind state for a host pc occurring in - * translated code. If @host_pc is not in translated code, the - * function returns false; otherwise @data is loaded. + * Attempt to load the the unwind state for a host pc occurring in translated + * code. If @host_pc is not in translated code, the function returns NULL; + * otherwise @data is loaded and the TranslationBlock is returned. * This is the same unwind info as given to restore_state_to_opc. */ -bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); +const TranslationBlock *cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, + uint64_t *data); /** * cpu_restore_state: diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index fdf6d8ac19..45a1cf57bc 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -243,15 +243,16 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) return false; } -bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data) +const TranslationBlock * +cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data) { if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) { TranslationBlock *tb = tcg_tb_lookup(host_pc); - if (tb) { - return cpu_unwind_data_from_tb(tb, host_pc, data) >= 0; + if (tb && cpu_unwind_data_from_tb(tb, host_pc, data) >= 0) { + return tb; } } - return false; + return NULL; } void page_init(void) diff --git a/target/i386/helper.c b/target/i386/helper.c index f9d1381f90..565e01a3a9 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -521,13 +521,15 @@ static inline target_ulong get_memio_eip(CPUX86State *env) #ifdef CONFIG_TCG uint64_t data[TARGET_INSN_START_WORDS]; CPUState *cs = env_cpu(env); + const TranslationBlock *tb; - if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) { + tb = cpu_unwind_state_data(cs, cs->mem_io_pc, data); + if (!tb) { return env->eip; } /* Per x86_restore_state_to_opc. */ - if (tcg_cflags_has(cs, CF_PCREL)) { + if (tb->cflags & CF_PCREL) { return (env->eip & TARGET_PAGE_MASK) | data[0]; } else { return data[0] - env->segs[R_CS].base; From patchwork Thu Jun 6 03:29:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801968 Delivered-To: patch@linaro.org Received: by 2002:adf:f147:0:b0:35b:5a80:51b4 with SMTP id y7csp96219wro; Wed, 5 Jun 2024 20:29:53 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU/fJZXqdbHkn4Rw3vjvA7QB9vjNByWcMMgBnFCitgr8y/VDyWzgt24tOkftSCl356zukpeeYvTEW1P+Y60FEqT X-Google-Smtp-Source: AGHT+IHLTNMjWd1Nlh0kUG+bvhQl5QjzA0VnhyUN0hbH/vHZPuGzqVlXk+5Qdv6w61uu0a8xoY3X X-Received: by 2002:ac8:7c44:0:b0:43e:11a5:ca21 with SMTP id d75a77b69052e-4403628d750mr29223701cf.21.1717644593422; Wed, 05 Jun 2024 20:29:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717644593; cv=none; d=google.com; s=arc-20160816; b=se29Alezx8gIZyxErcDHW36G3rHGyPDiYAGSJZow977YGL9FWvhkMQddfGTK/CfnPw aIgWXWxoSk1WiJvmMmttCwm5qR15tmMQDmkLj6RWxfIy1VxKx+Hj7n5S1H3P1kNRwf10 Yyzr2D33NbpW+VEwxwECs4s60bik448j3SIMqupuCK/ED7sz1Msa61ZfKf7h5rVw8hCh kt83wOV1RUWsG7uHjSDp05gcIWhocSkYzhIqPMc45JimHq61i0+aqJMjkXfWrSMEuEU6 bieinbR6IyUfMUWtetIILTmMSpTDpvY54DM7xEmT5THgkLqUgJDMXzScjkz7OFM8DQ4a VxmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=C1FZU7Kp9GU8lGWAPo6y4bl6njrrndV/cpVZs+Mkosw=; fh=DfUxOGz7MnM49MBgqH5VPROGi+97fYtPWhcEZCG1Y5Q=; b=BYp/VCIOpJbOJ3qzp4aKnR6ZG6e+ROQmo0Jvza0fjybjbA4Dlha/oliIxeypbr7eJK fQ2lbgaA45Kb7SptHSXKdhtA7yanFFptgj/P5gstD5GFcFdr/0zTZvwkAerfL1CVb+fR xBPPOq/18na6XQLykhzPLwCYjTCnfsuUX41OjMCDftwl3L/fFJINVmvXO9G1uJ+YOvcL jxEZfHCy1+6qWPZVdrfEpEJ4H00+E/noMEjvsRd600tcs3hQfTRrijXJHD93ZkqNpySo azOdsraBTp6E6u0lg2mw8EtPFiy0QKqruVyI5iJ+pDJvn+fwbyYQMfI7cwoeGvzpxRFM 08+g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x67uD4W+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c254a76729sm4826265a91.0.2024.06.05.20.29.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 20:29:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, alex.bennee@linaro.org Subject: [PATCH v2 4/9] plugins: Introduce TCGCPUOps callbacks for mid-tb register reads Date: Wed, 5 Jun 2024 20:29:21 -0700 Message-Id: <20240606032926.83599-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606032926.83599-1-richard.henderson@linaro.org> References: <20240606032926.83599-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Certain target registers are not updated continuously within the translation block. For normal exception handling we use unwind info to re-generate the correct value when required. Leverage that same info for reading those registers for plugins. All targets will need updating for these new callbacks. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- include/hw/core/tcg-cpu-ops.h | 14 ++++++++++++++ plugins/api.c | 36 +++++++++++++++++++++++++++++++++-- 2 files changed, 48 insertions(+), 2 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 099de3375e..b34f999e78 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -53,6 +53,20 @@ struct TCGCPUOps { /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); + /** + * @plugin_need_unwind_for_reg: + * True if unwind info needed for reading reg. + */ + bool (*plugin_need_unwind_for_reg)(CPUState *cpu, int reg); + /** + * @plugin_unwind_read_reg: + * Like CPUClass.gdb_read_register, but for registers that require + * regeneration using unwind info, like in @restore_state_to_opc. + */ + int (*plugin_unwind_read_reg)(CPUState *cpu, GByteArray *buf, int reg, + const TranslationBlock *tb, + const uint64_t *data); + #ifdef CONFIG_USER_ONLY /** * @fake_user_interrupt: Callback for 'fake exception' handling. diff --git a/plugins/api.c b/plugins/api.c index 5a0a7f8c71..53127ed9ee 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -40,10 +40,12 @@ #include "qemu/plugin.h" #include "qemu/log.h" #include "tcg/tcg.h" +#include "tcg/insn-start-words.h" #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "exec/translator.h" #include "disas/disas.h" +#include "hw/core/tcg-cpu-ops.h" #include "plugin.h" #ifndef CONFIG_USER_ONLY #include "exec/ram_addr.h" @@ -526,9 +528,39 @@ GArray *qemu_plugin_get_registers(void) int qemu_plugin_read_register(struct qemu_plugin_register *reg, GByteArray *buf) { - g_assert(current_cpu); + CPUState *cs; + uintptr_t ra; + int regno; - return gdb_read_register(current_cpu, buf, GPOINTER_TO_INT(reg)); + assert(current_cpu); + cs = current_cpu; + ra = cs->neg.plugin_ra; + regno = GPOINTER_TO_INT(reg); + + /* + * When plugin_ra is 0, we have no unwind info. This will be true for + * TB callbacks that happen before any insns of the TB have started. + */ + if (ra) { + const TCGCPUOps *tcg_ops = cs->cc->tcg_ops; + + /* + * For plugins in the middle of the TB, we may need to locate + * and use unwind data to reconstruct a register value. + * Usually this required for the PC, but there may be others. + */ + if (tcg_ops->plugin_need_unwind_for_reg && + tcg_ops->plugin_need_unwind_for_reg(cs, regno)) { + uint64_t data[TARGET_INSN_START_WORDS]; + const TranslationBlock *tb; + + tb = cpu_unwind_state_data(cs, ra, data); + assert(tb); + return tcg_ops->plugin_unwind_read_reg(cs, buf, regno, tb, data); + } + } + + return gdb_read_register(cs, buf, regno); } struct qemu_plugin_scoreboard *qemu_plugin_scoreboard_new(size_t element_size) From patchwork Thu Jun 6 03:29:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801970 Delivered-To: patch@linaro.org Received: by 2002:adf:f147:0:b0:35b:5a80:51b4 with SMTP id y7csp96321wro; Wed, 5 Jun 2024 20:30:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWeRajsofBcS6rgDRW1okRKFDthrzBT7k79RDGENzqsAyftRWa/WgpkSazoqd5dz+h0oI3EGJNFqOCwFEvrG5Ep X-Google-Smtp-Source: AGHT+IHNPZzbKDOMTxbZYBBOaCsj2jEFSpZlvaA3qTqGUdZicP7eb1Bz0NVF8I/5zIC45duooHAQ X-Received: by 2002:a05:6830:4b9:b0:6f8:e8e1:ae73 with SMTP id 46e09a7af769-6f943483f2amr5158654a34.20.1717644614928; Wed, 05 Jun 2024 20:30:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717644614; cv=none; d=google.com; s=arc-20160816; b=AG2znvMkuT032NaSTI3tVLhBtUPlriPAuAN5GjEvHtbP8jsvMkm7rYSdamlhaSHw3Y SZgmlVCs7WauvN1bD5BPP2mxmC/OUYHKZVrT2UzYl8MoM0uyn5bytxA5TydnqTChMEp/ /YKmmhTzG/BpVw85ooGArNoUCnL0YrfG5cYq2tyg8FdSl5EKXs5UnjvNhXzEqn0R6mic YFzpkq2bcPbMWfWO02RKWL8iXUgkgpYdvjAydLanB8cYoogAymIm3izVDqCA2VoHcxAu YAO16cCAAVeCNjf4UjsGKnCThgsLubxYl0g0LUyAikFhzQmYQJsa/udHD8yx26lgczqt k8Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1OdJEwOKA51hh/7jatyHlydDt1TQ7phcNBkbolfhN74=; fh=DfUxOGz7MnM49MBgqH5VPROGi+97fYtPWhcEZCG1Y5Q=; b=NY/4wN+hlih64GBJaD4UAHXyy+b9JRMNcum8Z4nYhA1P/QMIObp/e2Pxb/PhmQkdFN S3nU4EXxBWyGabBqyxSvcxHSMbAd0CMV6W6ZOOVhNxpsVzKdINruEZ/xxr0uj7hho7VN obAMRf7omX65h3zdPh21BGUoawUHnPR3IXXCnzsHrAfVJk5Wotam2yUuhPPNdPuBv6Qt 9x+KLbuQIMKcYyAskMmIZD2ta28VftiaGUK16OqIPlF4E9dUXMWXiCqnzNq3CLGLCklO AhOXO/u1OlD+YKLyotIMIVWfb/WHfLeXLjleJwkQnrIKSGFxvYc6pBY4cshoI3PHnpK9 A++w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="CSM/W7SI"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c254a76729sm4826265a91.0.2024.06.05.20.29.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 20:29:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, alex.bennee@linaro.org Subject: [PATCH v2 5/9] target/i386: Split out gdb-internal.h Date: Wed, 5 Jun 2024 20:29:22 -0700 Message-Id: <20240606032926.83599-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606032926.83599-1-richard.henderson@linaro.org> References: <20240606032926.83599-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Alex Bennée Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/i386/gdb-internal.h | 65 ++++++++++++++++++++++++++++++++++++++ target/i386/gdbstub.c | 1 + 2 files changed, 66 insertions(+) create mode 100644 target/i386/gdb-internal.h diff --git a/target/i386/gdb-internal.h b/target/i386/gdb-internal.h new file mode 100644 index 0000000000..7cf4c1a656 --- /dev/null +++ b/target/i386/gdb-internal.h @@ -0,0 +1,65 @@ +/* + * x86 gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef I386_GDB_INTERNAL_H +#define I386_GDB_INTERNAL_H + +/* + * Keep these in sync with assignment to + * gdb_num_core_regs in target/i386/cpu.c + * and with the machine description + */ + +/* + * SEG: 6 segments, plus fs_base, gs_base, kernel_gs_base + */ + +/* + * general regs -----> 8 or 16 + */ +#define IDX_NB_IP 1 +#define IDX_NB_FLAGS 1 +#define IDX_NB_SEG (6 + 3) +#define IDX_NB_CTL 6 +#define IDX_NB_FP 16 +/* + * fpu regs ----------> 8 or 16 + */ +#define IDX_NB_MXCSR 1 +/* + * total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66 + */ + +#define IDX_IP_REG CPU_NB_REGS +#define IDX_FLAGS_REG (IDX_IP_REG + IDX_NB_IP) +#define IDX_SEG_REGS (IDX_FLAGS_REG + IDX_NB_FLAGS) +#define IDX_CTL_REGS (IDX_SEG_REGS + IDX_NB_SEG) +#define IDX_FP_REGS (IDX_CTL_REGS + IDX_NB_CTL) +#define IDX_XMM_REGS (IDX_FP_REGS + IDX_NB_FP) +#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS) + +#define IDX_CTL_CR0_REG (IDX_CTL_REGS + 0) +#define IDX_CTL_CR2_REG (IDX_CTL_REGS + 1) +#define IDX_CTL_CR3_REG (IDX_CTL_REGS + 2) +#define IDX_CTL_CR4_REG (IDX_CTL_REGS + 3) +#define IDX_CTL_CR8_REG (IDX_CTL_REGS + 4) +#define IDX_CTL_EFER_REG (IDX_CTL_REGS + 5) + +#endif diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 4acf485879..96b4382a5d 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "gdbstub/helpers.h" +#include "gdb-internal.h" #ifdef TARGET_X86_64 static const int gpr_map[16] = { From patchwork Thu Jun 6 03:29:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801977 Delivered-To: patch@linaro.org Received: by 2002:adf:f147:0:b0:35b:5a80:51b4 with SMTP id y7csp96557wro; Wed, 5 Jun 2024 20:31:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUY+eHf+JrRx1WLGk7SZLOZhXULnHpgJIbw0zMUL6RgCIcCT8JDTZq1IfndfFVSCERHjDrNXQBFfWPBiMV5hvvR X-Google-Smtp-Source: AGHT+IF27lLONCWVbubChwDEYX9ShFQM4V1a8b/k1+cZ3aqrGZ/RFZsHV/27PwcTq0eixJP4DIGp X-Received: by 2002:a05:622a:3cf:b0:43e:1231:1040 with SMTP id d75a77b69052e-44036267b85mr27732391cf.20.1717644665937; Wed, 05 Jun 2024 20:31:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717644665; cv=none; d=google.com; s=arc-20160816; b=j/wDsRWBQ9src8oa+bDyMO+rhUD25BlmvSgU1rt0THi8iKfU4yLpITdSdSm+2AUq6V kDELON9kGaOvJyG47/9FRDinPCViqcDAw8CJ9otjMmQLcIAPa8F6KRf729FTBM/+lXWR Hz4NAh7TYbk8M/P2NFuvCdD1kBF62ctGorxGrRuoYtyRXG9SaIrdSHajUhdCf6N6KeU5 uJbFUPln/6m8PLJ/zZuXcVO+TIX2GAnzg0FGtXuhc5F5AGfMgIfn263H2dm9PTNels+U 8NyGYGwCxy9KGyAQDhdXqtTNgilk4PovJIRRG/IhKA9Ru2szQK4fomS8hxCSoNDrOCRQ Q1og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+Ta0pM6KcQt7rsvA3Ju6z7MgKxBm5RGfKrSL9DmIR7Q=; fh=DfUxOGz7MnM49MBgqH5VPROGi+97fYtPWhcEZCG1Y5Q=; b=un0RFqS/84pvNULZhLIppoMvhIEy5m2WPeLaEqiT5i4u71XgShK9Nl7HGxkpsspwQJ Z+Nd0K//WqLH758+tWzmIK4+mo4fCO8LqBxBHDSFl15zRwDg7F7WdGQexrNKW1r+VkWu obtW8INCVjMoKQvLxrIEVDX8jtZ5efRHEEqZRPW5vGKRwO2Dntz/lIDSlbUr9BMlQHv5 BqJMymSDdwbtU1rXDbH8qpG7S8Tw3d3/jGXUuFoOaIjo4sdhlD8znwhLF4mzIouleEmp m5wkyl7SO1D1Dxyxcp/wJMUaEZCOX55tWPObudSytEmscLldOhzWEKc/F1AS9+7V8uaD 3iaQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yF5Jty6E; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c254a76729sm4826265a91.0.2024.06.05.20.29.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 20:29:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, alex.bennee@linaro.org Subject: [PATCH v2 6/9] target/i386: Introduce cpu_compute_eflags_ccop Date: Wed, 5 Jun 2024 20:29:23 -0700 Message-Id: <20240606032926.83599-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606032926.83599-1-richard.henderson@linaro.org> References: <20240606032926.83599-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is a generalization of cpu_compute_eflags, with a dynamic value of cc_op, and is thus tcg specific. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/i386/cpu.h | 2 ++ target/i386/tcg/cc_helper.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c64ef0c1a2..48ad6f495b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2431,6 +2431,8 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, uint32_t cpu_cc_compute_all(CPUX86State *env1); +uint32_t cpu_compute_eflags_ccop(CPUX86State *env, CCOp op); + static inline uint32_t cpu_compute_eflags(CPUX86State *env) { uint32_t eflags = env->eflags; diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c index f76e9cb8cf..8203682ca8 100644 --- a/target/i386/tcg/cc_helper.c +++ b/target/i386/tcg/cc_helper.c @@ -225,6 +225,16 @@ uint32_t cpu_cc_compute_all(CPUX86State *env) return helper_cc_compute_all(CC_DST, CC_SRC, CC_SRC2, CC_OP); } +uint32_t cpu_compute_eflags_ccop(CPUX86State *env, CCOp op) +{ + uint32_t eflags; + + eflags = helper_cc_compute_all(CC_DST, CC_SRC, CC_SRC2, op); + eflags |= env->df & DF_MASK; + eflags |= env->eflags & ~(VM_MASK | RF_MASK); + return eflags; +} + target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1, target_ulong src2, int op) { From patchwork Thu Jun 6 03:29:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801972 Delivered-To: patch@linaro.org Received: by 2002:adf:f147:0:b0:35b:5a80:51b4 with SMTP id y7csp96359wro; Wed, 5 Jun 2024 20:30:22 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU/67iRKMMh6BsmCEdaaNHPfude7BL5CvrGQafUDCPkEH4vJOlKs6VBB2JW0ipr4s1j9ENmLzA9m0DE2mV7cFEn X-Google-Smtp-Source: AGHT+IFIc3Dp5huIlMljU5H2ZUDZcbmN4vynljaWhxJQXwLLvV4GEcsHuNMdOG5xxO6wBk4VS8CU X-Received: by 2002:a05:620a:46a9:b0:794:fa8f:41ba with SMTP id af79cd13be357-79523ec287cmr614463085a.60.1717644622654; Wed, 05 Jun 2024 20:30:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717644622; cv=none; d=google.com; s=arc-20160816; b=lKhxJkA6akqDY4Q7tfcBNRhg6FrR7HOjWUXRmY4k8/OaVp0CQZCbDo93iF3M7mf7f1 uTWoxViOuoHQ8flFOB4el1tCEKYp2cTiBde54ZBJYHnh8mMKnQSIJt+1Wqt74Z1thMwN Tb1OGISfMXnYv6/f5+0ex9NHgk5eQczRY2o/czHP1LGYj06vUvUcwv4w8Ga17S3x8EWa jj3b95b4FsPg56B3MuNngcedgOxRzXoDPnM6XYkZ0b9PQdruL5QA+Odp1sVMzzCLMu9x FBpssVmcHEng3L2RCwaOJ9RK5EWTGsDTmgG0GOGzgNk7RId6xD8e04+pnT9zPPUY0z/V rwKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=O0va1mHnZfjZEpAwkwYedRlpjIR4vW0RMlDktvC8XHk=; fh=DfUxOGz7MnM49MBgqH5VPROGi+97fYtPWhcEZCG1Y5Q=; b=Ltd3AdCbrrToFpLR2rhCaAUhIQuU0agqUw7iG7D8rJNXAbVlGAcMAVDhwzY3YiRFo7 5q4f9pkRpCtKfhSUsI50WkIzHIs57ki2Vhil9hM6lZMQi0tnCPbYoQ1L3b/8gZ/FexGq rSe0is3Z4UP8vhIVEDg4wCJP4slvPy58W5hD3k6j8cb7J0F0fvNto0jIbWsN809BmWsp u4b3gDZHI/2Y5GRI+73dnhKqO1aCLyeqfq7z4QYaAz6xaQyCEmxC6jrKrR7+mBr46TCH qPiLAy86QeYpMSvqViIHA9G77SB8QC7JxCnvAy2h+T6oQzL6o8O3BCjTkydMP5eavTfE cEsg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hxRI3vtG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c254a76729sm4826265a91.0.2024.06.05.20.29.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 20:29:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, alex.bennee@linaro.org Subject: [PATCH v2 7/9] target/i386: Implement TCGCPUOps for plugin register reads Date: Wed, 5 Jun 2024 20:29:24 -0700 Message-Id: <20240606032926.83599-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606032926.83599-1-richard.henderson@linaro.org> References: <20240606032926.83599-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/i386/tcg/tcg-cpu.c | 72 ++++++++++++++++++++++++++++++--------- 1 file changed, 56 insertions(+), 16 deletions(-) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index cca19cd40e..2370053df2 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -22,9 +22,11 @@ #include "helper-tcg.h" #include "qemu/accel.h" #include "hw/core/accel-cpu.h" - +#include "gdbstub/helpers.h" +#include "gdb-internal.h" #include "tcg-cpu.h" + /* Frob eflags into and out of the CPU temporary format. */ static void x86_cpu_exec_enter(CPUState *cs) @@ -61,38 +63,74 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, } } -static void x86_restore_state_to_opc(CPUState *cs, - const TranslationBlock *tb, - const uint64_t *data) +static uint64_t eip_from_unwind(CPUX86State *env, const TranslationBlock *tb, + uint64_t data0) { - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - int cc_op = data[1]; uint64_t new_pc; if (tb_cflags(tb) & CF_PCREL) { /* - * data[0] in PC-relative TBs is also a linear address, i.e. an address with - * the CS base added, because it is not guaranteed that EIP bits 12 and higher - * stay the same across the translation block. Add the CS base back before - * replacing the low bits, and subtract it below just like for !CF_PCREL. + * data[0] in PC-relative TBs is also a linear address, + * i.e. an address with the CS base added, because it is + * not guaranteed that EIP bits 12 and higher stay the + * same across the translation block. Add the CS base + * back before replacing the low bits, and subtract it + * below just like for !CF_PCREL. */ uint64_t pc = env->eip + tb->cs_base; - new_pc = (pc & TARGET_PAGE_MASK) | data[0]; + new_pc = (pc & TARGET_PAGE_MASK) | data0; } else { - new_pc = data[0]; + new_pc = data0; } if (tb->flags & HF_CS64_MASK) { - env->eip = new_pc; - } else { - env->eip = (uint32_t)(new_pc - tb->cs_base); + return new_pc; } + return (uint32_t)(new_pc - tb->cs_base); +} +static void x86_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data) +{ + CPUX86State *env = cpu_env(cs); + CCOp cc_op; + + env->eip = eip_from_unwind(env, tb, data[0]); + + cc_op = data[1]; if (cc_op != CC_OP_DYNAMIC) { env->cc_op = cc_op; } } +static bool x86_plugin_need_unwind_for_reg(CPUState *cs, int reg) +{ + return reg == IDX_IP_REG || reg == IDX_FLAGS_REG; +} + +static int x86_plugin_unwind_read_reg(CPUState *cs, GByteArray *buf, int reg, + const TranslationBlock *tb, + const uint64_t *data) +{ + CPUX86State *env = cpu_env(cs); + CCOp cc_op; + + switch (reg) { + case IDX_IP_REG: + return gdb_get_regl(buf, eip_from_unwind(env, tb, data[0])); + + case IDX_FLAGS_REG: + cc_op = data[1]; + if (cc_op == CC_OP_DYNAMIC) { + cc_op = env->cc_op; + } + return gdb_get_reg32(buf, cpu_compute_eflags_ccop(env, cc_op)); + + default: + g_assert_not_reached(); + } +} + #ifndef CONFIG_USER_ONLY static bool x86_debug_check_breakpoint(CPUState *cs) { @@ -110,6 +148,8 @@ static const TCGCPUOps x86_tcg_ops = { .initialize = tcg_x86_init, .synchronize_from_tb = x86_cpu_synchronize_from_tb, .restore_state_to_opc = x86_restore_state_to_opc, + .plugin_need_unwind_for_reg = x86_plugin_need_unwind_for_reg, + .plugin_unwind_read_reg = x86_plugin_unwind_read_reg, .cpu_exec_enter = x86_cpu_exec_enter, .cpu_exec_exit = x86_cpu_exec_exit, #ifdef CONFIG_USER_ONLY From patchwork Thu Jun 6 03:29:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801974 Delivered-To: patch@linaro.org Received: by 2002:adf:f147:0:b0:35b:5a80:51b4 with SMTP id y7csp96478wro; Wed, 5 Jun 2024 20:30:51 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVa0r3zcZtW2vBhq9HFKxuC3/xxkDhXa3g544GqbVI2kID0X73uJ+sRTRWcZPQc4hLoOP4DSCmvtDoTN9rcWLAe X-Google-Smtp-Source: AGHT+IECAeoYuNEUKmLcQa7Wrks2SjckktjdZWCyGWtu20wh9u+6l6BrWWl9Q9HIDloETkQn1G2+ X-Received: by 2002:a05:6808:981:b0:3d2:8a3:f238 with SMTP id 5614622812f47-3d208a3f44amr2322715b6e.46.1717644650935; Wed, 05 Jun 2024 20:30:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717644650; cv=none; d=google.com; s=arc-20160816; b=oSFUhrCDhPsIQXiPKmpCXlzWUIfMwzys1FI08XsFSzFNVqfGoeVrMY/wSoACF7eCGL M+zXloS/rO7JYHPygs3gpmKAQ8f64xcQk/VckO6VKJH0x+JcAIVL9MdMCwNuWkdlooXt YivaLH+MAVBK2KLSpu3SVDnY5Ux7RNclTqRTPDjo4kjzCcZs2LkeN30X48+GPeyWX6qZ o4KaLxAdhjH2vcI23/N1784AZqcHyNGPEC0ov7vNan2fKYefd7BpwJyXssFTvR2222YA WcY/njjbVTV9KWpKMZlfevMf88HQ9r8ZjfpJpJql1GxhtJo3BOkc9e8cLXc9mwumq2Y2 drjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qk6fRoAsjXUiIOMAFv1hh9xLZybNH+lhJEtz8n7pvqs=; fh=DfUxOGz7MnM49MBgqH5VPROGi+97fYtPWhcEZCG1Y5Q=; b=mNrWw0P5k3FMfB5mI2Z9rv3wYJ6nH7PmQmH33u1cJ1HykfS8banLsXIuezxeBgDWYo FPLQoBF1VTvI3xJOqHW/RR0abZuttnzoyZ0IMHsB258eyFdUpCj3afo2eNHSbBkIN+ju ebBNh6OEWHnNwUQ+G7eN6M3Uq9gBXBramglPYU0LWq+M5HrzFNgwo07haO2i5y8TBASy bgRUuVQit2iKmDSsdboV0rCDPivYBRc8ruTitLjFhECxvzNfMV1QFsBd5EskYZuSXLq8 YapBnQ5wDeXcXC3jjzF4iVKIFzuug9U1EF1APWnE6jZixUlPBz2jxxpEAMuSgZoGFDvh XrPA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A4LWK6yH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c254a76729sm4826265a91.0.2024.06.05.20.29.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 20:29:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, alex.bennee@linaro.org Subject: [PATCH v2 8/9] target/arm: Add aarch64_tcg_ops Date: Wed, 5 Jun 2024 20:29:25 -0700 Message-Id: <20240606032926.83599-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606032926.83599-1-richard.henderson@linaro.org> References: <20240606032926.83599-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For the moment, this is an exact copy of arm_tcg_ops. Export arm_cpu_exec_interrupt for the cross-file reference. Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/cpu.c | 2 +- target/arm/cpu64.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 11b5da2562..dc53d86249 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -364,6 +364,7 @@ void arm_restore_state_to_opc(CPUState *cs, #ifdef CONFIG_TCG void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); +bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request); #endif /* CONFIG_TCG */ typedef enum ARMFPRounding { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 35fa281f1b..3cd4711064 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -824,7 +824,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, return unmasked || pstate_unmasked; } -static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); CPUARMState *env = cpu_env(cs); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 262a1d6c0b..7ba80099af 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -31,6 +31,9 @@ #include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +#endif #include "internals.h" #include "cpu-features.h" #include "cpregs.h" @@ -793,6 +796,29 @@ static const gchar *aarch64_gdb_arch_name(CPUState *cs) return "aarch64"; } +#ifdef CONFIG_TCG +static const TCGCPUOps aarch64_tcg_ops = { + .initialize = arm_translate_init, + .synchronize_from_tb = arm_cpu_synchronize_from_tb, + .debug_excp_handler = arm_debug_excp_handler, + .restore_state_to_opc = arm_restore_state_to_opc, + +#ifdef CONFIG_USER_ONLY + .record_sigsegv = arm_cpu_record_sigsegv, + .record_sigbus = arm_cpu_record_sigbus, +#else + .tlb_fill = arm_cpu_tlb_fill, + .cpu_exec_interrupt = arm_cpu_exec_interrupt, + .do_interrupt = arm_cpu_do_interrupt, + .do_transaction_failed = arm_cpu_do_transaction_failed, + .do_unaligned_access = arm_cpu_do_unaligned_access, + .adjust_watchpoint_address = arm_adjust_watchpoint_address, + .debug_check_watchpoint = arm_debug_check_watchpoint, + .debug_check_breakpoint = arm_debug_check_breakpoint, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); @@ -802,6 +828,10 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_core_xml_file = "aarch64-core.xml"; cc->gdb_arch_name = aarch64_gdb_arch_name; +#ifdef CONFIG_TCG + cc->tcg_ops = &aarch64_tcg_ops; +#endif + object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, aarch64_cpu_set_aarch64); object_class_property_set_description(oc, "aarch64", From patchwork Thu Jun 6 03:29:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801975 Delivered-To: patch@linaro.org Received: by 2002:adf:f147:0:b0:35b:5a80:51b4 with SMTP id y7csp96481wro; Wed, 5 Jun 2024 20:30:52 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVBkBKzgmjQymViuFx5KfGwgehAPArDX33XunF+HA/EV75wm2iQzfWvZ1YgEhGX/61gYaLnAqnvcgksOvCkLOWC X-Google-Smtp-Source: AGHT+IF1/+dO3X/PW8uY23UoW3aXB9XinnthtoCSw6ca7w7aJHvG0nUWKRI8Qno2MFssQnCBPNJM X-Received: by 2002:a05:6830:1553:b0:6ef:9156:c814 with SMTP id 46e09a7af769-6f9437d758fmr4802174a34.32.1717644651922; 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c254a76729sm4826265a91.0.2024.06.05.20.29.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 20:29:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, alex.bennee@linaro.org Subject: [PATCH v2 9/9] target/arm: Implement TCGCPUOps for plugin register reads Date: Wed, 5 Jun 2024 20:29:26 -0700 Message-Id: <20240606032926.83599-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606032926.83599-1-richard.henderson@linaro.org> References: <20240606032926.83599-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/internals.h | 7 +++++-- target/arm/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++ target/arm/cpu64.c | 25 +++++++++++++++++++++++++ target/arm/tcg/cpu-v7m.c | 2 ++ 4 files changed, 70 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index dc53d86249..fe28937515 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -358,11 +358,14 @@ void init_cpreg_list(ARMCPU *cpu); void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); +#ifdef CONFIG_TCG void arm_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data); - -#ifdef CONFIG_TCG +bool arm_plugin_need_unwind_for_reg(CPUState *cs, int reg); +int arm_plugin_unwind_read_reg(CPUState *cs, GByteArray *buf, int reg, + const TranslationBlock *tb, + const uint64_t *data); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request); #endif /* CONFIG_TCG */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3cd4711064..e8ac3da351 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -29,6 +29,7 @@ #include "cpu.h" #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" +#include "gdbstub/helpers.h" #endif /* CONFIG_TCG */ #include "internals.h" #include "cpu-features.h" @@ -120,6 +121,41 @@ void arm_restore_state_to_opc(CPUState *cs, env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; } } + +bool arm_plugin_need_unwind_for_reg(CPUState *cs, int reg) +{ + return reg == 15 || reg == 25; /* pc (r15) or cpsr */ +} + +int arm_plugin_unwind_read_reg(CPUState *cs, GByteArray *buf, int reg, + const TranslationBlock *tb, + const uint64_t *data) +{ + CPUARMState *env = cpu_env(cs); + uint32_t val, condexec; + + switch (reg) { + case 15: /* PC */ + val = data[0]; + if (tb_cflags(tb) & CF_PCREL) { + val |= env->regs[15] & TARGET_PAGE_MASK; + } + break; + case 25: /* CPSR, or XPSR for M-profile */ + if (arm_feature(env, ARM_FEATURE_M)) { + val = xpsr_read(env); + } else { + val = cpsr_read(env); + } + condexec = data[1] & 0xff; + val = (val & ~(3 << 25)) | ((condexec & 3) << 25); + val = (val & ~(0xfc << 8)) | ((condexec & 0xfc) << 8); + break; + default: + g_assert_not_reached(); + } + return gdb_get_reg32(buf, val); +} #endif /* CONFIG_TCG */ /* @@ -2657,6 +2693,8 @@ static const TCGCPUOps arm_tcg_ops = { .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, .restore_state_to_opc = arm_restore_state_to_opc, + .plugin_need_unwind_for_reg = arm_plugin_need_unwind_for_reg, + .plugin_unwind_read_reg = arm_plugin_unwind_read_reg, #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv, diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7ba80099af..1595be5d8f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -33,6 +33,8 @@ #include "hw/qdev-properties.h" #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" +#include "exec/translation-block.h" +#include "gdbstub/helpers.h" #endif #include "internals.h" #include "cpu-features.h" @@ -797,11 +799,34 @@ static const gchar *aarch64_gdb_arch_name(CPUState *cs) } #ifdef CONFIG_TCG +static bool aarch64_plugin_need_unwind_for_reg(CPUState *cs, int reg) +{ + return reg == 32; /* pc */ +} + +static int aarch64_plugin_unwind_read_reg(CPUState *cs, GByteArray *buf, + int reg, const TranslationBlock *tb, + const uint64_t *data) +{ + CPUARMState *env = cpu_env(cs); + uint64_t val; + + assert(reg == 32); + + val = data[0]; + if (tb_cflags(tb) & CF_PCREL) { + val |= env->pc & TARGET_PAGE_MASK; + } + return gdb_get_reg64(buf, val); +} + static const TCGCPUOps aarch64_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, .restore_state_to_opc = arm_restore_state_to_opc, + .plugin_need_unwind_for_reg = aarch64_plugin_need_unwind_for_reg, + .plugin_unwind_read_reg = aarch64_plugin_unwind_read_reg, #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index c059c681e9..47e44f70c7 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -237,6 +237,8 @@ static const TCGCPUOps arm_v7m_tcg_ops = { .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, .restore_state_to_opc = arm_restore_state_to_opc, + .plugin_need_unwind_for_reg = arm_plugin_need_unwind_for_reg, + .plugin_unwind_read_reg = arm_plugin_unwind_read_reg, #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv,