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Fri, 07 Jun 2024 13:42:55 -0700 (PDT) From: Caleb Connolly Date: Fri, 07 Jun 2024 22:42:49 +0200 Subject: [PATCH v2 1/3] arm64: mmu.h: fix PTE_TABLE_AP MIME-Version: 1.0 Message-Id: <20240607-caleb-upstreaming-v2-1-bae407f51f22@linaro.org> References: <20240607-caleb-upstreaming-v2-0-bae407f51f22@linaro.org> In-Reply-To: <20240607-caleb-upstreaming-v2-0-bae407f51f22@linaro.org> To: Tom Rini Cc: Michal Simek , Ilias Apalodimas , Neil Armstrong , u-boot@lists.denx.de, Caleb Connolly X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=757; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=e1xnCDVDSraolIJhnHUmQGQpqz/i168ZLEa3Z2JGSc4=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBmY3DNhlAVaJxhjawwZ8bCbycDngCkw0RvRqukd 34PImRHhf6JAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZmNwzQAKCRAFgzErGV9k tg6/EACKow8Ts27bdvHpV1Rf8LElKobpNcsgsEyiM206qdP8wJeO8k6XGCsZ/Ju3gib/IpV4g4D X0i+0YIXkzNaTP0JfEZpRH08JZWBOveCaGbLJ0cA2KClbuvwFcxOiRgzN0feAPHZKSdqhDOVElW MaOBtLMjDRpdclLN7L4Bc4sfYdq7u7+XUT3iq78AhBSyYVsd5/bsKmluZ788Ga7VpdW/p8u2AKw gEJH1E5g571rrDBed4Nehc6bgbtYwG9ZdDrSc+A15P7unZW+8MigZYEegoO+0VexJduWYpo96lI YxpBdteAoc8POWUTn1BwtX1Epgu2nbWGI0qnMVV+aioMRU149ML+iXoNPz+R2JB2JeT3zxhWmaR 9d60LBmoiLr0HFSNoYYhmoTnPOqVjM7r9a5lCZO7/x1BR2uCqhDLOZnwS2FGX2CwhL9/i4oQ6WT fKVM+UynJeDevgrV2Ohzvu7rGjD0beAF0t0a4pagV5Iick2S1LX2EZ9hv3vy524eITPcPSZ4uZT JkJr0mtvBfV82RwpDoPsSUQ9WQZV+kHx+a+Msm4ZmtguYjIyxd/Ps6DlgofuHXDD+cNRyk7qsf3 gae7/EcfcJAhrubpoQLFqY0/jYnrnETMaAC0u+PX4Zvn2ba5NuS42RZTqfoXF1jrwZ/INFz7Ny+ t8uLMAyxrEbHshA== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The APTable attribute is two bits wide according to the ARMv8-A architecture reference manual. Fix the macro accordingly. Signed-off-by: Caleb Connolly --- arch/arm/include/asm/armv8/mmu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index ce655ce7a952..52cb18b9ed5e 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -50,9 +50,9 @@ #define PTE_TYPE_VALID (1 << 0) #define PTE_TABLE_PXN (1UL << 59) #define PTE_TABLE_XN (1UL << 60) -#define PTE_TABLE_AP (1UL << 61) +#define PTE_TABLE_AP (3UL << 61) #define PTE_TABLE_NS (1UL << 63) /* * Block From patchwork Fri Jun 7 20:42:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 802345 Delivered-To: patch@linaro.org Received: by 2002:adf:f147:0:b0:35b:5a80:51b4 with SMTP id y7csp985882wro; Fri, 7 Jun 2024 13:43:20 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVCh4OikB0oVcsl48n0+RO+v6kJXYheVbbVR2r9u0wnTxiYTcUyAWQNlHzsUOb6xJ7pO3qAxROFN4IyEwMnQQLq X-Google-Smtp-Source: AGHT+IGNXMBqonzm39apmYpDurGqU8e/KukG8mCmT3If692gTRnahcM+xQIlRu7xAfi0lD44QzPS X-Received: by 2002:a05:651c:1028:b0:2e1:e33d:67f6 with SMTP id 38308e7fff4ca-2eadce408a5mr22085771fa.28.1717793000026; Fri, 07 Jun 2024 13:43:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717792999; cv=none; d=google.com; s=arc-20160816; b=FeEy3u2vUIG2VQHYckJVR5dl/d7awOV6Nz6n/8gZ19vAs9m7l9/QrorA2nqEoiE5G5 8jnF0wNjfcWFD7+uRrBMhj7/CDYTsYM6xP4MV6rfy2wmUrU2/pQ2J4rFiZKAw4yuH4C/ qxCH89+/oQLjS6/9d4KNMLPpGn3q4ZVCqOITJazdtY1Sfigq6ilUMLy0yR7cWQVfqhnn AA3+622/UJtIM88KRL8od9luZQMK/5Q225qIXkgwUHFml//qT95TeC/7xXFcpLqgSRXy tSlGoExaS4orpEV6lcocsoxrDv6HDEDfrlHpqORtZicXQVN+YxDypYB/nmdd8BAetZkw nFGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=RpXaHECFBRPu1AelIvGTfl9hHhS021JeTZxOEiELyvc=; fh=d2SWGfB07KM42tH3klM7UGb3Z+0slnPAcfAp+sHDCKQ=; b=F6sYjK1YtFL2mP3/hPf70qdUEUyK5NkRkWLbriMO3qWH7hP7uhXIS3F7tMT+Au4sK+ DFR3kuofvdTfqzBAuXIJeGDAyY1a54AL6kg3apgvglPUcrenl3vcVPSsgNsxdEHkYn+E s2LNEcEuYM1KVlGvhaeeKHhWpSejjZ7CHn+BPUTdxxFGGfgqpQ6S34vq9sEGr9J7bhae WaLYammiwfTyOxiD+xkznGYXSTelUYFDz09nZcA+2580hLpys+x/lDlnv/6OtwizPxG+ cG6oi7TkEtVeEbHWTsgnIDOdn1a9wGFQGvfCsirNZNgM/HjRLTEJOnWBPRphFeTvAqA5 DUhA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kk84Wt4s; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add a basic software implementation of the ARM64 pagetable walker. This can be used for debugging U-Boot's pagetable, as well as dumping the pagetable from the previous bootloader stage if it used one (by reading out the ttbr address). One can either call dump_pagetable() to print the pagetable to the console with the default formatter, or implement their own pagetable handler using walke_pagetable() with a custom pte_walker_cb_t callback. All of the added code is discarded when unused, hence there is no need to add an additional Kconfig option for this. Signed-off-by: Caleb Connolly --- arch/arm/cpu/armv8/cache_v8.c | 202 +++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/armv8/mmu.h | 55 +++++++++++ 2 files changed, 257 insertions(+) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index d4c64f2d60d9..cb7c0e61ba70 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -395,8 +395,210 @@ static int count_ranges(void) return count; } +#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK) +#define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3) + +enum walker_state { + WALKER_STATE_START = 0, + WALKER_STATE_TABLE, + WALKER_STATE_REGION, /* block or page, depending on level */ +}; + +static void __pagetable_walk(u64 addr, u64 tcr, int level, pte_walker_cb_t cb, void *priv) +{ + u64 *table = (u64 *)addr; + u64 attrs, last_attrs = 0, last_addr = 0, entry_start = 0; + int i; + u64 va_bits = 64 - (tcr & (BIT(6) - 1)); + static enum walker_state state[4] = { 0 }; + static bool exit; + + if (!level) { + exit = false; + if (va_bits < 39) + level = 1; + } + + state[level] = WALKER_STATE_START; + + /* Walk through the table entries */ + for (i = 0; i < MAX_PTE_ENTRIES; i++) { + u64 pte = table[i]; + u64 _addr = pte & GENMASK_ULL(va_bits, PAGE_SHIFT); + + if (exit) + return; + + if (pte_type(&pte) == PTE_TYPE_FAULT) + continue; + + attrs = pte & ALL_ATTRS; + /* If we're currently inside a block or set of pages */ + if (state[level] > WALKER_STATE_START && state[level] != WALKER_STATE_TABLE) { + /* + * Continue walking if this entry has the same attributes as the last and + * is one page/block away -- it's a contiguous region. + */ + if (attrs == last_attrs && _addr == last_addr + (1 << level2shift(level))) { + last_attrs = attrs; + last_addr = _addr; + continue; + } else { + /* We either hit a table or a new region */ + exit = cb(entry_start, last_addr + (1 << level2shift(level)), + va_bits, level, priv); + if (exit) + return; + state[level] = WALKER_STATE_START; + } + } + last_attrs = attrs; + last_addr = _addr; + + if (PTE_IS_TABLE(pte, level)) { + /* After the end of the table might be corrupted data */ + if (!_addr || (pte & 0xfff) > 0x3ff) + return; + state[level] = WALKER_STATE_TABLE; + /* Signify the start of a table */ + exit = cb(pte, 0, va_bits, level, priv); + if (exit) + return; + + /* Go down a level */ + __pagetable_walk(_addr, tcr, level + 1, cb, priv); + state[level] = WALKER_STATE_START; + } else if (pte_type(&pte) == PTE_TYPE_BLOCK || pte_type(&pte) == PTE_TYPE_PAGE) { + /* We foud a block or page, start walking */ + entry_start = pte; + state[level] = WALKER_STATE_REGION; + } + } + + if (state[level] > WALKER_STATE_START) + exit = cb(entry_start, last_addr + (1 << level2shift(level)), va_bits, level, priv); +} + +static void pretty_print_pte_type(u64 pte) +{ + switch (pte_type(&pte)) { + case PTE_TYPE_FAULT: + printf(" %-5s", "Fault"); + break; + case PTE_TYPE_BLOCK: + printf(" %-5s", "Block"); + break; + case PTE_TYPE_PAGE: + printf(" %-5s", "Pages"); + break; + default: + printf(" %-5s", "Unk"); + } +} + +static void pretty_print_table_attrs(u64 pte) +{ + int ap = (pte & PTE_TABLE_AP) >> 61; + + printf(" | %2s %10s", + (ap & 2) ? "RO" : "", + (ap & 1) ? "!EL0" : ""); + printf(" | %3s %2s %2s", + (pte & PTE_TABLE_PXN) ? "PXN" : "", + (pte & PTE_TABLE_XN) ? "XN" : "", + (pte & PTE_TABLE_NS) ? "NS" : ""); +} + +static void pretty_print_block_attrs(u64 pte) +{ + u64 attrs = pte & PMD_ATTRINDX_MASK; + + switch (attrs) { + case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE): + printf(" | %-13s", "Device-nGnRnE"); + break; + case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE): + printf(" | %-13s", "Device-nGnRE"); + break; + case PTE_BLOCK_MEMTYPE(MT_DEVICE_GRE): + printf(" | %-13s", "Device-GRE"); + break; + case PTE_BLOCK_MEMTYPE(MT_NORMAL_NC): + printf(" | %-13s", "Normal-NC"); + break; + case PTE_BLOCK_MEMTYPE(MT_NORMAL): + printf(" | %-13s", "Normal"); + break; + default: + printf(" | %-13s", "Unknown"); + } +} + +static void pretty_print_block_memtype(u64 pte) +{ + u64 share = pte & (3 << 8); + + switch (share) { + case PTE_BLOCK_NON_SHARE: + printf(" | %-16s", "Non-shareable"); + break; + case PTE_BLOCK_OUTER_SHARE: + printf(" | %-16s", "Outer-shareable"); + break; + case PTE_BLOCK_INNER_SHARE: + printf(" | %-16s", "Inner-shareable"); + break; + default: + printf(" | %-16s", "Unknown"); + } +} + +static void print_pte(u64 pte, int level) +{ + if (PTE_IS_TABLE(pte, level)) { + printf(" %-5s", "Table"); + pretty_print_table_attrs(pte); + } else { + pretty_print_pte_type(pte); + pretty_print_block_attrs(pte); + pretty_print_block_memtype(pte); + } + printf("\n"); +} + +static bool pagetable_print_entry(u64 start_attrs, u64 end, int va_bits, int level, void *priv) +{ + u64 _addr = start_attrs & GENMASK_ULL(va_bits, PAGE_SHIFT); + int indent = va_bits < 39 ? level - 1 : level; + + printf("%*s", indent * 2, ""); + if (PTE_IS_TABLE(start_attrs, level)) + printf("[%#011llx]%14s", _addr, ""); + else + printf("[%#011llx - %#011llx]", _addr, end); + + printf("%*s | ", (3 - level) * 2, ""); + print_pte(start_attrs, level); + + return false; +} + +void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv) +{ + __pagetable_walk(ttbr, tcr, 0, cb, priv); +} + +void dump_pagetable(u64 ttbr, u64 tcr) +{ + u64 va_bits = 64 - (tcr & (BIT(6) - 1)); + + printf("Walking pagetable at %p, va_bits: %lld. Using %d levels\n", (void *)ttbr, + va_bits, va_bits < 39 ? 3 : 4); + walk_pagetable(ttbr, tcr, pagetable_print_entry, NULL); +} + /* Returns the estimated required size of all page tables */ __weak u64 get_page_table_size(void) { u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 52cb18b9ed5e..eed121784247 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -128,8 +128,63 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) } asm volatile("isb"); } +static inline void get_ttbr_tcr_mair(int el, u64 *table, u64 *tcr, u64 *attr) +{ + if (el == 1) { + asm volatile("mrs %0, ttbr0_el1" : "=r" (*table)); + asm volatile("mrs %0, tcr_el1" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el1" : "=r" (*attr)); + } else if (el == 2) { + asm volatile("mrs %0, ttbr0_el2" : "=r" (*table)); + asm volatile("mrs %0, tcr_el2" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el2" : "=r" (*attr)); + } else if (el == 3) { + asm volatile("mrs %0, ttbr0_el3" : "=r" (*table)); + asm volatile("mrs %0, tcr_el3" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el3" : "=r" (*attr)); + } else { + hang(); + } +} + +/** + * pte_walker_cb_t - callback function for walk_pagetable. + * + * This function is called when the walker finds a table entry + * or after parsing a block or pages. For a table the @end address + * is 0, and @addr is the address of the table. Otherwise, they + * are the start and end physical addresses of the block or page. + * + * @addr: PTE start address (PA), or address of table. Includes attributes. + * @end: End address of the region (or 0 for a table) + * @va_bits: Number of bits in the virtual address + * @level: Table level + * @priv: Private data for the callback + * + * Return: true to stop walking, false to continue + */ +typedef bool (*pte_walker_cb_t)(u64 addr, u64 end, int va_bits, int level, void *priv); + +/** + * walk_pagetable() - Walk the pagetable at ttbr and call cb for each region + * + * @ttbr: Address of the pagetable to dump + * @tcr: TCR value to use + * @cb: Callback function to call for each entry + * @priv: Private data for the callback + */ +void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv); + +/** + * dump_pagetable() - Dump the pagetable at ttbr by printing each region + * + * @ttbr: Address of the pagetable to dump + * @tcr: TCR value to use + */ +void dump_pagetable(u64 ttbr, u64 tcr); + struct mm_region { u64 virt; u64 phys; u64 size; From patchwork Fri Jun 7 20:42:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 802346 Delivered-To: patch@linaro.org Received: by 2002:adf:f147:0:b0:35b:5a80:51b4 with SMTP id y7csp985947wro; Fri, 7 Jun 2024 13:43:30 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVJ4GpNhRy0Zu7IVpn0fTLL4INp8T5Dyfk8wixW0n2/m+RI9+9OXDkE9c8yWJn97NgMt4D65tCcQciIe8VyUE0s X-Google-Smtp-Source: AGHT+IGIPFkX7dB5n/g/1e3oCwNq70+Us/w83lfAMtn9AtcJ5rbpA6WTs0yfKGh8kPaFRsWAqPuN X-Received: by 2002:ac2:5610:0:b0:52b:bad2:b198 with SMTP id 2adb3069b0e04-52bbad2b29amr2180757e87.4.1717793010232; Fri, 07 Jun 2024 13:43:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717793010; cv=none; d=google.com; s=arc-20160816; b=h+7l02hUnHO9fzmJzsVcqB+NnTwk9Fs1NYcv7224WC0yS0oKeHk8OqdegYyPJCYIoM 5HhHiWvq9B3Ts4FgiTmEuyMuBqxuXBFioKVIWowni09D4NYMXvGaTj3LHgSICw6AJc34 DJxrTK8Y/nlhmHDAOIL7gmwQv7/fu/stLaYGGzGbhm716FErPYCZGBSdmuQC40SzGmiK EQv4t9XtT8XDecyYNR06q7LT7oj2SW/u4JQKTv3i/PlAPCFVPcB3yGCZU0y5ZrJUR+yj 1Ftu5RMyZGeYHjR+pIgnVSbsPv2s67NkrRgF+xvwXlbYtuB4h4zn4r+DUm29UAoB2lw8 gTNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=VFG4WdYnJXL1HIRac9zQBh+jJKA5eSiwDUsq05zXZ3I=; fh=WDxzchFVPLqtzRERkjLU8vs10HuwYjuragoetZvLqy0=; b=PU8GR22XjQhRY3qwx1PyT/M7i/HjBl2kLrDzzXhrz2HtRoSQmDmcJuX/xiJ4dX3D38 AWrqLvaxBxPJE2rB/6Uc9ixbmr3gWyMl61+wEdNf8sEYZijCwP2WwRw/pqICkNtyZ9Ag 6xkqdK/SiwxFxy/9xGuClwoysnO/MZqS56PbRAgMLAv32xLdGg9lJx5T6Tozl/Yg1X/N GIT8BveQJXo0ukkxrXg0EggY8QW5Gefb59XkenhfPfqo5QQwPcMzbknZYSraK0WmOipw 1EYbY68E2iq9zAjfmeiRvYU6UH3HifkTMeKVmYGKGa2qy37d11oi1UYRn959o3blVDJp pMkg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NVH+bqo0; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Fri, 07 Jun 2024 13:42:57 -0700 (PDT) From: Caleb Connolly Date: Fri, 07 Jun 2024 22:42:51 +0200 Subject: [PATCH v2 3/3] doc: arch: arm64: describe pagetable debugging MIME-Version: 1.0 Message-Id: <20240607-caleb-upstreaming-v2-3-bae407f51f22@linaro.org> References: <20240607-caleb-upstreaming-v2-0-bae407f51f22@linaro.org> In-Reply-To: <20240607-caleb-upstreaming-v2-0-bae407f51f22@linaro.org> To: Tom Rini Cc: Michal Simek , Ilias Apalodimas , Neil Armstrong , u-boot@lists.denx.de, Caleb Connolly X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2437; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=MTi4eb3QnNK3dMRRUrL76HdHjW1mfzW7AiL6LzWeZKg=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBmY3DN6v4y/j4pAc7EZtiXICHxkTcTRzjmGysbG bov6sNmewqJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZmNwzQAKCRAFgzErGV9k trLpD/9xSY5gwpZqszdEVW10K3btClJ5kXysUZxDvK7QBFcOsnf3DLb48vddNW6VQztjgM2P/Cd BSYcTHmtYyuQsFR3txlADGfwIMZezdWGfvg/CqbthdaAGIA1zFV0dQpetdBrhBWmDYNEzDYFHN6 sB3+0J4orYsHLJkeBvR/LktAlkJbQoJf7ShoJLvH7N2Rwevhh8QPL4NnNJo2y1sto4LHT6zufbR o/3xfUU0jgw4Nj7BlNOqcShPvECPjc8iJY5Vu9dAYAnp0Vxko/Ld6A/RoinGs0pDcjiUu4LxO5T jSY0SjVDsqFZXgMBX7xD3+PfUnVjNzjzKmWqA0/6n9DtSk32IsJGfDD1zkgpBI7Ncxv3txPEVkR 8Ris2BgrD4ChgZk+b2ZKbNECT3AuQofSqDu4Vl52LPrIMmDCzCkk2Y3WCmDkNcyWVOKrNkLIzIn PQVxdcFVuY3LPNrHL07Ua3cjsSE4hWJEoBNIDQewyGpjXGfQlIM5Bwu1fWhx/HLNTserM4bBDMd i3288IU+cmD0YUgIKJy2Ml5Tbam/N2El7bj5dkitRujEEUk49tMdeooplljG2ForPiDRdJ7vjGi +q3gOjS3bBWniws5Y8QrO5nAsD8NDRMyWoVOg6Q5rhMPk2WwqRfvERfMsOuN7+4BIQTBP6QVdX9 iddAtgnAnUUlfyQ== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add some brief documentation on using dump_pagetables() to print out U-Boot's pagetables during boot. Signed-off-by: Caleb Connolly --- doc/arch/arm64.rst | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/doc/arch/arm64.rst b/doc/arch/arm64.rst index 7c0713504c47..0c851304aad4 100644 --- a/doc/arch/arm64.rst +++ b/doc/arch/arm64.rst @@ -47,8 +47,45 @@ Notes 6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and aarch32 specific codes. +MMU +--- + +U-Boot uses a simple page table for MMU setup. It uses the smallest number of bits +possible for the virtual address based on the maximum memory address (see the logic +in ``get_tcr()``). + +As with all platforms, U-Boot on ARM64 uses a 1:1 mapping of virtual to physical addresses. +In general, the memory map is expected to remain static once the MMU is enabled. + +It is possible to debug the pagetable generated by U-Boot with the built in +``dump_pagetable()`` and ``walk_pagetable()`` functions (the former being a simple +wrapper for the latter). For example the following can be added to ``setup_all_pgtables()`` +after the first call to ``setup_pgtables()``: + +.. code-block:: c + + dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL)); + +This will result in a print like the following: + +.. code-block:: text + + Walking pagetable at 000000017df90000, va_bits: 36. Using 3 levels + [0x17df91000] | Table | | + [0x17df92000] | Table | | + [0x000001000 - 0x000200000] | Pages | Device-nGnRnE | Non-shareable + [0x000200000 - 0x040000000] | Block | Device-nGnRnE | Non-shareable + [0x040000000 - 0x080000000] | Block | Device-nGnRnE | Non-shareable + [0x080000000 - 0x140000000] | Block | Normal | Inner-shareable + [0x17df93000] | Table | | + [0x140000000 - 0x17de00000] | Block | Normal | Inner-shareable + [0x17df94000] | Table | | + [0x17de00000 - 0x17dfa0000] | Pages | Normal | Inner-shareable + +For more information, please refer to the function documentation in +``arch/arm/include/asm/armv8/mmu.h``. Contributors ------------ * Tom Rini