From patchwork Wed Oct 23 08:49:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177249 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp416414ill; Wed, 23 Oct 2019 01:49:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqzJVeU1HUeSD08lDeuVyIHvXTgaQO9M9JgPY/giZ9mOOyeisTNbykd6oyOtilHTtW6WZZZL X-Received: by 2002:a17:906:9391:: with SMTP id l17mr17569290ejx.315.1571820574463; Wed, 23 Oct 2019 01:49:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571820574; cv=none; d=google.com; s=arc-20160816; b=lD2z0FblfD6bhr1hdnvELiev2gRwqNl4vwmzeeybssC8v8qw8GCVhKNGD5HtiWOhBT CQ7dMBf/WAgb1Fn3bHjQ92uG2dzHzTtBDkgAyUZbcYW0eEzYEgsWILXM1uUrO7DVP5+w NWq2ROf3TCklZS0rGMMRANtrSHfqgsb0OwDzO/0OlNxVKH8/pqhouczUegDPaB7Kd+qG ll30c6jf7Ccyg+3LCfa0eTt3hFdPB3QVNu/jEiSbSg3lmXRbXF5x3acojjdgMqdq3zhM 5FfZfay1FQ4SFkGKYLDf7bnLrdOgXNraKiFK6UPoWXWjT1hOGljZ+Jhk8ZzTm6leEusp Z/hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=gR7OAXsQc4OiOhV7DWYE58CP8SVL3y7X8+jWjC3qNZ0=; b=1FurXYKXmqjJhz542Ee9W5S8xCgOoqmLy/Td1OzFstbYPh9HDYwnKhV7VfZ/X79Qr3 kqRfM5b+yOD07d+o79Z0siJRO+9dGpJWd038xQmfpWirYNo5wgPIpvd8ZEqhD5vKLMOt dNoDz95tsCbJ0cMHN8g9O7ua2OzRNzfqiERgLxxCE47DG6jOyDLE9pdYZvhu9cEZZ2ei Xiv8Vim6g5AaBiiMQuy/qW4OAex7Ymhcgrjc8tL25CkgNwuPtyvz3yL5jFb+XpMpzJqW WohmvvYB5Aqp2cBGHHn3zRBJ55GMIwSClI103EpxSIrq88uJkWOlQSTS41yNnjhSMPtV tDbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jNUlaw1D; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id gg10si11859917ejb.206.2019.10.23.01.49.34; Wed, 23 Oct 2019 01:49:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jNUlaw1D; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390575AbfJWItb (ORCPT + 26 others); Wed, 23 Oct 2019 04:49:31 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:41296 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390553AbfJWIta (ORCPT ); Wed, 23 Oct 2019 04:49:30 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9N8nRor085350; Wed, 23 Oct 2019 03:49:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571820567; bh=gR7OAXsQc4OiOhV7DWYE58CP8SVL3y7X8+jWjC3qNZ0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jNUlaw1DqfYHX8dAttAr0l+BIvyYssXG6zN7BBS2xur1mqQNT6GCZXqudNpnZl70b OIZ+6QoePoHJL5ZIvqPuAsYzC06pZSdeLPDm7s9W/oNvBprzoYnCIkkyYPfRZBG1sf bxbbErB3ZeAQDQ7rHG+u7JU0jOzvyBX/tUPHRo24= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9N8nQUV011800 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 23 Oct 2019 03:49:27 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 23 Oct 2019 03:49:14 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 23 Oct 2019 03:49:14 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9N8nHVv061069; Wed, 23 Oct 2019 03:49:21 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH v2 2/3] dt-bindings: phy: ti, phy-j721e-wiz: Add Type-C dir GPIO Date: Wed, 23 Oct 2019 11:49:15 +0300 Message-ID: <20191023084916.26895-3-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023084916.26895-1-rogerq@ti.com> References: <20191023084916.26895-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is an optional GPIO, if specified will be used to swap lane 0 and lane 1 based on GPIO status. This is required to achieve plug flip support for USB Type-C. Type-C companions typically need some time after the cable is plugged before and before they reflect the correct status of Type-C plug orientation on the DIR line. Type-C Spec specifies CC attachment debounce time (tCCDebounce) of 100 ms (min) to 200 ms (max). Allow the DT node to specify the time (in ms) that we need to wait before sampling the DIR line. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- .../devicetree/bindings/phy/ti,phy-j721e-wiz.txt | 9 +++++++++ 1 file changed, 9 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt index 19b4c3e855d6..253535a8819f 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt @@ -24,6 +24,15 @@ Optional properties: assigned-clocks and assigned-clock-parents: As documented in the generic clock bindings in Documentation/devicetree/bindings/clock/clock-bindings.txt + - typec-dir-gpios: GPIO to signal Type-C cable orientation for lane swap. + If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to + achieve the funtionality of an exernal type-C plug flip mux. + + - typec-dir-debounce: Number of milliseconds to wait before sampling + typec-dir-gpio. If not specified, the GPIO will be sampled ASAP. + Type-C spec states minimum CC pin debounce of 100 ms and maximum + of 200 ms. + Required subnodes: - Clock Subnode: WIZ node should have '3' subnodes for each of the clock selects it supports. The clock subnodes should have the following names From patchwork Wed Oct 23 08:49:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177250 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp416479ill; Wed, 23 Oct 2019 01:49:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqxpp04HSAykclYSXkCi/LcXKjc2xcuuX7xGZNg4b1n5zTnkAnzxo0gfYHwL0RdDXpfHASfk X-Received: by 2002:a05:6402:1252:: with SMTP id l18mr35957642edw.64.1571820578709; Wed, 23 Oct 2019 01:49:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571820578; cv=none; d=google.com; s=arc-20160816; b=VWN5dtObks2ZFRLWv5svlxmVJCReggSRodowQQP5h6MK3f2PXYNuu2hQI7CYxHuiBe 2y4VFtlZqRH4SpzS2+ESVp5ijo/pFAiluQ4m3uI+K4lPpjQqL6wbtq6He6y5bfksO91n jbl0OP1pzsQAHS6VTgYA9wx6Zy6vGWi28TpXwspFDhGwXj4aVnQRuq3d6Vfcsu51cWFx v1yWL/kECNKjx1hw9JtDTA++/E0ONhHi9uO8o/EX0Apckp80sU9GI2lQslz8LXaqFPmX UhSRzitl3oAfMUWXzni0JjUXYnErsmNcC9a1jY9np5diMZxmxh2PrPUsyxKSBU/0Qqj7 YrDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=XVlyGMuG7+3U0rgQC9b014GHHO/Le8hO721FgVpW9rE=; b=yZbNeGsIWPFq80A6ymjjpzV4hi/df0pbDGGKQsJqqLfvp7CgdfVohPLPafzr6kbo+s BVUspz/S/HvhTWCo9ZjXkUL6/L4buO/CQSPESuCq9m5N4qmAj6IQAiCPjeNsqoAzda3o Zk0D2dSTic3fW1FfLcWhHjgy4IuNzpvVmzADz3oJF1DHJ8l6qfCtE/LulUUZX9fodMQn p9UQBOhmnzsD3iBnfTGZAY4b1sWfnwcuKbJKfqzS549JFN5+Fr5kRWIoulsWTGxBFFp6 OXZHEuLYhKFeFRH1fDgmVfeNOk4KL6jyBKO4kSz5pT4J5RHj80vRbIbm4Lo/hGQmDa1C sY3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iVyDSUh+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ca4si12862616ejb.39.2019.10.23.01.49.38; Wed, 23 Oct 2019 01:49:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iVyDSUh+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390587AbfJWItf (ORCPT + 26 others); Wed, 23 Oct 2019 04:49:35 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:47762 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390567AbfJWItb (ORCPT ); Wed, 23 Oct 2019 04:49:31 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9N8nTkR093741; Wed, 23 Oct 2019 03:49:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571820569; bh=XVlyGMuG7+3U0rgQC9b014GHHO/Le8hO721FgVpW9rE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iVyDSUh+dGgF6FxIlQArkMUBlrz1l+1DgSywuE1UQBO1lJQE0F8zkGhJuzxJAtOwh EEz7PYDhywWlLT4wAzZ0hQICBIuWmhmMDO75E3TjpfpT0rm2t4ro3m5awhEdXXeq9V MDaQqsTtlOTr5NQvgoD5vtDmi+uHxuVi6Eq6v3mg= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9N8nSYP011837 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 23 Oct 2019 03:49:29 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 23 Oct 2019 03:49:26 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 23 Oct 2019 03:49:16 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9N8nHVw061069; Wed, 23 Oct 2019 03:49:24 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH v2 3/3] phy: ti: j721e-wiz: Manage typec-gpio-dir Date: Wed, 23 Oct 2019 11:49:16 +0300 Message-ID: <20191023084916.26895-4-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023084916.26895-1-rogerq@ti.com> References: <20191023084916.26895-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Based on this GPIO state we need to configure LN10 bit to swap lane0 and lane1 if required (flipped connector). Type-C companions typically need some time after the cable is plugged before and before they reflect the correct status of Type-C plug orientation on the DIR line. Type-C Spec specifies CC attachment debounce time (tCCDebounce) of 100 ms (min) to 200 ms (max). Use the DT property to figure out if we need to add delay or not before sampling the Type-C DIR line. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- drivers/phy/ti/phy-j721e-wiz.c | 48 ++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 2a95da843e9f..02b949406b7b 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include #include @@ -22,6 +24,7 @@ #define WIZ_SERDES_CTRL 0x404 #define WIZ_SERDES_TOP_CTRL 0x408 #define WIZ_SERDES_RST 0x40c +#define WIZ_SERDES_TYPEC 0x410 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) #define WIZ_MAX_LANES 4 @@ -29,6 +32,8 @@ #define WIZ_DIV_NUM_CLOCKS_16G 2 #define WIZ_DIV_NUM_CLOCKS_10G 1 +#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) + enum wiz_lane_standard_mode { LANE_MODE_GEN1, LANE_MODE_GEN2, @@ -94,6 +99,9 @@ static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { REG_FIELD(WIZ_LANECTL(3), 24, 25), }; +static const struct reg_field typec_ln10_swap = + REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); + struct wiz_clk_mux { struct clk_hw hw; struct regmap_field *field; @@ -201,11 +209,14 @@ struct wiz { struct regmap_field *pma_cmn_refclk_mode; struct regmap_field *pma_cmn_refclk_dig_div; struct regmap_field *pma_cmn_refclk1_dig_div; + struct regmap_field *typec_ln10_swap; struct device *dev; u32 num_lanes; struct platform_device *serdes_pdev; struct reset_controller_dev wiz_phy_reset_dev; + struct gpio_desc *gpio_typec_dir; + int typec_dir_delay; }; static int wiz_reset(struct wiz *wiz) @@ -404,6 +415,13 @@ static int wiz_regfield_init(struct wiz *wiz) } } + wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, + typec_ln10_swap); + if (IS_ERR(wiz->typec_ln10_swap)) { + dev_err(dev, "LN10_SWAP reg field init failed\n"); + return PTR_ERR(wiz->typec_ln10_swap); + } + return 0; } @@ -703,6 +721,17 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, struct wiz *wiz = dev_get_drvdata(dev); int ret; + /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ + if (id == 0 && wiz->gpio_typec_dir) { + if (wiz->typec_dir_delay) + msleep_interruptible(wiz->typec_dir_delay); + + if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) + regmap_field_write(wiz->typec_ln10_swap, 1); + else + regmap_field_write(wiz->typec_ln10_swap, 0); + } + if (id == 0) { ret = regmap_field_write(wiz->phy_reset_n, true); return ret; @@ -789,6 +818,25 @@ static int wiz_probe(struct platform_device *pdev) goto err_addr_to_resource; } + wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", + GPIOD_IN); + if (IS_ERR(wiz->gpio_typec_dir)) { + ret = PTR_ERR(wiz->gpio_typec_dir); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to request typec-dir gpio: %d\n", + ret); + goto err_addr_to_resource; + } + + if (wiz->gpio_typec_dir) { + ret = of_property_read_u32(node, "typec-dir-debounce", + &wiz->typec_dir_delay); + if (ret && ret != -EINVAL) { + dev_err(dev, "Invalid typec-dir-debounce property\n"); + goto err_addr_to_resource; + } + } + wiz->dev = dev; wiz->regmap = regmap; wiz->num_lanes = num_lanes;