From patchwork Wed Nov 6 10:26:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 178660 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp401024ilf; Wed, 6 Nov 2019 02:26:53 -0800 (PST) X-Google-Smtp-Source: APXvYqxVbECJZM08H+27hkgInS5vLJV9DScrwlZyUO5FQCT4z6pOy1qX0vIamWhiHY2D0AK4gPHT X-Received: by 2002:a50:d713:: with SMTP id t19mr1739548edi.185.1573036012987; Wed, 06 Nov 2019 02:26:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573036012; cv=none; d=google.com; s=arc-20160816; b=SNgNeKFAsEKCL67vkksqBCwq3bmlwrv1kpf7CtMuxCAEerZmOrZK+a5aJtbxYz5TtG +aCrqppQoZfhIbVnHIc0OQY0FFsSqwZHkg/rl24uIos3H7z36dx9JxatsbzQrWahTJro ToSzx2MfQCpmeM/UvupU6HN9ahqlq1STe309rICVp5ZHgvkkqAG9i9m/u5/BDiStT9de RfOy0J1ZRVrjNBeTyqCHFbif2aTdmCTmtBLf6EZNiOZuCX6zdN3JMkkDZobfMPs0YVaY uSiMkG2KeZsXU/D8tzw+8SfjTDV4cQfieHI6msC8i7v3inrK/ThQ02DVs/jNRVtjVC8h 7d8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=VQ7WJ8ZsAvGcW4mlU90P2IF2aD0aLGXpUMhLdSI6d40=; b=ebAPxG9/LXNn6qYFCagWMNZiJo42Vg1XnN24ddkip0AciVSwtwWDGPVDJB43c5m9Tw 2MMBYa09jPIU4WBrtW3/g2PtWRNmbItnrAyond+YsoOALHpe9iPrBSoGZlQBmtm5jTDX KfnA/bd5w6ITgYl3pH2O2nJeUmJW/8f0lorEAq+Fkhgn45jV4L3bVDD6QjouoxpyXw4Q sQIJKwcGdbxCGtdzWuqrV6zYHZv32iuCdaiP5U3Efd59LF3WIuqDVsmN7u6N8U84OAvU OUNEV1OwMHg1BSwHcsPQf1aU8fNHiz7PjfMg/JQllEpccgfwgzEQr83176GP0kZbL4HN lyYw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f8si11891618edf.428.2019.11.06.02.26.52; Wed, 06 Nov 2019 02:26:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731412AbfKFK0v (ORCPT + 8 others); Wed, 6 Nov 2019 05:26:51 -0500 Received: from mx.socionext.com ([202.248.49.38]:44272 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731317AbfKFK0v (ORCPT ); Wed, 6 Nov 2019 05:26:51 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 06 Nov 2019 19:26:49 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 9FE5A605F8; Wed, 6 Nov 2019 19:26:49 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 6 Nov 2019 19:26:59 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 0A8F81A04FC; Wed, 6 Nov 2019 19:26:49 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 4/6] phy: uniphier-usb3hs: Add legacy SoC support for Pro5 Date: Wed, 6 Nov 2019 19:26:17 +0900 Message-Id: <1573035979-32200-5-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573035979-32200-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1573035979-32200-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add legacy SoC support that needs to manage gio clock and reset. This supports Pro5. Signed-off-by: Kunihiko Hayashi --- drivers/phy/socionext/phy-uniphier-usb3hs.c | 68 ++++++++++++++++++++++------- 1 file changed, 53 insertions(+), 15 deletions(-) -- 2.7.4 diff --git a/drivers/phy/socionext/phy-uniphier-usb3hs.c b/drivers/phy/socionext/phy-uniphier-usb3hs.c index 1d3f9e8..bdf696e 100644 --- a/drivers/phy/socionext/phy-uniphier-usb3hs.c +++ b/drivers/phy/socionext/phy-uniphier-usb3hs.c @@ -66,13 +66,14 @@ struct uniphier_u3hsphy_trim_param { struct uniphier_u3hsphy_priv { struct device *dev; void __iomem *base; - struct clk *clk, *clk_parent, *clk_ext; - struct reset_control *rst, *rst_parent; + struct clk *clk, *clk_parent, *clk_ext, *clk_parent_gio; + struct reset_control *rst, *rst_parent, *rst_parent_gio; struct regulator *vbus; const struct uniphier_u3hsphy_soc_data *data; }; struct uniphier_u3hsphy_soc_data { + bool is_legacy; int nparams; const struct uniphier_u3hsphy_param param[MAX_PHY_PARAMS]; u32 config0; @@ -256,11 +257,20 @@ static int uniphier_u3hsphy_init(struct phy *phy) if (ret) return ret; - ret = reset_control_deassert(priv->rst_parent); + ret = clk_prepare_enable(priv->clk_parent_gio); if (ret) goto out_clk_disable; - if (!priv->data->config0 && !priv->data->config1) + ret = reset_control_deassert(priv->rst_parent); + if (ret) + goto out_clk_gio_disable; + + ret = reset_control_deassert(priv->rst_parent_gio); + if (ret) + goto out_rst_assert; + + if ((priv->data->is_legacy) + || (!priv->data->config0 && !priv->data->config1)) return 0; config0 = priv->data->config0; @@ -280,6 +290,8 @@ static int uniphier_u3hsphy_init(struct phy *phy) out_rst_assert: reset_control_assert(priv->rst_parent); +out_clk_gio_disable: + clk_disable_unprepare(priv->clk_parent_gio); out_clk_disable: clk_disable_unprepare(priv->clk_parent); @@ -290,7 +302,9 @@ static int uniphier_u3hsphy_exit(struct phy *phy) { struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy); + reset_control_assert(priv->rst_parent_gio); reset_control_assert(priv->rst_parent); + clk_disable_unprepare(priv->clk_parent_gio); clk_disable_unprepare(priv->clk_parent); return 0; @@ -325,22 +339,34 @@ static int uniphier_u3hsphy_probe(struct platform_device *pdev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - priv->clk = devm_clk_get(dev, "phy"); - if (IS_ERR(priv->clk)) - return PTR_ERR(priv->clk); + if (!priv->data->is_legacy) { + priv->clk = devm_clk_get(dev, "phy"); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + priv->clk_ext = devm_clk_get_optional(dev, "phy-ext"); + if (IS_ERR(priv->clk_ext)) + return PTR_ERR(priv->clk_ext); + + priv->rst = devm_reset_control_get_shared(dev, "phy"); + if (IS_ERR(priv->rst)) + return PTR_ERR(priv->rst); + + } else { + priv->clk_parent_gio = devm_clk_get(dev, "gio"); + if (IS_ERR(priv->clk_parent_gio)) + return PTR_ERR(priv->clk_parent_gio); + + priv->rst_parent_gio = + devm_reset_control_get_shared(dev, "gio"); + if (IS_ERR(priv->rst_parent_gio)) + return PTR_ERR(priv->rst_parent_gio); + } priv->clk_parent = devm_clk_get(dev, "link"); if (IS_ERR(priv->clk_parent)) return PTR_ERR(priv->clk_parent); - priv->clk_ext = devm_clk_get_optional(dev, "phy-ext"); - if (IS_ERR(priv->clk_ext)) - return PTR_ERR(priv->clk_ext); - - priv->rst = devm_reset_control_get_shared(dev, "phy"); - if (IS_ERR(priv->rst)) - return PTR_ERR(priv->rst); - priv->rst_parent = devm_reset_control_get_shared(dev, "link"); if (IS_ERR(priv->rst_parent)) return PTR_ERR(priv->rst_parent); @@ -362,11 +388,18 @@ static int uniphier_u3hsphy_probe(struct platform_device *pdev) return PTR_ERR_OR_ZERO(phy_provider); } +static const struct uniphier_u3hsphy_soc_data uniphier_pro5_data = { + .is_legacy = true, + .nparams = 0, +}; + static const struct uniphier_u3hsphy_soc_data uniphier_pxs2_data = { + .is_legacy = false, .nparams = 0, }; static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = { + .is_legacy = false, .nparams = 2, .param = { { LS_SLEW, 1 }, @@ -378,6 +411,7 @@ static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = { }; static const struct uniphier_u3hsphy_soc_data uniphier_pxs3_data = { + .is_legacy = false, .nparams = 0, .trim_func = uniphier_u3hsphy_trim_ld20, .config0 = 0x92316680, @@ -386,6 +420,10 @@ static const struct uniphier_u3hsphy_soc_data uniphier_pxs3_data = { static const struct of_device_id uniphier_u3hsphy_match[] = { { + .compatible = "socionext,uniphier-pro5-usb3-hsphy", + .data = &uniphier_pro5_data, + }, + { .compatible = "socionext,uniphier-pxs2-usb3-hsphy", .data = &uniphier_pxs2_data, }, From patchwork Wed Nov 6 10:26:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 178664 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp401207ilf; Wed, 6 Nov 2019 02:27:02 -0800 (PST) X-Google-Smtp-Source: APXvYqwY4m76UI7YixweXIBEFCgf/vDuORMfxXyEZOaYNVJw0OcCaWF9ion7AI6WxdfHcifQLVux X-Received: by 2002:a17:906:1812:: with SMTP id v18mr34141662eje.86.1573036021961; Wed, 06 Nov 2019 02:27:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573036021; cv=none; d=google.com; s=arc-20160816; b=fe6//CfBaxTaGN6cXvD7U+tTdOpGBlyE4eqgWJrduj8mVOsf1I5EMFvBlVrXzNnYQN QfYgaJ+UnfZduNO2ylJB0z854cnRi5nmQnIr2HPsOL+/e+5gmDQfwvirynMf0B+vGEPH jcDd0+5f7PPaS7aq1Mvmz0Gfq43sd6DUYTIcBKzYmswubUxdifXrcKRYpTFSQXiH5MqT UdFgZ49u3Ux2zZh1roqoiujHz7awdxxpGovvTFzTOPwG9GYnt+iWReihhUB+GtROSuue PaD0uEUFZNdH6JobOSpUsu2W0g3I2kYvjwKn+APV49ExoDOgPjU/FUY8pTTlJo8NOmtU XIqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=75vVAEqmXN7CrlXgI6/rHTXLaTCPGygl6BXxEPwWerc=; b=aAn2mWQe5BLlStdbm8LuzMZ4wKTnxu5MB3ZPpXXwdUdFx0hBAUCYJJoKZk08KFphSY jzVu6g56+/KD7UOmzRuwpNcMlrKlNit58e76EY2kea11AgSJzyh4WHNQIndKVgJqy25E Eq09fqmB96Zdy4o5z2bksxHsTPfTZWBWi/J2BrNg7aWLQSju/LrafWFE/FJxkh9N+5Bg CSgyyXbsNBrUVtj2koXkqtbJ8LIllzRvQ1B+NU4eA5toUKnpxouIQhAifhYxhG46Hqu7 7dESxZxlelZWCXpbseTrzCdHPybSeB03U4swX+3FdUxPOk2BEHDGlN09CHOkziJtPPT/ wARg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v9si12829381edf.36.2019.11.06.02.27.01; Wed, 06 Nov 2019 02:27:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731677AbfKFK1B (ORCPT + 8 others); Wed, 6 Nov 2019 05:27:01 -0500 Received: from mx.socionext.com ([202.248.49.38]:44295 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731418AbfKFK0x (ORCPT ); Wed, 6 Nov 2019 05:26:53 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 06 Nov 2019 19:26:51 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 3DE4F180095; Wed, 6 Nov 2019 19:26:51 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 6 Nov 2019 19:26:57 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id D78D11A04FC; Wed, 6 Nov 2019 19:26:50 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 5/6] phy: uniphier-usb3hs: Change Rx sync mode to avoid communication failure Date: Wed, 6 Nov 2019 19:26:18 +0900 Message-Id: <1573035979-32200-6-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573035979-32200-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1573035979-32200-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In case of using default parameters, communication failure might occur in rare cases. This sets Rx sync mode parameter to avoid the issue. Signed-off-by: Kunihiko Hayashi --- drivers/phy/socionext/phy-uniphier-usb3hs.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/phy/socionext/phy-uniphier-usb3hs.c b/drivers/phy/socionext/phy-uniphier-usb3hs.c index bdf696e..a9bc741 100644 --- a/drivers/phy/socionext/phy-uniphier-usb3hs.c +++ b/drivers/phy/socionext/phy-uniphier-usb3hs.c @@ -41,10 +41,12 @@ #define PHY_F(regno, msb, lsb) { (regno), (msb), (lsb) } +#define RX_CHK_SYNC PHY_F(0, 5, 5) /* RX sync mode */ +#define RX_SYNC_SEL PHY_F(1, 1, 0) /* RX sync length */ #define LS_SLEW PHY_F(10, 6, 6) /* LS mode slew rate */ #define FS_LS_DRV PHY_F(10, 5, 5) /* FS/LS slew rate */ -#define MAX_PHY_PARAMS 2 +#define MAX_PHY_PARAMS 4 struct uniphier_u3hsphy_param { struct { @@ -395,13 +397,19 @@ static const struct uniphier_u3hsphy_soc_data uniphier_pro5_data = { static const struct uniphier_u3hsphy_soc_data uniphier_pxs2_data = { .is_legacy = false, - .nparams = 0, + .nparams = 2, + .param = { + { RX_CHK_SYNC, 1 }, + { RX_SYNC_SEL, 1 }, + }, }; static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = { .is_legacy = false, - .nparams = 2, + .nparams = 4, .param = { + { RX_CHK_SYNC, 1 }, + { RX_SYNC_SEL, 1 }, { LS_SLEW, 1 }, { FS_LS_DRV, 1 }, }, @@ -412,7 +420,11 @@ static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = { static const struct uniphier_u3hsphy_soc_data uniphier_pxs3_data = { .is_legacy = false, - .nparams = 0, + .nparams = 2, + .param = { + { RX_CHK_SYNC, 1 }, + { RX_SYNC_SEL, 1 }, + }, .trim_func = uniphier_u3hsphy_trim_ld20, .config0 = 0x92316680, .config1 = 0x00000106, From patchwork Wed Nov 6 10:26:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 178663 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp401143ilf; Wed, 6 Nov 2019 02:26:58 -0800 (PST) X-Google-Smtp-Source: APXvYqysQ7ywHzyVd8JorC8fhbTgD06SP1HbgldPjjNxCcUIOyCjE77YTa0NpSB7gsh+tauYYs/I X-Received: by 2002:aa7:c0c8:: with SMTP id j8mr1714803edp.235.1573036018626; Wed, 06 Nov 2019 02:26:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573036018; cv=none; d=google.com; s=arc-20160816; b=ELPV4azh8E2DZAxTJcwIH9w0KNqRkEPC/LPHhtt6JtH8wDMcx59eVltPTpuIrv6TU+ Z5g2p18jZn+xnQERGvFTE8aW1WOWg+4pD5gP86tUzZ5IRJKwRtGAw2zz9poCT/XhLwdc QkyKSAGLMDtlWA6aY6InVlyigwmbCDgzs1qLzHxTLKlks/GArJrnVIRQMnSsj4SH/l2I Ch/AfzXPw53pqxUvpsaKylg8h19y7z/O9lNMD5C55oLA8OVQZMPw999REo7LFAG3LTKF u2k09bRSis26kJEf+ixQzv9j5W64GWuzBpHZy0zhFVx7s2G6XoX8ay4pg+p2HqzR4gvH AmVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=tOZwVJ1p7tsBvN9GwHooqY5QH49HeugL/UH2fmkmnfs=; b=hcKZd6p/PvFPK/RmxtDvW6abhccUeLbvSWDG0tIoyF+1YIYEBizaW3+5NEVda3RMF3 DywUwSlheG6zXau5imYLdeXV+isclg/cPJENvAfB7I/XB7FPogBe6E49p/lKzUjorKTP cspnXmZ7CAmqV5qzx8Q/tN1Nq8M3QSIVuabyUQ0awZWHrZeWrRbfQGwrbfxRDfs/UgIN YEUeVZFK7/LUVkAFM81WA5VrSBFbgKgx5WKRTfFSLTN06jYIEsoH5FEacJ7OkYx8YxTP n16hQ/kinM2e9L9xODwIA1Tk2dYXlakA4hjrCvHswUql8OqkHFd7AVXmY6okK9DtpKio 0Wcw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v9si12829381edf.36.2019.11.06.02.26.58; Wed, 06 Nov 2019 02:26:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731589AbfKFK0y (ORCPT + 8 others); Wed, 6 Nov 2019 05:26:54 -0500 Received: from mx.socionext.com ([202.248.49.38]:44272 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731471AbfKFK0y (ORCPT ); Wed, 6 Nov 2019 05:26:54 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 06 Nov 2019 19:26:52 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id C0080605F8; Wed, 6 Nov 2019 19:26:52 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 6 Nov 2019 19:26:59 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 318481A04FC; Wed, 6 Nov 2019 19:26:52 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 6/6] phy: uniphier-pcie: Add legacy SoC support for Pro5 Date: Wed, 6 Nov 2019 19:26:19 +0900 Message-Id: <1573035979-32200-7-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573035979-32200-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1573035979-32200-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add legacy SoC support that needs to manage gio clock and reset and to skip setting unimplemented phy parameters. This supports Pro5. This specifies only 1 port use because Pro5 doesn't set it in the power-on sequence. Signed-off-by: Kunihiko Hayashi --- drivers/phy/socionext/phy-uniphier-pcie.c | 83 +++++++++++++++++++++++++++---- 1 file changed, 72 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c index 25d1d9d..cd17c70 100644 --- a/drivers/phy/socionext/phy-uniphier-pcie.c +++ b/drivers/phy/socionext/phy-uniphier-pcie.c @@ -19,6 +19,10 @@ #include /* PHY */ +#define PCL_PHY_CLKCTRL 0x0000 +#define PORT_SEL_MASK GENMASK(11, 9) +#define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1) + #define PCL_PHY_TEST_I 0x2000 #define PCL_PHY_TEST_O 0x2004 #define TESTI_DAT_MASK GENMASK(13, 6) @@ -45,13 +49,14 @@ struct uniphier_pciephy_priv { void __iomem *base; struct device *dev; - struct clk *clk; - struct reset_control *rst; + struct clk *clk, *clk_gio; + struct reset_control *rst, *rst_gio; const struct uniphier_pciephy_soc_data *data; }; struct uniphier_pciephy_soc_data { bool has_syscon; + bool is_legacy; }; static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv, @@ -111,16 +116,35 @@ static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv) static int uniphier_pciephy_init(struct phy *phy) { struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); + u32 val; int ret; ret = clk_prepare_enable(priv->clk); if (ret) return ret; - ret = reset_control_deassert(priv->rst); + ret = clk_prepare_enable(priv->clk_gio); if (ret) goto out_clk_disable; + ret = reset_control_deassert(priv->rst); + if (ret) + goto out_clk_gio_disable; + + ret = reset_control_deassert(priv->rst_gio); + if (ret) + goto out_rst_assert; + + /* support only 1 port */ + val = readl(priv->base + PCL_PHY_CLKCTRL); + val &= ~PORT_SEL_MASK; + val |= PORT_SEL_1; + writel(val, priv->base + PCL_PHY_CLKCTRL); + + /* legacy controller doesn't have phy_reset and parameters */ + if (priv->data->is_legacy) + return 0; + uniphier_pciephy_set_param(priv, PCL_PHY_R00, RX_EQ_ADJ_EN, RX_EQ_ADJ_EN); uniphier_pciephy_set_param(priv, PCL_PHY_R06, RX_EQ_ADJ, @@ -134,6 +158,10 @@ static int uniphier_pciephy_init(struct phy *phy) return 0; +out_rst_assert: + reset_control_assert(priv->rst); +out_clk_gio_disable: + clk_disable_unprepare(priv->clk_gio); out_clk_disable: clk_disable_unprepare(priv->clk); @@ -144,8 +172,11 @@ static int uniphier_pciephy_exit(struct phy *phy) { struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); - uniphier_pciephy_assert(priv); + if (!priv->data->is_legacy) + uniphier_pciephy_assert(priv); + reset_control_assert(priv->rst_gio); reset_control_assert(priv->rst); + clk_disable_unprepare(priv->clk_gio); clk_disable_unprepare(priv->clk); return 0; @@ -179,13 +210,32 @@ static int uniphier_pciephy_probe(struct platform_device *pdev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - priv->clk = devm_clk_get(dev, NULL); - if (IS_ERR(priv->clk)) - return PTR_ERR(priv->clk); - - priv->rst = devm_reset_control_get_shared(dev, NULL); - if (IS_ERR(priv->rst)) - return PTR_ERR(priv->rst); + if (priv->data->is_legacy) { + priv->clk_gio = devm_clk_get(dev, "gio"); + if (IS_ERR(priv->clk_gio)) + return PTR_ERR(priv->clk_gio); + + priv->rst_gio = + devm_reset_control_get_shared(dev, "gio"); + if (IS_ERR(priv->rst_gio)) + return PTR_ERR(priv->rst_gio); + + priv->clk = devm_clk_get(dev, "link"); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + priv->rst = devm_reset_control_get_shared(dev, "link"); + if (IS_ERR(priv->rst)) + return PTR_ERR(priv->rst); + } else { + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + priv->rst = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(priv->rst)) + return PTR_ERR(priv->rst); + } phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops); if (IS_ERR(phy)) @@ -203,16 +253,27 @@ static int uniphier_pciephy_probe(struct platform_device *pdev) return PTR_ERR_OR_ZERO(phy_provider); } +static const struct uniphier_pciephy_soc_data uniphier_pro5_data = { + .has_syscon = false, + .is_legacy = true, +}; + static const struct uniphier_pciephy_soc_data uniphier_ld20_data = { .has_syscon = true, + .is_legacy = false, }; static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = { .has_syscon = false, + .is_legacy = false, }; static const struct of_device_id uniphier_pciephy_match[] = { { + .compatible = "socionext,uniphier-pro5-pcie-phy", + .data = &uniphier_pro5_data, + }, + { .compatible = "socionext,uniphier-ld20-pcie-phy", .data = &uniphier_ld20_data, },