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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36e4cfee676sm10654792f8f.49.2024.08.13.08.20.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Aug 2024 08:20:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/4] hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values Date: Tue, 13 Aug 2024 16:20:51 +0100 Message-Id: <20240813152054.2445099-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240813152054.2445099-1-peter.maydell@linaro.org> References: <20240813152054.2445099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zheyu Ma This commit adds validation checks for the MCOPRE and MCOSEL values in the rcc_update_cfgr_register function. If the MCOPRE value exceeds 0b100 or the MCOSEL value exceeds 0b111, an error is logged and the corresponding clock mux is disabled. This helps in identifying and handling invalid configurations in the RCC registers. Reproducer: cat << EOF | qemu-system-aarch64 -display \ none -machine accel=qtest, -m 512M -machine b-l475e-iot01a -qtest \ stdio writeq 0x40021008 0xffffffff EOF Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2356 Signed-off-by: Zheyu Ma Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/stm32l4x5_rcc.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rcc.c index 417bd5e85f6..59d428fa662 100644 --- a/hw/misc/stm32l4x5_rcc.c +++ b/hw/misc/stm32l4x5_rcc.c @@ -543,19 +543,31 @@ static void rcc_update_cfgr_register(Stm32l4x5RccState *s) uint32_t val; /* MCOPRE */ val = FIELD_EX32(s->cfgr, CFGR, MCOPRE); - assert(val <= 0b100); - clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_MCO], - 1, 1 << val); + if (val > 0b100) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid MCOPRE value: 0x%"PRIx32"\n", + __func__, val); + clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false); + } else { + clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_MCO], + 1, 1 << val); + } /* MCOSEL */ val = FIELD_EX32(s->cfgr, CFGR, MCOSEL); - assert(val <= 0b111); - if (val == 0) { + if (val > 0b111) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid MCOSEL value: 0x%"PRIx32"\n", + __func__, val); clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false); } else { - clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], true); - clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_MCO], - val - 1); + if (val == 0) { + clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false); + } else { + clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], true); + clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_MCO], + val - 1); + } } /* STOPWUCK */ From patchwork Tue Aug 13 15:20:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 818826 Delivered-To: patch@linaro.org Received: by 2002:adf:cd01:0:b0:367:895a:4699 with SMTP id w1csp321096wrm; Tue, 13 Aug 2024 08:22:08 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUj/Hhg/SHB5ul2puY3g0tGXjKi/wNuHeihgQudddTHo9zvQjVQA4Mf6nya+1O392ZS6aiStDmsqHdMeGY4uhcP X-Google-Smtp-Source: AGHT+IFc8QGHkEPVtjE6H+DTUAMCu+/bZdr7hv/DabvyT2EeXd31uD7LmdLIenf3TbxYlsS9/xPh X-Received: by 2002:a05:6830:6f8a:b0:709:3ab8:cd5d with SMTP id 46e09a7af769-70c9399dcf0mr5240324a34.29.1723562527864; Tue, 13 Aug 2024 08:22:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1723562527; cv=none; d=google.com; s=arc-20160816; b=fl3VVdSjQhgnGM6UDoSOiXGd0rgZ0OAAXcuDBjvBhl4CkG5BsckTFYB4Oqc8HqF1aG 7oS5EdtW8Uu1pHXXYECwa2MtvQYkeX04PGUJ6DB46WVSN4qBiqU2LjezFqi2TeRGimsf 0LafEKtwAhAbkWLsI3KQboUtA++Pr4HFQm4CM0Ur8RCevuxcBEDAxKPidyxxV53XIcwx ZzbrARHJyj35evCbYE2A1FaVKvok1eMiYJypG5t9rxgsOWeRaicEraXQwqlKV1UXSV4v yNFAUmMa4866Y/d3/2y3cEghOvWl0fVuInZDiAE9tUtqKauAdb5OVOyqAttDBkyMPq05 pkXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=x85ykqFDZu8XaN2LTiNqxv27m2mGls/KZaM5tdOiodw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=PxKNn7LsdO6OmoYdrQe2AJ8wLGe20rbN5gVCbzLR7Qy05VHBwDbyWfV4HtGepeCNtl t1KWDGi0RMcIattib/PkNQHNnxxKMudSDkoim2vvrcotSN7l6BRIQUKt7FiEzSfZx0UO 1jnI2Pwvynp0Ohv7Q4h61sf2mbCbgLILTlltL1CawdF43V8XTy4yTOAwiBuF3lVv5ZCt EYtlBK6OgD6Oa40woQoxGlbwZv6v8e8fmw81G3aef7KVxPr9HvDt2vbUWAw+x7peBp4z CMUguv1JNyyFN9hJ4lSIZXkRvEMTClROMWneiN+/b+WLLRqO+hyvKYqdJZ550s6NeRwl Ihjw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rcW3STUo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36e4cfee676sm10654792f8f.49.2024.08.13.08.20.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Aug 2024 08:20:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/4] target/arm: Clear high SVE elements in handle_vec_simd_wshli Date: Tue, 13 Aug 2024 16:20:52 +0100 Message-Id: <20240813152054.2445099-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240813152054.2445099-1-peter.maydell@linaro.org> References: <20240813152054.2445099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson AdvSIMD instructions are supposed to zero bits beyond 128. Affects SSHLL, USHLL, SSHLL2, USHLL2. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Message-id: 20240717060903.205098-15-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 28a10135032..bc2d64e8835 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10756,6 +10756,7 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); write_vec_element(s, tcg_rd, rd, i, size + 1); } + clear_vec_high(s, true, rd); } /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ From patchwork Tue Aug 13 15:20:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 818827 Delivered-To: patch@linaro.org Received: by 2002:adf:cd01:0:b0:367:895a:4699 with SMTP id w1csp321122wrm; Tue, 13 Aug 2024 08:22:11 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV1yv4k3eguxnFtfy1XALpsSRsyNvvzCe7Amv0mcjFdMXJnCx0iHhuNk3DmjRj2nyKI/D8Vd8cJDtZyOfSfptEX X-Google-Smtp-Source: AGHT+IFKj6zYsd5Tg4H4IVKFB4F63ZgZDDP8fPf9akBcE0OezbZgI5G6K8Q99cQaha9PChMOGWCm X-Received: by 2002:a05:622a:90c:b0:447:e550:8274 with SMTP id d75a77b69052e-45349977e35mr59433281cf.37.1723562531356; Tue, 13 Aug 2024 08:22:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1723562531; cv=none; d=google.com; s=arc-20160816; b=OpoS+vDQT/C1bNF0s08QQyxvatVvUuMn+hJ6zrEMgXw/BV05aUE4dztkr0GCEmeDcf m062b2DxP9Si1D9oESfkxsuv60rgNFwI7lS4wL90H8giWXUjpiDQM/LocJtw+nd3yxh5 NJbh18I4/ILTW3w5j6Vkt7376owaf3L/0Zj2vHqrSgq4zWcMpvD5nlwvhc5WnUn6Fb2j YnW8laDGZjPtA0KvoZoHChjVbiNw4/mHbsElOCqBEVyvXlA3OPfmyPOv/bNmfLW56MCc 7NiNunq6d7RP9OVu6a/aaorcl6LXYqFD23u/YzExTNTFtsE7uF63al1XHxsS7EfPRSc+ /cPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9YuTGRjD2i97kf8nmOQNNKGq72EmNNRMMhomIVoZje0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=xTPYH0gGWCayYX78t/LT1GDX5ePRAyQnHNDh3SNhnJu/LBCisrAf5ugANER87jG6Cy pIfes9rIUKBsRKHGb4PgRgL6aGYvcBsC4TqJ6a7LeXUibpRaD1n6GzRrhzlNFQNlyfbL X04te3+h1UXlZATJ9eOcnZ7u0R4CUxjvYqe6dPbQsRmcpw0UKBSOAOd0m8PPGJ+Id2Lg sredgtGtLnpoiUG/RaW0xtT/nqcYXCbouMB/Qn5rR0VxVNDBNYljt4xMyWkjueau7G4Z wqB6aM5dFJIub63/pP1FBadXiUWMHk+Ie21Zyu9oyUlh09JKOXmdiaxC3dSd68hIAldD qCWg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DZjI3yd0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36e4cfee676sm10654792f8f.49.2024.08.13.08.20.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Aug 2024 08:20:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/4] target/arm: Update translation regime comment for new features Date: Tue, 13 Aug 2024 16:20:53 +0100 Message-Id: <20240813152054.2445099-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240813152054.2445099-1-peter.maydell@linaro.org> References: <20240813152054.2445099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We have a long comment describing the Arm architectural translation regimes and how we map them to QEMU MMU indexes. This comment has got a bit out of date: * FEAT_SEL2 allows Secure EL2 and corresponding new regimes * FEAT_RME introduces Realm state and its translation regimes * We now model the Cortex-R52 so that is no longer a hypothetical * We separated Secure Stage 2 and NonSecure Stage 2 MMU indexes * We have an MMU index per physical address spacea Add the missing pieces so that the list of architectural translation regimes matches the Arm ARM, and the list and count of QEMU MMU indexes in the comment matches the enum. Signed-off-by: Peter Maydell Tested-by: Bernhard Beschow Reviewed-by: Richard Henderson Message-id: 20240809160430.1144805-2-peter.maydell@linaro.org --- target/arm/cpu.h | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a12859fc533..216774f5d3a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2772,8 +2772,14 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); * + NonSecure EL1 & 0 stage 2 * + NonSecure EL2 * + NonSecure EL2 & 0 (ARMv8.1-VHE) - * + Secure EL1 & 0 - * + Secure EL3 + * + Secure EL1 & 0 stage 1 + * + Secure EL1 & 0 stage 2 (FEAT_SEL2) + * + Secure EL2 (FEAT_SEL2) + * + Secure EL2 & 0 (FEAT_SEL2) + * + Realm EL1 & 0 stage 1 (FEAT_RME) + * + Realm EL1 & 0 stage 2 (FEAT_RME) + * + Realm EL2 (FEAT_RME) + * + EL3 * If EL3 is 32-bit: * + NonSecure PL1 & 0 stage 1 * + NonSecure PL1 & 0 stage 2 @@ -2805,10 +2811,12 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); * table over and over. * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access * Never (PAN) bit within PSTATE. - * 7. we fold together the secure and non-secure regimes for A-profile, + * 7. we fold together most secure and non-secure regimes for A-profile, * because there are no banked system registers for aarch64, so the * process of switching between secure and non-secure is * already heavyweight. + * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, + * because both are in use simultaneously for Secure EL2. * * This gives us the following list of cases: * @@ -2820,14 +2828,15 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); * EL2 EL2&0 +PAN * EL2 (aka NS PL2) * EL3 (aka S PL1) - * Physical (NS & S) - * Stage2 (NS & S) + * Stage2 Secure + * Stage2 NonSecure + * plus one TLB per Physical address space: S, NS, Realm, Root * - * for a total of 12 different mmu_idx. + * for a total of 14 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish EL0 and EL1 (and - * EL2 if we ever model a Cortex-R52). + * EL2 for cores like the Cortex-R52). * * M profile CPUs are rather different as they do not have a true MMU. * They have the following different MMU indexes: From patchwork Tue Aug 13 15:20:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 818829 Delivered-To: patch@linaro.org Received: by 2002:adf:cd01:0:b0:367:895a:4699 with SMTP id w1csp321215wrm; Tue, 13 Aug 2024 08:22:26 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXtn+DNWwvYxV8hIQaTnOzWElv2DGMVb6t2jjUWXxidqpjwlc3Sykec8XsaQnxe+TTzIv08QlwBtnbAsOmuf42a X-Google-Smtp-Source: AGHT+IElnFUmT9yVaoKlVYXHIooD7irlg0/aHkI+tGdykfAwjb7c/a46aGhca3iWKzNnv2zwZziv X-Received: by 2002:a05:620a:1709:b0:79e:fed9:795c with SMTP id af79cd13be357-7a4ee1434cemr8458385a.19.1723562545853; Tue, 13 Aug 2024 08:22:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1723562545; cv=none; d=google.com; s=arc-20160816; b=IQPeRelL5jTfw9JqAlSbol2J4CYW7LKWarpL3OD/XAXJmh4cMBC2mg9MqQwXqUkVmv qgCkGb+232QPu3kp52DIGHYLBB8VfnpwQCY3CnsbY523NsKkq3CMTzkDQGMuHZtgdAo+ FoQ59oMxf/zzd6kk6O4H694WzcfuF/I6NiVWNYQDitiEsYp/npgJPcAFPllaIt6daSvm Cus7Z94Tmzm6OQKt5B46+0+vf3YFDk6Mfzorrs783NKxBboAUavBRR2ZN8DyqNwRqoRx TQdZRNO9zRSn98XEGEKcRKVA5RNv8OcZURRtdZNrGRTasbnr1XWwFZM2tKA3oFGY3/2i y/ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FFI54K3qWCfR6N2VCEfFFaegAvjAkBmK5qTkEKFnn4o=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=O9s4U5J9mRyr/BjUFFKDzddmExKItZ1du1beVSJoLrgiycBHzcyYR266Fn8XI7Zvgg V1Y0HfdBjOYcpkTtqQB/28OZDTlkPWyrqqDIsDK1o5WpToOYyFjYHDUvVHi5d038S99Q Woj4SYTqv0OoVixzQAzHio95t7b6Vb1S5Ve444+Q+YkJekomwzhk3fedIxcFlJ4kZwae bn32ST5JtcotSRw8UPrJlBD0iR9L2cr2Z52fE5/AW5YRVGa29es6gEGsWfWgLLup6nZR zUAUfYUNufa7TNr7poup2I5HDwxvqNLv0R7/E9k1lD2kIeIKC2sk1dXNApAshACCqOqu 7HrQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TdT3lMhL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36e4cfee676sm10654792f8f.49.2024.08.13.08.20.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Aug 2024 08:20:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/4] target/arm: Fix usage of MMU indexes when EL3 is AArch32 Date: Tue, 13 Aug 2024 16:20:54 +0100 Message-Id: <20240813152054.2445099-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240813152054.2445099-1-peter.maydell@linaro.org> References: <20240813152054.2445099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Our current usage of MMU indexes when EL3 is AArch32 is confused. Architecturally, when EL3 is AArch32, all Secure code runs under the Secure PL1&0 translation regime: * code at EL3, which might be Mon, or SVC, or any of the other privileged modes (PL1) * code at EL0 (Secure PL0) This is different from when EL3 is AArch64, in which case EL3 is its own translation regime, and EL1 and EL0 (whether AArch32 or AArch64) have their own regime. We claimed to be mapping Secure PL1 to our ARMMMUIdx_EL3, but didn't do anything special about Secure PL0, which meant it used the same ARMMMUIdx_EL10_0 that NonSecure PL0 does. This resulted in a bug where arm_sctlr() incorrectly picked the NonSecure SCTLR as the controlling register when in Secure PL0, which meant we were spuriously generating alignment faults because we were looking at the wrong SCTLR control bits. The use of ARMMMUIdx_EL3 for Secure PL1 also resulted in the bug that we wouldn't honour the PAN bit for Secure PL1, because there's no equivalent _PAN mmu index for it. We could fix this in one of two ways: * The most straightforward is to add new MMU indexes EL30_0, EL30_3, EL30_3_PAN to correspond to "Secure PL1&0 at PL0", "Secure PL1&0 at PL1", and "Secure PL1&0 at PL1 with PAN". This matches how we use indexes for the AArch64 regimes, and preserves propirties like being able to determine the privilege level from an MMU index without any other information. However it would add two MMU indexes (we can share one with ARMMMUIdx_EL3), and we are already using 14 of the 16 the core TLB code permits. * The more complicated approach is the one we take here. We use the same MMU indexes (E10_0, E10_1, E10_1_PAN) for Secure PL1&0 than we do for NonSecure PL1&0. This saves on MMU indexes, but means we need to check in some places whether we're in the Secure PL1&0 regime or not before we interpret an MMU index. The changes in this commit were created by auditing all the places where we use specific ARMMMUIdx_ values, and checking whether they needed to be changed to handle the new index value usage. Note for potential stable backports: taking also the previous (comment-change-only) commit might make the backport easier. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2326 Signed-off-by: Peter Maydell Tested-by: Bernhard Beschow Reviewed-by: Richard Henderson Message-id: 20240809160430.1144805-3-peter.maydell@linaro.org --- target/arm/cpu.h | 31 ++++++++++++++++++------------- target/arm/internals.h | 27 +++++++++++++++++++++++---- target/arm/tcg/translate.h | 2 ++ target/arm/helper.c | 34 +++++++++++++++++++++++----------- target/arm/ptw.c | 6 +++++- target/arm/tcg/hflags.c | 4 ++++ target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/translate.c | 9 +++++---- 8 files changed, 81 insertions(+), 34 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 216774f5d3a..9a3fd595621 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2784,8 +2784,7 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); * + NonSecure PL1 & 0 stage 1 * + NonSecure PL1 & 0 stage 2 * + NonSecure PL2 - * + Secure PL0 - * + Secure PL1 + * + Secure PL1 & 0 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) * * For QEMU, an mmu_idx is not quite the same as a translation regime because: @@ -2803,37 +2802,39 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); * The only use of stage 2 translations is either as part of an s1+2 * lookup or when loading the descriptors during a stage 1 page table walk, * and in both those cases we don't use the TLB. - * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" - * translation regimes, because they map reasonably well to each other - * and they can't both be active at the same time. - * 5. we want to be able to use the TLB for accesses done as part of a + * 4. we want to be able to use the TLB for accesses done as part of a * stage1 page table walk, rather than having to walk the stage2 page * table over and over. - * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access + * 5. we need separate EL1/EL2 mmu_idx for handling the Privileged Access * Never (PAN) bit within PSTATE. - * 7. we fold together most secure and non-secure regimes for A-profile, + * 6. we fold together most secure and non-secure regimes for A-profile, * because there are no banked system registers for aarch64, so the * process of switching between secure and non-secure is * already heavyweight. - * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, + * 7. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, * because both are in use simultaneously for Secure EL2. * * This gives us the following list of cases: * - * EL0 EL1&0 stage 1+2 (aka NS PL0) - * EL1 EL1&0 stage 1+2 (aka NS PL1) - * EL1 EL1&0 stage 1+2 +PAN + * EL0 EL1&0 stage 1+2 (or AArch32 PL0 PL1&0 stage 1+2) + * EL1 EL1&0 stage 1+2 (or AArch32 PL1 PL1&0 stage 1+2) + * EL1 EL1&0 stage 1+2 +PAN (or AArch32 PL1 PL1&0 stage 1+2 +PAN) * EL0 EL2&0 * EL2 EL2&0 * EL2 EL2&0 +PAN * EL2 (aka NS PL2) - * EL3 (aka S PL1) + * EL3 (not used when EL3 is AArch32) * Stage2 Secure * Stage2 NonSecure * plus one TLB per Physical address space: S, NS, Realm, Root * * for a total of 14 different mmu_idx. * + * Note that when EL3 is AArch32, the usage is potentially confusing + * because the MMU indexes are named for their AArch64 use, so code + * using the ARMMMUIdx_E10_1 might be at EL3, not EL1. This is because + * Secure PL1 is always at EL3. + * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish EL0 and EL1 (and * EL2 for cores like the Cortex-R52). @@ -3126,6 +3127,10 @@ FIELD(TBFLAG_A32, NS, 10, 1) * This requires an SME trap from AArch32 mode when using NEON. */ FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) +/* + * Indicates whether we are in the Secure PL1&0 translation regime + */ +FIELD(TBFLAG_A32, S_PL1_0, 12, 1) /* * Bit usage when in AArch32 state, for M-profile only. diff --git a/target/arm/internals.h b/target/arm/internals.h index 757b1fae925..203a2dae148 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -275,6 +275,20 @@ FIELD(CNTHCTL, CNTPMASK, 19, 1) #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ +/** + * arm_aa32_secure_pl1_0(): Return true if in Secure PL1&0 regime + * + * Return true if the CPU is in the Secure PL1&0 translation regime. + * This requires that EL3 exists and is AArch32 and we are currently + * Secure. If this is the case then the ARMMMUIdx_E10* apply and + * mean we are in EL3, not EL1. + */ +static inline bool arm_aa32_secure_pl1_0(CPUARMState *env) +{ + return arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3) && arm_is_secure(env); +} + /** * raise_exception: Raise the specified exception. * Raise a guest exception with the specified value, syndrome register @@ -808,7 +822,12 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) return mmu_idx | ARM_MMU_IDX_A; } -int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); +/** + * Return the exception level we're running at if our current MMU index + * is @mmu_idx. @s_pl1_0 should be true if this is the AArch32 + * Secure PL1&0 translation regime. + */ +int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx, bool s_pl1_0); /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); @@ -903,11 +922,11 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) return 3; case ARMMMUIdx_E10_0: case ARMMMUIdx_Stage1_E0: - return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1 : 3; - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1 : 3; case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 01c217f4a45..3f0e9ceaa39 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -165,6 +165,8 @@ typedef struct DisasContext { uint8_t gm_blocksize; /* True if the current insn_start has been updated. */ bool insn_start_updated; + /* True if this is the AArch32 Secure PL1&0 translation regime */ + bool s_pl1_0; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 8fb4b474e83..0a582c1cd3b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3700,7 +3700,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, */ format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); - if (arm_feature(env, ARM_FEATURE_EL2)) { + if (arm_feature(env, ARM_FEATURE_EL2) && !arm_aa32_secure_pl1_0(env)) { if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1 || mmu_idx == ARMMMUIdx_E10_1_PAN) { @@ -3774,13 +3774,11 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) case 0: /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ switch (el) { - case 3: - mmu_idx = ARMMMUIdx_E3; - break; case 2: g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ /* fall through */ case 1: + case 3: if (ri->crm == 9 && arm_pan_enabled(env)) { mmu_idx = ARMMMUIdx_Stage1_E1_PAN; } else { @@ -11861,8 +11859,11 @@ void arm_cpu_do_interrupt(CPUState *cs) uint64_t arm_sctlr(CPUARMState *env, int el) { - /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ - if (el == 0) { + if (arm_aa32_secure_pl1_0(env)) { + /* In Secure PL1&0 SCTLR_S is always controlling */ + el = 3; + } else if (el == 0) { + /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); el = mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1; } @@ -12522,8 +12523,12 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } -/* Return the exception level we're running at if this is our mmu_idx */ -int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) +/* + * Return the exception level we're running at if this is our mmu_idx. + * s_pl1_0 should be true if this is the AArch32 Secure PL1&0 translation + * regime. + */ +int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx, bool s_pl1_0) { if (mmu_idx & ARM_MMU_IDX_M) { return mmu_idx & ARM_MMU_IDX_M_PRIV; @@ -12535,7 +12540,7 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) return 0; case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - return 1; + return s_pl1_0 ? 3 : 1; case ARMMMUIdx_E2: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: @@ -12573,6 +12578,15 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) idx = ARMMMUIdx_E10_0; } break; + case 3: + /* + * AArch64 EL3 has its own translation regime; AArch32 EL3 + * uses the Secure PL1&0 translation regime. + */ + if (arm_el_is_aa64(env, 3)) { + return ARMMMUIdx_E3; + } + /* fall through */ case 1: if (arm_pan_enabled(env)) { idx = ARMMMUIdx_E10_1_PAN; @@ -12592,8 +12606,6 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) idx = ARMMMUIdx_E2; } break; - case 3: - return ARMMMUIdx_E3; default: g_assert_not_reached(); } diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4476b32ff50..278004661bf 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3576,7 +3576,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: - ss = arm_security_space_below_el3(env); + if (arm_aa32_secure_pl1_0(env)) { + ss = ARMSS_Secure; + } else { + ss = arm_security_space_below_el3(env); + } break; case ARMMMUIdx_Stage2: /* diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index f03977b4b00..bab7822ef66 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -198,6 +198,10 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); } + if (arm_aa32_secure_pl1_0(env)) { + DP_TBFLAG_A32(flags, S_PL1_0, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index bc2d64e8835..4684e7eb6ea 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -11979,7 +11979,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->tbii = EX_TBFLAG_A64(tb_flags, TBII); dc->tbid = EX_TBFLAG_A64(tb_flags, TBID); dc->tcma = EX_TBFLAG_A64(tb_flags, TCMA); - dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); + dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx, false); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index c5bc691d92b..e2748ff2bb8 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -7546,10 +7546,6 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) core_mmu_idx = EX_TBFLAG_ANY(tb_flags, MMUIDX); dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); - dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); -#if !defined(CONFIG_USER_ONLY) - dc->user = (dc->current_el == 0); -#endif dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); @@ -7580,7 +7576,12 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) } dc->sme_trap_nonstreaming = EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); + dc->s_pl1_0 = EX_TBFLAG_A32(tb_flags, S_PL1_0); } + dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx, dc->s_pl1_0); +#if !defined(CONFIG_USER_ONLY) + dc->user = (dc->current_el == 0); +#endif dc->lse2 = false; /* applies only to aarch64 */ dc->cp_regs = cpu->cp_regs; dc->features = env->features;