From patchwork Sat Nov 9 15:15:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 179021 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp4307155ilf; Sat, 9 Nov 2019 07:15:49 -0800 (PST) X-Google-Smtp-Source: APXvYqwx652MzxKjw45PPPrsiqsIVF/kazzY0E+W3Dq+gLpb0S6L1PtZZYXEI6NLDZl6K5f00MJ2 X-Received: by 2002:a50:870c:: with SMTP id i12mr16302068edb.16.1573312549004; Sat, 09 Nov 2019 07:15:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573312549; cv=none; d=google.com; s=arc-20160816; b=YNUVBa2rfOGB57iayZ3CShTADVJownXkLjSpt2ZO7SOZHp6cm5GyWb/YX0fd5/PJBP Ky2HJQptdWJWon6eOAT6LYO569jmLrkm4WKalEL2qkY+RdXnxuKGuzs8M1dE1CRgeO1L eGXFybvcZ0DiArTT1Cvow1+4mUmNKnvY2Wc9EVDwlmvYEBZkxIeB2F0v9W/MwTannGjl 4jr4X7BvcTuzVuQjCMMWMYAlaTrKckI/nvnIaU+RaOtHGkEWLq55iCkN8guRahplS3XC xDxgv12pIDqcVN0LcnvZOY6TehbroaEu3KG8uquNl4KKeo086/WjSsnwPjQSHb9YWlJj Gx+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Adn9YCxB93/dkCBHMnDfzFbMC9kwY9M8O9KGdNuZYdY=; b=KgJHSO4Jrc4UpZy6oWVX7P2Llp7kubnQWcf16eS3nqts/99k4dwSKOa1IVynhAvoYB HQEO+ZdBSiaiXFf7n+6Lq0UsjeaHVHZt1/fBLYkjvqO2O3HC+JsQecGTNYxeCdSAS7Di N7+dPjI95F+5SrqSd/BuSZlRr37VYYC5WFcYzeUDOg8So93l3EFx1U51DEVx4rB/2VsG Bko0IAdGUVH8lxmdMOiKXxnwo4e90fE27rA/w7pY7K8wNeHojGUguIb1jvJDq2cXUtAr kLjS2knUMahzh8KjLSN3+iyIpSn+MXPldMcS0MJM5VL0VeVjxU77powvJVYbl+XVoJ6K Jd5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="HD/bpT6c"; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id uz25si5948670ejb.43.2019.11.09.07.15.48; Sat, 09 Nov 2019 07:15:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="HD/bpT6c"; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726289AbfKIPPr (ORCPT + 5 others); Sat, 9 Nov 2019 10:15:47 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:39440 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726597AbfKIPPo (ORCPT ); Sat, 9 Nov 2019 10:15:44 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xA9FFbpo066989; Sat, 9 Nov 2019 09:15:37 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1573312537; bh=Adn9YCxB93/dkCBHMnDfzFbMC9kwY9M8O9KGdNuZYdY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HD/bpT6cvZAyiVEDyvqfSlhxsh5QVsZUoso2P5Jg4IWQQ6kR2j4Qv+qT8VNdN54mZ hoPA0+CauaK9DOwXndpax0ZxYqOoFh2LnhVsWfpsTxqKXBVTzDaR9oSFNjOdrnJJzn oIQfWG+nv9Gd7W4UjrK2MHx04zOYv5WT4MeXktvA= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xA9FFbAn128742 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 9 Nov 2019 09:15:37 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Sat, 9 Nov 2019 09:15:37 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Sat, 9 Nov 2019 09:15:21 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xA9FFaH0024134; Sat, 9 Nov 2019 09:15:36 -0600 From: Grygorii Strashko To: Florian Fainelli , , Ilias Apalodimas , Andrew Lunn , "David S . Miller" , Ivan Khoronzhuk , Jiri Pirko CC: Sekhar Nori , , , Murali Karicheri , Ivan Vecera , Rob Herring , , Grygorii Strashko Subject: [PATCH v6 net-next 01/13] net: ethernet: ti: ale: clean ale tbl on init and intf restart Date: Sat, 9 Nov 2019 17:15:13 +0200 Message-ID: <20191109151525.18651-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191109151525.18651-1-grygorii.strashko@ti.com> References: <20191109151525.18651-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Clean CPSW ALE on init and intf restart (up/down) to avoid reading obsolete or garbage entries from ALE table. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw_ale.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 84025dcc78d5..e7c24396933e 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -779,6 +779,7 @@ void cpsw_ale_start(struct cpsw_ale *ale) void cpsw_ale_stop(struct cpsw_ale *ale) { del_timer_sync(&ale->timer); + cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); } @@ -862,6 +863,7 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS; } + cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); return ale; } From patchwork Sat Nov 9 15:15:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 179022 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp4307256ilf; Sat, 9 Nov 2019 07:15:55 -0800 (PST) X-Google-Smtp-Source: APXvYqy2lRrnUmQRziGNtohHOPPlk0C3/mAUObpi/Hbp6iiNW3Zh4v7pmoVmqFTf9Cptld0Z9YZ2 X-Received: by 2002:a50:af44:: with SMTP id g62mr16863692edd.164.1573312555817; Sat, 09 Nov 2019 07:15:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573312555; cv=none; d=google.com; s=arc-20160816; b=gmNgTlRrGBylgl//wBhFlpeGOqYEdoYFQxzWqURahvOFMvLzBM9GO+uvDGhzZ1bDRR 9s5hKyqOy494NlOJts6Hhbwgc22aFtKfyGsf/uYkX847XcPsyKQcwjuPs+DFLAGcHVwM X15U7CTKifvDX1iyZX+c9/gixoCz+9iw9TlocuG/RhgS6/vXrEhBvlZ3hnqVeEuyjexu eKpGyIc3EQLPQ7R/GHWKh6NuqcRdEDzKOVe9nSfpY3t8olR/2UA8rQfYLzGLrs2UtOfz QeD2XZArmubbUvrPXu9ZszxjZ07XWMegMa89v/NCtn4LdSZtViP+eFsuyMQPejKP0N3p M6tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=2SChlmTyfIFsa6oMmJU6CdK7MyJ3jnSEtHLZMXdh/uU=; b=Q8SdU34SgP0hxgeAQXAfrzTBY0Pe2HIedS9j/Oc33XyPgAhmLjwm30EQmbouuDCVXl ccgg284k238CaioCyUZriEEB8beg6r9GsaCrLKALt4PCwTX4Xt3sOD86H0ciLHBUH6zx v9MdnS+KBDSmU0axhk1JAfEOfxfCTENuotzQzAWUPBoFMBO/Il2H8K6CPeP0VrlVRpkc bnR6I25dwI1yV5wuQcCK2c5WA4qxnnT14UTpqv6waBIVBgdFP1CtE5RCBaYCxFg2JOBr H1GnSOoZr+9q3gUeOjuduMWgJDfaOYmccutybqVwQtxI4+Ck3UajKJGwzOrBE5PR+UXS PJEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="f9w4/zxd"; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Ivan Khoronzhuk , Jiri Pirko CC: Sekhar Nori , , , Murali Karicheri , Ivan Vecera , Rob Herring , , Grygorii Strashko Subject: [PATCH v6 net-next 02/13] net: ethernet: ti: cpsw: allow untagged traffic on host port Date: Sat, 9 Nov 2019 17:15:14 +0200 Message-ID: <20191109151525.18651-3-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191109151525.18651-1-grygorii.strashko@ti.com> References: <20191109151525.18651-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Now untagged vlan traffic is not support on Host P0 port. This patch adds in ALE context bitmap of VLANs for which Host P0 port bit set in Force Untagged Packet Egress bitmask in VLANs ALE entries, and adds corresponding check in VLAN incapsulation header parsing function cpsw_rx_vlan_encap(). Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw.c | 17 ++++++++--------- drivers/net/ethernet/ti/cpsw_ale.c | 21 ++++++++++++++++++++- drivers/net/ethernet/ti/cpsw_ale.h | 5 +++++ 3 files changed, 33 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 329671e66fe4..15a76d3842c5 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -428,17 +428,16 @@ static void cpsw_rx_vlan_encap(struct sk_buff *skb) /* Ignore vid 0 and pass packet as is */ if (!vid) return; - /* Ignore default vlans in dual mac mode */ - if (cpsw->data.dual_emac && - vid == cpsw->slaves[priv->emac_port].port_vlan) - return; - prio = (rx_vlan_encap_hdr >> - CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) & - CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK; + /* Untag P0 packets if set for vlan */ + if (!cpsw_ale_get_vlan_p0_untag(cpsw->ale, vid)) { + prio = (rx_vlan_encap_hdr >> + CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) & + CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK; - vtag = (prio << VLAN_PRIO_SHIFT) | vid; - __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag); + vtag = (prio << VLAN_PRIO_SHIFT) | vid; + __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag); + } /* strip vlan tag for VLAN-tagged packet */ if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) { diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index e7c24396933e..977bb4251100 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -5,6 +5,8 @@ * Copyright (C) 2012 Texas Instruments * */ +#include +#include #include #include #include @@ -415,6 +417,17 @@ static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry, writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); } +static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry, + u16 vid, int untag_mask) +{ + cpsw_ale_set_vlan_untag_force(ale_entry, + untag_mask, ale->vlan_field_bits); + if (untag_mask & ALE_PORT_HOST) + bitmap_set(ale->p0_untag_vid_mask, vid, 1); + else + bitmap_clear(ale->p0_untag_vid_mask, vid, 1); +} + int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag, int reg_mcast, int unreg_mcast) { @@ -427,8 +440,8 @@ int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag, cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN); cpsw_ale_set_vlan_id(ale_entry, vid); + cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); - cpsw_ale_set_vlan_untag_force(ale_entry, untag, ale->vlan_field_bits); if (!ale->params.nu_switch_ale) { cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast, ale->vlan_field_bits); @@ -460,6 +473,7 @@ int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) return -ENOENT; cpsw_ale_read(ale, idx, ale_entry); + cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0); if (port_mask) cpsw_ale_set_vlan_member_list(ale_entry, port_mask, @@ -792,6 +806,11 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) if (!ale) return NULL; + ale->p0_untag_vid_mask = + devm_kmalloc_array(params->dev, BITS_TO_LONGS(VLAN_N_VID), + sizeof(unsigned long), + GFP_KERNEL); + ale->params = *params; ale->ageout = ale->params.ale_ageout * HZ; diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 370df254eb12..93d6d56d12f4 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -35,6 +35,7 @@ struct cpsw_ale { u32 port_mask_bits; u32 port_num_bits; u32 vlan_field_bits; + unsigned long *p0_untag_vid_mask; }; enum cpsw_ale_control { @@ -115,4 +116,8 @@ int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control, int value); void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data); +static inline int cpsw_ale_get_vlan_p0_untag(struct cpsw_ale *ale, u16 vid) +{ + return test_bit(vid, ale->p0_untag_vid_mask); +} #endif From patchwork Sat Nov 9 15:15:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 179026 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp4307896ilf; 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Miller" , Ivan Khoronzhuk , Jiri Pirko CC: Sekhar Nori , , , Murali Karicheri , Ivan Vecera , Rob Herring , , Grygorii Strashko Subject: [PATCH v6 net-next 06/13] dt-bindings: net: ti: add new cpsw switch driver bindings Date: Sat, 9 Nov 2019 17:15:18 +0200 Message-ID: <20191109151525.18651-7-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191109151525.18651-1-grygorii.strashko@ti.com> References: <20191109151525.18651-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add bindings for the new TI CPSW switch driver. Comparing to the legacy bindings (net/cpsw.txt): - ports definition follows DSA bindings (net/dsa/dsa.txt) and ports can be marked as "disabled" if not physically wired. - all deprecated properties dropped; - all legacy propertiies dropped which represent constant HW cpapbilities (cpdma_channels, ale_entries, bd_ram_size, mac_control, slaves, active_slave) - TI CPTS DT properties are reused as is, but grouped in "cpts" sub-node - TI Davinci MDIO DT bindings are reused as is, because Davinci MDIO is reused. Signed-off-by: Grygorii Strashko --- .../bindings/net/ti,cpsw-switch.yaml | 245 ++++++++++++++++++ 1 file changed, 245 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml new file mode 100644 index 000000000000..afeb6a4f1ada --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml @@ -0,0 +1,245 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings + +maintainers: + - Grygorii Strashko + - Sekhar Nori + +description: + The 3-port switch gigabit ethernet subsystem provides ethernet packet + communication and can be configured as an ethernet switch. It provides the + gigabit media independent interface (GMII),reduced gigabit media + independent interface (RGMII), reduced media independent interface (RMII), + the management data input output (MDIO) for physical layer device (PHY) + management. + +properties: + compatible: + oneOf: + - const: ti,cpsw-switch + - items: + - const: ti,am335x-cpsw-switch + - const: ti,cpsw-switch + - items: + - const: ti,am4372-cpsw-switch + - const: ti,cpsw-switch + - items: + - const: ti,dra7-cpsw-switch + - const: ti,cpsw-switch + + reg: + maxItems: 1 + description: + The physical base address and size of full the CPSW module IO range + + ranges: true + + clocks: + maxItems: 1 + description: CPSW functional clock + + clock-names: + maxItems: 1 + items: + - const: fck + + interrupts: + maxItems: 4 + items: + - description: RX_THRESH interrupt + - description: RX interrupt + - description: TX interrupt + - description: MISC interrupt + + interrupt-names: + maxItems: 4 + items: + - const: "rx_thresh" + - const: "rx" + - const: "tx" + - const: "misc" + + pinctrl-names: true + + syscon: + $ref: /schemas/types.yaml#definitions/phandle + maxItems: 1 + description: + Phandle to the system control device node which provides access to + efuse IO range with MAC addresses + + + ethernet-ports: + type: object + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + "^port@[0-9]+$": + type: object + minItems: 1 + maxItems: 2 + description: CPSW external ports + + allOf: + - $ref: ethernet-controller.yaml# + + properties: + reg: + maxItems: 1 + enum: [1, 2] + description: CPSW port number + + phys: + $ref: /schemas/types.yaml#definitions/phandle-array + maxItems: 1 + description: phandle on phy-gmii-sel PHY + + label: + $ref: /schemas/types.yaml#/definitions/string-array + maxItems: 1 + description: label associated with this port + + ti,dual-emac-pvid: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + minimum: 1 + maximum: 1024 + description: + Specifies default PORT VID to be used to segregate + ports. Default value - CPSW port number. + + required: + - reg + - phys + + mdio: + type: object + allOf: + - $ref: "ti,davinci-mdio.yaml#" + description: + CPSW MDIO bus. + + cpts: + type: object + description: + The Common Platform Time Sync (CPTS) module + + properties: + clocks: + maxItems: 1 + description: CPTS reference clock + + clock-names: + maxItems: 1 + items: + - const: cpts + + cpts_clock_mult: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: + Numerator to convert input clock ticks into ns + + cpts_clock_shift: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: + Denominator to convert input clock ticks into ns. + Mult and shift will be calculated basing on CPTS rftclk frequency if + both cpts_clock_shift and cpts_clock_mult properties are not provided. + + required: + - clocks + - clock-names + +required: + - compatible + - reg + - ranges + - clocks + - clock-names + - interrupts + - interrupt-names + - '#address-cells' + - '#size-cells' + +examples: + - | + #include + #include + #include + + mac_sw: switch@0 { + compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; + reg = <0x0 0x4000>; + ranges = <0 0 0x4000>; + clocks = <&gmac_main_clk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + syscon = <&scm_conf>; + inctrl-names = "default", "sleep"; + + interrupts = , + , + , + ; + interrupt-names = "rx_thresh", "rx", "tx", "misc"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + label = "port1"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1>; + phy-handle = <ðphy0_sw>; + phy-mode = "rgmii"; + ti,dual_emac_pvid = <1>; + }; + + cpsw_port2: port@2 { + reg = <2>; + label = "wan"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2>; + phy-handle = <ðphy1_sw>; + phy-mode = "rgmii"; + ti,dual_emac_pvid = <2>; + }; + }; + + davinci_mdio_sw: mdio@1000 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x1000 0x100>; + clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + + ethphy0_sw: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1_sw: ethernet-phy@1 { + reg = <41>; + }; + }; + + cpts { + clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; + clock-names = "cpts"; + }; + };