From patchwork Fri Aug 16 04:06:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 819970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4885E83CA0; Fri, 16 Aug 2024 04:06:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723781176; cv=none; b=BCcPfhWyjPZH/m/WXPGz6bHa6T8VIgPQgr9Yf24ZGrg4LuNTaTW0JlzbZ3WO3rygOEwK42TWzpdCS49fTBi5rUl5FDat+U5zQBbMkfqcDtdgJV8PPmDUr8zmss4YMWpW8bQcrIQeT2yJpsReUvvFTkmCFchRTop6kA+LQzd/UhM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723781176; c=relaxed/simple; bh=ysYUgCiujfaTybXqioFulPopZi37CP7a8Iadi2yWj3I=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=QU3ZtW5IxFAtdmrYTw8n7jv1kFJsRZ3lHo/WzyqTEwrlYhANmHcHaH+FZik+VKYb/oothTjZt7LvL3eBtsrhZ/61pFqkd3T2eiCs/TmOTvXLcOrBPOXP/nkiYTFTzIDbw71VBZFK2tsRUOBisn7uvCsgDIFbdKCDwGcYB9SRGww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VsV1ZVTh; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VsV1ZVTh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723781175; x=1755317175; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=ysYUgCiujfaTybXqioFulPopZi37CP7a8Iadi2yWj3I=; b=VsV1ZVThOzZBanBk7iqRnM4kGnUR4E1fTRZDwEcE1h3emgDyz72u9NO+ lNNbult+fuOmua3wXvrpqjy10ek9cyF5W3OZrbiwxTc5C3MZcCHo/Lebz FLJ6O55+YyZr+YK8voM1xUDgWuONDnh1RI3udx5FaOLb4+wExBokYx0sd O2/0bRQGE2IvHQ6o80c6HyIr/rAF935eZ39DhAtj1pSsZHeCd6snlzl0h B16WWWdttG0AKezvA+dA5DyELIVoBW82tf7o6I2GvxOANSBWYLDy6B6KQ xQ/2NqY/8BBBAxZNxjmzscMYWb8wWZbJ3ibxOgxKVMeQvzrXR176qgJ7N Q==; X-CSE-ConnectionGUID: DdELEOUtQkam5ftDgUrbWg== X-CSE-MsgGUID: iZy2Ln4cTM2YcHoHmrcG0Q== X-IronPort-AV: E=McAfee;i="6700,10204,11165"; a="39521710" X-IronPort-AV: E=Sophos;i="6.10,150,1719903600"; d="scan'208";a="39521710" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2024 21:06:15 -0700 X-CSE-ConnectionGUID: hYVM8tdqT9u/JZaLdGr8DA== X-CSE-MsgGUID: iUujCzfGTIubs8muKB5a7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,150,1719903600"; d="scan'208";a="97070305" Received: from kerandaa-mobl.amr.corp.intel.com (HELO desk) ([10.125.112.221]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2024 21:06:14 -0700 Date: Thu, 15 Aug 2024 21:06:13 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v3 01/10] x86/cpu: Prepend 0x to the hex values in cpu_debug_show() Message-ID: <20240815-add-cpu-type-v3-1-234162352057@linux.intel.com> X-Mailer: b4 0.14.1 References: <20240815-add-cpu-type-v3-0-234162352057@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240815-add-cpu-type-v3-0-234162352057@linux.intel.com> The hex values in CPU debug interface are not prepended with 0x. This may cause misinterpretation of values. Fix it. Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/debugfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/debugfs.c b/arch/x86/kernel/cpu/debugfs.c index 3baf3e435834..ca373b990c47 100644 --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -16,8 +16,8 @@ static int cpu_debug_show(struct seq_file *m, void *p) if (!c->initialized) return 0; - seq_printf(m, "initial_apicid: %x\n", c->topo.initial_apicid); - seq_printf(m, "apicid: %x\n", c->topo.apicid); + seq_printf(m, "initial_apicid: 0x%x\n", c->topo.initial_apicid); + seq_printf(m, "apicid: 0x%x\n", c->topo.apicid); seq_printf(m, "pkg_id: %u\n", c->topo.pkg_id); seq_printf(m, "die_id: %u\n", c->topo.die_id); seq_printf(m, "cu_id: %u\n", c->topo.cu_id); From patchwork Fri Aug 16 04:06:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 819969 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99A9C13CFA5; Fri, 16 Aug 2024 04:06:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723781194; cv=none; b=ew5PaEonDFLz2Qkst1/BqQ+5NV8G6W8JLhs7LtJue9CPuRR86IKgHMNcan66WKPWru0GwwXWCNMRZUUQ0V5UnpmYbJVJk54AetnfBsdAnjRr+zdedqsZggBhU30u/s3Rk8JILvKgTu92To5CX3wt4MYk2Cm+5qM5sEOgtkKOMNI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723781194; c=relaxed/simple; bh=Exn6IbYfVXDxGcqCe/b6TH8T+b6+3Z9dfEuR7SuZcsk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=FkoxdykL+qU09CsIPkt6bdNH2pfjOMLhb64zv4rGzHO02UNp9vYNcMT/Zg1lccfoKJ6u34WeELvbNjzT+LiV3xNkJLk2RW/P8C1RH6O7NssUZUxxLGouvJx3Z+dHzXWXQbzvq0xE/RRdMgZ2TTggK9X7jInNFbg3TlK7ogEMr4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Zids3swb; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Zids3swb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723781193; x=1755317193; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=Exn6IbYfVXDxGcqCe/b6TH8T+b6+3Z9dfEuR7SuZcsk=; b=Zids3swbhAjMT6ovUk22KLlNbN/vMv5p0bXPZpl9U0vFa/Q9iZICF+M+ HVdJMrHzbHsH0ImVWDz/BfJ07U7sle/79nFoo2EpQVHCZyZ5RtpDAu3mO KuVINGtE6z1A+KPLEGayYjQEcpzAP9/bgSBiaGULF9QoPS9r4XKorUenb iD0bnApfo68J+GF5+HiPZ4w6IjtAczuB3TPA2v0XLgkBg+QwyT18cgtUl CjM5bqImorxNUehYeRYyEyfyC8fCRHoHB6QJ1Spo4nforqBAHdniSZuOQ qJUu55IxLLIYa+RVzU/LsKw7YvauVFVIiVPUNe7bKHeiYR62+Gd8BUDi6 A==; X-CSE-ConnectionGUID: 3dbHhVOiTuWncs8jA/vmGw== X-CSE-MsgGUID: bAcOyMFoTEmHE/Mbiwx+Pg== X-IronPort-AV: E=McAfee;i="6700,10204,11165"; a="39521760" X-IronPort-AV: E=Sophos;i="6.10,150,1719903600"; d="scan'208";a="39521760" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2024 21:06:31 -0700 X-CSE-ConnectionGUID: 6P8t+7/aSL6pUYpCsJduSw== X-CSE-MsgGUID: bEMLXJYgQBuCcQrGIVajrw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,150,1719903600"; d="scan'208";a="97070329" Received: from kerandaa-mobl.amr.corp.intel.com (HELO desk) ([10.125.112.221]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2024 21:06:26 -0700 Date: Thu, 15 Aug 2024 21:06:25 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi , "Rafael J. Wysocki" Subject: [PATCH v3 03/10] cpufreq: intel_pstate: Use topology_hw_cpu_type() Message-ID: <20240815-add-cpu-type-v3-3-234162352057@linux.intel.com> X-Mailer: b4 0.14.1 References: <20240815-add-cpu-type-v3-0-234162352057@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240815-add-cpu-type-v3-0-234162352057@linux.intel.com> Intel pstate driver relies on SMP calls to get the cpu-type of a given CPU. Replace the SMP calls with more efficient topology_hw_cpu_type(cpu) that returns the per-cpu cached value. Suggested-by: Dave Hansen Acked-by: Srinivas Pandruvada Acked-by: Rafael J. Wysocki Signed-off-by: Pawan Gupta --- drivers/cpufreq/intel_pstate.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index c0278d023cfc..b3df766ef029 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -1971,24 +1971,16 @@ static int knl_get_turbo_pstate(int cpu) return ret; } -static void hybrid_get_type(void *data) -{ - u8 *cpu_type = data; - - *cpu_type = get_this_hybrid_cpu_type(); -} - static int hwp_get_cpu_scaling(int cpu) { - u8 cpu_type = 0; + u8 cpu_type = topology_hw_cpu_type(&cpu_data(cpu)); - smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1); /* P-cores have a smaller perf level-to-freqency scaling factor. */ - if (cpu_type == 0x40) + if (cpu_type == TOPO_HW_CPU_TYPE_INTEL_CORE) return hybrid_scaling_factor; /* Use default core scaling for E-cores */ - if (cpu_type == 0x20) + if (cpu_type == TOPO_HW_CPU_TYPE_INTEL_ATOM) return core_get_scaling(); /* From patchwork Fri Aug 16 04:06:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 819968 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75C5D78C73; Fri, 16 Aug 2024 04:06:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723781202; cv=none; b=WS5FJooPhO8mwa50BZTJJKKGT5yLK1SIQtvqVSmaQZpKkOrG9TYikzjz7K74sSukbNuxnL4sp0E6X8fTd5Sk7NgMh0VPtszr1Jn+r6W82yj74mFV3PfdlhsqkTfqWHQQBjiKQ+m7fnSflyz1O+/YKsZzmxe1ZEWFqudxuNovUx0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723781202; c=relaxed/simple; bh=gXed3CM4au/pZEiN4zH4SDAKAVR50p0fuE+ekmc0NyA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=c3T7+staO9Mtn6WPDGh/M2RZtC5max3rn9yVsh3Z3a3I+HZw+34SfdHKyJxBPwcyHMijzOGqdbf1eg0T15bQLTGk+72sZqExrmgG+yk4Uw3l5/72rO3eXWkriurCZcbRenvwjXKCN72VQ2xVfOQ1KgQ2TTWERvwq7cvGHQ0npnA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hRxrmRpl; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hRxrmRpl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723781201; x=1755317201; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=gXed3CM4au/pZEiN4zH4SDAKAVR50p0fuE+ekmc0NyA=; b=hRxrmRpls2fG1ZCDNCUorP93qJ90lR0L+mW06B6tp4h25uQ7+cp5Z6Vj aGizFS16cE6G8mMFiAFOXOKeNGyZRSlPGgovVZ48xPpj5K1KBbe3LFxQr eesHzDtaWjb8UjjR32kUSVZXdUwXW2Sv+LNMObAQ83d0ZXpFnX5mdhiiB oaaprNBftRzAfwx1yK4Iste/VS2mlwLffP8jVgH3hr6QeS6j3xWL/0yBI MWza7it/fAQP1VGxF3bG1rUOq/ye88NSgGpVr9lcOAaskdlGk4JXs4M4e uJof7kqDKqmYpawsKINR81kuTQXA8DOtIrS/7yPiSxvOE+0IsAjpWGbLF g==; X-CSE-ConnectionGUID: Ipb+e69lT+eHBInNI41oDg== X-CSE-MsgGUID: HIuQ7mcCTpGFmOlBDAapzQ== X-IronPort-AV: E=McAfee;i="6700,10204,11165"; a="33220568" X-IronPort-AV: E=Sophos;i="6.10,150,1719903600"; d="scan'208";a="33220568" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2024 21:06:40 -0700 X-CSE-ConnectionGUID: 2WDiU3UITiO7sMc0Sl3Aow== X-CSE-MsgGUID: zaJO10m+T96AWjbuc9JH2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,150,1719903600"; d="scan'208";a="59718282" Received: from kerandaa-mobl.amr.corp.intel.com (HELO desk) ([10.125.112.221]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2024 21:06:39 -0700 Date: Thu, 15 Aug 2024 21:06:39 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v3 05/10] x86/cpu: Remove get_this_hybrid_cpu_type() Message-ID: <20240815-add-cpu-type-v3-5-234162352057@linux.intel.com> X-Mailer: b4 0.14.1 References: <20240815-add-cpu-type-v3-0-234162352057@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240815-add-cpu-type-v3-0-234162352057@linux.intel.com> Because calls to get_this_hybrid_cpu_type() were replaced by topology_hw_cpu_type(). Signed-off-by: Pawan Gupta --- arch/x86/include/asm/cpu.h | 6 ------ arch/x86/kernel/cpu/intel.c | 16 ---------------- 2 files changed, 22 deletions(-) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index f480c36a07b7..026151d9da50 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -31,7 +31,6 @@ extern void __init sld_setup(struct cpuinfo_x86 *c); extern bool handle_user_split_lock(struct pt_regs *regs, long error_code); extern bool handle_guest_split_lock(unsigned long ip); extern void handle_bus_lock(struct pt_regs *regs); -u8 get_this_hybrid_cpu_type(void); u32 intel_hw_native_model_id(struct cpuinfo_x86 *c); #else static inline void __init sld_setup(struct cpuinfo_x86 *c) {} @@ -47,11 +46,6 @@ static inline bool handle_guest_split_lock(unsigned long ip) static inline void handle_bus_lock(struct pt_regs *regs) {} -static inline u8 get_this_hybrid_cpu_type(void) -{ - return 0; -} - static u32 intel_hw_native_model_id(struct cpuinfo_x86 *c) { return 0; diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index e47a53280369..eba7a93f4bdf 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -1282,22 +1282,6 @@ void __init sld_setup(struct cpuinfo_x86 *c) sld_state_show(); } -#define X86_HYBRID_CPU_TYPE_ID_SHIFT 24 - -/** - * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU - * - * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in - * a hybrid processor. If the processor is not hybrid, returns 0. - */ -u8 get_this_hybrid_cpu_type(void) -{ - if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) - return 0; - - return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT; -} - u32 intel_hw_native_model_id(struct cpuinfo_x86 *c) { return c->topo.intel_core_native_model_id; From patchwork Fri Aug 16 04:06:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 819967 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AF71145B3B; Fri, 16 Aug 2024 04:06:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723781215; cv=none; b=Dq2ty9SE3geUiJhFFqa0zTVKKZ8At0h/rmVVnMMkWIbFdrYu/77iiIV/yeWu8mdGpNVE0sbfg3p35DCJ3fp70ykA6YNDmuI9ljyJfHrpfh8dzprFFU2mUkadPCD9hpIlS7zeOM+6lEvjhLQMcK3+5wzfZqZeKSCI+kZHtqq/zmI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723781215; c=relaxed/simple; bh=ouPlDYXSqC8qv2bsTOk97bxDMz92XjsnjihOFKxZ0kw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=hH2gjASgE9mDnQkInum4rXzvjWgsSBIYb805tu5LcXE1hHaFXBQk9fYdr6Kg8EOlK4ui4vcOwezkvfTItaD034kR4KG4QrpSbFceVNiVVeRtpSig3MxrNYGxidEmilxiTMZSvtw+EbXQofJelHNN/Izm3SD2JcJdrNj7/FpwQPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WeY64sdP; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WeY64sdP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723781213; x=1755317213; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=ouPlDYXSqC8qv2bsTOk97bxDMz92XjsnjihOFKxZ0kw=; b=WeY64sdPCLbEYY1Fn6zxFxZCw0k5mFkbdcuOywFPrCbo2lmGBmiIbZP7 +Dps22qjNLMKZGEKY+dUBnrgtHeNAqikNo7p5BDF2HhnbJYSMhXSFelF3 cja5ltSpghIvQIa0kbHx6u9P27KUgYe6h6KEsoq2RhbU4uLEzyH44969W 0rTel4UST5i7FwqhTlKsRyY9C4dsTO5eziHPfv36H9z6yO5/8oVMbozRY hWTD47U1TqKu5scXWDYoTaz32zWiTJroqv1BLxGQqH5X9dICmqMiFckQP MQiweVLGkXAimEhQV4mCE0zJtvLADDwDN31gkGjLh58xe93UFOzIfSexn A==; X-CSE-ConnectionGUID: 5+dR4JpjTbyn30PlIclFBg== X-CSE-MsgGUID: Khp1VjNtRSyaM5QvkBGkZg== X-IronPort-AV: E=McAfee;i="6700,10204,11165"; a="25826247" X-IronPort-AV: E=Sophos;i="6.10,150,1719903600"; d="scan'208";a="25826247" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2024 21:06:53 -0700 X-CSE-ConnectionGUID: J6+XkusgRBiCNlVp/D920Q== X-CSE-MsgGUID: GcevHyjMTHmp7UJZVpDPrw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,150,1719903600"; d="scan'208";a="59571867" Received: from kerandaa-mobl.amr.corp.intel.com (HELO desk) ([10.125.112.221]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2024 21:06:53 -0700 Date: Thu, 15 Aug 2024 21:06:51 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v3 07/10] x86/cpu: Add cpu_type to struct x86_cpu_id Message-ID: <20240815-add-cpu-type-v3-7-234162352057@linux.intel.com> X-Mailer: b4 0.14.1 References: <20240815-add-cpu-type-v3-0-234162352057@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240815-add-cpu-type-v3-0-234162352057@linux.intel.com> In addition to matching vendor/family/model/feature, for hybrid variants it is required to also match cpu-type also. For example some CPU vulnerabilities only affect a specific cpu-type. RFDS only affects Intel Atom parts. To be able to also match CPUs based on type add a new field cpu_type to struct x86_cpu_id which is used by the CPU-matching tables. Introduce X86_CPU_TYPE_ANY for the cases that don't care about the cpu-type. Signed-off-by: Pawan Gupta --- arch/x86/include/asm/cpu_device_id.h | 35 ++++++++++++++++++++++++----------- include/linux/mod_devicetable.h | 2 ++ 2 files changed, 26 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h index 4bdf4baefbc0..fa7bd0c454e7 100644 --- a/arch/x86/include/asm/cpu_device_id.h +++ b/arch/x86/include/asm/cpu_device_id.h @@ -75,13 +75,14 @@ * into another macro at the usage site for good reasons, then please * start this local macro with X86_MATCH to allow easy grepping. */ -#define X86_MATCH_CPU(_vendor, _family, _model, _steppings, _feature, _data) { \ +#define X86_MATCH_CPU(_vendor, _family, _model, _steppings, _feature, _cpu_type, _data) { \ .vendor = _vendor, \ .family = _family, \ .model = _model, \ .steppings = _steppings, \ .feature = _feature, \ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, \ + .cpu_type = _cpu_type, \ .driver_data = (unsigned long) _data \ } @@ -98,7 +99,7 @@ */ #define X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, feature, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ - feature, data) + feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FAM_FEATURE - Macro for matching vendor, family and CPU feature @@ -112,7 +113,7 @@ */ #define X86_MATCH_VENDOR_FAM_FEATURE(vendor, family, feature, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FEATURE - Macro for matching vendor and CPU feature @@ -125,7 +126,7 @@ */ #define X86_MATCH_VENDOR_FEATURE(vendor, feature, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, X86_FAMILY_ANY, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_FEATURE - Macro for matching a CPU feature @@ -136,7 +137,7 @@ */ #define X86_MATCH_FEATURE(feature, data) \ X86_MATCH_CPU(X86_VENDOR_ANY, X86_FAMILY_ANY, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FAM_MODEL - Match vendor, family and model @@ -150,7 +151,7 @@ */ #define X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ - X86_FEATURE_ANY, data) + X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FAM - Match vendor and family @@ -163,7 +164,7 @@ */ #define X86_MATCH_VENDOR_FAM(vendor, family, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ - X86_STEPPING_ANY, X86_FEATURE_ANY, data) + X86_STEPPING_ANY, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_INTEL_FAM6_MODEL - Match vendor INTEL, family 6 and model @@ -183,7 +184,7 @@ #define X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(model, steppings, data) \ X86_MATCH_CPU(X86_VENDOR_INTEL, 6, INTEL_FAM6_##model, \ - steppings, X86_FEATURE_ANY, data) + steppings, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VFM - Match encoded vendor/family/model @@ -194,7 +195,7 @@ */ #define X86_MATCH_VFM(vfm, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - X86_STEPPING_ANY, X86_FEATURE_ANY, data) + X86_STEPPING_ANY, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VFM_STEPPINGS - Match encoded vendor/family/model/stepping @@ -206,7 +207,7 @@ */ #define X86_MATCH_VFM_STEPPINGS(vfm, steppings, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - steppings, X86_FEATURE_ANY, data) + steppings, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VFM_FEATURE - Match encoded vendor/family/model/feature @@ -218,7 +219,19 @@ */ #define X86_MATCH_VFM_FEATURE(vfm, feature, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) + +/** + * X86_MATCH_VFM_CPU_TYPE - Match encoded vendor/family/model/cpu-type + * @vfm: Encoded 8-bits each for vendor, family, model + * @cpu_type: CPU type e.g. P-core, E-core on Intel + * @data: Driver specific data or NULL. The internal storage + * format is unsigned long. The supplied value, pointer + * etc. is cast to unsigned long internally. + */ +#define X86_MATCH_VFM_CPU_TYPE(vfm, cpu_type, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + X86_STEPPING_ANY, X86_FEATURE_ANY, cpu_type, data) /* * Match specific microcode revisions. diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index 4338b1b4ac44..b8a2e88f966f 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -692,6 +692,7 @@ struct x86_cpu_id { __u16 feature; /* bit index */ /* Solely for kernel-internal use: DO NOT EXPORT to userspace! */ __u16 flags; + __u8 cpu_type; kernel_ulong_t driver_data; }; @@ -701,6 +702,7 @@ struct x86_cpu_id { #define X86_MODEL_ANY 0 #define X86_STEPPING_ANY 0 #define X86_FEATURE_ANY 0 /* Same as FPU, you can't test for that */ +#define X86_CPU_TYPE_ANY 0 /* * Generic table type for matching CPU features. From patchwork Fri Aug 16 04:07:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 819966 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D2C814F12F; Fri, 16 Aug 2024 04:07:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723781231; cv=none; b=a2CjU/D/c3p1U801qMJCsHMGT6k0ts/CaAR1W/OzXPqw5KwD0bI/BJIEf82QQHAb3ExgYWuOK21ZHimbD3ko8TKIfAC1hzVrYouR2yUy+/MKu2QBYtMWdhUmoRbcTINIT2d+56Bx8hAo8zVpcZrqYZGMiXTSIj/hkDSs7+BMD+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723781231; c=relaxed/simple; bh=5S2A3uPwKrWieZIT+1sjtnHd8vxNUzhPVdB+Ij7jH78=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ui7ul8uZ+ySqmiU/cvNbEf0asuavlxXz9jLrAI2b2G4Ezk2Hk8RasXb5cupwiPXGKJWVLvCtaV9l09oxBwwuVok1iEXIrdgpmsVeOliBBBnrFg6wLUIbUrKpA/8Sa5ucI6PJvOc5l0FAGMqpXZ1LEDGuBLIXbVtNOPMh7PSACtk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=I2ex/iQg; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="I2ex/iQg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723781230; x=1755317230; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=5S2A3uPwKrWieZIT+1sjtnHd8vxNUzhPVdB+Ij7jH78=; b=I2ex/iQghd8LPS/EFm1O20hhBkAwrIvmvgLjy7mzfqlLE9bB+l8Wu3Ct Z9kprtxBlmurrqS2KFVYNmpatp4ZC2DC7cvjhhF9KDS2fkitk2UehFGew jAyng+7FQsXcN2EAFrgmB5mhAyCqd//plFIQtMfB0NLMk43bBMpP0hnYL bTwRhuKchpffF+RMrHDjvPUsGHH0+vf84GqwATdEyt/L4vuy5HHPuxmnf Te6nrKKr96rVvd/r35lqyQM/5KuCG+THcTkiRLvOQRzuD8RGrHqe8S102 T7w2vrCmY69QQv/RQu2+N/u+su+EAkgrF64yTD6prytiIDzrhR4FfiS0P A==; X-CSE-ConnectionGUID: UPfattgGRD2c3BDeOt4EdA== X-CSE-MsgGUID: gJ8+q/jpTUufCIPti6oaBA== X-IronPort-AV: E=McAfee;i="6700,10204,11165"; a="21617838" X-IronPort-AV: E=Sophos;i="6.10,150,1719903600"; d="scan'208";a="21617838" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2024 21:07:07 -0700 X-CSE-ConnectionGUID: xTmaydNcRpS6KTiA01cs6A== X-CSE-MsgGUID: iygSvXvgTEe+IpUGY1jE4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,150,1719903600"; d="scan'208";a="82758956" Received: from kerandaa-mobl.amr.corp.intel.com (HELO desk) ([10.125.112.221]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2024 21:07:05 -0700 Date: Thu, 15 Aug 2024 21:07:04 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v3 09/10] x86/bugs: Declutter vulnerable CPU list Message-ID: <20240815-add-cpu-type-v3-9-234162352057@linux.intel.com> X-Mailer: b4 0.14.1 References: <20240815-add-cpu-type-v3-0-234162352057@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240815-add-cpu-type-v3-0-234162352057@linux.intel.com> The affected processor table has a lot of repetition and redundant information that can be omitted. For example: VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS), can easily be simplified to: VULNBL_INTEL(IVYBRIDGE, SRBDS), Apply this to all the entries in the affected processor table. No functional change. Disassembly of cpu_vuln_blacklist: objdump -j .init.data --disassemble=cpu_vuln_blacklist vmlinux doesn't show any difference before and after the change. Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/common.c | 143 ++++++++++++++++++++++--------------------- 1 file changed, 73 insertions(+), 70 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index d4e539d4e158..68115240eea9 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1128,7 +1128,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) #define VULNWL_INTEL(vfm, whitelist) \ - X86_MATCH_VFM(vfm, whitelist) + X86_MATCH_VFM(INTEL_##vfm, whitelist) #define VULNWL_AMD(family, whitelist) \ VULNWL(AMD, family, X86_MODEL_ANY, whitelist) @@ -1145,32 +1145,32 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), /* Intel Family 6 */ - VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO), - VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO), - VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO), - VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO), + VULNWL_INTEL(TIGERLAKE, NO_MMIO), + VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), + VULNWL_INTEL(ALDERLAKE, NO_MMIO), + VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), - VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB), + VULNWL_INTEL(CORE_YONAH, NO_SSB), - VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), - VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), - VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), + VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), + VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), /* * Technically, swapgs isn't serializing on AMD (despite it previously @@ -1180,9 +1180,9 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { * good enough for our purposes. */ - VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB), - VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB), - VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), /* AMD Family 0xf - 0x12 */ VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), @@ -1203,8 +1203,11 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { #define VULNBL(vendor, family, model, blacklist) \ X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) -#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \ - X86_MATCH_VFM_STEPPINGS(vfm, steppings, issues) +#define VULNBL_INTEL(vfm, issues) \ + X86_MATCH_VFM(INTEL_##vfm, issues) + +#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \ + X86_MATCH_VFM_STEPPINGS(INTEL_##vfm, steppings, issues) #define VULNBL_AMD(family, blacklist) \ VULNBL(AMD, family, X86_MODEL_ANY, blacklist) @@ -1229,49 +1232,49 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { #define RFDS BIT(7) static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { - VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_L, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_G, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_G, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE_L, X86_STEPPING_ANY, GDS), - VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE, X86_STEPPING_ANY, GDS), - VULNBL_INTEL_STEPPINGS(INTEL_LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE_L, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_P, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_S, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_D, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY, RFDS), - - VULNBL_AMD(0x15, RETBLEED), - VULNBL_AMD(0x16, RETBLEED), - VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO), - VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO), - VULNBL_AMD(0x19, SRSO), + VULNBL_INTEL( IVYBRIDGE, SRBDS), + VULNBL_INTEL( HASWELL, SRBDS), + VULNBL_INTEL( HASWELL_L, SRBDS), + VULNBL_INTEL( HASWELL_G, SRBDS), + VULNBL_INTEL( HASWELL_X, MMIO), + VULNBL_INTEL( BROADWELL_D, MMIO), + VULNBL_INTEL( BROADWELL_G, SRBDS), + VULNBL_INTEL( BROADWELL_X, MMIO), + VULNBL_INTEL( BROADWELL, SRBDS), + VULNBL_INTEL( SKYLAKE_X, MMIO | RETBLEED | GDS), + VULNBL_INTEL( SKYLAKE_L, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( SKYLAKE, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( KABYLAKE_L, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( KABYLAKE, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( CANNONLAKE_L, RETBLEED), + VULNBL_INTEL( ICELAKE_L, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL( ICELAKE_D, MMIO | GDS), + VULNBL_INTEL( ICELAKE_X, MMIO | GDS), + VULNBL_INTEL( COMETLAKE, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS( COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), + VULNBL_INTEL( COMETLAKE_L, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL( TIGERLAKE_L, GDS), + VULNBL_INTEL( TIGERLAKE, GDS), + VULNBL_INTEL( LAKEFIELD, MMIO | MMIO_SBDS | RETBLEED), + VULNBL_INTEL( ROCKETLAKE, MMIO | RETBLEED | GDS), + VULNBL_INTEL( ALDERLAKE, RFDS), + VULNBL_INTEL( ALDERLAKE_L, RFDS), + VULNBL_INTEL( RAPTORLAKE, RFDS), + VULNBL_INTEL( RAPTORLAKE_P, RFDS), + VULNBL_INTEL( RAPTORLAKE_S, RFDS), + VULNBL_INTEL( ATOM_GRACEMONT, RFDS), + VULNBL_INTEL( ATOM_TREMONT, MMIO | MMIO_SBDS | RFDS), + VULNBL_INTEL( ATOM_TREMONT_D, MMIO | RFDS), + VULNBL_INTEL( ATOM_TREMONT_L, MMIO | MMIO_SBDS | RFDS), + VULNBL_INTEL( ATOM_GOLDMONT, RFDS), + VULNBL_INTEL( ATOM_GOLDMONT_D, RFDS), + VULNBL_INTEL( ATOM_GOLDMONT_PLUS, RFDS), + + VULNBL_AMD( 0x15, RETBLEED), + VULNBL_AMD( 0x16, RETBLEED), + VULNBL_AMD( 0x17, RETBLEED | SMT_RSB | SRSO), + VULNBL_HYGON( 0x18, RETBLEED | SMT_RSB | SRSO), + VULNBL_AMD( 0x19, SRSO), {} };