From patchwork Mon Aug 19 12:59:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Gonzalez X-Patchwork-Id: 820363 Received: from ns.iliad.fr (ns.iliad.fr [212.27.33.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9C541487FE; Mon, 19 Aug 2024 12:59:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.27.33.1 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724072388; cv=none; b=ORvKgNFFoewI8hehIK4pcveXGAJnPAl4rvxkBIwVNU1ZXS6XnfSJi78MidfUlyZyT8xfyG15/SblEl1LOW+uYazvBeN8EcnoqHczMDGSvZeCv7gv9rNUh8/4R9n86+UDffsKYNURfEqYi3t4R8+f8qyJPfFrv90HYoBu/C/LYZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724072388; c=relaxed/simple; bh=mVTUdHZIMPJ1+Lpr64UfYpEMVVQCY4Gv9UsTuKmzLRE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UVLSM0EoBGQbivkenHQuH5nE74UVW08vkmr2UD1b6bReGteLjqAhg+LkkidpjxuOxO+/IGCQJgsuWyCoI6pVMciUqtYLnxChXlcs0BcDiIfF9wlMlMDINJa50dCD0Qjanwp0DQVyeG613Lk6GB5fsPZwb7uQQm8dQsCXQLTttXs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=freebox.fr; spf=pass smtp.mailfrom=srs.iliad.fr; arc=none smtp.client-ip=212.27.33.1 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=freebox.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=srs.iliad.fr Received: from ns.iliad.fr (localhost [127.0.0.1]) by ns.iliad.fr (Postfix) with ESMTP id 936A820990; Mon, 19 Aug 2024 14:59:37 +0200 (CEST) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr [213.36.7.13]) by ns.iliad.fr (Postfix) with ESMTP id 83A9C20987; Mon, 19 Aug 2024 14:59:37 +0200 (CEST) From: Marc Gonzalez Date: Mon, 19 Aug 2024 14:59:35 +0200 Subject: [PATCH 1/2] iommu/arm-smmu-qcom: hide last LPASS SMMU context bank from linux Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240819-smmu-v1-1-bce6e4738825@freebox.fr> References: <20240819-smmu-v1-0-bce6e4738825@freebox.fr> In-Reply-To: <20240819-smmu-v1-0-bce6e4738825@freebox.fr> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , Konrad Dybcio , Arnaud Vrac , Pierre-Hugues Husson , Marijn Suijten , Caleb Connolly , Marc Gonzalez X-Mailer: b4 0.13.0 On qcom msm8998, writing to the last context bank of lpass_q6_smmu (base address 0x05100000) produces a system freeze & reboot. The hardware/hypervisor reports 13 context banks for the LPASS SMMU on msm8998, but only the first 12 are accessible... Override the number of context banks [ 2.546101] arm-smmu 5100000.iommu: probing hardware configuration... [ 2.552439] arm-smmu 5100000.iommu: SMMUv2 with: [ 2.558945] arm-smmu 5100000.iommu: stage 1 translation [ 2.563627] arm-smmu 5100000.iommu: address translation ops [ 2.568923] arm-smmu 5100000.iommu: non-coherent table walk [ 2.574566] arm-smmu 5100000.iommu: (IDR0.CTTW overridden by FW configuration) [ 2.580220] arm-smmu 5100000.iommu: stream matching with 12 register groups [ 2.587263] arm-smmu 5100000.iommu: 13 context banks (0 stage-2 only) [ 2.614447] arm-smmu 5100000.iommu: Supported page sizes: 0x63315000 [ 2.621358] arm-smmu 5100000.iommu: Stage-1: 36-bit VA -> 36-bit IPA [ 2.627772] arm-smmu 5100000.iommu: preserved 0 boot mappings Specifically, the crashes occur here: qsmmu->bypass_cbndx = smmu->num_context_banks - 1; arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); and here: arm_smmu_write_context_bank(smmu, i); arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); It is likely that FW reserves the last context bank for its own use, thus a simple work-around is: DON'T USE IT in Linux. If we decrease the number of context banks, last one will be "hidden". Signed-off-by: Marc Gonzalez --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 7e65189ca7b8c..d08c18edf5732 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -282,6 +282,11 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) u32 smr; int i; + if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-lpass-smmu")) { + dev_warn(smmu->dev, "hide last ctx bank from linux"); + --smmu->num_context_banks; + } + /* * Some platforms support more than the Arm SMMU architected maximum of * 128 stream matching groups. For unknown reasons, the additional From patchwork Mon Aug 19 12:59:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Gonzalez X-Patchwork-Id: 820692 Received: from ns.iliad.fr (ns.iliad.fr [212.27.33.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBA0716BE0A; Mon, 19 Aug 2024 12:59:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.27.33.1 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724072388; cv=none; b=W+Q2+5CFbR5REsBjD4qtZnxH7zS1zM+rE9eEiUA1kCCzIEt/9A49U+MtTr4g71pMiJzj+tKT7jDFnLGteinsbypQdg1DWhrwsaVVazm28l7AwHBUqNCuFfAGcPx41hfen/ojXljUyXD4xtt8W9EaE8NwB13MAmQ6wnC6EaaPEdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724072388; c=relaxed/simple; bh=Hq4ibJI9wfXkMmsJH/7UzMwLACf07c0x4cL/Qzyv7+8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LBRSOHfJEtDcOgJPBUjpGt1Ls6YCxNmFcDcFmwgfONzyYwOtVzLwdM4RPQxBhijdIB7ISpG/vWVSXxnV8+ifBNMDcTwsqvbC9tk65Gd5zVmMwFd/nXVG28RnoVDlRcIitlyiPtpB5Ybk/9w9TaVFcImUQyFUNQCz95SiCJPMj0A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=freebox.fr; spf=pass smtp.mailfrom=srs.iliad.fr; arc=none smtp.client-ip=212.27.33.1 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=freebox.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=srs.iliad.fr Received: from ns.iliad.fr (localhost [127.0.0.1]) by ns.iliad.fr (Postfix) with ESMTP id 9B2B220998; Mon, 19 Aug 2024 14:59:37 +0200 (CEST) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr [213.36.7.13]) by ns.iliad.fr (Postfix) with ESMTP id 88DF420988; Mon, 19 Aug 2024 14:59:37 +0200 (CEST) From: Marc Gonzalez Date: Mon, 19 Aug 2024 14:59:36 +0200 Subject: [PATCH 2/2] arm64: dts: qcom: msm8998: add qcom,msm8998-lpass-smmu compatible Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240819-smmu-v1-2-bce6e4738825@freebox.fr> References: <20240819-smmu-v1-0-bce6e4738825@freebox.fr> In-Reply-To: <20240819-smmu-v1-0-bce6e4738825@freebox.fr> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , Konrad Dybcio , Arnaud Vrac , Pierre-Hugues Husson , Marijn Suijten , Caleb Connolly , Marc Gonzalez X-Mailer: b4 0.13.0 The msm8998 LPASS SMMU requires special treatment, because FW reserves the last context bank for its own use. Signed-off-by: Marc Gonzalez --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 1537e42fa03ca..f169f2dd281c3 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1616,7 +1616,7 @@ gpucc: clock-controller@5065000 { }; lpass_q6_smmu: iommu@5100000 { - compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; + compatible = "qcom,msm8998-lpass-smmu", "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; reg = <0x05100000 0x40000>; clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; clock-names = "iface";