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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.04.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:04:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller Subject: [PATCH v3 01/20] accel/tcg: Assert noreturn from write-only page for atomics Date: Tue, 8 Oct 2024 17:04:34 -0700 Message-ID: <20241009000453.315652-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org There should be no "just in case"; the page is already in the tlb, and known to be not readable. Reviewed-by: Helge Deller Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 117b516739..fd6459b695 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1852,10 +1852,9 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, /* * Since we don't support reads and writes to different * addresses, and we do have the proper page loaded for - * write, this shouldn't ever return. But just in case, - * handle via stop-the-world. + * write, this shouldn't ever return. */ - goto stop_the_world; + g_assert_not_reached(); } /* Collect tlb flags for read. */ tlb_addr |= tlbe->addr_read; From patchwork Wed Oct 9 00:04:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833825 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp556204wrv; Tue, 8 Oct 2024 17:07:25 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUvEK5VOKEO9PSfpaMgGrpypvEQQknZE2Rxlv7zo2P6aZ8C86udsNeNXIYP8d3ZZXZTTqaftA==@linaro.org X-Google-Smtp-Source: AGHT+IEsbZ1IwuMqVRnw9ljVk1/MVnAjB1fxE4TR371UoLwHez7gEONcaCy8HW6O6wqPsclsjXZb X-Received: by 2002:a05:622a:1886:b0:45f:762:2e31 with SMTP id d75a77b69052e-45fa5ef4d99mr12106781cf.20.1728432445095; Tue, 08 Oct 2024 17:07:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432445; cv=none; d=google.com; s=arc-20240605; b=GZO/H5iQP6ul4Ez8rEDz0DgQUmR0pq5KqHWTQVJQdJyiDEqy5dVy8uhJCdDYLHbLoB VpunCOAGOb8a1sKhCshdD2CX1Tfdzs+GqxZeG5jAHb5KVpAbGzA1RPk6XhbbgCa39LbR qKn48u3SE4H5Mhkc9W+Z/APoU+T7m9LMNuaVc/7w3wewW2eI/MsKRnF4LEqioytCPeC1 5PeGFtXdQCu0bGdZCzDdSyOmPwWLfUk0sv1sHZvw9bpafzXZkd0CBkA6X0pfKUxmSKzw sX/RTp3Q5JOpzATCAMIyTVeQPWXuZbRS8CYeFJC4dh8LlgdDdpFU8qGeCOCboKhnJLhe PF3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=O9DVukvxY0Nz2lbOkkF1UGxIJ0HiyrlwFe+DiEN47Z4=; fh=3RK8noKPsRgJpwHDkrKY6p9N6ePZuLOt1ZjdS1VodvU=; b=FP0EXPtUZcq7MlOqkBlHhDu0vefhaUC0hFZHuDsjNNaqSkYb0cQ5F9rnuWRwNva9Mm 4PUaiWXjHheJEX6IWMlPSuG0X09E+C7YeY1CyRK8c/Z/1KS85LQcRY7Za8fsKGfWB7Es tgkDl4bVIV+ENr0awnNEh592ByW6CwvloDbki+sECJqTq35Z1D7N8HkJkoHVfUb0QHMf EH2b5ehA6Lr5JvItw/grW8hUKT0MBloDgGpvexEDSf44bix1nbGj4hE71mqavuyQsdM/ MTIOIJKtSMXj2KYam1USlxnVS+b6KvsBXFzEuUf7i8CKthzDUUhRA2JKodfL3D2Xr2OM Uphw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HlZTf1Mw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:04:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 02/20] include/exec/memop: Move get_alignment_bits from tcg.h Date: Tue, 8 Oct 2024 17:04:35 -0700 Message-ID: <20241009000453.315652-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is specific to MemOp, not TCG in general. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/memop.h | 23 +++++++++++++++++++++++ include/tcg/tcg.h | 23 ----------------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index f881fe7af4..97720a8ee7 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -170,4 +170,27 @@ static inline bool memop_big_endian(MemOp op) return (op & MO_BSWAP) == MO_BE; } +/** + * get_alignment_bits + * @memop: MemOp value + * + * Extract the alignment size from the memop. + */ +static inline unsigned get_alignment_bits(MemOp memop) +{ + unsigned a = memop & MO_AMASK; + + if (a == MO_UNALN) { + /* No alignment required. */ + a = 0; + } else if (a == MO_ALIGN) { + /* A natural alignment requirement. */ + a = memop & MO_SIZE; + } else { + /* A specific alignment requirement. */ + a = a >> MO_ASHIFT; + } + return a; +} + #endif diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 21d5884741..824fb3560d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -281,29 +281,6 @@ static inline int tcg_type_size(TCGType t) return 4 << i; } -/** - * get_alignment_bits - * @memop: MemOp value - * - * Extract the alignment size from the memop. - */ -static inline unsigned get_alignment_bits(MemOp memop) -{ - unsigned a = memop & MO_AMASK; - - if (a == MO_UNALN) { - /* No alignment required. */ - a = 0; - } else if (a == MO_ALIGN) { - /* A natural alignment requirement. */ - a = memop & MO_SIZE; - } else { - /* A specific alignment requirement. */ - a = a >> MO_ASHIFT; - } - return a; -} - typedef tcg_target_ulong TCGArg; /* Define type and accessor macros for TCG variables. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:04:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 03/20] include/exec/memop: Rename get_alignment_bits Date: Tue, 8 Oct 2024 17:04:36 -0700 Message-ID: <20241009000453.315652-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rename to use "memop_" prefix, like other functions that operate on MemOp. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/memop.h | 4 ++-- accel/tcg/cputlb.c | 4 ++-- accel/tcg/user-exec.c | 4 ++-- target/arm/tcg/translate-a64.c | 4 ++-- target/xtensa/translate.c | 2 +- tcg/tcg-op-ldst.c | 6 +++--- tcg/tcg.c | 2 +- tcg/arm/tcg-target.c.inc | 4 ++-- tcg/sparc64/tcg-target.c.inc | 2 +- 9 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 97720a8ee7..f53bf618c6 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -171,12 +171,12 @@ static inline bool memop_big_endian(MemOp op) } /** - * get_alignment_bits + * memop_alignment_bits: * @memop: MemOp value * * Extract the alignment size from the memop. */ -static inline unsigned get_alignment_bits(MemOp memop) +static inline unsigned memop_alignment_bits(MemOp memop) { unsigned a = memop & MO_AMASK; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index fd6459b695..a975fe5f89 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1709,7 +1709,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, tcg_debug_assert(l->mmu_idx < NB_MMU_MODES); /* Handle CPU specific unaligned behaviour */ - a_bits = get_alignment_bits(l->memop); + a_bits = memop_alignment_bits(l->memop); if (addr & ((1 << a_bits) - 1)) { cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); } @@ -1797,7 +1797,7 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, { uintptr_t mmu_idx = get_mmuidx(oi); MemOp mop = get_memop(oi); - int a_bits = get_alignment_bits(mop); + int a_bits = memop_alignment_bits(mop); uintptr_t index; CPUTLBEntry *tlbe; vaddr tlb_addr; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7ddc47b0ba..08a6df9987 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -959,7 +959,7 @@ void page_reset_target_data(target_ulong start, target_ulong last) { } static void *cpu_mmu_lookup(CPUState *cpu, vaddr addr, MemOp mop, uintptr_t ra, MMUAccessType type) { - int a_bits = get_alignment_bits(mop); + int a_bits = memop_alignment_bits(mop); void *ret; /* Enforce guest required alignment. */ @@ -1241,7 +1241,7 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, int size, uintptr_t retaddr) { MemOp mop = get_memop(oi); - int a_bits = get_alignment_bits(mop); + int a_bits = memop_alignment_bits(mop); void *ret; /* Enforce guest required alignment. */ diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 071b6349fc..ec0b1ee252 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -294,7 +294,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(memop)); + desc = FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(memop)); desc = FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1); ret = tcg_temp_new_i64(); @@ -326,7 +326,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(single_mop)); + desc = FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(single_mop)); desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); ret = tcg_temp_new_i64(); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 75b7bfda4c..f4da4a40f9 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -521,7 +521,7 @@ static MemOp gen_load_store_alignment(DisasContext *dc, MemOp mop, mop |= MO_ALIGN; } if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { - tcg_gen_andi_i32(addr, addr, ~0 << get_alignment_bits(mop)); + tcg_gen_andi_i32(addr, addr, ~0 << memop_alignment_bits(mop)); } return mop; } diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 23dc807f11..a318011229 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -45,7 +45,7 @@ static void check_max_alignment(unsigned a_bits) static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) { - unsigned a_bits = get_alignment_bits(op); + unsigned a_bits = memop_alignment_bits(op); check_max_alignment(a_bits); @@ -559,7 +559,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr, TCGv_i64 ext_addr = NULL; TCGOpcode opc; - check_max_alignment(get_alignment_bits(memop)); + check_max_alignment(memop_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); /* In serial mode, reduce atomicity. */ @@ -676,7 +676,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr, TCGv_i64 ext_addr = NULL; TCGOpcode opc; - check_max_alignment(get_alignment_bits(memop)); + check_max_alignment(memop_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); /* In serial mode, reduce atomicity. */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 34e3056380..5decd83cf4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -5506,7 +5506,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, MemOp host_atom, bool allow_two_ops) { - MemOp align = get_alignment_bits(opc); + MemOp align = memop_alignment_bits(opc); MemOp size = opc & MO_SIZE; MemOp half = size ? size - 1 : 0; MemOp atom = opc & MO_ATOM_MASK; diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 3de5f50b62..56072d89a2 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1587,7 +1587,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, tcg_debug_assert((datalo & 1) == 0); tcg_debug_assert(datahi == datalo + 1); /* LDRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >= MO_64) { + if (memop_alignment_bits(opc) >= MO_64) { if (h.index < 0) { tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); break; @@ -1691,7 +1691,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, tcg_debug_assert((datalo & 1) == 0); tcg_debug_assert(datahi == datalo + 1); /* STRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >= MO_64) { + if (memop_alignment_bits(opc) >= MO_64) { if (h.index < 0) { tcg_out_strd_8(s, h.cond, datalo, h.base, 0); } else { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 176c98740b..32f9ec24b5 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1133,7 +1133,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, * Otherwise, test for at least natural alignment and defer * everything else to the helper functions. */ - if (s_bits != get_alignment_bits(opc)) { + if (s_bits != memop_alignment_bits(opc)) { tcg_debug_assert(check_fit_tl(a_mask, 13)); tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); From patchwork Wed Oct 9 00:04:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833796 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp555727wrv; Tue, 8 Oct 2024 17:06:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXGaxdHBVsvlFkwnnH+FK7AwP68FHChR5Bc49wjvkOg6E0sM3M7IKlQ4+bSxVS6d8o0LWOvZA==@linaro.org X-Google-Smtp-Source: AGHT+IEbHMc1ktdbYFenBKZAIdNt4fngQBbBbbmO8lHZpUhGB5FsxllAtELq1sw8wFQvcquIHoe9 X-Received: by 2002:a05:6102:94f:b0:49c:5f:e816 with SMTP id ada2fe7eead31-4a448e1d331mr739128137.18.1728432365930; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:04:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller Subject: [PATCH v3 04/20] include/exec/memop: Introduce memop_atomicity_bits Date: Tue, 8 Oct 2024 17:04:37 -0700 Message-ID: <20241009000453.315652-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Split out of mmu_lookup. Reviewed-by: Helge Deller Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/exec/memop.h | 24 ++++++++++++++++++++++++ accel/tcg/cputlb.c | 16 ++-------------- 2 files changed, 26 insertions(+), 14 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index f53bf618c6..b699bf7688 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -193,4 +193,28 @@ static inline unsigned memop_alignment_bits(MemOp memop) return a; } +/* + * memop_atomicity_bits: + * @memop: MemOp value + * + * Extract the atomicity size from the memop. + */ +static inline unsigned memop_atomicity_bits(MemOp memop) +{ + unsigned size = memop & MO_SIZE; + + switch (memop & MO_ATOM_MASK) { + case MO_ATOM_NONE: + size = MO_8; + break; + case MO_ATOM_IFALIGN_PAIR: + case MO_ATOM_WITHIN16_PAIR: + size = size ? size - 1 : 0; + break; + default: + break; + } + return size; +} + #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a975fe5f89..35cda1e2b0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1767,20 +1767,8 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, * Device memory type require alignment. */ if (unlikely(flags & TLB_CHECK_ALIGNED)) { - MemOp size = l->memop & MO_SIZE; - - switch (l->memop & MO_ATOM_MASK) { - case MO_ATOM_NONE: - size = MO_8; - break; - case MO_ATOM_IFALIGN_PAIR: - case MO_ATOM_WITHIN16_PAIR: - size = size ? size - 1 : 0; - break; - default: - break; - } - if (addr & ((1 << size) - 1)) { + a_bits = memop_atomicity_bits(l->memop); + if (addr & ((1 << a_bits) - 1)) { cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); } } From patchwork Wed Oct 9 00:04:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833824 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp556202wrv; Tue, 8 Oct 2024 17:07:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUXb0885MCS1H/GX90RAJR+iNU0lZGviRLpS3XB1iTkRUlh2NG6+QoShBlfXc7nZJXHA2IyRw==@linaro.org X-Google-Smtp-Source: AGHT+IFw8zntlNhunuu3DBdJ5wMTwZwDbr+ix+Becc2Wcny6dTPOotcRC2gRu8bWmUVpCBrVytQk X-Received: by 2002:ac8:5843:0:b0:458:4ce6:5874 with SMTP id d75a77b69052e-45fa5ef954cmr9925071cf.21.1728432444466; Tue, 08 Oct 2024 17:07:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432444; cv=none; d=google.com; s=arc-20240605; b=OAua4OuATunIDZeYT5hFOmLCobXe8Acu+KodCDQJQtGnPABF2J4QeqQqS9Q+vy3Zhz BFdyS8zIgkqllMZNOhF2crIeBfhJ7b4fYfrYpCYPzTURkFf2jM8O5zY/7y+vyMpYv0t1 qK+H5vDLhp/9KeA4S1a9RWO8ppxvTaSV12fN3pictRpXIWGsB2TouCmfC3YiFlkBvxFj vhK8Ew8qYLbR0zpn+GFkPO5N22GEkVpd8PGPYe4FvLMNuLFmlBCfQO1s3H8zCjrgX7IQ 3onztF/83KYR7VAdR6SezRUaLbIIuDHS/FxOkQkPS37Y/HmaiIK/5O0UIhaPzX3dXYf8 BagA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KRlC3mms3e9Sb+Qb/UGEoW53IughvKHiILVrUessrrs=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=iXKg18HjpVtrKr5g6wAmOk+7aOtbQF7cc4pDYDhOFg1u2qZklDzlmH4j6heP1dW/3s v0bIEcZsdNspv9ZPlkm7dzPL5FBd00cxAX1n+a12ZC4GW3H5wjKPFXFGj65fMgSwpPOB gkfFk33uXoOWAgGLcLSMPlmpV5DTRNMH+FjQrHVJDwnieZgQuB+f84fUwBd1lUM4I80H Y8MDE0EPw2qPj/qVp4+kz8EFaj0WNsnZpInl6gIZ1SS00B+2YGYZSWfg/LAYAmMSs8Da P7qWYOith8tjcB0FM1ecVub7aGqedyyJ2X/5wOBCGqC+iE9P8kLwuM/3/4yJ8Hfs+ktc XUSw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cq0JQAO1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:04:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH v3 05/20] accel/tcg: Add TCGCPUOps.tlb_fill_align Date: Tue, 8 Oct 2024 17:04:38 -0700 Message-ID: <20241009000453.315652-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a new callback to handle softmmu paging. Return the page details directly, instead of passing them indirectly to tlb_set_page. Handle alignment simultaneously with paging so that faults are handled with target-specific priority. Route all calls the two hooks through a tlb_fill_align function local to cputlb.c. As yet no targets implement the new hook. As yet cputlb.c does not use the new alignment check. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Reviewed-by: Peter Maydell --- include/hw/core/cpu.h | 4 +-- include/hw/core/tcg-cpu-ops.h | 26 +++++++++++++++ include/qemu/typedefs.h | 1 + accel/tcg/cputlb.c | 61 ++++++++++++++++++++++------------- 4 files changed, 67 insertions(+), 25 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 04e9ad4996..d21a24c82f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -205,7 +205,7 @@ struct CPUClass { * so the layout is not as critical as that of CPUTLBEntry. This is * also why we don't want to combine the two structs. */ -typedef struct CPUTLBEntryFull { +struct CPUTLBEntryFull { /* * @xlat_section contains: * - in the lower TARGET_PAGE_BITS, a physical section number @@ -261,7 +261,7 @@ typedef struct CPUTLBEntryFull { bool guarded; } arm; } extra; -} CPUTLBEntryFull; +}; /* * Data elements that are per MMU mode, minus the bits accessed by diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 34318cf0e6..c932690621 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -13,6 +13,7 @@ #include "exec/breakpoint.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" +#include "exec/memop.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" @@ -131,6 +132,31 @@ struct TCGCPUOps { * same function signature. */ bool (*cpu_exec_halt)(CPUState *cpu); + /** + * @tlb_fill_align: Handle a softmmu tlb miss + * @cpu: cpu context + * @out: output page properties + * @addr: virtual address + * @access_type: read, write or execute + * @mmu_idx: mmu context + * @memop: memory operation for the access + * @size: memory access size, or 0 for whole page + * @probe: test only, no fault + * @ra: host return address for exception unwind + * + * If the access is valid, fill in @out and return true. + * Otherwise if probe is true, return false. + * Otherwise raise and exception and do not return. + * + * The alignment check for the access is deferred to this hook, + * so that the target can determine the priority of any alignment + * fault with respect to other potential faults from paging. + * Zero may be passed for @memop to skip any alignment check + * for non-memory-access operations such as probing. + */ + bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra); /** * @tlb_fill: Handle a softmmu tlb miss * diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 9d222dc376..3d84efcac4 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -40,6 +40,7 @@ typedef struct ConfidentialGuestSupport ConfidentialGuestSupport; typedef struct CPUArchState CPUArchState; typedef struct CPUPluginState CPUPluginState; typedef struct CPUState CPUState; +typedef struct CPUTLBEntryFull CPUTLBEntryFull; typedef struct DeviceState DeviceState; typedef struct DirtyBitmapSnapshot DirtyBitmapSnapshot; typedef struct DisasContextBase DisasContextBase; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 35cda1e2b0..d72f454e9e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1221,22 +1221,35 @@ void tlb_set_page(CPUState *cpu, vaddr addr, } /* - * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the - * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must - * be discarded and looked up again (e.g. via tlb_entry()). + * Note: tlb_fill_align() can trigger a resize of the TLB. + * This means that all of the caller's prior references to the TLB table + * (e.g. CPUTLBEntry pointers) must be discarded and looked up again + * (e.g. via tlb_entry()). */ -static void tlb_fill(CPUState *cpu, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +static bool tlb_fill_align(CPUState *cpu, vaddr addr, MMUAccessType type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t ra) { - bool ok; + const TCGCPUOps *ops = cpu->cc->tcg_ops; + CPUTLBEntryFull full; - /* - * This is not a probe, so only valid return is success; failure - * should result in exception + longjmp to the cpu loop. - */ - ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, - access_type, mmu_idx, false, retaddr); - assert(ok); + if (ops->tlb_fill_align) { + if (ops->tlb_fill_align(cpu, &full, addr, type, mmu_idx, + memop, size, probe, ra)) { + tlb_set_page_full(cpu, mmu_idx, addr, &full); + return true; + } + } else { + /* Legacy behaviour is alignment before paging. */ + if (addr & ((1u << memop_alignment_bits(memop)) - 1)) { + ops->do_unaligned_access(cpu, addr, type, mmu_idx, ra); + } + if (ops->tlb_fill(cpu, addr, size, type, mmu_idx, probe, ra)) { + return true; + } + } + assert(probe); + return false; } static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, @@ -1351,22 +1364,22 @@ static int probe_access_internal(CPUState *cpu, vaddr addr, if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, page_addr)) { - if (!cpu->cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type, - mmu_idx, nonfault, retaddr)) { + if (!tlb_fill_align(cpu, addr, access_type, mmu_idx, + 0, fault_size, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost = NULL; *pfull = NULL; return TLB_INVALID_MASK; } - /* TLB resize via tlb_fill may have moved the entry. */ + /* TLB resize via tlb_fill_align may have moved the entry. */ index = tlb_index(cpu, mmu_idx, addr); entry = tlb_entry(cpu, mmu_idx, addr); /* * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, - * to force the next access through tlb_fill. We've just - * called tlb_fill, so we know that this entry *is* valid. + * to force the next access through tlb_fill_align. We've just + * called tlb_fill_align, so we know that this entry *is* valid. */ flags &= ~TLB_INVALID_MASK; } @@ -1613,7 +1626,7 @@ typedef struct MMULookupLocals { * * Resolve the translation for the one page at @data.addr, filling in * the rest of @data with the results. If the translation fails, - * tlb_fill will longjmp out. Return true if the softmmu tlb for + * tlb_fill_align will longjmp out. Return true if the softmmu tlb for * @mmu_idx may have resized. */ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, @@ -1631,7 +1644,8 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, addr & TARGET_PAGE_MASK)) { - tlb_fill(cpu, addr, data->size, access_type, mmu_idx, ra); + tlb_fill_align(cpu, addr, access_type, mmu_idx, + 0, data->size, false, ra); maybe_resized = true; index = tlb_index(cpu, mmu_idx, addr); entry = tlb_entry(cpu, mmu_idx, addr); @@ -1821,8 +1835,8 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, MMU_DATA_STORE, addr & TARGET_PAGE_MASK)) { - tlb_fill(cpu, addr, size, - MMU_DATA_STORE, mmu_idx, retaddr); + tlb_fill_align(cpu, addr, MMU_DATA_STORE, mmu_idx, + 0, size, false, retaddr); index = tlb_index(cpu, mmu_idx, addr); tlbe = tlb_entry(cpu, mmu_idx, addr); } @@ -1836,7 +1850,8 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, * but addr_read will only be -1 if PAGE_READ was unset. */ if (unlikely(tlbe->addr_read == -1)) { - tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); + tlb_fill_align(cpu, addr, MMU_DATA_LOAD, mmu_idx, + 0, size, false, retaddr); /* * Since we don't support reads and writes to different * addresses, and we do have the proper page loaded for From patchwork Wed Oct 9 00:04:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833811 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp555735wrv; Tue, 8 Oct 2024 17:06:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVoPApk2qm+vpbMz+EIaHx5zCPohG/V7N0yjtu0Erp0wuUeW6OBjFhGmrC2h8PT8cZA7ZsGDQ==@linaro.org X-Google-Smtp-Source: AGHT+IEUVjV1rQOgHjVbpVRacuvixcj88pURcG0dMWj+FVkTAAbdSK2H7ckllKo2MTW5n0oRN/X2 X-Received: by 2002:a05:620a:40a:b0:7a7:fdef:27a with SMTP id af79cd13be357-7b0874d7cdemr78145585a.58.1728432366645; Tue, 08 Oct 2024 17:06:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432366; cv=none; d=google.com; s=arc-20240605; b=RwaCvMQUv/xxDAEbdxPOppA3/nDF44PeXWbi8vepDXUoqy/LHu9KuybuYQedaKNRZR pX5DaT1Vrl17nBtUqzPk6PiMzy5TS5b7q/fvGR65tD3UmeZOxGipiCESNsHypRZ3inxE g1GAsnsVA2G/kqb6+7gotm1zvWIjPQr0QD5o0CvZnz25CnZgWmR4xGAcY34upUtG66Pg skHsLyIaL2/TNW8zer3D7mH34aj8cYvUbH/t2YUs5lLtVAHpFadVok0IhifyJ7f1ddeG VThXOBHMELwXO/SnIFzvRPAF63q6NgGwbcdWFIwOrGr2a973H/FXXMykJi7ujMp08Akm 9Ziw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/dFojoXE4+jjskAlQVsQMp2S+E0WFZ4r9iQmpRIn1e0=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=Y/4ryKB1YKRBMc31N+Ca+WwUub2rF5cvcdD5uEG4v90TjHeNolb7Z+0DyWhQ0HXoRo swXeafnzBSGhsWx/euJnj7XKstOjKEgR9bn1V4ETsLW0l3xzt5Go4j1sK7vb5Zv70Utr SIDJCbGf4mVDSpmL37dGbttacEI9TGAKPEv/OncSkEohhLbZm8c94N6LODp5CkzxEZuE fhPJl7iDv/IkaD4rz9ZfjgxClX3KP8930bKqNxS/AKzQn01v8bsrfxN0V0GgINcNSVvB bJzXPG0NyMGDSL7fy40VxYi39U7tllgCfanGJOhjzkb5EC9Jd1PqRdGRKu1eK0VAh/IR /ZaQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iAL7m1sB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH v3 06/20] accel/tcg: Use the alignment test in tlb_fill_align Date: Tue, 8 Oct 2024 17:04:39 -0700 Message-ID: <20241009000453.315652-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we have a tlb miss, defer the alignment check to the new tlb_fill_align hook. Move the existing alignment check so that we only perform it with a tlb hit. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- accel/tcg/cputlb.c | 88 ++++++++++++++++++++++++---------------------- 1 file changed, 45 insertions(+), 43 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d72f454e9e..b76a4eac4e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1620,6 +1620,7 @@ typedef struct MMULookupLocals { * mmu_lookup1: translate one page * @cpu: generic cpu state * @data: lookup parameters + * @memop: memory operation for the access, or 0 * @mmu_idx: virtual address context * @access_type: load/store/code * @ra: return address into tcg generated code, or 0 @@ -1629,7 +1630,7 @@ typedef struct MMULookupLocals { * tlb_fill_align will longjmp out. Return true if the softmmu tlb for * @mmu_idx may have resized. */ -static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, +static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, MemOp memop, int mmu_idx, MMUAccessType access_type, uintptr_t ra) { vaddr addr = data->addr; @@ -1645,7 +1646,7 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, addr & TARGET_PAGE_MASK)) { tlb_fill_align(cpu, addr, access_type, mmu_idx, - 0, data->size, false, ra); + memop, data->size, false, ra); maybe_resized = true; index = tlb_index(cpu, mmu_idx, addr); entry = tlb_entry(cpu, mmu_idx, addr); @@ -1657,6 +1658,25 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, flags = tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); flags |= full->slow_flags[access_type]; + if (likely(!maybe_resized)) { + /* Alignment has not been checked by tlb_fill_align. */ + int a_bits = memop_alignment_bits(memop); + + /* + * This alignment check differs from the one above, in that this is + * based on the atomicity of the operation. The intended use case is + * the ARM memory type field of each PTE, where access to pages with + * Device memory type require alignment. + */ + if (unlikely(flags & TLB_CHECK_ALIGNED)) { + int at_bits = memop_atomicity_bits(memop); + a_bits = MAX(a_bits, at_bits); + } + if (unlikely(addr & ((1 << a_bits) - 1))) { + cpu_unaligned_access(cpu, addr, access_type, mmu_idx, ra); + } + } + data->full = full; data->flags = flags; /* Compute haddr speculatively; depending on flags it might be invalid. */ @@ -1713,7 +1733,6 @@ static void mmu_watch_or_dirty(CPUState *cpu, MMULookupPageData *data, static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type, MMULookupLocals *l) { - unsigned a_bits; bool crosspage; int flags; @@ -1722,12 +1741,6 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, tcg_debug_assert(l->mmu_idx < NB_MMU_MODES); - /* Handle CPU specific unaligned behaviour */ - a_bits = memop_alignment_bits(l->memop); - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); - } - l->page[0].addr = addr; l->page[0].size = memop_size(l->memop); l->page[1].addr = (addr + l->page[0].size - 1) & TARGET_PAGE_MASK; @@ -1735,7 +1748,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, crosspage = (addr ^ l->page[1].addr) & TARGET_PAGE_MASK; if (likely(!crosspage)) { - mmu_lookup1(cpu, &l->page[0], l->mmu_idx, type, ra); + mmu_lookup1(cpu, &l->page[0], l->memop, l->mmu_idx, type, ra); flags = l->page[0].flags; if (unlikely(flags & (TLB_WATCHPOINT | TLB_NOTDIRTY))) { @@ -1754,8 +1767,8 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, * Lookup both pages, recognizing exceptions from either. If the * second lookup potentially resized, refresh first CPUTLBEntryFull. */ - mmu_lookup1(cpu, &l->page[0], l->mmu_idx, type, ra); - if (mmu_lookup1(cpu, &l->page[1], l->mmu_idx, type, ra)) { + mmu_lookup1(cpu, &l->page[0], l->memop, l->mmu_idx, type, ra); + if (mmu_lookup1(cpu, &l->page[1], 0, l->mmu_idx, type, ra)) { uintptr_t index = tlb_index(cpu, l->mmu_idx, addr); l->page[0].full = &cpu->neg.tlb.d[l->mmu_idx].fulltlb[index]; } @@ -1774,19 +1787,6 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, tcg_debug_assert((flags & TLB_BSWAP) == 0); } - /* - * This alignment check differs from the one above, in that this is - * based on the atomicity of the operation. The intended use case is - * the ARM memory type field of each PTE, where access to pages with - * Device memory type require alignment. - */ - if (unlikely(flags & TLB_CHECK_ALIGNED)) { - a_bits = memop_atomicity_bits(l->memop); - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); - } - } - return crosspage; } @@ -1799,34 +1799,18 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, { uintptr_t mmu_idx = get_mmuidx(oi); MemOp mop = get_memop(oi); - int a_bits = memop_alignment_bits(mop); uintptr_t index; CPUTLBEntry *tlbe; vaddr tlb_addr; void *hostaddr; CPUTLBEntryFull *full; + bool did_tlb_fill = false; tcg_debug_assert(mmu_idx < NB_MMU_MODES); /* Adjust the given return address. */ retaddr -= GETPC_ADJ; - /* Enforce guest required alignment. */ - if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) { - /* ??? Maybe indicate atomic op to cpu_unaligned_access */ - cpu_unaligned_access(cpu, addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* Enforce qemu required alignment. */ - if (unlikely(addr & (size - 1))) { - /* We get here if guest alignment was not requested, - or was not enforced by cpu_unaligned_access above. - We might widen the access and emulate, but for now - mark an exception and exit the cpu loop. */ - goto stop_the_world; - } - index = tlb_index(cpu, mmu_idx, addr); tlbe = tlb_entry(cpu, mmu_idx, addr); @@ -1836,7 +1820,8 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, if (!victim_tlb_hit(cpu, mmu_idx, index, MMU_DATA_STORE, addr & TARGET_PAGE_MASK)) { tlb_fill_align(cpu, addr, MMU_DATA_STORE, mmu_idx, - 0, size, false, retaddr); + mop, size, false, retaddr); + did_tlb_fill = true; index = tlb_index(cpu, mmu_idx, addr); tlbe = tlb_entry(cpu, mmu_idx, addr); } @@ -1859,6 +1844,23 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, */ g_assert_not_reached(); } + + /* Enforce guest required alignment, if not handled by tlb_fill_align. */ + if (!did_tlb_fill && (addr & ((1 << memop_alignment_bits(mop)) - 1))) { + cpu_unaligned_access(cpu, addr, MMU_DATA_STORE, mmu_idx, retaddr); + } + + /* Enforce qemu required alignment. */ + if (unlikely(addr & (size - 1))) { + /* + * We get here if guest alignment was not requested, or was not + * enforced by cpu_unaligned_access or tlb_fill_align above. + * We might widen the access and emulate, but for now + * mark an exception and exit the cpu loop. + */ + goto stop_the_world; + } + /* Collect tlb flags for read. */ tlb_addr |= tlbe->addr_read; From patchwork Wed Oct 9 00:04:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833813 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp555829wrv; Tue, 8 Oct 2024 17:06:23 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU7Jm6hczL/9V55SuS/0BrLAyHs25bj+p9h0V+We2DcFAyaskG1VC8Xjjwq/PbdzumN0M/LCA==@linaro.org X-Google-Smtp-Source: AGHT+IHdLmfg2f1HGkXKiEM40nkp/3jEwZ+pxwOH3I5Cb/8/eBlQ4khYKuOUz7zmIbCjQgnRSovs X-Received: by 2002:a05:620a:3908:b0:7a9:bdd4:b4ea with SMTP id af79cd13be357-7b0795277d9mr111274485a.9.1728432383783; Tue, 08 Oct 2024 17:06:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432383; cv=none; d=google.com; s=arc-20240605; b=kL92ZXSxx3A6T8s/sgy/lPGV+peERbdP/7gxZMplV23JcbPgtayV5eHyByKTWb0M51 lMH7oWgw7k1VRFvLDUUIsDZKCi8pkzeUh89ER/ph1ES+y3YC8SSh92fYZvBnAXL5p5sN U8g2qbpLhpe2hCCl/y5acsq7GQCyT0fLM5CcDY1fabJxLt9zLkzAoa25MisRAsbIEZ1d ziWaDErOlqnbOR7X2n77fkbvcQwA1GBCxScE4pN4IZeI5Ps3orE3MyVuDKorTWtY3tEF SACp7TjiOt/Sgvvj1SpoJr3ntGASVBRBTVJkFdSMhbvQx3+ETSe3ZISpli3A2ilfHeHM uk/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZMaSkZRoz5YPXdGi4Fagk1yb2WqLYDqE0+TVeXDEoMY=; fh=3RK8noKPsRgJpwHDkrKY6p9N6ePZuLOt1ZjdS1VodvU=; b=lqnVR4y8/6UlghLvrJySX71LxLK+tOcHf4NpMsAAxL92yjX+stPeZo13TD7ur1SMQ8 GDGUXAC+JOWxRuWS+sBFQUI3KcoXJPgjNNCP0BGl0BHCN9ijuITDKX9/OeDYODdJPtHa 68k6Vj6glq9Ij3Ckf6J5Jsz9Ycn+0BDmKpmX83VnsqvxLI2InDXH/CLCC4nGBvAnAiOK YqANiyXD22Kmr6L6F0SCVvi9V/ggSBoaYdVs9NHSA9rFEtL/IR/yKwFLR38mEC8wh1BO /8nKeJ8BtXogBEVHWfoKfepZQ1uLzDNcJRI7+5zDrXGr2Hf3MAIxAY1C6CUruHZNJc3i qfQQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IzYQGvb6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 07/20] target/hppa: Add MemOp argument to hppa_get_physical_address Date: Tue, 8 Oct 2024 17:04:40 -0700 Message-ID: <20241009000453.315652-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Just add the argument, unused at this point. Zero is the safe do-nothing value for all callers. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 +- target/hppa/int_helper.c | 2 +- target/hppa/mem_helper.c | 9 +++++---- target/hppa/op_helper.c | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f4e051f176..526855f982 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -369,7 +369,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot); + int type, MemOp mop, hwaddr *pphys, int *pprot); void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 391f32f27d..58695def82 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -167,7 +167,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, - 0, &paddr, &prot); + 0, 0, &paddr, &prot); if (t >= 0) { /* We can't re-load the instruction. */ env->cr[CR_IIR] = 0; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index b984f730aa..a386c80fa4 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -197,7 +197,7 @@ static int match_prot_id64(CPUHPPAState *env, uint32_t access_id) } int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot) + int type, MemOp mop, hwaddr *pphys, int *pprot) { hwaddr phys; int prot, r_prot, w_prot, x_prot, priv; @@ -340,7 +340,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) mmu_idx = (cpu->env.psw & PSW_D ? MMU_KERNEL_IDX : cpu->env.psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); - excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, 0, + excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, 0, 0, &phys, &prot); /* Since we're translating for debugging, the only error that is a @@ -438,7 +438,8 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, break; } - excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, &phys, &prot); + excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, 0, + &phys, &prot); if (unlikely(excp >= 0)) { if (probe) { return false; @@ -678,7 +679,7 @@ target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) hwaddr phys; int prot, excp; - excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0, + excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0, 0, &phys, &prot); if (excp >= 0) { if (excp == EXCP_DTLB_MISS) { diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 7f79196fff..744325969f 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -334,7 +334,7 @@ target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr, } mmu_idx = PRIV_P_TO_MMU_IDX(level, env->psw & PSW_P); - excp = hppa_get_physical_address(env, addr, mmu_idx, 0, &phys, &prot); + excp = hppa_get_physical_address(env, addr, mmu_idx, 0, 0, &phys, &prot); if (excp >= 0) { cpu_restore_state(env_cpu(env), GETPC()); hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); From patchwork Wed Oct 9 00:04:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833805 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp555728wrv; Tue, 8 Oct 2024 17:06:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV19vxZ/0+RdpY4DIeNHLQl5yNmFPiXrg1MC/oKaO1Scjh06PMXAz9JfipnlfGi/ltXGnW6Ow==@linaro.org X-Google-Smtp-Source: AGHT+IG6MOwXlQdl2081nz7PLRN+1TwbfqZBIyAAEZTTJSajQ3jGT5bijCpYFA8eP7C9XEU9chhZ X-Received: by 2002:a05:6122:310c:b0:50c:a177:74c9 with SMTP id 71dfb90a1353d-50cf0c6634amr596914e0c.9.1728432365986; Tue, 08 Oct 2024 17:06:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432365; cv=none; d=google.com; s=arc-20240605; b=L1SlTmCYirpDa/PfFenZYAQMQz1rbqrP5BTKUANMOu0Stxh2OXa+V2Mj+OHIZqD1Zc 2Eph8kjXJHKey+QLdDpuI8e9ppv0PzbMDOeR7ppoz5XJHUBdIQu69G+aqvLTDGnqgJyN ufsMfY/4ugas5JX+sm9biceS99p6A3xIPjne5WAThkj2n4DIIzv9Bza4ba9xQh+Ir13Q pxdPh2ItFN6j4myS+dC6CxSV+XAy3x3qapPeXXNMcr0/sbgH2z1X8ZuNuqKRCyZtMt6R QlXAUGaHZgvcbxY+TRw4qbAfoCYizqxJcCnKaJfnhpZWQBy8iZHF9YlS446gnM2R59KQ BSMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jvwlrMz3Fk2P5q43/JWG8Wh7xLnVWB9wP6XAmMUyGN8=; fh=OJsPEozDPca3XcPjdO/16PfdVlYCY+jq5nAc4caG25E=; b=Rf9jRRBRMncROQcu46o+9QpVwXsD0f2BQL3PbtCkmIDgtBn/mq9R/eEQ/mS2Q4ac2X lD5L5/02Rd85Hwtk3W/t56M8GKUejNYp1E8Qpto7/KlnDgX6+kgP9KIADsrviyo7TXWJ T8wr0lImk5y7mDYXCkeVSQDVL3Wd+JICamH3sJyMOom0Rg/t9LVU61kAtnaCfrBpZOWI dDYvsv4CUyCvJ1DZ4iPTSYp3AS42fOMQ7rD9K3SPAr1r4JvA2gVwcCtZJjWe8RrY8TM/ UUHB5awy7P5uG8ng7MFyhwLB/5RxRk3GlHE4Otncj9YGgcfltB+FJTLl0xDVhCMp7L5D c5ng==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vxSzVVqe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller Subject: [PATCH v3 08/20] target/hppa: Perform access rights before protection id check Date: Tue, 8 Oct 2024 17:04:41 -0700 Message-ID: <20241009000453.315652-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In Chapter 5, Interruptions, the group 3 exceptions lists "Data memory access rights trap" in priority order ahead of "Data memory protection ID trap". Swap these checks in hppa_get_physical_address. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index a386c80fa4..f027c494e2 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -267,6 +267,12 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, goto egress; } + if (unlikely(!(prot & type))) { + /* Not allowed -- Inst/Data Memory Access Rights Fault. */ + ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR; + goto egress; + } + /* access_id == 0 means public page and no check is performed */ if (ent->access_id && MMU_IDX_TO_P(mmu_idx)) { int access_prot = (hppa_is_pa20(env) @@ -281,12 +287,6 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, prot &= access_prot; } - if (unlikely(!(prot & type))) { - /* Not allowed -- Inst/Data Memory Access Rights Fault. */ - ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR; - goto egress; - } - /* * In priority order, check for conditions which raise faults. * Remove PROT bits that cover the condition we want to check, From patchwork Wed Oct 9 00:04:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833826 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp556225wrv; Tue, 8 Oct 2024 17:07:27 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWataVHkvrEfuX/1xPJI6I/UMJF5dP921nSNTDCrbTWOdW00+hMdm9iX+mmmAStZXR5rlBErQ==@linaro.org X-Google-Smtp-Source: AGHT+IGz4UfKQEfX+LNe6kypJAoMwRr7YW0JWyQscJ+JWb4gFg+nYfxsfYFza0clSSiGj1ussnT+ X-Received: by 2002:a05:622a:2990:b0:458:34b4:7cd with SMTP id d75a77b69052e-45fb0e77a72mr9232211cf.58.1728432447735; Tue, 08 Oct 2024 17:07:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432447; cv=none; d=google.com; s=arc-20240605; b=CJgROoIc0I/Lib5crLJWziDUpG+13cfbgvdEoRQNacI/0s+/NOu8LwLoLeOXPe8yOd DyCQPZQV1Q6cC2LvuShbFyruvPFTNYUAof9VeS8neS0LzmlLIlF9Jl+ipYF1rzqssWyR ZnoTH9EcURISvxRklDDdG6ML9sMK5QS2vgzwy1EPUhJ8aB/9Qg9k9KHsa5InvgFdPWUM 7eoXljDjvgScE0K4Vr+2VXyKHpWbhaN7mxlzBG+AAnE4WyKuxIgCsJ8/eB8nhym8F5Yk AhUp1GXKOyQIrKQJaDFPN8pP3WDCNLr5cs9l2WGlvbk0AiEH/zEK1ZGP6gw0IvImTp45 CCHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8E2Z9ZSy95UZsg9Y2N2fIiaRxpU5aj12TR1V9ijHxjM=; fh=3RK8noKPsRgJpwHDkrKY6p9N6ePZuLOt1ZjdS1VodvU=; b=VTJVb2nqqFZapvZMiJ9FVEUPBN61H3nSnIdSzvr7ZhQGvSlD1HfdF1qj4UJ7uz5D/3 9BsJP+WWBEX2ScsbeV7R1N78g9oATDnW0DooF54+p79GC28ozDqFs1SvIIGt2+iSdP1e zK+8nFR8/Ck0EwVsfNM01QBx6rbAcZJaM5gBo+n1r+Ht3QwU3lq/TdIlJ16CJYDecSe9 cQP4wcmvNA79AUTZfMvTIBIz7EAdmfn5gfeshPH/c55fR+gRCiCK1XDEgWU4hW4O65Av qk846smXKIdeP+Ry5WMU7AG47DENZemtFCRLC8+7g+Pdg2WgxI1Wn+Y+RoaSPvtQ7qPz /Aiw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QG1nPvj4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 09/20] target/hppa: Fix priority of T, D, and B page faults Date: Tue, 8 Oct 2024 17:04:42 -0700 Message-ID: <20241009000453.315652-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Drop the 'else' so that ret is overridden with the highest priority fault. Fixes: d8bc1381250 ("target/hppa: Implement PSW_X") Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index f027c494e2..f71cedd7a9 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -288,7 +288,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, } /* - * In priority order, check for conditions which raise faults. + * In reverse priority order, check for conditions which raise faults. * Remove PROT bits that cover the condition we want to check, * so that the resulting PROT will force a re-check of the * architectural TLB entry for the next access. @@ -299,13 +299,15 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, /* The T bit is set -- Page Reference Fault. */ ret = EXCP_PAGE_REF; } - } else if (!ent->d) { + } + if (unlikely(!ent->d)) { prot &= PAGE_READ | PAGE_EXEC; if (type & PAGE_WRITE) { /* The D bit is not set -- TLB Dirty Bit Fault. */ ret = EXCP_TLB_DIRTY; } - } else if (unlikely(ent->b)) { + } + if (unlikely(ent->b)) { prot &= PAGE_READ | PAGE_EXEC; if (type & PAGE_WRITE) { /* From patchwork Wed Oct 9 00:04:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833823 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp556111wrv; Tue, 8 Oct 2024 17:07:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVzR3mSiE5o1gbZQtIzMnAT16BTmLI46H1qhJQS6TXTUe+3GkCy0E5QmIQyI3bxgh1+6EyZKQ==@linaro.org X-Google-Smtp-Source: AGHT+IG0CsFZVUC41JkGRZTuXCjXhRtPL+ztpNb2ffljhl7bcchOqLIJEZdlCT5KanVVxgNdWKZw X-Received: by 2002:a05:6214:310a:b0:6cb:4479:647a with SMTP id 6a1803df08f44-6cbc958fcdamr12105056d6.51.1728432430152; Tue, 08 Oct 2024 17:07:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432430; cv=none; d=google.com; s=arc-20240605; b=R8ABw/FCTvypxAaeAl9yIBiHG8V9zAa7ftFc90Qj6XI0L3d+iKqibeDSGDDkBhsiCb A2ubaHmcrVLbIrSGL7IJ+l2YLBZdo5ip/EPf7LA2hpy2NgCB6AEBeG9EfCIfZ2gwbYql y20CoolRUr0+XIDma/3FTzF8dTZyjXCzAC5QD+nSQ71rJ3sTYe1+2OWprmrl7RYRlPud /Ly36DlbWXd0Cy+lPlHzfeqdBV+vULDogX5FsRoMLv82BPFVVTOxaby96QVGnuNbRDDI Vyx8hYlSsY+6cmAQAUW7/YoEVZBpNaNZ3Jkx9eWWfCzIF+PgUGvNGKLPugfYO9Uaa1Ki +Vnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xQhK8NjjgW/kNvx5X1m22TpA6VVxTZtyOqTVcWaZJho=; fh=OJsPEozDPca3XcPjdO/16PfdVlYCY+jq5nAc4caG25E=; b=eUs07fT8bFfHjlKeKZg59EQ75OsQty/s5eyRPZxxJnOiT2RjBq1KjvFtuksAKJJSaP NBsEt5o1CB6J0/Rgi4StAv98tTlbYAgPAF1uwpxiuw+wlKKGEVfV40fg0hG4Zx4VnRKT TIMO7eppBTIn8kLI3sQlyvCOOQHlV6OP0rRw9p8bNCxF0SfToIm6+95XB+QC6+pQ/3pu lmxPJoYQWX1Q//b9DPId3B+tKtqonl7iOiAhsHuXCx8bYpbLq4PGExEcS1Ll+v8hqnT5 GbQO4HUs6rRRuhmrmH3Qix3YqOkg79t6V1ID7s+jK1/YLPGIs/kXOGz7mRRieVSKgxI9 mbNw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Dmn9fQ2v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller Subject: [PATCH v3 10/20] target/hppa: Handle alignment faults in hppa_get_physical_address Date: Tue, 8 Oct 2024 17:04:43 -0700 Message-ID: <20241009000453.315652-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In Chapter 5, Interruptions, the group 3 exceptions lists "Unaligned data reference trap" has higher priority than "Data memory break trap". Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index f71cedd7a9..d38054da8a 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -221,7 +221,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, g_assert_not_reached(); } prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - goto egress; + goto egress_align; } /* Find a valid tlb entry that matches the virtual address. */ @@ -323,6 +323,11 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, } } + egress_align: + if (addr & ((1u << memop_alignment_bits(mop)) - 1)) { + ret = EXCP_UNALIGN; + } + egress: *pphys = phys; *pprot = prot; From patchwork Wed Oct 9 00:04:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833836 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp556829wrv; Tue, 8 Oct 2024 17:09:05 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCURF8gCGbTBaJ+T+JZvyl11d7WfbeWHBJFuq7NSEh3c4x3DS2gQGCf/IBDnIh2okaNJpaINSA==@linaro.org X-Google-Smtp-Source: AGHT+IEooTbEGDGs5+B8X2MQSVjR5gbrI48XLto7eQyEGT/5n112CycAxhZIduAcModHPuK70fvx X-Received: by 2002:a05:620a:4452:b0:7ac:bfb6:8202 with SMTP id af79cd13be357-7b07954fd55mr119241885a.38.1728432545683; Tue, 08 Oct 2024 17:09:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432545; cv=none; d=google.com; s=arc-20240605; b=O/AV5xPJjyL7M8OjV8kzldVtqAeA4fYqURJ8BLat2zEXF4NxpglRCYFmATjwOIOQMQ dRLsRZVO4gHorHcrl90/084MwadYOMJHh0O4+yeTYC4YvQ9gz/sYAOqvD55H5YXSKfXO fWWnV0Q4v+/3+IlYi82oaWlo/3+IMK2urGCdsxLypLwelECO/012BlWVwbp7aIQtPK/P qogtUiGwyDQxK7Ikd9MYtLDFiufAdQUyOr3go0DMMJh5D0t/ugbgyLWFT8eAw2tqRpja GPOdgoC8u/k6rTD5XRptQF3ah0DBvBMKkVB0lc2yRjDbQfwTBLcVUelCVOEHOG99tv0B zeaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iV2KSUuCTdEDpKpG+VIBV8pupsJQOA9ecDi8J+rVd34=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=kMJ631w3SZ0WGfuJ1lo+ESv/C3DEh58oXsYvXxoysiBIg+Iwa7DWSyUn5hNnSr8dQi IUEDwKBVWmGIGilbAfUgtcZRTjfQSjXaIsDHjtZQCajuvr/RXjn53+qAD+Zn7qusRc7V LGEPR5roSuo+Fqnhm7rOk05ZmhXO38JpO+4MXHik9mYt5KtMX8PPIbqGB/ackyuQs8Yv pj4J2C1RHuswVc49+2Hdyj6Xv0WTJ3CmJhamrlraLs15k3RBXah4UeE9YP7UrP1oT00B T+qcP9wxLUnBNbCaDpSRl33YM+2idKSEdb9gDSymCoFky+tjA8bnK0ayAyfy0qL7EsqZ P7vA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J3aKb9Iy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH v3 11/20] target/hppa: Implement TCGCPUOps.tlb_fill_align Date: Tue, 8 Oct 2024 17:04:44 -0700 Message-ID: <20241009000453.315652-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert hppa_cpu_tlb_fill to hppa_cpu_tlb_fill_align so that we can recognize alignment exceptions in the correct priority order. Resolves: https://bugzilla.kernel.org/show_bug.cgi?id=219339 Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Tested-by: Helge Deller --- target/hppa/cpu.h | 6 +++--- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 21 ++++++++++++--------- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 526855f982..e45ba50a59 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -363,9 +363,9 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); void hppa_ptlbe(CPUHPPAState *env); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled); -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7cf2e2f266..c38439c180 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -226,7 +226,7 @@ static const TCGCPUOps hppa_tcg_ops = { .restore_state_to_opc = hppa_restore_state_to_opc, #ifndef CONFIG_USER_ONLY - .tlb_fill = hppa_cpu_tlb_fill, + .tlb_fill_align = hppa_cpu_tlb_fill_align, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .cpu_exec_halt = hppa_cpu_has_work, .do_interrupt = hppa_cpu_do_interrupt, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index d38054da8a..b8c3e55170 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -424,12 +424,11 @@ void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, } } -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra) { - HPPACPU *cpu = HPPA_CPU(cs); - CPUHPPAState *env = &cpu->env; + CPUHPPAState *env = cpu_env(cs); int prot, excp, a_prot; hwaddr phys; @@ -445,7 +444,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, break; } - excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, 0, + excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, memop, &phys, &prot); if (unlikely(excp >= 0)) { if (probe) { @@ -454,7 +453,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx); /* Failure. Raise the indicated exception. */ - raise_exception_with_ior(env, excp, retaddr, addr, + raise_exception_with_ior(env, excp, ra, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); } @@ -468,8 +467,12 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, * the large page protection mask. We do not require this, * because we record the large page here in the hppa tlb. */ - tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); + memset(out, 0, sizeof(*out)); + out->phys_addr = phys; + out->prot = prot; + out->attrs = MEMTXATTRS_UNSPECIFIED; + out->lg_page_size = TARGET_PAGE_BITS; + return true; } From patchwork Wed Oct 9 00:04:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833814 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp555896wrv; Tue, 8 Oct 2024 17:06:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUH1axMjT8R6zpHewc1YRFQcR0Qtsh6Eua8KQDgKZ/uj9ddw+Oi8PzZvknnEWyniNsjEUY30Q==@linaro.org X-Google-Smtp-Source: AGHT+IGXyb3Fqlbp3I63wJ3KsgStGRxTLzcburq6uaLBVHKm6i8pmlZ6vqKYVJ4/LFKTU6KBWQo2 X-Received: by 2002:a05:622a:1b15:b0:45f:873:ff5e with SMTP id d75a77b69052e-45fb0e6ef82mr9535251cf.57.1728432393428; Tue, 08 Oct 2024 17:06:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432393; cv=none; d=google.com; s=arc-20240605; b=bfnlDUZdh1rkzkvGiydOojBfI2jhBqgsXhwMIKMGP/pfA8IMX0LTKiCPl0jrrmM/g8 ZMTaRHWB8CptwuxcjZF93F0N93drqI2hWVGSi80od7zsYQCw5WR5zW31oOoM6wUqs9aL S74oGRE7v8QGaRa5UD25LvVCdKGYxKbb92tgsmvEvAHcPEHyn6ztVQ/4mSBXvcFib9Wr K/K6d+EyAKhnaORa4fdEKJSpY3G8GG8c/WQFcldud2SRJuGdYVN3/g4sieU8967cYx0R cuOQGcGrsPBB+ziJ2Tmy3LBHIdNkMCgdZgfqr4jzbWoK4700dSmjnaUTkAbywtubjhhA QnaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RUID/VOY3Ga2ZN/DeZx4JrZs9/xknXUyzF7dZ/9YQNo=; fh=3RK8noKPsRgJpwHDkrKY6p9N6ePZuLOt1ZjdS1VodvU=; b=YhC8tVj19xIYopBY9Ze32DKsiq1MNMkVdhGgNMCdv86Ld06H58oVCZJazCetPlsOsZ k9ikOQGCkwWFWr4lzwsrDomJMp0d1YAaOwyU82pqbSe7gH0FFbtNr5OeamQHffnH80sg MEDJgqWmHSudkOCiKMlK8WZ6fFAeD8DcU35o3sy0PNjFkH5/f/tc5qzPUbEN5JehpwE3 DO/w8A1vk4nXjPtd2Y0LnzY1Eee6CGPp095VIktuBckPmLuMfAOicNhWcNPy4jYId0dZ f3/m+hccYTYyBWWtsjzNlQV2Vaebe/QSl7qQinvgBamnhagrBIRvZ5NAfcHS0+adgcd3 kWLw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m4nCceRm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 12/20] target/arm: Pass MemOp to get_phys_addr Date: Tue, 8 Oct 2024 17:04:45 -0700 Message-ID: <20241009000453.315652-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 ++- target/arm/ptw.c | 2 +- target/arm/tcg/m_helper.c | 8 ++++---- target/arm/tcg/tlb_helper.c | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1e5da81ce9..2b16579fa5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1432,6 +1432,7 @@ typedef struct GetPhysAddrResult { * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute + * @memop: memory operation feeding this access, or 0 for none * @mmu_idx: MMU index indicating required translation regime * @result: set on translation success. * @fi: set to fault info if the translation fails @@ -1450,7 +1451,7 @@ typedef struct GetPhysAddrResult { * value. */ bool get_phys_addr(CPUARMState *env, vaddr address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 659855133c..373095a339 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3572,7 +3572,7 @@ bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, } bool get_phys_addr(CPUARMState *env, vaddr address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { S1Translate ptw = { diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 23d7f73035..f7354f3c6e 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -222,7 +222,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, int exc; bool exc_secure; - if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_STORE, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { if (mode == STACK_LAZYFP) { @@ -311,7 +311,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, bool exc_secure; uint32_t value; - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, @@ -2009,7 +2009,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure, "...really SecureFault with SFSR.INVEP\n"); return false; } - if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_INST_FETCH, 0, mmu_idx, &res, &fi)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); @@ -2045,7 +2045,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, ARMMMUFaultInfo fi = {}; uint32_t value; - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 885bf4ec14..1d8b7bcaa2 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -344,7 +344,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * return false. Otherwise populate fsr with ARM DFSR/IFSR fault * register format, and signal the fault. */ - ret = get_phys_addr(&cpu->env, address, access_type, + ret = get_phys_addr(&cpu->env, address, access_type, 0, core_to_arm_mmu_idx(&cpu->env, mmu_idx), &res, fi); if (likely(!ret)) { From patchwork Wed Oct 9 00:04:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833833 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp556503wrv; Tue, 8 Oct 2024 17:08:12 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU0CqiSWiW8NeVR3JVfSXH+CpZfACTStMw0H5fxC2d8ryOh8Nz8Zln92j94AXHf5JV2D9MXVA==@linaro.org X-Google-Smtp-Source: AGHT+IHkbOFU7CfVszUrZ9x/kLhfFX0HI9Ivyvw/rmm1lqEQOWdJbQ8dUZoUEu0z7QnnRBRWDqjD X-Received: by 2002:ac8:574a:0:b0:45b:16b:ecb7 with SMTP id d75a77b69052e-45fa5eca583mr9591091cf.1.1728432492399; Tue, 08 Oct 2024 17:08:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432492; cv=none; d=google.com; s=arc-20240605; b=lOVTcleTQm0drQYRwuKpWpzxxjuh6WtjZUnzsOIy7fgyhPgHLfgBgW85OADsTXy+hH Hjtuc92h7IEYOTZQloSPEONztTFT2/TzIR/MvIDn/XsVpg7TXDmOqs2hlSRyueCDv8aM sY6ZMufmhGPbc/hm7h+mMazD47MuFmno4USeV+15xGsFjDqVxAWkKoCejeoU+yZGFEO2 +C6Ylpvo5IVo/QW7QDFLWiMFWqdkP3uX8XOGhy7jsAlf2k69RC3jVYx6T78PR3xMcXi0 tVeSGHSp+guhABBNLIMqmtmAYhWh222+to2r/Zn6CtSBCcvVp1nhAQtqMw8koDJpdHVo TKvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=I928rOfU7rFS4/uAexBKDkmn1Lv4VMSl/VKyNRV9wmg=; fh=3RK8noKPsRgJpwHDkrKY6p9N6ePZuLOt1ZjdS1VodvU=; b=KZrFV8bIQnxd/YqVbxqu41refUKx0n9mJNMZTdhp0XgNO/w3vAd60APWG7/Xb7msG4 Kgg8f3H0yr1o/xcz4G/dVEXlcbeRddgYczgCPTJtfBGF/psBV5qPPQGUz4S4OETF8PGe G5DNcNEAdbhCLkpojPpbVvQcHt2bsFUJihp9Y2HdpsaOCv4OTzWHcYKJt8HhgpwfRViv vXn5JIghSy01jPjAPmwGD2seOyLEcbpJeGzMDhDIdn8VccmlkfI75zc0MgrHHGu20eRM yV4F09f5H8eP1Aff1qXZ2hxSOmUytGgJi7iP05tPiV0qQuPvsuZyhtKbjW3HZYdEp2xO NYsA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="yc0D//L+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 13/20] target/arm: Pass MemOp to get_phys_addr_with_space_nogpc Date: Tue, 8 Oct 2024 17:04:46 -0700 Message-ID: <20241009000453.315652-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 ++- target/arm/helper.c | 9 +++++---- target/arm/ptw.c | 2 +- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2b16579fa5..a6088d551c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1461,6 +1461,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address, * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute + * @memop: memory operation feeding this access, or 0 for none * @mmu_idx: MMU index indicating required translation regime * @space: security space for the access * @result: set on translation success. @@ -1470,7 +1471,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address, * a Granule Protection Check on the resulting address. */ bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, ARMSecuritySpace space, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f77b40734..0a731a38e8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3599,11 +3599,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, GetPhysAddrResult res = {}; /* - * I_MXTJT: Granule protection checks are not performed on the final address - * of a successful translation. + * I_MXTJT: Granule protection checks are not performed on the final + * address of a successful translation. This is a translation not a + * memory reference, so "memop = none = 0". */ - ret = get_phys_addr_with_space_nogpc(env, value, access_type, mmu_idx, ss, - &res, &fi); + ret = get_phys_addr_with_space_nogpc(env, value, access_type, 0, + mmu_idx, ss, &res, &fi); /* * ATS operations only do S1 or S1+S2 translations, so we never diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 373095a339..9af86da597 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3559,7 +3559,7 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, } bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, ARMSecuritySpace space, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) From patchwork Wed Oct 9 00:04:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833854 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp556847wrv; Tue, 8 Oct 2024 17:09:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV8om+PileI7et1metFdkF2tpI8gOlppDMRzZF2qWUdkFwA5HrvUNaZf/M78qT/2XZbDUj7Ug==@linaro.org X-Google-Smtp-Source: AGHT+IFs3cUW4aEixBZ4mIoGj/8//vsfR1VOjHsK5s5GIk1JNcrZC56+d3z80pryOhatXD6CJixW X-Received: by 2002:a05:620a:4452:b0:7a2:e53:3f5d with SMTP id af79cd13be357-7b0874e1560mr75029185a.66.1728432550148; Tue, 08 Oct 2024 17:09:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432550; cv=none; d=google.com; s=arc-20240605; b=aPc7dVMAW2l6herQh0OvfOWf1/zG8A1jRt5LczfRaiUgvN6zeryUnmkDfmTDZwkARh YYCx1UdH+w4OEjRVPNWF4WZZQ3YhwiW9Lj+c4t+YMwy5biC4SX0AufsM4UiJ5OU83YXZ 5q/d8sFVBDLbcklNY1kjC71+uW7OvqRCI+nNaOXeHFcHJPaXgovWNX0fTM4TmBWs8bcw xoiO4hkyD70v6rZ6nOPXGLRcmALI6T3tpn9JMOYoqficX+ViCLT8EOMeIV/nmzxdMxs5 iZA/DUHFv3jU2zzvHz6BlO6qfdBUKleXoFT9NsDxepLZ5iJTGUWIu7nWrh6IA3PofJYJ D3jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=617h4byv7OP/ct3y2kJCr5k6Qy1wZsttJUBcCYmwvNQ=; fh=3RK8noKPsRgJpwHDkrKY6p9N6ePZuLOt1ZjdS1VodvU=; b=SrU5KpzN1sBSuTPnfjnHpymqaLHSUGeDD5P/+CTYSkQ3o7r0lWyPRg3nTXS+pKzD9f pUWUzJxwHHFpQO4AaROsKT4ogzLNZWJP+7twSeB57aU43FsCAcIsCnRTydxnXtHZk9HA saN7tPBrW8O6uf3ljVobAECsAZjE0VPr2xBdIFpTH+LgboTW+yhfzue1l1qcAfj+PhYC 9XlVlNSeJePWnU0irqMZhX7xmq+t+Z0ZcrXET375fWnO9UIdosymmSzjTwWd/Uf3JdID l9nn8vDVmlylKpD14W3CDORUPlXQkFAEclF0y1Il4gwqa77nlLq30+EbJCDWH14X+DsE EGKw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BjRYaOoD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 14/20] target/arm: Pass MemOp to get_phys_addr_gpc Date: Tue, 8 Oct 2024 17:04:47 -0700 Message-ID: <20241009000453.315652-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Pass the value through from get_phys_addr. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9af86da597..e92537d8f2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -81,7 +81,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi); @@ -579,7 +579,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, }; GetPhysAddrResult s2 = { }; - if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, &s2, fi)) { + if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, 0, &s2, fi)) { goto fail; } @@ -3543,7 +3543,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { @@ -3641,7 +3641,8 @@ bool get_phys_addr(CPUARMState *env, vaddr address, } ptw.in_space = ss; - return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); + return get_phys_addr_gpc(env, &ptw, address, access_type, + memop, result, fi); } hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -3660,7 +3661,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, ARMMMUFaultInfo fi = {}; bool ret; - ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); + ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, 0, &res, &fi); *attrs = res.f.attrs; if (ret) { From patchwork Wed Oct 9 00:04:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833832 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp556494wrv; Tue, 8 Oct 2024 17:08:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVYrv52I0ozkZX7jkuwbV3zVhS+CeoE7FA0HK604GpYUuUZu+dD4mcHYSrnnHH/W+o5+7RFRw==@linaro.org X-Google-Smtp-Source: AGHT+IFOrASz8cl6jWNQlrENw5jbN+0yaKYkpAguQFoYr+T4kfn7MbzEhKEyAbcE0PzIZHRKduRy X-Received: by 2002:a05:620a:2945:b0:7a9:9a64:cdab with SMTP id af79cd13be357-7b0874b2f3dmr87957085a.45.1728432490731; Tue, 08 Oct 2024 17:08:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432490; cv=none; d=google.com; s=arc-20240605; b=Hj3GLOTV74Z8MaKsdj0fyvsUm21EBu2U8AdtSFPwdZO391TmG0il2w0ootI/hHUb5J PBhMfDggxo90xETmnClvd5VlThUvwaH2kuyR/Qj0xFO08HXJ8vK5MXwiWcg4CTjBLRAC MfttIylUXUtdHUkcmQJ8HW7cO73DOqLBFePCZDlL8Fvmo7uudZ2e+5SVt79xLfhYNqnR rWMXtvWiAhKOYgdhRXZt/xQvcUVKyoqH4wV2+bT1vT7lKWCfCzFUWqVF+ett1WBFcCJ5 8UrDrLkH6IcKWbJ10yHT7gKqtkiiJMMnN0eHjC0eo8vmTrvSwGPqdJauhxhXscYjJrfb C0BA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HpCts7Lc7po90jMJZMaWUdEUzHFwVBTsaL90Hh3zO7Y=; fh=3RK8noKPsRgJpwHDkrKY6p9N6ePZuLOt1ZjdS1VodvU=; b=cgW+JoHRRq04LOCdwB/w+q5OyN87OhFb4SVA33Xee14IIvXu2dx+gcr6ISYxZVwavH 68dh8h0mHfOfvwkTL0Bl24lq/ZTrq4lu7OALL9IHQWO9FXC9BssQAk2SxfmYMPDg6pYA rKnfHj2tTd/iuAr/grigDlpIDDGmgE5KMxYn75UYnFzgBWt6D83xcPyGgTXC0/wcmEGx lRVyFbfajHB2bvOjWR9CLtYVORL5FYMXjLiwLJkVjnm4txs8LLHl8tM2EI3wB2C+5VYG UT3GkEja2I0Y2VO7Lf+p+a7m5/GlcBZAM9FoEsoFLlJODfB5wHLglX0VAPW9UI7Osgyr 07gQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CkEt7i4A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 15/20] target/arm: Pass MemOp to get_phys_addr_nogpc Date: Tue, 8 Oct 2024 17:04:48 -0700 Message-ID: <20241009000453.315652-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Pass the value through from get_phys_addr_gpc and get_phys_addr_with_space_nogpc. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e92537d8f2..0445c3ccf3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -75,7 +75,7 @@ typedef struct S1Translate { static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi); @@ -3313,7 +3313,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ARMSecuritySpace ipa_space; uint64_t hcr; - ret = get_phys_addr_nogpc(env, ptw, address, access_type, result, fi); + ret = get_phys_addr_nogpc(env, ptw, address, access_type, 0, result, fi); /* If S1 fails, return early. */ if (ret) { @@ -3339,7 +3339,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, result, fi); + ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, 0, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ @@ -3406,7 +3406,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { @@ -3547,7 +3547,8 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - if (get_phys_addr_nogpc(env, ptw, address, access_type, result, fi)) { + if (get_phys_addr_nogpc(env, ptw, address, access_type, + memop, result, fi)) { return true; } if (!granule_protection_check(env, result->f.phys_addr, @@ -3568,7 +3569,8 @@ bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, .in_mmu_idx = mmu_idx, .in_space = space, }; - return get_phys_addr_nogpc(env, &ptw, address, access_type, result, fi); + return get_phys_addr_nogpc(env, &ptw, address, access_type, + memop, result, fi); } bool get_phys_addr(CPUARMState *env, vaddr address, From patchwork Wed Oct 9 00:04:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833828 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp556490wrv; Tue, 8 Oct 2024 17:08:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU545C6/FtnuEsZv579NcWdmliuaCxOCugH1gBf33XrPMlfIpREM36PgCYTLmGZnRc8pAwwhw==@linaro.org X-Google-Smtp-Source: AGHT+IFCsxZ1f+UybI+lf1/bDr1Yiwcah5vCneaGRn4hOPUMIeXqDAR4vQNJG8oFXOP2dHSD2rGA X-Received: by 2002:ac8:7d46:0:b0:458:4e4c:b692 with SMTP id d75a77b69052e-45fa5f21917mr8335771cf.36.1728432490209; Tue, 08 Oct 2024 17:08:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432490; cv=none; d=google.com; s=arc-20240605; b=eZZ83e5Ugx6kDrKPfnEKJlR0kxt1/wdG+dLKoIG/xdN5QitBTCUBp5Zz8FDbftOe/D aZCih+pA0kvk+wcRwTuPAsqHpfnBKec9kiuvEFIsRpdpdqOogFYZHUEOWm+9E4rOXGKz wm2yQ7npuWYtOOzt5GfABdwJTqEpMi7uTCMqi7c4Rdav/OJOv2+9duvnca6lTSwWDPEg zp9SkO4xnl9gCbrhLtpN3dWP08CkLcsW+2kiWdedEhPWn+4PZG7crmw7PnY0eEMx72Qc dJDoLItsD+hzV1NcoRL2BP1vOqGofQX7/F8rviz/kqKXNvvLJ0GfzhH+RmGQV9YyPpRp N9Fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nPsGlRApUHllpr7HECmYu85LwKI3gq1PeB/gQzKhtMY=; fh=3RK8noKPsRgJpwHDkrKY6p9N6ePZuLOt1ZjdS1VodvU=; b=Ptzl/R8HEQ2xkzrCrtCfbU2D668lUlfdwE1AjwZJNUywONFk2biwuLjACcBU+UumVY 0awMe6jkv+iqOi7ObHbCUpYJx5khnkrlF8YNRnwM0OX3y4Wx+gfh5Q/vdiQRSbKgVSqJ k1vDrKE5qEjwIhLaANAyETuNIQLqrQCNfYHE0D04o10TTvXyNoI2n88if1flX2i7x3d9 hwxzBSmlqTsMKulDn/UNjMI/nlQURmJ0Wwz2UuhjfbpKXe4+sVLP9ThcY0HBs+bkjvwj m1kHJc82XMNC08qW4gk22wd2FTQbpt2xHF6lwCxNj4FfJI0fEVV0w86k4xQQB3dtcrin UrWw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RCevTzLB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 16/20] target/arm: Pass MemOp through get_phys_addr_twostage Date: Tue, 8 Oct 2024 17:04:49 -0700 Message-ID: <20241009000453.315652-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass memop through get_phys_addr_twostage with its recursion with get_phys_addr_nogpc. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0445c3ccf3..f1fca086a4 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3301,7 +3301,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { @@ -3313,7 +3313,8 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ARMSecuritySpace ipa_space; uint64_t hcr; - ret = get_phys_addr_nogpc(env, ptw, address, access_type, 0, result, fi); + ret = get_phys_addr_nogpc(env, ptw, address, access_type, + memop, result, fi); /* If S1 fails, return early. */ if (ret) { @@ -3339,7 +3340,8 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, 0, result, fi); + ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, + memop, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ @@ -3469,7 +3471,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, if (arm_feature(env, ARM_FEATURE_EL2) && !regime_translation_disabled(env, ARMMMUIdx_Stage2, ptw->in_space)) { return get_phys_addr_twostage(env, ptw, address, access_type, - result, fi); + memop, result, fi); } /* fall through */ From patchwork Wed Oct 9 00:04:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833834 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp556693wrv; Tue, 8 Oct 2024 17:08:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXNvCybMu4T/dmRW9hNLtLRQwwEWDdT4Qomq2URQyegS5TcZnokpNjzDBSBQsIZN18f5zzFGA==@linaro.org X-Google-Smtp-Source: AGHT+IEsd6PzFXAscFR8yppmEmucwBXFTJ7fLiIkhV3SMruvsNHccpjkLQ95xT+0Q3HHxZ/zkOCw X-Received: by 2002:a05:620a:1987:b0:7a1:e2d4:4ff3 with SMTP id af79cd13be357-7b0795258c1mr97444985a.3.1728432520101; Tue, 08 Oct 2024 17:08:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432520; cv=none; d=google.com; s=arc-20240605; b=JvWsKK+3XUsEwmv0pFr4MwiJ7s7hAy/2pOBOIneRT8woiqhpRkycxcByJv1XL4VBE1 fAlUJ/wf1S0w+jXOoHFkJXFkRCeA2ROB8q2qmdiOmGAuRjiQvdh7L24STRcf00ZRaKjT XA0aKEF0UH/GUdMAbp+02KwZSiuntrzNwxIsF5MsxO+nzss5+hsnC0XLx1HRMgRSFhoS atO/RY4psqc4nHJN2ERlc+YVDzszu9s3WieNe7KC5YcKiWjW5kdDyHyrBx6YJUVQj3Ys kcvsRNe4xKSM2xjWrxc32eFYhpHGsozcMwl0w3NVv/a8QO/trmiGPnPAUFUhy8zOLzaz l2BQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zDNpltdoK5BIHBCpA0bLYhC/fVRvo8Z+4KE41wqkR3g=; fh=3RK8noKPsRgJpwHDkrKY6p9N6ePZuLOt1ZjdS1VodvU=; b=SewvXVOpU9j/oB1CCZsCmhOKWsg2G58QcS0983RFQzmtt7PwEs2+zrS/MQ+GlgnPwX QlfIX5Be2zwtQ0QXGHeEwPk0K5EZe/oCUtEc4dc6tXnohC71P3U21ZRIQh57z0H6evU1 Xq2o+C/cFd1Vbo6k9XaErT6uYCVK4/CzxWcu5q8wYhp7OlstEOl+o8Vp9f2vjORD1lb+ UkjCFCbaEhIdxFCpJUhsJpMlFI8ZCzSMxYtLBkp9m9nIEXxn2YgmW1HPJcWWGoSDGAKi ZIBDiQ0nHuv5mbs6CWRrcPxntQWs5KlVO9moUze1QgHaCyDh7OLfGVdominGSuRWuICF L9Tw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="U6kx0i/e"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org, Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 17/20] target/arm: Pass MemOp to get_phys_addr_lpae Date: Tue, 8 Oct 2024 17:04:50 -0700 Message-ID: <20241009000453.315652-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass the value through from get_phys_addr_nogpc. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f1fca086a4..238b2c92a9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1684,12 +1684,13 @@ static bool nv_nv1_enabled(CPUARMState *env, S1Translate *ptw) * @ptw: Current and next stage parameters for the walk. * @address: virtual address to get physical address for * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH + * @memop: memory operation feeding this access, or 0 for none * @result: set on translation success, * @fi: set to fault info if the translation fails */ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); @@ -3534,7 +3535,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, } if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, ptw, address, access_type, result, fi); + return get_phys_addr_lpae(env, ptw, address, access_type, + memop, result, fi); } else if (arm_feature(env, ARM_FEATURE_V7) || regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, ptw, address, access_type, result, fi); From patchwork Wed Oct 9 00:04:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833810 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp555732wrv; Tue, 8 Oct 2024 17:06:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXJG+DWWZI1UbXgyj8Caq50HZoP/yrBE8+wRKVyIeQXNEj+dm5eRjHg4+ODYZFhZ5YyDJDKsA==@linaro.org X-Google-Smtp-Source: AGHT+IFfh5X1WB6rVMc8JjwUJNnmUKitBbjVe/XcKs6pqUShv/LRg6h6iU+FDbS9XBPZ7v+MTiSt X-Received: by 2002:a05:620a:1a8e:b0:7a9:a991:f6d7 with SMTP id af79cd13be357-7b079547907mr101780285a.48.1728432366523; Tue, 08 Oct 2024 17:06:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432366; cv=none; d=google.com; s=arc-20240605; b=DOw8AIdZni49eIYXWQCt/2Jk10v5Xa0suBuPr2f6Va8DwUVa+MZn1t0ai2RyAsHG1y WEIb4Jlx+q04bJfF7sO8VeTuNqpyv5dIuj6HCKmtLBwxlNloSTOckY/hO8uBY8ZgC8gT 9WMtcOWIWoZg5yBM7/B2iTVjPbK/NUbh1qxMywTb+hx0N2EsKLvzYy+Cgo1+L81oiEko ZjNi0m/CppFaT9fGhl8hd2s5qqrd8poAFxtr+dZZUd1L3DJtz1QAE3fdiDZytUTa0nNN 0J9ZbS0d/OKSGZCVRcknbX6iiGEdsvNBxq5+0rmriGwAskmDPWlapBrbbOVdTuM/niz1 zqWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oOELs1GBJLtlq8nQGFT7BbF8Y02om3aScvqBsVkX7+Q=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=hoYYWQAnOi66jaBQo1RhCo1GSb13EtDFM7vZAwYJocQIU4wSssUyxeFWfsRTGNFGtO 2HjEijJkHDQE6G3DpYYB7JmEP77iUxL8yvGH/jAJacMuguvphIxxEc43V9dDU6Gc7QcM zWEaT+eRE8I35p85g1NPfOxR/Ecs1ua8DKeEiC0xffvF5kl5GldYVOXcfGpwUGXv1tua Qa+Jv+5NX1uazzCgHDEYgsKk0Euk3qnhEniFCJqIz8j02PAR18vTs5EWRyLVtZv/Uluw UpwkuoTCiY0RXcSH+n4I+uaM1IChx1GESngiT9P5H+YahXx8BVFt9P2FJERpZGGNEdK6 hAyw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O05Tx7zV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH v3 18/20] target/arm: Move device detection earlier in get_phys_addr_lpae Date: Tue, 8 Oct 2024 17:04:51 -0700 Message-ID: <20241009000453.315652-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Determine cache attributes, and thence Device vs Normal memory, earlier in the function. We have an existing regime_is_stage2 if block into which this can be slotted. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 238b2c92a9..0a1a820362 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2029,8 +2029,20 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, xn = extract64(attrs, 53, 2); result->f.prot = get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } + + result->cacheattrs.is_s2_format = true; + result->cacheattrs.attrs = extract32(attrs, 2, 4); + /* + * Security state does not really affect HCR_EL2.FWB; + * we only need to filter FWB for aa32 or other FEAT. + */ + device = S2_attrs_are_device(arm_hcr_el2_eff(env), + result->cacheattrs.attrs); } else { int nse, ns = extract32(attrs, 5, 1); + uint8_t attrindx; + uint64_t mair; + switch (out_space) { case ARMSS_Root: /* @@ -2102,6 +2114,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, */ result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, result->f.attrs.space, out_space); + + /* Index into MAIR registers for cache attributes */ + attrindx = extract32(attrs, 2, 3); + mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; + assert(attrindx <= 7); + result->cacheattrs.is_s2_format = false; + result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); + + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { + result->f.extra.arm.guarded = extract64(attrs, 50, 1); /* GP */ + } + device = S1_attrs_are_device(result->cacheattrs.attrs); } if (!(result->f.prot & (1 << access_type))) { @@ -2131,30 +2156,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, result->f.attrs.space = out_space; result->f.attrs.secure = arm_space_is_secure(out_space); - if (regime_is_stage2(mmu_idx)) { - result->cacheattrs.is_s2_format = true; - result->cacheattrs.attrs = extract32(attrs, 2, 4); - /* - * Security state does not really affect HCR_EL2.FWB; - * we only need to filter FWB for aa32 or other FEAT. - */ - device = S2_attrs_are_device(arm_hcr_el2_eff(env), - result->cacheattrs.attrs); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx = extract32(attrs, 2, 3); - uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <= 7); - result->cacheattrs.is_s2_format = false; - result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); - - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.extra.arm.guarded = extract64(attrs, 50, 1); /* GP */ - } - device = S1_attrs_are_device(result->cacheattrs.attrs); - } - /* * Enable alignment checks on Device memory. * From patchwork Wed Oct 9 00:04:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833812 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp555797wrv; Tue, 8 Oct 2024 17:06:19 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWBjOO/MOQSBWVP5lITwc7Gb/zsPThSTJ49KzRoW8nl/Fu47BwtMkCpxMJht9MCFlNqwC6X5g==@linaro.org X-Google-Smtp-Source: AGHT+IF2csCTW8Enqt0CH0ibMzem2zVcprFuaBvSCGDNUmrbLvJgJO9ePNiJveBC4D6f6Pe0nx5n X-Received: by 2002:a05:620a:240b:b0:7a9:b8dd:eb96 with SMTP id af79cd13be357-7b07954a696mr70029285a.30.1728432379149; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH v3 19/20] target/arm: Implement TCGCPUOps.tlb_fill_align Date: Tue, 8 Oct 2024 17:04:52 -0700 Message-ID: <20241009000453.315652-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fill in the tlb_fill_align hook. Handle alignment not due to memory type, since that's no longer handled by generic code. Pass memop to get_phys_addr. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 6 ++--- target/arm/cpu.c | 2 +- target/arm/tcg/cpu-v7m.c | 2 +- target/arm/tcg/tlb_helper.c | 49 ++++++++++++++----------------------- 4 files changed, 24 insertions(+), 35 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a6088d551c..299a96a81a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -816,9 +816,9 @@ void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, MMUAccessType access_type, uintptr_t ra); #else -bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra); #endif static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 19191c2391..1320fd8c8f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2663,7 +2663,7 @@ static const TCGCPUOps arm_tcg_ops = { .record_sigsegv = arm_cpu_record_sigsegv, .record_sigbus = arm_cpu_record_sigbus, #else - .tlb_fill = arm_cpu_tlb_fill, + .tlb_fill_align = arm_cpu_tlb_fill_align, .cpu_exec_interrupt = arm_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, .do_interrupt = arm_cpu_do_interrupt, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 5496f14dc1..58e54578d6 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -242,7 +242,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = { .record_sigsegv = arm_cpu_record_sigsegv, .record_sigbus = arm_cpu_record_sigbus, #else - .tlb_fill = arm_cpu_tlb_fill, + .tlb_fill_align = arm_cpu_tlb_fill_align, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, .do_interrupt = arm_v7m_cpu_do_interrupt, diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 1d8b7bcaa2..8841f039bc 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -318,14 +318,13 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } -bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr address, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra) { ARMCPU *cpu = ARM_CPU(cs); GetPhysAddrResult res = {}; ARMMMUFaultInfo local_fi, *fi; - int ret; /* * Allow S1_ptw_translate to see any fault generated here. @@ -339,37 +338,27 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } /* - * Walk the page table and (if the mapping exists) add the page - * to the TLB. On success, return true. Otherwise, if probing, - * return false. Otherwise populate fsr with ARM DFSR/IFSR fault - * register format, and signal the fault. + * Per R_XCHFJ, alignment fault not due to memory type has + * highest precedence. Otherwise, walk the page table and + * and collect the page description. */ - ret = get_phys_addr(&cpu->env, address, access_type, 0, - core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &res, fi); - if (likely(!ret)) { - /* - * Map a single [sub]page. Regions smaller than our declared - * target page size are handled specially, so for those we - * pass in the exact addresses. - */ - if (res.f.lg_page_size >= TARGET_PAGE_BITS) { - res.f.phys_addr &= TARGET_PAGE_MASK; - address &= TARGET_PAGE_MASK; - } - + if (address & ((1 << memop_alignment_bits(memop)) - 1)) { + fi->type = ARMFault_Alignment; + } else if (!get_phys_addr(&cpu->env, address, access_type, memop, + core_to_arm_mmu_idx(&cpu->env, mmu_idx), + &res, fi)) { res.f.extra.arm.pte_attrs = res.cacheattrs.attrs; res.f.extra.arm.shareability = res.cacheattrs.shareability; - - tlb_set_page_full(cs, mmu_idx, address, &res.f); + *out = res.f; return true; - } else if (probe) { - return false; - } else { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - arm_deliver_fault(cpu, address, access_type, mmu_idx, fi); } + if (probe) { + return false; + } + + /* Now we have a real cpu fault. */ + cpu_restore_state(cs, ra); + arm_deliver_fault(cpu, address, access_type, mmu_idx, fi); } #else void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, From patchwork Wed Oct 9 00:04:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 833827 Delivered-To: patch@linaro.org Received: by 2002:adf:a1d9:0:b0:367:895a:4699 with SMTP id v25csp556319wrv; Tue, 8 Oct 2024 17:07:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW2tNPoHfeMQnYPHbidhBYs/UtrW3r6jssP0GGKCagHPLNEREZw7DPb1Vz2jgqpAxQjWTrfHg==@linaro.org X-Google-Smtp-Source: AGHT+IGF+nPEybP1JCy4bT3FtUiO+vwns+L8gdAKtJv/ZLyvhWS6pvAgHHbck0XWPxPBQSQfZqfb X-Received: by 2002:a05:620a:17a3:b0:7af:c67c:9efe with SMTP id af79cd13be357-7b079541c7bmr100736685a.24.1728432462252; Tue, 08 Oct 2024 17:07:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728432462; cv=none; d=google.com; s=arc-20240605; b=Y6Oc2dEAzi3qN+OYvCAOwzOizpnYauA60yxxgCiFOOm+8PFZi+8eXKLGQn6JhQUB8c EF11ju2wqmNSfMajB9SCekbBUUQQVAcGFjDCryf6jqVEwB6ITQN/DCh5WC7y5TJQVJrT SSPLEEbWiBRvuSifX4WDPXdnKheR2aXK1QQvwb246uOGv2lQudNkB+Dx57UtF/xg85LU 36ujI8OZtS0NtpY0HRlbKzDkPxxe+tizgmkE56/iOtnWqokQeOG4wKZ99wrm0XQSyTBB 6ziQkhlczuZr85n/OSnUczKxiL1zJWLHAJSYBAkwH0AvifI7zi0nUkuyWEFYTUUk0Dy0 6Weg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=G2SEeBS4yBn5Ue1nQmA6MrWE5kNjL002NNNwwbKYNls=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=eTLM3VydJZt6QNW/e5LPQYNLULCTllo3jXFIfmnkdI9ejUAXzLR593lDUZEXcv96vs b02AZftoUlveJfZbFslNvFhcJITS6E08ZzOZ7/PsXvOwhZdJXG06jDL1ioNGZF8XfcAP bJlxyk+NGbORmBBvSHNqtGlUFO3bZY9r52i9TsFn3wkabz1ETCRNDHZDoCraOIPquOtN K9A+bsVZ2F3HM3EjtIYx9RO+tERtPZfsDfvqLXlT97njUuoI+o2f4gjbtysiV01iWrUy 2TivHj56YIHVItoKZqzmxT/ft65Do+cPMgdIyjiDHbwaDeSJizBN4HtzpMEWhoHORc6g Bwow==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nyHqqErl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH v3 20/20] target/arm: Fix alignment fault priority in get_phys_addr_lpae Date: Tue, 8 Oct 2024 17:04:53 -0700 Message-ID: <20241009000453.315652-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that we have the MemOp for the access, we can order the alignment fault caused by memory type before the permission fault for the page. For subsequent page hits, permission and stage 2 checks are known to pass, and so the TLB_CHECK_ALIGNED fault raised in generic code is not mis-ordered. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 51 ++++++++++++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0a1a820362..dd40268397 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2129,6 +2129,36 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, device = S1_attrs_are_device(result->cacheattrs.attrs); } + /* + * Enable alignment checks on Device memory. + * + * Per R_XCHFJ, the correct ordering for alignment, permission, + * and stage 2 faults is: + * - Alignment fault caused by the memory type + * - Permission fault + * - A stage 2 fault on the memory access + * Perform the alignment check now, so that we recognize it in + * the correct order. Set TLB_CHECK_ALIGNED so that any subsequent + * softmmu tlb hit will also check the alignment; clear along the + * non-device path so that tlb_fill_flags is consistent in the + * event of restart_atomic_update. + * + * In v7, for a CPU without the Virtualization Extensions this + * access is UNPREDICTABLE; we choose to make it take the alignment + * fault as is required for a v7VE CPU. (QEMU doesn't emulate any + * CPUs with ARM_FEATURE_LPAE but not ARM_FEATURE_V7VE anyway.) + */ + if (device) { + unsigned a_bits = memop_atomicity_bits(memop); + if (address & ((1 << a_bits) - 1)) { + fi->type = ARMFault_Alignment; + goto do_fault; + } + result->f.tlb_fill_flags = TLB_CHECK_ALIGNED; + } else { + result->f.tlb_fill_flags = 0; + } + if (!(result->f.prot & (1 << access_type))) { fi->type = ARMFault_Permission; goto do_fault; @@ -2156,27 +2186,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, result->f.attrs.space = out_space; result->f.attrs.secure = arm_space_is_secure(out_space); - /* - * Enable alignment checks on Device memory. - * - * Per R_XCHFJ, this check is mis-ordered. The correct ordering - * for alignment, permission, and stage 2 faults should be: - * - Alignment fault caused by the memory type - * - Permission fault - * - A stage 2 fault on the memory access - * but due to the way the TCG softmmu TLB operates, we will have - * implicitly done the permission check and the stage2 lookup in - * finding the TLB entry, so the alignment check cannot be done sooner. - * - * In v7, for a CPU without the Virtualization Extensions this - * access is UNPREDICTABLE; we choose to make it take the alignment - * fault as is required for a v7VE CPU. (QEMU doesn't emulate any - * CPUs with ARM_FEATURE_LPAE but not ARM_FEATURE_V7VE anyway.) - */ - if (device) { - result->f.tlb_fill_flags |= TLB_CHECK_ALIGNED; - } - /* * For FEAT_LPA2 and effective DS, the SH field in the attributes * was re-purposed for output address bits. The SH attribute in