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Sun, 20 Oct 2024 08:53:32 -0700 (PDT) X-Received: by 2002:adf:fd44:0:b0:37d:42ce:f3a5 with SMTP id ffacd0b85a97d-37ea213c624mr5061611f8f.12.1729439612098; Sun, 20 Oct 2024 08:53:32 -0700 (PDT) Received: from avogadro.local ([151.95.144.54]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a49180sm2007266f8f.39.2024.10.20.08.53.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 08:53:30 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org Subject: [PATCH 02/14] target/i386: Tidy cc_op_str usage Date: Sun, 20 Oct 2024 17:53:12 +0200 Message-ID: <20241020155324.35273-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241020155324.35273-1-pbonzini@redhat.com> References: <20241020155324.35273-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.527, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Make const. Use the read-only strings directly; do not copy them into an on-stack buffer with snprintf. Allow for holes in the cc_op_str array, now present with CC_OP_POPCNT. Fixes: 460231ad369 ("target/i386: give CC_OP_POPCNT low bits corresponding to MO_TL") Signed-off-by: Richard Henderson Link: https://lore.kernel.org/r/20240701025115.1265117-2-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini --- target/i386/cpu-dump.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c index 3bb8e440916..dc6723aedee 100644 --- a/target/i386/cpu-dump.c +++ b/target/i386/cpu-dump.c @@ -27,7 +27,7 @@ /***********************************************************/ /* x86 debug */ -static const char *cc_op_str[CC_OP_NB] = { +static const char * const cc_op_str[] = { [CC_OP_DYNAMIC] = "DYNAMIC", [CC_OP_EFLAGS] = "EFLAGS", @@ -347,7 +347,6 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; int eflags, i, nb; - char cc_op_name[32]; static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" }; eflags = cpu_compute_eflags(env); @@ -456,10 +455,16 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) env->dr[6], env->dr[7]); } if (flags & CPU_DUMP_CCOP) { - if ((unsigned)env->cc_op < CC_OP_NB) - snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]); - else - snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); + const char *cc_op_name = NULL; + char cc_op_buf[32]; + + if ((unsigned)env->cc_op < ARRAY_SIZE(cc_op_str)) { + cc_op_name = cc_op_str[env->cc_op]; + } + if (cc_op_name == NULL) { + snprintf(cc_op_buf, sizeof(cc_op_buf), "[%d]", env->cc_op); + cc_op_name = cc_op_buf; + } #ifdef TARGET_X86_64 if (env->hflags & HF_CS64_MASK) { qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%s\n", From patchwork Sun Oct 20 15:53:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 837185 Delivered-To: patch@linaro.org Received: by 2002:a5d:50c9:0:b0:37d:45d0:187 with SMTP id f9csp1658837wrt; Sun, 20 Oct 2024 08:56:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWxMtImwikxpYkMF7Nifv+7P5qUbYhX1QuoMDsngq3aoiiPmFjgkMJ0S2O/aWqjUk/wFP0Sdg==@linaro.org X-Google-Smtp-Source: AGHT+IFu8sgaMI1IhBpfPZvcBtNZCF31ny3g/pOADMailo9hnX2o9S4tgy4zwUVbadIVO+W++G1W X-Received: by 2002:a05:622a:1a20:b0:460:ac33:431c with SMTP id d75a77b69052e-460aede9828mr126675101cf.53.1729439805534; Sun, 20 Oct 2024 08:56:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729439805; cv=none; d=google.com; s=arc-20240605; b=Lf0S05DiSlEfDPFc6nVwNxmyFwn3l9B7RTR0p9f2zHByDwabYfq7iivytwZ7QbeNHn 7XN6M8xNrUN62yKN9ffjgIADZDafckVzhgDMd6YLZTrLid1HORp9Ub222kRHdko6O96n bFat8MfZeK/UV/Qh+RJTge69+UlPTxeetjHxtYKD69+8pp/X3UL6BQUkFaN0DlmLyTk2 A9PRKe4rJnHKiK2YLdFjD4S5KMbuHSsTE3m5FlsihhkaBW7hpZOGrNgLpk6+bMRZPIjY 12mbDGfFhXWFBUhiZnveZ6uB/zOSDMwOnMdlJ8DsAX3azQZgVBu0dao5WWSdm4QZjstI CMVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uPHb5ByYipPEkRTaBja/s+S6rotpUpBmTRUGPYsW6is=; fh=MmLbUYMFRk+lJjthCIVqr42l66o0jnBuoFM0CcrBzlo=; b=AzsEjDEoRJzEu82+AgwcGG14+z5TIqf5PoZcYnoVgKFmol7fcwRilM/qmX8Umw7fQW cRbRO0jKe7kTxidBtTCRzwrAxsLrzRQkhCyEUBP7S4MeVYINy6sisJ2rQORJA08W5Shy tpXFl4W/2TK6tj+ZTlvjhMuUWXTcXdg+NjWrChKvT6C2NYrxq1aqEOdKANTN2Y9+qPCL VFm0IIL6CtZwOQNyteqHujMff7PgevkaIptyuU1VwGup8O4ic5f3uC0T+I8pTuthtgHu +sZHqxXJMQi9lYLxqi0wgy8IaMkG4Crzlbb5BHYeSHlb4k8ZGbk65hZUP3085nMdFtrQ hIvw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=f10Z7w5g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This will be used to simplify ((op - CC_OP_*B) & 3). Signed-off-by: Richard Henderson Link: https://lore.kernel.org/r/20240701025115.1265117-4-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 567fefa1d7b..f292463c34a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1278,11 +1278,10 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); * are only needed for conditional branches. */ typedef enum { - CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ - CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ - CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ - CC_OP_ADOX, /* CC_SRC2 = O, CC_SRC = rest. */ - CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ + CC_OP_EFLAGS = 0, /* all cc are explicitly computed, CC_SRC = flags */ + CC_OP_ADCX = 1, /* CC_DST = C, CC_SRC = rest. */ + CC_OP_ADOX = 2, /* CC_SRC2 = O, CC_SRC = rest. */ + CC_OP_ADCOX = 3, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ CC_OP_MULW, @@ -1355,9 +1354,12 @@ typedef enum { CC_OP_POPCNTQ__, CC_OP_POPCNT = sizeof(target_ulong) == 8 ? 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Assert that the op has a size and that it is valid for the configuration. Signed-off-by: Richard Henderson Link: https://lore.kernel.org/r/20240701025115.1265117-6-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 17 ++++++++++++++++- target/i386/tcg/translate.c | 17 +++++++---------- target/i386/tcg/emit.c.inc | 5 +++-- 3 files changed, 26 insertions(+), 13 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f292463c34a..51a0a463c3e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -24,6 +24,7 @@ #include "cpu-qom.h" #include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" +#include "exec/memop.h" #include "hw/i386/topology.h" #include "qapi/qapi-types-common.h" #include "qemu/cpu-float.h" @@ -1283,7 +1284,9 @@ typedef enum { CC_OP_ADOX = 2, /* CC_SRC2 = O, CC_SRC = rest. */ CC_OP_ADCOX = 3, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ - CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ + /* Low 2 bits = MemOp constant for the size */ +#define CC_OP_FIRST_BWLQ CC_OP_MULB + CC_OP_MULB = 4, /* modify all flags, C, O = (CC_SRC != 0) */ CC_OP_MULW, CC_OP_MULL, CC_OP_MULQ, @@ -1353,6 +1356,7 @@ typedef enum { CC_OP_POPCNTL__, CC_OP_POPCNTQ__, CC_OP_POPCNT = sizeof(target_ulong) == 8 ? CC_OP_POPCNTQ__ : CC_OP_POPCNTL__, +#define CC_OP_LAST_BWLQ CC_OP_POPCNTQ__ CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ CC_OP_NB, @@ -1361,6 +1365,17 @@ typedef enum { /* See X86DecodedInsn.cc_op, using int8_t. */ QEMU_BUILD_BUG_ON(CC_OP_DYNAMIC > INT8_MAX); +static inline MemOp cc_op_size(CCOp op) +{ + MemOp size = op & 3; + + QEMU_BUILD_BUG_ON(CC_OP_FIRST_BWLQ & 3); + assert(op >= CC_OP_FIRST_BWLQ && op <= CC_OP_LAST_BWLQ); + assert(size <= MO_TL); + + return size; +} + typedef struct SegmentCache { uint32_t selector; target_ulong base; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a20fbb019c8..46062002c02 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -885,7 +885,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) case CC_OP_ADDB ... CC_OP_ADDQ: /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */ - size = s->cc_op - CC_OP_ADDB; + size = cc_op_size(s->cc_op); tcg_gen_ext_tl(cpu_cc_dst, cpu_cc_dst, size); tcg_gen_ext_tl(cpu_cc_src, cpu_cc_src, size); return (CCPrepare) { .cond = TCG_COND_LTU, .reg = cpu_cc_dst, @@ -902,7 +902,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) case CC_OP_SHLB ... CC_OP_SHLQ: /* (CC_SRC >> (DATA_BITS - 1)) & 1 */ - size = s->cc_op - CC_OP_SHLB; + size = cc_op_size(s->cc_op); return gen_prepare_sign_nz(cpu_cc_src, size); case CC_OP_MULB ... CC_OP_MULQ: @@ -910,11 +910,11 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) .reg = cpu_cc_src }; case CC_OP_BMILGB ... CC_OP_BMILGQ: - size = s->cc_op - CC_OP_BMILGB; + size = cc_op_size(s->cc_op); return gen_prepare_val_nz(cpu_cc_src, size, true); case CC_OP_BLSIB ... CC_OP_BLSIQ: - size = s->cc_op - CC_OP_BLSIB; + size = cc_op_size(s->cc_op); return gen_prepare_val_nz(cpu_cc_src, size, false); case CC_OP_ADCX: @@ -966,10 +966,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg) case CC_OP_POPCNT: return (CCPrepare) { .cond = TCG_COND_NEVER }; default: - { - MemOp size = (s->cc_op - CC_OP_ADDB) & 3; - return gen_prepare_sign_nz(cpu_cc_dst, size); - } + return gen_prepare_sign_nz(cpu_cc_dst, cc_op_size(s->cc_op)); } } @@ -1007,7 +1004,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) .imm = CC_Z }; default: { - MemOp size = (s->cc_op - CC_OP_ADDB) & 3; + MemOp size = cc_op_size(s->cc_op); return gen_prepare_val_nz(cpu_cc_dst, size, true); } } @@ -1028,7 +1025,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) switch (s->cc_op) { case CC_OP_SUBB ... CC_OP_SUBQ: /* We optimize relational operators for the cmp/jcc case. */ - size = s->cc_op - CC_OP_SUBB; + size = cc_op_size(s->cc_op); switch (jcc_op) { case JCC_BE: tcg_gen_ext_tl(s->cc_srcT, s->cc_srcT, size); diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 790307dbba8..45ac5edb1ae 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1466,7 +1466,7 @@ static void gen_bt_flags(DisasContext *s, X86DecodedInsn *decode, TCGv src, TCGv */ decode->cc_src = tcg_temp_new(); decode->cc_dst = cpu_cc_dst; - decode->cc_op = ((s->cc_op - CC_OP_MULB) & 3) + CC_OP_SARB; + decode->cc_op = CC_OP_SARB + cc_op_size(s->cc_op); tcg_gen_shr_tl(decode->cc_src, src, s->T1); } } @@ -3346,7 +3346,8 @@ static bool gen_eflags_adcox(DisasContext *s, X86DecodedInsn *decode, bool want_ * bit, we might as well fish CF out of EFLAGS and save a shift. */ if (want_carry && (!need_flags || s->cc_op == CC_OP_SHLB + MO_TL)) { - tcg_gen_shri_tl(decode->cc_dst, cpu_cc_src, (8 << (s->cc_op - CC_OP_SHLB)) - 1); + MemOp size = cc_op_size(s->cc_op); + tcg_gen_shri_tl(decode->cc_dst, cpu_cc_src, (8 << size) - 1); got_cf = true; } gen_mov_eflags(s, decode->cc_src); From patchwork Sun Oct 20 15:53:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 837183 Delivered-To: patch@linaro.org Received: by 2002:a5d:50c9:0:b0:37d:45d0:187 with SMTP id f9csp1658483wrt; Sun, 20 Oct 2024 08:55:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUBylP5TzlQY5vzezjwE0T80/QBce2ETp7HUdc+BtCq4oB90mv5Tvgy4Wh1y/dF+J8pB8a7Ig==@linaro.org X-Google-Smtp-Source: AGHT+IFWB7R7nzvvO94CTvQIQFMqef+BNc2WgPRCE0Xk8jEqxuJW6zbGiYBGSd9YFPlOSPsupn8+ X-Received: by 2002:a0c:f64e:0:b0:6cc:3fb:376a with SMTP id 6a1803df08f44-6cc379048b5mr159081566d6.25.1729439731922; Sun, 20 Oct 2024 08:55:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729439731; cv=none; d=google.com; s=arc-20240605; b=IhMAHlsxY0ZRJh7W3+HN0IjhbgVWrYGW6ItsljAr+aRbxobsr6MLgxl/WLyHtN5JkU YO2m9txFjiYV+jNhSwSnfoMfGc+TY+WDAQ3hkL/wn4JIU+nwy2PlGeyYlLSJ8iDZ11EJ SRvVwnAlawqpCv4pxzHVIPPGXyJTCaCNpDo7xjk/xDYBu+hinj/9Z/QpbCXnLrioXS6R R3iIFkSTGVdfYoEc0TJLoZkfjl0jPKRotSNbgtX/hmyHWik50C5u/ExF7prQRmoxkJlr UDsU1EVfnEegbs8NUTwwmYqEvRXFibmEitVa4lGloXXGGJ4a+lR0+zR5WWM4MD+m1ShB cVRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=q6Atrid02n+aIsNXR6t6jfxIFvTGj0hOmgcUWqfqLMk=; fh=MmLbUYMFRk+lJjthCIVqr42l66o0jnBuoFM0CcrBzlo=; b=Vezybz7eU98+YTwpXf8asSdhbpTzRzDaLcXLf/FAdhka7crues4TumAEgCebMAk1Ya CM3QjjJwq7Kipu8QW/HMm5vi/r60i80HFYsisxisFIr1abF6kwbizbJvi7BAkF8sfkBA 4RhvaJQU6uSKPphHnv1Ir6q20bxwQzbeBe7JJ/Y5jngGI8UgEC55/NDhdljyOPPpotVc VA/SQ0/D64Q5Di8RvzQjCnp2/j3WJ7VDd93P20j5oqil5tmt58GWW3dDL5r9HPjIQzXu u0ScQlkQ5wP1BnWtgXMlaFK1UxgviNig7GziAkWQjWtbsmw9yiZBIZfPLGnavCfEJeP+ kGLA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=R48dcR+z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/cpu.h | 1 - target/i386/tcg/translate.c | 21 ++++++++++++++++++--- target/i386/tcg/decode-new.c.inc | 2 +- target/i386/tcg/emit.c.inc | 4 ++-- 4 files changed, 21 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 51a0a463c3e..782e329c15c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1359,7 +1359,6 @@ typedef enum { #define CC_OP_LAST_BWLQ CC_OP_POPCNTQ__ CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ - CC_OP_NB, } CCOp; /* See X86DecodedInsn.cc_op, using int8_t. */ diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 46062002c02..1a9a2fe709e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -291,7 +291,7 @@ enum { }; /* Bit set if the global variable is live after setting CC_OP to X. */ -static const uint8_t cc_op_live[CC_OP_NB] = { +static const uint8_t cc_op_live_[] = { [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, [CC_OP_EFLAGS] = USES_CC_SRC, [CC_OP_MULB ... CC_OP_MULQ] = USES_CC_DST | USES_CC_SRC, @@ -312,6 +312,21 @@ static const uint8_t cc_op_live[CC_OP_NB] = { [CC_OP_POPCNT] = USES_CC_DST, }; +static uint8_t cc_op_live(CCOp op) +{ + uint8_t result; + assert(op >= 0 && op < ARRAY_SIZE(cc_op_live_)); + + /* + * Check that the array is fully populated. A zero entry would correspond + * to a fixed value of EFLAGS, which can be obtained with CC_OP_EFLAGS + * as well. + */ + result = cc_op_live_[op]; + assert(result); + return result; +} + static void set_cc_op_1(DisasContext *s, CCOp op, bool dirty) { int dead; @@ -321,7 +336,7 @@ static void set_cc_op_1(DisasContext *s, CCOp op, bool dirty) } /* Discard CC computation that will no longer be used. */ - dead = cc_op_live[s->cc_op] & ~cc_op_live[op]; + dead = cc_op_live(s->cc_op) & ~cc_op_live(op); if (dead & USES_CC_DST) { tcg_gen_discard_tl(cpu_cc_dst); } @@ -808,7 +823,7 @@ static void gen_mov_eflags(DisasContext *s, TCGv reg) src2 = cpu_cc_src2; /* Take care to not read values that are not live. */ - live = cc_op_live[s->cc_op] & ~USES_CC_SRCT; + live = cc_op_live(s->cc_op) & ~USES_CC_SRCT; dead = live ^ (USES_CC_DST | USES_CC_SRC | USES_CC_SRC2); if (dead) { TCGv zero = tcg_constant_tl(0); diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc index 1f193716468..ee2a508ae9a 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -2865,7 +2865,7 @@ static void disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_mov_i32(cpu_cc_op, decode.cc_op_dynamic); } set_cc_op(s, decode.cc_op); - cc_live = cc_op_live[decode.cc_op]; + cc_live = cc_op_live(decode.cc_op); } else { cc_live = 0; } diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 45ac5edb1ae..785ff63f2ac 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -3777,13 +3777,13 @@ static void gen_shift_dynamic_flags(DisasContext *s, X86DecodedInsn *decode, TCG decode->cc_op_dynamic = tcg_temp_new_i32(); assert(decode->cc_dst == s->T0); - if (cc_op_live[s->cc_op] & USES_CC_DST) { + if (cc_op_live(s->cc_op) & USES_CC_DST) { decode->cc_dst = tcg_temp_new(); tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_dst, count, tcg_constant_tl(0), cpu_cc_dst, s->T0); } - if (cc_op_live[s->cc_op] & USES_CC_SRC) { + if (cc_op_live(s->cc_op) & USES_CC_SRC) { tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_src, count, tcg_constant_tl(0), cpu_cc_src, decode->cc_src); }