From patchwork Wed Jun 21 09:00:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 106061 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp1830091qgd; Wed, 21 Jun 2017 02:24:05 -0700 (PDT) X-Received: by 10.84.199.170 with SMTP id r39mr40740632pld.204.1498037044921; Wed, 21 Jun 2017 02:24:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498037044; cv=none; d=google.com; s=arc-20160816; b=jH/1CgAtOolNLjuePkWPR3D6DqnoKJfe4dy50xPM9KwqnFYHEpKMyD2rRGeMxMNWf7 j5ZazuzjSXmu5poff6qisQOxZQPbch8NkAWlejf07rBTAtfAOyfES9SFQh3A8qHaf+Kr E0Pt5Jp9s2cQjPs0unYxus4kMjm2KyTJ0De2fCQaR1YRlFNDCOVI8+wEJLw4dDNDZJ2B PrTHY5ZA5aI/srLbSRHxfbJrFupB6MK9XiAOrj7bYGko+U+09C8OrGTYpxh3/wK3RPLQ UYHvFJLrsJUryMsPFOlwa+bkK1SB6fYmG6U4cbR3titrrXyAFudDkyUTZ3mwGfGp5OBq mwlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=V3mh3QWblrPmZKtimJQ1QPSb5AYnpZkEjc4Q97+5sX8=; b=y/WK6UPBq0RV/hTNE19RzSjdxiaexiPoJ5ZviqEshr9hnRljY1/Z4f8UClci8q/Jvt xptv0WooczVH0aGqlqRyVdOgQbaOgkNs+g5gxaDmA6MkkHeIg+MUqQj3eMhLUuMmlQt2 6VW9uzCpVeipNy7GZBCXfUvd1esjqwIHppgaeWpzboOQ3MqSz+n+y/OfgVk8u0AoKknf PzFpDMDDEbWVPb8BkztPG43nBbesutA+a8gaY/IUBIrGGZEntou6lhdAKuv7rk6ry1De Ik26JKK9Ci5kBOuQrAnBWVRcu+XrfsT0u9ZS0s3HSsx3Rp5dGfcZ1Zizmji7khRH53AQ dPOg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u25si13156235pgn.424.2017.06.21.02.24.04; Wed, 21 Jun 2017 02:24:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752881AbdFUJXy (ORCPT + 25 others); Wed, 21 Jun 2017 05:23:54 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:8371 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752377AbdFUJXS (ORCPT ); Wed, 21 Jun 2017 05:23:18 -0400 Received: from 172.30.72.53 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APT48849; Wed, 21 Jun 2017 17:23:11 +0800 (CST) Received: from wind-Tecal-RH2285.huawei.com (10.67.212.71) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Wed, 21 Jun 2017 17:23:00 +0800 From: Jiancheng Xue To: , , , , , CC: , , , , , , , Jiancheng Xue Subject: [PATCH 1/5] clk: hisilicon: add usb2 clocks for hi3798cv200 SoC Date: Wed, 21 Jun 2017 17:00:41 +0800 Message-ID: <1498035645-22804-2-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> References: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.594A3B00.0126, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d56f0dbec712dc452ac6a3af8b82d45d Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add usb2 clocks for hi3798cv200 SoC. Signed-off-by: Jiancheng Xue Reviewed-by: Daniel Thompson --- drivers/clk/hisilicon/crg-hi3798cv200.c | 21 +++++++++++++++++++++ include/dt-bindings/clock/histb-clock.h | 9 ++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index fc8b5bc..ed8bb5f 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -44,6 +44,9 @@ #define HI3798CV200_ETH_BUS0_CLK 78 #define HI3798CV200_ETH_BUS1_CLK 79 #define HI3798CV200_COMBPHY1_MUX 80 +#define HI3798CV200_FIXED_12M 81 +#define HI3798CV200_FIXED_48M 82 +#define HI3798CV200_FIXED_60M 83 #define HI3798CV200_CRG_NR_CLKS 128 @@ -51,9 +54,12 @@ { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, + { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, }, { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, }, { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, }, + { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, }, { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, }, + { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, }, { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, }, { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, }, { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, }, @@ -134,6 +140,21 @@ /* COMBPHY1 */ { HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux", CLK_SET_RATE_PARENT, 0x188, 8, 0, }, + /* USB2 */ + { HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb", + CLK_SET_RATE_PARENT, 0xb8, 0, 0, }, + { HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m", + CLK_SET_RATE_PARENT, 0xb8, 4, 0, }, + { HISTB_USB2_12M_CLK, "clk_u2_12m", "12m", + CLK_SET_RATE_PARENT, 0xb8, 2, 0 }, + { HISTB_USB2_48M_CLK, "clk_u2_48m", "48m", + CLK_SET_RATE_PARENT, 0xb8, 1, 0 }, + { HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m", + CLK_SET_RATE_PARENT, 0xb8, 5, 0 }, + { HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 0, 0 }, + { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 2, 0 }, }; static struct hisi_clock_data *hi3798cv200_clk_register( diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h index 181c0f0..067f5e5 100644 --- a/include/dt-bindings/clock/histb-clock.h +++ b/include/dt-bindings/clock/histb-clock.h @@ -53,7 +53,14 @@ #define HISTB_ETH1_MAC_CLK 31 #define HISTB_ETH1_MACIF_CLK 32 #define HISTB_COMBPHY1_CLK 33 - +#define HISTB_USB2_BUS_CLK 34 +#define HISTB_USB2_PHY_CLK 35 +#define HISTB_USB2_UTMI_CLK 36 +#define HISTB_USB2_12M_CLK 37 +#define HISTB_USB2_48M_CLK 38 +#define HISTB_USB2_OTG_UTMI_CLK 39 +#define HISTB_USB2_PHY1_REF_CLK 40 +#define HISTB_USB2_PHY2_REF_CLK 41 /* clocks provided by mcu CRG */ #define HISTB_MCE_CLK 1 From patchwork Wed Jun 21 09:00:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 106060 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp1829943qgd; Wed, 21 Jun 2017 02:23:36 -0700 (PDT) X-Received: by 10.98.56.6 with SMTP id f6mr35105568pfa.199.1498037016493; Wed, 21 Jun 2017 02:23:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498037016; cv=none; d=google.com; s=arc-20160816; b=e5/s7XynKd95GgLsSdh8Cl/3Ux2V/uyxEAXd2bbjOG0LMmMg8pqosTelTvTcFI831Z OBL3kGktPU0CMU2MFUWpmvum3x69UtHZ+t9asGkwkmmVz4g2Zfi4vOdeyp6xGB1K7DiV dmxCtOOIGx0o0A+3lzW17XbrQD+diGoqQ6j+MYQZlUb8HupabxxwtHY47+YV3TF8fpmF qAsjjRvMOWfEWvh5Pq9dxmOQ3S+TARor4pfh816nNS+F1WaVy9AXMMvwQF8lRflrg7k+ Kujr4e54zC7VMH/QIBY/d9ujGaeSBsdWm/1TZn/g6SZuG/SD4j3+UKeztMHbWhrsh2+J pdNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=rkA6VCjUTMVGdB68kt+zQWee75geFwESkQTHTidoXxE=; b=lZGJnnvKOjlJh4238TBLtydVEU8V7Sd4jfUWu3z1JODsUTpnNykPQxGz+8bDo10xSc CzENEhTNrPi3DlGjDHG5EHC8kkQEh5Q4lC0VPePTOKL1UUh5bb4X2tuB06YGcSuYFKoe hqqaBRY3atEVcPhXYGKRCJANvREx3pqS1to+rIwWV9XK7AentBP7OLUNL1sVXQVHT4km 3+G8oVnhUXwMpTJGD/ndpuTo8g32gbK6O6k7bSZ8qB/OqZdcffVeD/p7tyg0O11xTkzY WiirPwVjaOzKSj9edZxjnmVvQCWEHPqSUeUFI9Sjegoo4834BoyW3F4+ye1WVLT1dR0b aBDw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p75si12601954pfk.288.2017.06.21.02.23.36; Wed, 21 Jun 2017 02:23:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752851AbdFUJXY (ORCPT + 25 others); Wed, 21 Jun 2017 05:23:24 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:8806 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750927AbdFUJXS (ORCPT ); Wed, 21 Jun 2017 05:23:18 -0400 Received: from 172.30.72.53 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APT48851; Wed, 21 Jun 2017 17:23:12 +0800 (CST) Received: from wind-Tecal-RH2285.huawei.com (10.67.212.71) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Wed, 21 Jun 2017 17:23:02 +0800 From: Jiancheng Xue To: , , , , , CC: , , , , , , , Pengcheng Li , "Jiancheng Xue" Subject: [PATCH 3/5] phy: add inno-usb2-phy driver for hi3798cv200 SoC Date: Wed, 21 Jun 2017 17:00:43 +0800 Message-ID: <1498035645-22804-4-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> References: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.594A3B02.011B, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 29b54fa53f7f84e4d05f1ccc6881f1f8 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pengcheng Li Add inno-usb2-phy driver for hi3798cv200 SoC. Signed-off-by: Pengcheng Li Signed-off-by: Jiancheng Xue --- drivers/phy/Kconfig | 10 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-hisi-inno-usb2.c | 287 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 298 insertions(+) create mode 100644 drivers/phy/phy-hisi-inno-usb2.c -- 1.9.1 diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index afaf7b6..f86b9b7 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -225,6 +225,16 @@ config PHY_EXYNOS5250_SATA SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host port to accept one SATA device. +config PHY_HISI_INNO_USB2 + tristate "HiSilicon INNO USB2 PHY support" + depends on (ARCH_HISI) || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports + USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It supports one + USB host port to accept one USB device. + config PHY_HIX5HD2_SATA tristate "HIX5HD2 SATA PHY Driver" depends on ARCH_HIX5HD2 && OF && HAS_IOMEM diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index f8047b4..a275547 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o +obj-$(CONFIG_PHY_HISI_INNO_USB2) += phy-hisi-inno-usb2.o obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o diff --git a/drivers/phy/phy-hisi-inno-usb2.c b/drivers/phy/phy-hisi-inno-usb2.c new file mode 100644 index 0000000..582c500 --- /dev/null +++ b/drivers/phy/phy-hisi-inno-usb2.c @@ -0,0 +1,287 @@ +/* + * HiSilicon INNO USB2 PHY Driver. + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_PORTS 4 +#define REF_CLK_STABLE_TIME 100 /*unit:us*/ +#define UTMI_CLK_STABLE_TIME 200 /*unit:us*/ +#define UTMI_RST_COMPLETE_TIME 200 /*unit:us*/ +#define PORT_RST_COMPLETE_TIME 2 /*unit:ms*/ +#define TEST_RST_COMPLETE_TIME 100 /*unit:us*/ +#define POR_RST_COMPLETE_TIME 300 /*unit:us*/ + + +struct hisi_inno_phy_port { + struct clk *utmi_clk; + struct reset_control *port_rst; + struct reset_control *utmi_rst; +}; + +struct hisi_inno_phy_priv { + struct regmap *reg_peri; + struct clk *ref_clk; + struct reset_control *test_rst; + struct reset_control *por_rst; + const struct reg_sequence *reg_seq; + u32 reg_num; + struct hisi_inno_phy_port *ports; + u8 port_num; +}; + +#define HI3798CV200_PERI_USB0 0x120 +static const struct reg_sequence hi3798cv200_reg_seq[] = { + { HI3798CV200_PERI_USB0, 0x00a00604, }, + { HI3798CV200_PERI_USB0, 0x00e00604, }, + { HI3798CV200_PERI_USB0, 0x00a00604, 1000 }, +}; + +static int hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv) +{ + return regmap_multi_reg_write_bypassed(priv->reg_peri, + priv->reg_seq, priv->reg_num); +} + +static int hisi_inno_port_init(struct hisi_inno_phy_port *port) +{ + int ret; + + reset_control_deassert(port->port_rst); + msleep(PORT_RST_COMPLETE_TIME); + + ret = clk_prepare_enable(port->utmi_clk); + if (ret) + return ret; + udelay(UTMI_CLK_STABLE_TIME); + + reset_control_deassert(port->utmi_rst); + udelay(UTMI_RST_COMPLETE_TIME); + + return 0; +} + +static int hisi_inno_phy_init(struct phy *phy) +{ + struct hisi_inno_phy_priv *priv = phy_get_drvdata(phy); + int ret, port; + + ret = clk_prepare_enable(priv->ref_clk); + if (ret) + return ret; + udelay(REF_CLK_STABLE_TIME); + + if (priv->test_rst) { + reset_control_deassert(priv->test_rst); + udelay(TEST_RST_COMPLETE_TIME); + } + + reset_control_deassert(priv->por_rst); + udelay(POR_RST_COMPLETE_TIME); + + /* config phy clk and phy eye diagram */ + ret = hisi_inno_phy_setup(priv); + if (ret) + goto err_disable_ref_clk; + + for (port = 0; port < priv->port_num; port++) { + ret = hisi_inno_port_init(&priv->ports[port]); + if (ret) + goto err_disable_clks; + } + + return 0; + +err_disable_clks: + while (--port >= 0) + clk_disable_unprepare(priv->ports[port].utmi_clk); +err_disable_ref_clk: + clk_disable_unprepare(priv->ref_clk); + + return ret; +} + +static void hisi_inno_phy_disable(struct phy *phy) +{ + struct hisi_inno_phy_priv *priv = phy_get_drvdata(phy); + int i; + + for (i = 0; i < priv->port_num; i++) + clk_disable_unprepare(priv->ports[i].utmi_clk); + + clk_disable_unprepare(priv->ref_clk); +} + +static int hisi_inno_phy_of_get_ports(struct device *dev, + struct hisi_inno_phy_priv *priv) +{ + struct device_node *node = dev->of_node; + struct device_node *child; + int port = 0; + int ret; + + priv->port_num = of_get_child_count(node); + if (priv->port_num > MAX_PORTS) { + dev_err(dev, "too many ports : %d (max = %d)\n", + priv->port_num, MAX_PORTS); + return -EINVAL; + } + + priv->ports = devm_kcalloc(dev, priv->port_num, + sizeof(struct hisi_inno_phy_port), GFP_KERNEL); + if (!priv->ports) + return -ENOMEM; + + for_each_child_of_node(node, child) { + struct hisi_inno_phy_port *phy_port = &priv->ports[port]; + + phy_port->utmi_clk = devm_get_clk_from_child(dev, child, NULL); + if (IS_ERR(phy_port->utmi_clk)) { + ret = PTR_ERR(phy_port->utmi_clk); + goto fail; + } + + phy_port->port_rst = of_reset_control_get_exclusive(child, "port_rst"); + if (IS_ERR(phy_port->port_rst)) { + ret = PTR_ERR(phy_port->port_rst); + goto fail; + } + + phy_port->utmi_rst = of_reset_control_get_exclusive(child, "utmi_rst"); + if (IS_ERR(phy_port->utmi_rst)) { + ret = PTR_ERR(phy_port->utmi_rst); + reset_control_put(phy_port->port_rst); + goto fail; + } + port++; + } + + return 0; + +fail: + while (--port >= 0) { + struct hisi_inno_phy_port *phy_port = &priv->ports[port]; + + reset_control_put(phy_port->utmi_rst); + reset_control_put(phy_port->port_rst); + clk_put(phy_port->utmi_clk); + } + of_node_put(child); + + return ret; +} + +static int hisi_inno_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy *phy; + struct hisi_inno_phy_priv *priv; + struct device_node *node = dev->of_node; + int ret = 0; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + if (of_device_is_compatible(node, "hisilicon,hi3798cv200-usb2-phy")) { + priv->reg_seq = hi3798cv200_reg_seq; + priv->reg_num = sizeof(hi3798cv200_reg_seq) + / sizeof(struct reg_sequence); + } + + priv->reg_peri = syscon_regmap_lookup_by_phandle(node, + "hisilicon,peripheral-syscon"); + if (IS_ERR(priv->reg_peri)) { + dev_err(dev, "no hisilicon,peripheral-syscon\n"); + return PTR_ERR(priv->reg_peri); + } + + priv->ref_clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->ref_clk)) + return PTR_ERR(priv->ref_clk); + + priv->por_rst = devm_reset_control_get_exclusive(dev, "por_rst"); + if (IS_ERR(priv->por_rst)) + return PTR_ERR(priv->por_rst); + + priv->test_rst = devm_reset_control_get_optional_exclusive(dev, "test_rst"); + if (IS_ERR(priv->test_rst)) + return PTR_ERR(priv->test_rst); + + ret = hisi_inno_phy_of_get_ports(dev, priv); + if (ret) + return ret; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + platform_set_drvdata(pdev, phy); + phy_set_drvdata(phy, priv); + + return hisi_inno_phy_init(phy); +} + +#ifdef CONFIG_PM_SLEEP +static int hisi_inno_phy_suspend(struct device *dev) +{ + struct phy *phy = dev_get_drvdata(dev); + + hisi_inno_phy_disable(phy); + + return 0; +} + +static int hisi_inno_phy_resume(struct device *dev) +{ + struct phy *phy = dev_get_drvdata(dev); + + return hisi_inno_phy_init(phy); +} +#endif /* CONFIG_PM_SLEEP */ + +static const struct dev_pm_ops hisi_inno_phy_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(hisi_inno_phy_suspend, hisi_inno_phy_resume) +}; + +static const struct of_device_id hisi_inno_phy_of_match[] = { + {.compatible = "hisilicon,inno-usb2-phy",}, + {.compatible = "hisilicon,hi3798cv200-usb2-phy",}, + { }, +}; +MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match); + +static struct platform_driver hisi_inno_phy_driver = { + .probe = hisi_inno_phy_probe, + .driver = { + .name = "hisi-inno-phy", + .of_match_table = hisi_inno_phy_of_match, + .pm = &hisi_inno_phy_pm_ops, + } +}; +module_platform_driver(hisi_inno_phy_driver); + +MODULE_DESCRIPTION("HiSilicon INNO USB2 PHY Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Jun 21 09:00:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 106064 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp1830291qgd; Wed, 21 Jun 2017 02:24:42 -0700 (PDT) X-Received: by 10.84.128.67 with SMTP id 61mr41886145pla.246.1498037082071; Wed, 21 Jun 2017 02:24:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498037082; cv=none; d=google.com; s=arc-20160816; b=qUslGkGLfzwPcoWMz91lTH52FRiEDRgzb0NCFay2S5rfCuder6T1jbXzU7wSbRGBp7 eWLVzRmC0q8CBHbY7L+3CQGAGxC3/EtFU+QEBvbyExBW7oTvSvVh2CFKdXVhzTDQrgd2 yI6dCOH7CStlKs0uhB3FHJBHbCP3os2jOmp5y9BrnnImZtQfogjkajplswuZgyvaYH/s qGme3Mjd0Gmu8fAGLlII0racLJyYtMezRoFSAbJO/LEt+FKEhNqTs/VYwz8EU6rt7nYW 3rV/6I2YUcE/g0uRBhXdJOXHTg0hO5CW4o9eBIsurRQXs+TkBbz9AUAZITJ/QDhHR8pI cz2A== ARC-Message-Signature: i=1; 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Date: Wed, 21 Jun 2017 17:00:44 +0800 Message-ID: <1498035645-22804-5-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> References: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.594A3B00.0040, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a1b927784408f8bdcf589bb9b6dd1127 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add usb2 controller and phy nodes for poplar board. Signed-off-by: Jiancheng Xue Reviewed-by: Daniel Thompson --- .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 13 ++++++ arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 47 ++++++++++++++++++++++ 2 files changed, 60 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index 684fa09..40db803 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -64,6 +64,10 @@ }; }; +&ehci { + status = "okay"; +}; + &gmac1 { status = "okay"; #address-cells = <1>; @@ -147,6 +151,10 @@ status = "okay"; }; +&ohci { + status = "okay"; +}; + &spi0 { status = "okay"; label = "LS-SPI0"; @@ -161,3 +169,8 @@ label = "LS-UART0"; }; /* No optional LS-UART1 on Low Speed Expansion Connector. */ + +&usb2_phy1 { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 75865f8a..422aeaf 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -106,6 +106,11 @@ #reset-cells = <2>; }; + peri_ctrl: system-controller@8a20000 { + compatible = "syscon"; + reg = <0x8a20000 0x1000>; + }; + uart0: serial@8b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; @@ -407,5 +412,47 @@ clocks = <&sysctrl HISTB_IR_CLK>; status = "disabled"; }; + + ehci: ehci@0x9890000 { + compatible = "generic-ehci"; + reg = <0x9890000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_PHY_CLK>; + clock-names = "ehci_system", "phy"; + resets = <&crg 0xb8 12>, + <&crg 0xb8 16>; + reset-names = "bus", "phy"; + status = "disabled"; + }; + + ohci: ohci@0x9880000 { + compatible = "generic-ohci"; + reg = <0x9880000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_12M_CLK>, + <&crg HISTB_USB2_48M_CLK>; + clock-names = "ahb_biu", "clk12", "clk48"; + resets = <&crg 0xb8 12>; + reset-names = "bus"; + status = "disabled"; + }; + + usb2_phy1: usb-phy@1 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + #phy-cells = <0>; + hisilicon,peripheral-syscon = <&peri_ctrl>; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + resets = <&crg 0xbc 4>; + reset-names = "por_rst"; + status = "disabled"; + + usb2_port1: port@1 { + clocks = <&crg HISTB_USB2_UTMI_CLK>; + resets = <&crg 0xbc 9>, <&crg 0xb8 13>; + reset-names = "port_rst", "utmi_rst"; + }; + }; }; }; From patchwork Wed Jun 21 09:00:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 106063 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp1830192qgd; Wed, 21 Jun 2017 02:24:23 -0700 (PDT) X-Received: by 10.99.174.67 with SMTP id e3mr35593261pgp.119.1498037063290; Wed, 21 Jun 2017 02:24:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498037063; cv=none; d=google.com; s=arc-20160816; b=Z1ZgDojm7Eguq8sKkE13Ek4My1jZnoPyIWkynqYdXmVVvBqIrzOTvmVwJoWk/kjHxm 92/BhlnOw2JvRwVON9pTVYdMdRewtHUMpAWZADdnwmqUwxjxVyrsm2I1H64eAF5kGmMS xKflBvqTwhpa3InUG4ceVPej8sv6QC0Ux9hHhhd0NGhPBjByfCgU7z/FIiIfDsvwUEKm kTuQJAb8x0EXl2mE4VZaPz16c7qCDNgyQuFMWFOv9UeC71jfHbYaDHF9mayP0+V+xb/a lC+4SCN7DPKf8aOa0/YwPU30acUIicXPSsksbzSNms+ax+OMJ6vVG6oAe46Pz4/r4rN2 YDvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=TGVUnESLIxAkxLws1rMUNbKmSPLrFbUbjcCH5aK+DJ4=; b=KWrfGSOmSEEXDi84xkBZG1tR4t/+YCcGSRQ7ksj5CWJGA9eWkOqA7bh/4vj1eUPldp sYfd7HmV8UfrjuYECdfuuGq+VBlZUhf45naiuCiOS0VISqmAaPSnvuw653WB8DusMpRw lAUZdHVJv1E9+3ipdWCQjmz1rpkjeYlKm2iQi+f9vjrkKVAqNf6UYKQTKha5EuP6BQ8x ftWUA/e+f4XQlM4cpMHGrMMdkVo/RAsJzus2BDiRITLdwveUplTUaVBbovLnVbXXccrL N9DoeqBTwn2bXCb8o0APiqGKEZ/ek0ciQ3OXdeYvxqLCF3on36/jdgA79bRN30vAORzW lJCg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a3si14247552pld.500.2017.06.21.02.24.23; Wed, 21 Jun 2017 02:24:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752861AbdFUJXx (ORCPT + 25 others); Wed, 21 Jun 2017 05:23:53 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:8807 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752403AbdFUJXS (ORCPT ); Wed, 21 Jun 2017 05:23:18 -0400 Received: from 172.30.72.53 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APT48854; Wed, 21 Jun 2017 17:23:12 +0800 (CST) Received: from wind-Tecal-RH2285.huawei.com (10.67.212.71) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Wed, 21 Jun 2017 17:23:03 +0800 From: Jiancheng Xue To: , , , , , CC: , , , , , , , Jiancheng Xue Subject: [PATCH 5/5] arm64: defconfig: enable some drivers and configs for hi3798cv200-poplar board. Date: Wed, 21 Jun 2017 17:00:45 +0800 Message-ID: <1498035645-22804-6-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> References: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.594A3B03.00C4, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: e9842f9971373bb75e0c8bb2641925b5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable GMAC,I2C,IR,USB2-PHY for hi3798cv200-poplar board. Signed-off-by: Jiancheng Xue --- arch/arm64/configs/defconfig | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 97c123e..b45d760 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -31,6 +31,8 @@ CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_CMDLINE_PARTITION=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_ALPINE=y CONFIG_ARCH_BCM2835=y @@ -179,6 +181,7 @@ CONFIG_VIRTIO_NET=y CONFIG_AMD_XGBE=y CONFIG_NET_XGENE=y CONFIG_MACB=y +CONFIG_HIX5HD2_GMAC=y CONFIG_HNS_DSAF=y CONFIG_HNS_ENET=y CONFIG_E1000E=y @@ -259,6 +262,7 @@ CONFIG_I2C_TEGRA=y CONFIG_I2C_UNIPHIER_F=y CONFIG_I2C_RCAR=y CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_I2C_HIX5HD2=y CONFIG_SPI=y CONFIG_SPI_BCM2835=m CONFIG_SPI_BCM2835AUX=m @@ -277,6 +281,7 @@ CONFIG_PINCTRL_MSM8994=y CONFIG_PINCTRL_MSM8996=y CONFIG_PINCTRL_QDF2XXX=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_GPIO_SYSFS=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y @@ -322,7 +327,7 @@ CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_S2MPS11=y -CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y @@ -359,6 +364,10 @@ CONFIG_BACKLIGHT_GENERIC=m CONFIG_BACKLIGHT_LP855X=m CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y +CONFIG_MEDIA_RC_SUPPORT=y +CONFIG_RC_DEVICES=y +CONFIG_IR_HIX5HD2=y +CONFIG_LIRC=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_SOUND=y @@ -488,7 +497,9 @@ CONFIG_PWM_MESON=m CONFIG_PWM_ROCKCHIP=y CONFIG_PWM_SAMSUNG=y CONFIG_PWM_TEGRA=m +CONFIG_TI_SYSCON_RESET=y CONFIG_PHY_RCAR_GEN3_USB2=y +CONFIG_PHY_HISI_INNO_USB2=y CONFIG_PHY_HI6220_USB=y CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y