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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c113e687sm16288378f8f.84.2024.11.05.05.05.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:05:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 03/19] hw/microblaze/s3adsp1800: Explicit CPU endianness Date: Tue, 5 Nov 2024 14:04:15 +0100 Message-ID: <20241105130431.22564-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org By default the machine's CPU endianness is 'big' order ('little-endian' property set to %false). This corresponds to the default when this machine was added; see commits 6a8b1ae2020 "microblaze: Add petalogix s3a1800dsp MMU linux ref-design." and 72b675caacf "microblaze: Hook into the build-system." which added: [ "$target_cpu" = "microblaze" ] && target_bigendian=yes Later commit 877fdc12b1a ("microblaze: Allow targeting little-endian mb") added little-endian support, forgetting to set the CPU endianness to little-endian. Not an issue since this property was never used, but we will use it soon, so explicit the endianness to get the expected behavior. Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index dad46bd7f98..37e9a05a62a 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -71,6 +71,8 @@ petalogix_s3adsp1800_init(MachineState *machine) cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort); + object_property_set_bool(OBJECT(cpu), "little-endian", + !TARGET_BIG_ENDIAN, &error_abort); qdev_realize(DEVICE(cpu), NULL, &error_abort); /* Attach emulated BRAM through the LMB. */ From patchwork Tue Nov 5 13:04:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840796 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp328447wry; Tue, 5 Nov 2024 05:05:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVNQmWbPm33HtONE4nXj5G0zXZaVRdMR/Ve1Nha2GFiKLXT2GKXv6fj8LTDrg2XjzgtqrpiDQ==@linaro.org X-Google-Smtp-Source: AGHT+IEDn5ZN/kwZHS3rVB1LAcPzkHVBjWec93x8EagXoY3BLcrJkyvQWGEtAdgU89Ubzlj//Ye6 X-Received: by 2002:a05:620a:370c:b0:7b1:1313:1246 with SMTP id af79cd13be357-7b2fb96ab78mr1985875585a.24.1730811947450; Tue, 05 Nov 2024 05:05:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730811947; cv=none; d=google.com; s=arc-20240605; b=X8qYJX28/UUo//Te8VJ2q3KN0kMpst3JAnnz04SFTsaQhHfY96y2fAMBm8DWzz0fMT UJMiL6YwX7Kq4wvlZ76+XtiPqTAjvzLheGtldGPpAxwpY1ZgzVJ4m3zFyKqh3ywpo0HY 2rfkGljp7tDqqJab8/2N/s4dgWDPgGIMLvMgxRGrCZXzoFEvd7rdaJWX0eVZt7oTygj5 8c6Gz08YU5r2Ug5W6PwHKy7QNXG90WLGsxxWZlHdsqCn2NZQpJsxYmuliAKWrn5foGnC CtyCRz7bt/1zuSKPi4ZD9H6DyjFtyIFjd5NVAKtY0OIFDFJT7U1FZSNdl2QdhFvVq55D tHGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FTPJzGm6ARvkieLOl7sA7FxSacHjsJ3U8wjcC2hw8sY=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=bpOjJfE9a/i8Ctbhl5i9ziAkO7MSh5s/cLswi5+hWxG+uAgMgOS+FIYD21AX8kuQ9i 3Mj6kKP2+/lzImDTOavt+l+HtyGWA2P1Y/BqJpNzGBbTSCIdcbeHQ1ln6aHAiBqln6NR i6VgrjVJc0FxR1K5Xie/rxh01R7aDRywBiBTUn2SUjPbYKnKzN6y4zT0RnaDMI21DYwx MZgOc9l2f2VOBHMYeFvySbW+13F8ycOU7scyRp3wT7TornZS0NXpab287N+jssNABOhd M6gmI+rgU/yi0O8fePryYIvJfHGAL9PvoNa0KGYAgyg1fG7zJdiIy9EVnVDkIOS5iaT2 Mo9Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OI0zRu5W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd9a99d3sm219571055e9.38.2024.11.05.05.05.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:05:16 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 04/19] hw/microblaze/s3adsp1800: Rename unimplemented MMIO region as xps_gpio Date: Tue, 5 Nov 2024 14:04:16 +0100 Message-ID: <20241105130431.22564-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The machine datasheet mentions the GPIO device as 'xps_gpio'. Rename it accordingly to easily find its documentation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 37e9a05a62a..581b0411e29 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -124,7 +124,7 @@ petalogix_s3adsp1800_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); - create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000); + create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000); microblaze_load_kernel(cpu, ddr_base, ram_size, machine->initrd_filename, From patchwork Tue Nov 5 13:04:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840795 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp328448wry; Tue, 5 Nov 2024 05:05:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVKqi72K2nrWSowBNYj3oCLrVSZJDAHk5QmLEMAR/vc5eb2cw0cf2Vm8M0lapNPtNt9ydPFjQ==@linaro.org X-Google-Smtp-Source: AGHT+IE7wlER06KbPa6XZOSJEQd+KJS2f9ko/N7+vdhDGrOUTyJru41RhcmMWP8aH0VolKBEN2/G X-Received: by 2002:a05:620a:284a:b0:7ac:abb0:2317 with SMTP id af79cd13be357-7b2f24ef3eemr2759519385a.37.1730811947526; Tue, 05 Nov 2024 05:05:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730811947; cv=none; d=google.com; s=arc-20240605; b=kde2xy35RguSqnlmjY7Yu//12HhtbUUSdC93RujD2nhvKkXoYTLMI4iNHsOc3sYoqk qwDMihyAxwkgYUzYpd/eyYZb4PDreSnDKApj0IcOrJO+HAICKG1YX2ZhYtvi4iYG7ccH 5eo3L6b7wBAGvs6m/V2CR1z7lAk+1kUvwb1WGpB/P0OpLdgbBwamf+VNXpvw+fxT6j9I 83l3IA9JYphyra9RxW67lqJsiZtEh8WbWHSLNxt59LeG8DaIMTgAnukstPbSq+I/Sw4t bwWITfIWIt4w43rtnqvsLRRFWJ34sBaST5OzNIRuWS9sv2BitWbYUfEv+Se+d1gzg3rl GWkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mc9pl0ol0oGGc5F+E40Idu3stjpto+GEuMxBJrUIFDk=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=GpRktWMMYJhj1QcWOxOhtp61AZNzdv4EIsa/aX2ALAEBfX4uaDlxlNeJps1kc2Oq58 /CSgZj+NKkIbpZcYqQjAyArgfhDp6KP3/lWF4HLorcyXrQ9m9RzPB/N48XXFmdhRdQQq hP4azNDFGNZ05MkfGOiPH4A4uKgdIY7+10MvxBm0gO3X6ggCeICXLUq5wfT7R5jzrHkN uMvEhy/MnufeGrbP2OL5TvrpOk8XuGXTIM9FxrW0dx89sKUWU3vw7pE/L9BaC7zEdQ94 2kLUimRRIe/Sre3U2R9YigP5fqHeRNZeKk0MDIDQjmYX40455/BqbLNkzOFAsu8lC331 beXQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZXUPKuH2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c116abdasm16358789f8f.97.2024.11.05.05.05.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:05:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 05/19] hw/microblaze/s3adsp1800: Declare machine type using DEFINE_TYPES macro Date: Tue, 5 Nov 2024 14:04:17 +0100 Message-ID: <20241105130431.22564-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace DEFINE_MACHINE() by DEFINE_TYPES(), converting the class_init() handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 581b0411e29..6c0f5c6c651 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -55,6 +55,9 @@ #define ETHLITE_IRQ 1 #define UARTLITE_IRQ 3 +#define TYPE_PETALOGIX_S3ADSP1800_MACHINE \ + MACHINE_TYPE_NAME("petalogix-s3adsp1800") + static void petalogix_s3adsp1800_init(MachineState *machine) { @@ -132,11 +135,21 @@ petalogix_s3adsp1800_init(MachineState *machine) NULL); } -static void petalogix_s3adsp1800_machine_init(MachineClass *mc) +static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800"; mc->init = petalogix_s3adsp1800_init; mc->is_default = true; } -DEFINE_MACHINE("petalogix-s3adsp1800", petalogix_s3adsp1800_machine_init) +static const TypeInfo petalogix_s3adsp1800_machine_types[] = { + { + .name = TYPE_PETALOGIX_S3ADSP1800_MACHINE, + .parent = TYPE_MACHINE, + .class_init = petalogix_s3adsp1800_machine_class_init, + }, +}; + +DEFINE_TYPES(petalogix_s3adsp1800_machine_types) From patchwork Tue Nov 5 13:04:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840798 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp328723wry; Tue, 5 Nov 2024 05:06:17 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV7mbqZ3L7BTLzOA056G4NbSzLpDEQlhx6ZMFHdbX7kIy96uKwWW5qzo4jzeM7h5zb+YNDPZg==@linaro.org X-Google-Smtp-Source: AGHT+IEVtzCNaJ3CJm921FuExMy+jTBNqhCu6HDKsr9V+vFzB2wvYHuwC9n14zKYcWhskX/5FKU6 X-Received: by 2002:ad4:5443:0:b0:6d3:413c:745b with SMTP id 6a1803df08f44-6d351b2084dmr235185066d6.34.1730811977270; Tue, 05 Nov 2024 05:06:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730811977; cv=none; d=google.com; s=arc-20240605; b=SHVithHuN6bOj0cUQV3BjFxGLzK4yry/CSBhNn4i493t6m3ayv++8IT8Bv3sux9peT 5a0DWF85DTep05DaCBYRBi5yJ3hzu5OyA/p004ey3fZKXGXqbGlmzpsvrVry+IfwYBNm i3d9wIm4oyvmREy8WzYhLaxIwJkRUztGV1q9fTDwifAU/vTyfaqG5H1F8zMqSt43Xtvj ZkCPMZe1C50XeO8TjfTvXvlbbMc1uzxt9TCyyevTttePipbqhGG1dgZKxR12E47z5tn4 jercSl8hbbR4TcS16koi97ux915zXE1Nev9pUSmZd6ty/YVZHIDvAm0U6SLwmSR1RSBA 29sQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qAZ8YzntwrQh/mqW41UtJKIzn7e3ZbFGPYghnfpczwc=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=SQ8P15jGKhsLj8N9llYFi3EC7m9nJXrM4n+v7EnbuKJ3mrgDZDPM1oQvo4ahpn+1xF 1U2XlBhMVNTUBLFV4e6IHGi0PmGz7xkgMiaYq37cIG2QzqCpd0ZhytIBvoAlpuSOaibz Cs522Iqea/kHaEDcvSbg0BaB+QcCAoAJ6SPuwcSPlbPoj1tf2SJfoiIaxpvK+9m2e4Lm 6550VdDH7rlhqUnaq8sALLdSpCCn5/H11kiFEE1Bd39DFY8p0xDESpBq+FoVs+XRPccj sJmS7JJl5TPAQ4FVoC4/8Pv4W/ssbgwXrSzg7LaUU1uvnWdGfVtY5UyeLzXcO35S/Tn+ hNzQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="e3/WIxrZ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd8e848csm222180125e9.3.2024.11.05.05.05.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:05:35 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 06/19] hw/microblaze: Fix MemoryRegionOps coding style Date: Tue, 5 Nov 2024 14:04:18 +0100 Message-ID: <20241105130431.22564-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fix few MemoryRegionOps style before adding new fields in the following commits. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- hw/char/xilinx_uartlite.c | 4 ++-- hw/intc/xilinx_intc.c | 4 ++-- hw/net/xilinx_ethlite.c | 4 ++-- hw/timer/xilinx_timer.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index f325084f8b9..a69ad769cc4 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -172,8 +172,8 @@ static const MemoryRegionOps uart_ops = { .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 1, - .max_access_size = 4 - } + .max_access_size = 4, + }, }; static Property xilinx_uartlite_properties[] = { diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 6e5012e66eb..2b8246f6206 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -146,8 +146,8 @@ static const MemoryRegionOps pic_ops = { .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 4, - .max_access_size = 4 - } + .max_access_size = 4, + }, }; static void irq_handler(void *opaque, int irq, int level) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index bd812908085..11eb53c4d60 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -172,8 +172,8 @@ static const MemoryRegionOps eth_ops = { .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 4, - .max_access_size = 4 - } + .max_access_size = 4, + }, }; static bool eth_can_rx(NetClientState *nc) diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 32a9df69e0b..0822345779c 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -195,8 +195,8 @@ static const MemoryRegionOps timer_ops = { .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 4, - .max_access_size = 4 - } + .max_access_size = 4, + }, }; static void timer_hit(void *opaque) From patchwork Tue Nov 5 13:04:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840797 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp328692wry; Tue, 5 Nov 2024 05:06:14 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUtwbT09+Xqt7yjtP7ht4Cz/LPWqPA43P33aYPrXFyVFKXTQeIuPZAKW+Pl46j7bn9TvA5g4w==@linaro.org X-Google-Smtp-Source: AGHT+IEHNAZ5dtVaspIwjpPPTeQCrThicc7J51poeycg8S43w++hECEvVGJ06y4C7L7U7XndYecy X-Received: by 2002:a05:6214:2f84:b0:6cc:2cd6:24 with SMTP id 6a1803df08f44-6d35c199932mr208327126d6.36.1730811973745; Tue, 05 Nov 2024 05:06:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730811973; cv=none; d=google.com; s=arc-20240605; b=fzcpNNnk+gSW2padZBXhp5RADSNP+DoEmHIvvKTJkQsgpVFVH4AUposC95d20LT3lL pqMEFIWkI7oCqZheggjJfn1PhBet4dup1MS3McAXo0kRKox3uLrTZqX6Dx22G7rbvYDY qofmbWaANslMJ9xtCAQGPrPyih4LmtEfybzm1OIK7smuEXOHq89oksV76tt9+F7ihZLV 14q8cNhnruwxn/YgjMjOVeEwCjOOPFpsYJ2LNcuSYP+2Tn4xS8GV0zbEwbUMoSExFF4s s4vsFkd2v8WZKEbr7YoliMideWkQvv0ZmqqckeNZ59yoG02IWLHcozMg9Zdw3fDSK0mX WZcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UmQHqWTaQOMkWHXP0Jn/QpgcUfCH1B37UiHSpX6N2KA=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=kE7tFmkeKQb1z/4x/jFmuFhLTeI8e6hFtGGUFdIGnkIX6VCKExZP2nh/WSikA0YZkw 2Ni64vwkvkaVAzgy57vKIDtxpFqJ2IY7A/TXQPkuQDE+hOVslZjoZNsaenXZVewwLD+z 3XDHR/pIZkVWAvSzL5qW81py2YFNk/wnMgeHj82nNb3+CDPKT6R+syjjNnmb7+z3VVT5 UAJy+wJxFELhT/Cs8Rmc3J/INpei/DPwEuQmeDpPI82AtM3FYjmvzAqFGJpLF6KGzHL6 HR504yJqzyLye+lHKH85s7uY2Lw3S+aoTvu6zVxhQa9ONTbrdHxSZSqBX9AZ07tth+Xi uPzQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s5HPSlAw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c113e528sm16313895f8f.78.2024.11.05.05.05.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:05:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 07/19] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Date: Tue, 5 Nov 2024 14:04:19 +0100 Message-ID: <20241105130431.22564-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=philmd@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All these MemoryRegionOps read() and write() handlers are implemented expecting 32-bit accesses. Clarify that setting .impl.min/max_access_size fields. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- hw/char/xilinx_uartlite.c | 4 ++++ hw/intc/xilinx_intc.c | 4 ++++ hw/net/xilinx_ethlite.c | 4 ++++ hw/timer/xilinx_timer.c | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index a69ad769cc4..892efe81fee 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -170,6 +170,10 @@ static const MemoryRegionOps uart_ops = { .read = uart_read, .write = uart_write, .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 1, .max_access_size = 4, diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 2b8246f6206..1762b34564e 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -144,6 +144,10 @@ static const MemoryRegionOps pic_ops = { .read = pic_read, .write = pic_write, .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 4, .max_access_size = 4, diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 11eb53c4d60..ede7c172748 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -170,6 +170,10 @@ static const MemoryRegionOps eth_ops = { .read = eth_read, .write = eth_write, .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 4, .max_access_size = 4, diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 0822345779c..28ac95edea1 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -193,6 +193,10 @@ static const MemoryRegionOps timer_ops = { .read = timer_read, .write = timer_write, .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 4, .max_access_size = 4, From patchwork Tue Nov 5 13:04:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840801 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp329305wry; Tue, 5 Nov 2024 05:07:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVyAEqStRnB0A0wBVo9++Cd9jk6JOT2lE6r4Oxn+GNzZ2PzMlyzrYUp/JPWRCv+UmyYZ482TQ==@linaro.org X-Google-Smtp-Source: AGHT+IGdnMXn0/E0puwVBVDSr0D54LkBD0ACalN7mKgzLqM7HLxAMtrru9iKOOWTLSMs7A3ILaG6 X-Received: by 2002:a05:622a:3cf:b0:460:8fd3:b393 with SMTP id d75a77b69052e-462b869d7f8mr255376001cf.28.1730812035798; Tue, 05 Nov 2024 05:07:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730812035; cv=none; d=google.com; s=arc-20240605; b=ac6eX4GDt2bi6IBGkE8FKs9HiANCJzZgePdsDqyQHSUNhccUi+rWAeGpTcY8wgiqjm Qkm5W0cGLXCpAyevSqC4ilmMEMhBv2J1hmWs8I7kZFrE341lu+273SWTIrYBbgUBZNat oq2oA39mrQDQVti3Mp4NxpebGqO/y0hRaWlDcs7Sb7SoOMf3tj0h8t1NEYRvWw1LFuuv RJwBcVMj7YqqxyXHfezuSJ60CkUXzdQmgmKALimSFsvIvYM17hk6VFaxCx43CUU6iM4C uK9nDXp34I0B7mZLzpSlYBMTTz6u413OuYAhZuwrKLK55nKnjB4OavuaBSPHfoL+waXt 6WSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=owZyMcyuMkQxG2xNbQN7m9vwX8uFO4GAfwfRH2jZDis=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=XOcUS4MBmY9wLl7tw3pbIXf0G8by/jswXuLoUAbd28r5ArH/fLodU1hh0AaTJ6lnFG n3lWH1iYDfuru76hgS3VQ0jaNfm6jom8akXWQvEm2dEAl01JLGByIMAmUygt+pnTC2GC 3HyYaISOP4krJ4OthiFYOOfI7MyOwXCBLeJBUlX41V7xPBekKCH0+OTpPjT4jjEDrEzH sUq6BkYpuDTfpcnAoqMWyMnTLKPIUMC+DSDpswDkcTg86xTw/NpU4oFyfbP7ajxJOSuY nN7ejlbzkCDQDRejrWxAOIm7TQscrGeE/YrVRV3HsPfNQbgNSTVEM3H5Zpw8Pi/IY1nV yGhw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tTxcnEmW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd8e853esm223671995e9.8.2024.11.05.05.05.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:05:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 08/19] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel() Date: Tue, 5 Nov 2024 14:04:20 +0100 Message-ID: <20241105130431.22564-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass vCPU endianness as argument so we can load kernels with different endianness (different from the qemu-system-binary builtin one). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- hw/microblaze/boot.h | 4 ++-- hw/microblaze/boot.c | 8 ++++---- hw/microblaze/petalogix_ml605_mmu.c | 2 +- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 +- hw/microblaze/xlnx-zynqmp-pmu.c | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/microblaze/boot.h b/hw/microblaze/boot.h index 5a8c2f79750..d179a551a69 100644 --- a/hw/microblaze/boot.h +++ b/hw/microblaze/boot.h @@ -2,8 +2,8 @@ #define MICROBLAZE_BOOT_H -void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base, - uint32_t ramsize, +void microblaze_load_kernel(MicroBlazeCPU *cpu, bool is_little_endian, + hwaddr ddr_base, uint32_t ramsize, const char *initrd_filename, const char *dtb_filename, void (*machine_cpu_reset)(MicroBlazeCPU *)); diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c index ed61e483ee8..3675489fa5b 100644 --- a/hw/microblaze/boot.c +++ b/hw/microblaze/boot.c @@ -114,8 +114,8 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return addr - 0x30000000LL; } -void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base, - uint32_t ramsize, +void microblaze_load_kernel(MicroBlazeCPU *cpu, bool is_little_endian, + hwaddr ddr_base, uint32_t ramsize, const char *initrd_filename, const char *dtb_filename, void (*machine_cpu_reset)(MicroBlazeCPU *)) @@ -144,13 +144,13 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base, /* Boots a kernel elf binary. */ kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &entry, NULL, &high, NULL, - TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0); + !is_little_endian, EM_MICROBLAZE, 0, 0); base32 = entry; if (base32 == 0xc0000000) { kernel_size = load_elf(kernel_filename, NULL, translate_kernel_address, NULL, &entry, NULL, NULL, NULL, - TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0); + !is_little_endian, EM_MICROBLAZE, 0, 0); } /* Always boot into physical ram. */ boot_info.bootstrap_pc = (uint32_t)entry; diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 61e47d83988..d2b2109065d 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -204,7 +204,7 @@ petalogix_ml605_init(MachineState *machine) cpu->cfg.pvr_regs[5] = 0xc56be000; cpu->cfg.pvr_regs[10] = 0x0e000000; /* virtex 6 */ - microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size, + microblaze_load_kernel(cpu, true, MEMORY_BASEADDR, ram_size, machine->initrd_filename, BINARY_DEVICE_TREE_FILE, NULL); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 6c0f5c6c651..8110be83715 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -129,7 +129,7 @@ petalogix_s3adsp1800_init(MachineState *machine) create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000); - microblaze_load_kernel(cpu, ddr_base, ram_size, + microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size, machine->initrd_filename, BINARY_DEVICE_TREE_FILE, NULL); diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c index 567aad47bfc..bdbf7328bf4 100644 --- a/hw/microblaze/xlnx-zynqmp-pmu.c +++ b/hw/microblaze/xlnx-zynqmp-pmu.c @@ -172,7 +172,7 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine) qdev_realize(DEVICE(pmu), NULL, &error_fatal); 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c10b7bb7sm16338383f8f.3.2024.11.05.05.06.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:06:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 09/19] hw/intc/xilinx_intc: Only expect big-endian accesses Date: Tue, 5 Nov 2024 14:04:21 +0100 Message-ID: <20241105130431.22564-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Per the datasheet (reference added in file header, p.9) 'Programming Model' -> 'Register Data Types and Organization': "The XPS INTC registers are read as big-endian data" Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- hw/intc/xilinx_intc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 1762b34564e..71f743a1f14 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * https://docs.amd.com/v/u/en-US/xps_intc + * DS572: LogiCORE IP XPS Interrupt Controller (v2.01a) + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -143,12 +146,20 @@ static void pic_write(void *opaque, hwaddr addr, static const MemoryRegionOps pic_ops = { .read = pic_read, .write = pic_write, - .endianness = DEVICE_NATIVE_ENDIAN, + /* The XPS INTC registers are read as big-endian data. */ + .endianness = DEVICE_BIG_ENDIAN, .impl = { .min_access_size = 4, .max_access_size = 4, }, .valid = { + /* + * All XPS INTC registers are accessed through the PLB interface. + * The base address for these registers is provided by the + * configuration parameter, C_BASEADDR. Each register is 32 bits + * although some bits may be unused and is accessed on a 4-byte + * boundary offset from the base address. + */ .min_access_size = 4, .max_access_size = 4, }, From patchwork Tue Nov 5 13:04:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840799 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp328881wry; Tue, 5 Nov 2024 05:06:34 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVk/HjPyFNN5dOdtZVSVOWH2vqnxirwlfF4Vfo8lAr1lO499oaUsrO07VXCLOhRFr8Dw3iFsA==@linaro.org X-Google-Smtp-Source: AGHT+IFmuS7E8llkDUGW18aeeLi3eLZJfg5uHNPYlrxrThOvdpphcNWlngZB5aDP6vUweTGMafeQ X-Received: by 2002:a05:620a:19a9:b0:7b1:3754:7d83 with SMTP id af79cd13be357-7b2f24c532amr2816852985a.9.1730811993639; Tue, 05 Nov 2024 05:06:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730811993; cv=none; d=google.com; s=arc-20240605; b=SB59XIq+LOEeQjqMVlPNTOxEc2C6/kgrKcMfODyrNJ/umtExSSwRDTZRx/NOB88ieG tUp9CuqdmIU/9yF0oYkMxuD02WMz30J1t1eorUU2mAiOhmd3GMcoKiTz7eEQgAE1FL3e uIe2MOOnLKMxkvk7rYH/qmksHJLEpfbkkFDA9g5N7Wxk5CYdJkOMobZdL6dO71IRrZFG dM83ok9Cyv5PW4f2jDxM1P0QLa7IdOxxhIWmOWOFxCeiBmp3kN76/MihwVlBXAx7bClG 9Jh3Yj+z9NFex5HOfbXjl4NYT8RN6WLa/1HPAXldSKvmIXaaZp0DZ4DPODnOUexoqDVS LYUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ofAZFiczDEOu9xgPawLxt48aoodtpVY0sVqQebDNA74=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=gurRDiTSHwAzCwxjxI1LnrZwLHFKFT6vmXb3i5fsdWqDpv6PPhNj61Vd6K6932OdAf blp3mUcxRCM54bHthqnxzMJToeFQNt73h1WdHKMwB5uhg0CZyh0Taxf8ln2YSRTgM5p1 /Ibu6Du3LVLf1FEt+oPFMU/s7EGl2iTkhE4MPRvJlm1NpwBP/UKHcFGJPQCes+gdRHHl QBoRQqai4Q+XtfrxPSxIJvWtFBxttBUsDyRrOu63CpfzUb7nOemTbFvnkTBPClqUMXh9 +/x2kgCMGgV1QjbLIsUNGlAzBIEpLT63lJA4tSbs+vtrx2edrM2r5Q3anau69aDgecJu Mz7Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XeSG3ZtH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4327d5e7c8bsm193062535e9.26.2024.11.05.05.06.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:06:16 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 10/19] hw/timer/xilinx_timer: Only expect big-endian accesses Date: Tue, 5 Nov 2024 14:04:22 +0100 Message-ID: <20241105130431.22564-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Per the datasheet (reference added in file header, p.10): 'Register Data Types and Organization': "The XPS Timer/Counter registers are organized as big-endian data." Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- hw/timer/xilinx_timer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 28ac95edea1..3e272c8bb39 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * DS573: https://docs.amd.com/v/u/en-US/xps_timer + * LogiCORE IP XPS Timer/Counter (v1.02a) + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -192,7 +195,7 @@ timer_write(void *opaque, hwaddr addr, static const MemoryRegionOps timer_ops = { .read = timer_read, .write = timer_write, - .endianness = DEVICE_NATIVE_ENDIAN, + .endianness = DEVICE_BIG_ENDIAN, .impl = { .min_access_size = 4, .max_access_size = 4, From patchwork Tue Nov 5 13:04:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840806 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp329680wry; Tue, 5 Nov 2024 05:07:57 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXXSefMLkxF+gNIYK+7++3LeOVjBBufESGKD7lRGGQi2y1AE8FV1g9AvpJhXzGZpiTPHxGieg==@linaro.org X-Google-Smtp-Source: AGHT+IHO18XNHCxQN+IB9GQOenWj2ohYls/N6ZxZMEXHH7NXgmyfReS/LO7o6fUWjneBg+FzvGB0 X-Received: by 2002:ac8:7d8e:0:b0:460:a367:5d5f with SMTP id d75a77b69052e-461717c96a5mr324481451cf.59.1730812076857; Tue, 05 Nov 2024 05:07:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730812076; cv=none; d=google.com; s=arc-20240605; b=jxObPTPabfVpoz3Vs+6L5Yhkvgx4qeybbSNa4XCcN0J52aNBjKgmXxDH3LdVPmWdGI MrcpTrmAalFg2kYrcRZufVDCPKXKMS2dH59e+Zim6mQLqSk5doU/3vzkX9fJ1wa9rZIv f2T23y3T3cyE8H1Sq6udFM4Wfw0FeLSWLPSu7hezetuf0I/5Cu4Ftfusdwy66htf0+Y6 LffkGsY4NG4FBxg5wGpbaGgMtId4JZrtVSyaxVjsS7NfWWyf6NUHXv5aPf9m69rY3jlf yuBU14kOWDBrUk4l77FJcIaAcKoxRUqX6TiBc8aKvYl7v1nOzXBEHBtKszWwsLt1aYen A9pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wFGgkm5n4LzlLdg21RwAQ7vz4q2WxQLn0Ned6IA69o0=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=c2mDGxcDQLlccUWm5Q5Q/fEgEchYGEKkFbBk0kZz3e7CM/L9AsRilQ3fEcpQ4Jw2rS 6ATKpJOXm+qJBmO4I2rH3XUD5gUGnsw88IntwA3j/hgINN2cwjvUkEg7FJadgaJS36R2 iTq5LfQpYtiWYknuuM+bAJ4Z3PWYDA5+lcGADUnl23jELIoY/5VZroA+h/wxHroRHu9Y BPH1RojCZGFdxn3woeB0bO1ci07eMIGPiV6zVRuXgwriyypLJmnSESWxplqUa/a+dvPQ awmtHbJm8XyJeBCMVZEknySr4hdgQsIEyrynjR9DIH9Md25/1V031Tunrofg3iWT9Hxu pyTw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qJ30FYtU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c113e5e3sm16241441f8f.82.2024.11.05.05.06.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:06:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 11/19] hw/timer/xilinx_timer: Allow down to 8-bit memory access Date: Tue, 5 Nov 2024 14:04:23 +0100 Message-ID: <20241105130431.22564-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Allow down to 8-bit access, per the datasheet (reference added in previous commit): "Timer Counter registers are accessed as one of the following types: • Byte (8 bits) • Half word (2 bytes) • Word (4 bytes)" Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Acked-by: Alistair Francis --- hw/timer/xilinx_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 3e272c8bb39..e9498fc7eec 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -201,7 +201,7 @@ static const MemoryRegionOps timer_ops = { .max_access_size = 4, }, .valid = { - .min_access_size = 4, + .min_access_size = 1, .max_access_size = 4, }, }; From patchwork Tue Nov 5 13:04:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840800 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp329280wry; Tue, 5 Nov 2024 05:07:13 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVOf8xzJeBCtZtanvihpqxFBRIXB2VydTa0BZxH00C0jwdNruG4BW6QgGUCtFKKvQDvAHaFXQ==@linaro.org X-Google-Smtp-Source: AGHT+IGubH9pfYBNSPxPKw9gW87kd18/hpbxBjNMupAhiJKnkOtvpOfOYt6P628zroWI0hXECwVA X-Received: by 2002:a05:622a:50d:b0:458:3871:e062 with SMTP id d75a77b69052e-4613c039f1fmr551067391cf.34.1730812033082; Tue, 05 Nov 2024 05:07:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730812033; cv=none; d=google.com; s=arc-20240605; b=C7BJRx3RQvAD5Bot/B2TZbvUBo0sKhYvxutadgGQYBLLrSoq02xHgB20Bto8uC9T3B z5lCam3qLh5lS3A7g/d+3Gyyx+J2UmQMLRFEiXnmw2j+hUsp4xmxc3n/N8NzH4pWfDgj xPsj0FSrvAD6/CaEMbyJJf3QkLT3UY6w0fZE0jz4P7BPrbEqYpvcNLgqIUj4FjibFbCN jsjdTsQausHAL3KRK6K0ra9poAmx5uyIDC37oqRP8KtGukyMw2hmvLwvcRkbilJSMr4H PWh6wbbfTVgqmLWHwaRojSmg7UPhmZ3BjIBKuNYUrhiv+JNPlo07DiXx1VirTC4QtO/D HUyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8o7w6mm+R/wQGpGGVYXrXktqPkxmlHPhQB9iwAgMFYc=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=QbJYGNclS2sh1m/7oXbJusGVXkDESDYLRlt9Xz9PUh9HgbxfCiIl/v13XdaHTehpEe ovWdT1RuNdfXmY36sFAvA9B9p1BC7CaxGI2zcYWRDnzUp0MunG67wKnvexSBzQMdRed6 XBjf7B/Yf7v5J5YIO6XhV+lbEmfvOiUD99IhIPzQiHwLsqN3f6rTBsyy7OcWk6HQEsGE nX/cJqQTS9EP3Gaw0IKgyRz81PQkR+BssYHdDemzVKbVBvll5iZthys+J+Sao0tPAhL2 8TJaxUlHvdif2fsINZ/YZUiAChpBCSFBdamUsK/rJ8lEq6ekOnJpLDH/sYsoqikw0NkD lRBA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MxAp+1eh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4327d5c65absm185489175e9.16.2024.11.05.05.06.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:06:35 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 12/19] hw/net/xilinx_ethlite: Only expect big-endian accesses Date: Tue, 5 Nov 2024 14:04:24 +0100 Message-ID: <20241105130431.22564-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The Xilinx 'ethlite' device was added in commit b43848a100 ("xilinx: Add ethlite emulation"), being only built back then for a big-endian MicroBlaze target (see commit 72b675caac "microblaze: Hook into the build-system"). I/O endianness access was then clarified in commit d48751ed4f ("xilinx-ethlite: Simplify byteswapping to/from brams"). Here the 'fix' was to use tswap32(). Since the machine was built as big-endian target, tswap32() use means the fix was for a little endian host. While the datasheet (reference added in file header) is not precise about it, we interpret such change as the device expects accesses in big-endian order. Besides, this is what other Xilinx/MicroBlaze devices use (see the 3 previous commits). Correct the MemoryRegionOps endianness. Add a 'access-little-endian' property, so if the bus access expect little-endian order we swap the values. Replace the tswap32() calls accordingly. Set the property on the single machine using this device. Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + hw/net/xilinx_ethlite.c | 20 ++++++++++++++++---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 8110be83715..8407dbee12a 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -123,6 +123,7 @@ petalogix_s3adsp1800_init(MachineState *machine) qemu_configure_nic_device(dev, true, NULL); qdev_prop_set_uint32(dev, "tx-ping-pong", 0); qdev_prop_set_uint32(dev, "rx-ping-pong", 0); + qdev_prop_set_bit(dev, "access-little-endian", !TARGET_BIG_ENDIAN); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index ede7c172748..44ef11ebf89 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite + * LogiCORE IP XPS Ethernet Lite Media Access Controller + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -25,7 +28,6 @@ #include "qemu/osdep.h" #include "qemu/module.h" #include "qom/object.h" -#include "exec/tswap.h" #include "hw/sysbus.h" #include "hw/irq.h" #include "hw/qdev-properties.h" @@ -65,6 +67,7 @@ struct xlx_ethlite NICState *nic; NICConf conf; + bool access_little_endian; uint32_t c_tx_pingpong; uint32_t c_rx_pingpong; unsigned int txbuf; @@ -103,9 +106,12 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) break; default: - r = tswap32(s->regs[addr]); + r = s->regs[addr]; break; } + if (s->access_little_endian) { + bswap32s(&r); + } return r; } @@ -117,6 +123,10 @@ eth_write(void *opaque, hwaddr addr, unsigned int base = 0; uint32_t value = val64; + if (s->access_little_endian) { + bswap32s(&value); + } + addr >>= 2; switch (addr) { @@ -161,7 +171,7 @@ eth_write(void *opaque, hwaddr addr, break; default: - s->regs[addr] = tswap32(value); + s->regs[addr] = value; break; } } @@ -169,7 +179,7 @@ eth_write(void *opaque, hwaddr addr, static const MemoryRegionOps eth_ops = { .read = eth_read, .write = eth_write, - .endianness = DEVICE_NATIVE_ENDIAN, + .endianness = DEVICE_BIG_ENDIAN, .impl = { .min_access_size = 4, .max_access_size = 4, @@ -256,6 +266,8 @@ static void xilinx_ethlite_init(Object *obj) } static Property xilinx_ethlite_properties[] = { + DEFINE_PROP_BOOL("access-little-endian", struct xlx_ethlite, + access_little_endian, false), DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1), DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1), DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf), From patchwork Tue Nov 5 13:04:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840808 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp329897wry; Tue, 5 Nov 2024 05:08:20 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXu4jEYUdDaYXWx1o2Fq3cQrWVm8Y4xYJuIgy2UJTEgO3xrKhfKAKJdaKD+qMFJPT/fmebuDQ==@linaro.org X-Google-Smtp-Source: AGHT+IEkc+z4/g9sGOBspv246Cy1ngUaiPgtq5/Ied1FfE7C2ZlnqD5UUTs4m4BinoSfiBlxc44q X-Received: by 2002:a05:620a:284a:b0:7b1:2016:7775 with SMTP id af79cd13be357-7b2f24f0d83mr2904010685a.36.1730812099568; Tue, 05 Nov 2024 05:08:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730812099; cv=none; d=google.com; s=arc-20240605; b=KQChjE4xHxyZI7xg0uLtil1CsK6A9RzUH20kpZBx7vVpQwnWF1pZNyZ1MkNziERsw6 8E8Smy4X56bSETrf3dW/8D7MA+TdZYCxRtad439+w+vaXMXlQWaHufuXvO5NjwltLM8v fCoGt2/DKq0jyfHP2RPr7TE8YD8lehk2RamPnvgbh9AGCt9UxTqOwBmPXXqJSWOmq36n ejzJzFLxOQQdcpWMaL2tMKfklyzJvJAXtlJZ4bYV3pHfwzD+jX4BVsc3LUFH2FugnHzB 5SXDq0/9ZJPpEd0F/wlqm1RVY69/wLPMfSpIkPAmolM+9EWIGfjEm53dnFvWMiq6Xcg0 M2Wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2HA1iYoQhge6HN2CHRy7t3YqB3wWBO4DLLl9qjbY1CM=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=DiqOSxRqQFhT/7mBxBSD+0aGsCSV7fp5dUp+GUpZaxYwxRLVmMHSuAy+YbLlRhpBnB IgXc1sAlwqGyvb4XxemCHzQj56rjHAzEKQ4/rV18o7MJHzJf6rgTHN09qS2X/EXoc7kQ IA6IXMmankOOEl6tH/p5Q8cyDm4Yy0PXUbYFvlgTCIlcjOipDEivNWSQQsSpcQ3Wv2Fn K0i+6jvi24/1g/9XC33EJlcW2Gn+ULJ+Ek/rmbhZ4ovaFmRQMGymq9I6f8ILoevqX/nk lptiNCNvGGGJajQUr9zSFF8DEVIg/A5geaaRuYIrs4TXhtfomiVuaFkni4iKxe/NtQQN 6N5g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lpo9L8Rk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c10d4d1fsm16076930f8f.38.2024.11.05.05.06.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:06:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 13/19] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Date: Tue, 5 Nov 2024 14:04:25 +0100 Message-ID: <20241105130431.22564-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- target/microblaze/translate.c | 36 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4beaf69e76a..4c25b1e4383 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -779,13 +779,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg) static bool trans_lhu(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_lhur(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } static bool trans_lhuea(DisasContext *dc, arg_typea *arg) @@ -797,26 +797,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_lw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_lwr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } static bool trans_lwea(DisasContext *dc, arg_typea *arg) @@ -828,14 +828,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_lwx(DisasContext *dc, arg_typea *arg) @@ -845,7 +845,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); tcg_gen_mov_tl(cpu_res_addr, addr); if (arg->rd) { @@ -929,13 +929,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg) static bool trans_sh(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_shr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } static bool trans_shea(DisasContext *dc, arg_typea *arg) @@ -947,26 +947,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_shi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_sw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_swr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } static bool trans_swea(DisasContext *dc, arg_typea *arg) @@ -978,14 +978,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_swi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_swx(DisasContext *dc, arg_typea *arg) @@ -1014,7 +1014,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, reg_for_write(dc, arg->rd), - dc->mem_index, MO_TEUL); + dc->mem_index, MO_TE | MO_UL); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); From patchwork Tue Nov 5 13:04:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840803 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp329451wry; 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c113e51csm16313213f8f.79.2024.11.05.05.06.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:06:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 14/19] target/microblaze: Set MO_TE once in do_load() / do_store() Date: Tue, 5 Nov 2024 14:04:26 +0100 Message-ID: <20241105130431.22564-15-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All callers of do_load() / do_store() set MO_TE flag. Set it once in the callees. Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/translate.c | 36 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4c25b1e4383..86f3c196189 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -712,6 +712,8 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; + mop |= MO_TE; + /* * When doing reverse accesses we need to do two things. * @@ -779,13 +781,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg) static bool trans_lhu(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_lhur(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } static bool trans_lhuea(DisasContext *dc, arg_typea *arg) @@ -797,26 +799,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_lw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_lwr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } static bool trans_lwea(DisasContext *dc, arg_typea *arg) @@ -828,14 +830,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_lwx(DisasContext *dc, arg_typea *arg) @@ -862,6 +864,8 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; + mop |= MO_TE; + /* * When doing reverse accesses we need to do two things. * @@ -929,13 +933,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg) static bool trans_sh(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_shr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } static bool trans_shea(DisasContext *dc, arg_typea *arg) @@ -947,26 +951,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_shi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_sw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_swr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } static bool trans_swea(DisasContext *dc, arg_typea *arg) @@ -978,14 +982,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_swi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_swx(DisasContext *dc, arg_typea *arg) From patchwork Tue Nov 5 13:04:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840807 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp329745wry; Tue, 5 Nov 2024 05:08:03 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWgBLZOP31T+raXd0AINwz+U4nr8zYkiq1ZgBbbKIvkI/0O967m4EbEoz6nAdFHHk9zALTc1g==@linaro.org X-Google-Smtp-Source: AGHT+IFR9PPh9d/7b8am5rlYuxf0vL4Y7uj1Wu7JkdkF8irKNkuQllpGZ2utevzD4jvSY1ODYGtT X-Received: by 2002:a05:6214:3a84:b0:6cd:4972:59b1 with SMTP id 6a1803df08f44-6d1857030c9mr605870096d6.27.1730812083606; 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c113e073sm16114234f8f.66.2024.11.05.05.07.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:07:03 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 15/19] target/microblaze: Introduce mo_endian() helper Date: Tue, 5 Nov 2024 14:04:27 +0100 Message-ID: <20241105130431.22564-16-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org mo_endian() returns the target endianness, currently static. Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/translate.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 86f3c196189..0b466db694c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -707,12 +707,17 @@ static void record_unaligned_ess(DisasContext *dc, int rd, } #endif +static inline MemOp mo_endian(DisasContext *dc) +{ + return MO_TE; +} + static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) { MemOp size = mop & MO_SIZE; - mop |= MO_TE; + mop |= mo_endian(dc); /* * When doing reverse accesses we need to do two things. @@ -847,7 +852,8 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, + mo_endian(dc) | MO_UL); tcg_gen_mov_tl(cpu_res_addr, addr); if (arg->rd) { @@ -864,7 +870,7 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; - mop |= MO_TE; + mop |= mo_endian(dc); /* * When doing reverse accesses we need to do two things. @@ -1018,7 +1024,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, reg_for_write(dc, arg->rd), - dc->mem_index, MO_TE | MO_UL); + dc->mem_index, mo_endian(dc) | MO_UL); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); From patchwork Tue Nov 5 13:04:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840802 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp329426wry; Tue, 5 Nov 2024 05:07:29 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUQh/JFVwbK1aLeWIeeOh6WZN1pBBveI0dD5eZKcu4qtmDiCUJi/0lqHCUjGMUEkubHzs4Eaw==@linaro.org X-Google-Smtp-Source: AGHT+IFHJXjNex35WWZvHEDKwPWol1gW18OEI4dqCdwm/WB6hKXxHRvWUvhR8QR3QHmBGje09W/L X-Received: by 2002:a05:622a:1109:b0:460:8ede:cf48 with SMTP id d75a77b69052e-462b86567dcmr231703341cf.10.1730812048750; Tue, 05 Nov 2024 05:07:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730812048; cv=none; d=google.com; s=arc-20240605; b=MU4/Qmqn7w9M4aj+gKvnyEd+78hYCi79yqwuOKB78KGGUU9Z5nYH42ZzalEN7ir/zr XKic+iHiUxSvjULLQew6NRtoXFULVK2cAQhAWSZ1lkKr02zZ7gsonP2V8Nf4ClflgrEs fzbEzY7I69szJRV+/Zfc3UROMZMhyQw8NllXn/HdUl1GkkSoQeFDl2Y1rtPUJ3A79bM2 tbDG309FxP9gGjxysVVEU9/Uo6LtEZ4BiF6Z30RZ+WdTGMOep2HHr03rVNQBPgCnLb60 KAQmgf39ClLqbUnuTyypA4yOBZK2EahSM0n08Kb2QAcwM1dM4ORCgHFFJkjwBKW1sY6e XDBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=x3QZDoqX/9aQeCd67Fxf+7IHrX4YKBlVMoYZ3cKr6J0=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=Vx1lJKxq2kSuRSSPK2AIYwl6h8nKDVzSH+nt2K7wj5AXirevGnzqHq7AZ9jj7iFqBh 234uvkI9Z7EK8Zuq3uY+XJsWGvnrBWHL9Nm/3SVzrnaYQAaZsmlblETZzzzwYCb+so77 UltcjI1ba/AMED7H0RaQoSRuK8lW01O96JYQYgLjxIjyumKh0er33+oZ5WP6xv7dmByG D47HxTirgKkkuGV+963SGijT/6PVf9vLE2g1hbNHa1O0PefZ2bjSwqRVavDDPFSTAp1o Gmiq57FOK9C8GA6N8ybXiqKwGUYet1EigoyfswzWXl6X2zW75uE19zKEDZpD3aeCnnUG MxoA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Fx5T+/Nf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c116b11esm16096019f8f.104.2024.11.05.05.07.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:07:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 16/19] target/microblaze: Consider endianness while translating code Date: Tue, 5 Nov 2024 14:04:28 +0100 Message-ID: <20241105130431.22564-17-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Consider the CPU ENDI bit, swap instructions when the CPU endianness doesn't match the binary one. Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.h | 7 +++++++ target/microblaze/translate.c | 5 +++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 3e5a3e5c605..6d540713eb5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -412,6 +412,13 @@ void mb_tcg_init(void); /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); +static inline bool mb_cpu_is_big_endian(CPUState *cs) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + + return !cpu->cfg.endi; +} + static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0b466db694c..5595ae4fadb 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -709,7 +709,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd, static inline MemOp mo_endian(DisasContext *dc) { - return MO_TE; + return dc->cfg->endi ? MO_LE : MO_BE; } static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, @@ -1646,7 +1646,8 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->tb_flags_to_set = 0; - ir = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next); + ir = translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next, + mb_cpu_is_big_endian(cs) != TARGET_BIG_ENDIAN); if (!decode(dc, ir)) { trap_illegal(dc, true); } From patchwork Tue Nov 5 13:04:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840809 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp329933wry; Tue, 5 Nov 2024 05:08:22 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVzB4zROPg6fEX6/DuTo76ikq6aPt6nztTqdGtoEA5lGzz7pp20Ad10mGgi5J/RMNDfJ7MzUQ==@linaro.org X-Google-Smtp-Source: AGHT+IGTA3q8YpdL9h518Gw6r9rKHzdAmzuXossKGT8iBthbfUBuFpmRAcZfueIU21l87esboEp9 X-Received: by 2002:a05:622a:134c:b0:460:ab13:f53c with SMTP id d75a77b69052e-462b8688a59mr242178711cf.20.1730812102494; Tue, 05 Nov 2024 05:08:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730812102; cv=none; d=google.com; s=arc-20240605; b=J2Yv22fVKyJxM5LxW0fL8paTev2nVfXBWbWOrShSDm8oE4wBr3hJhy/coFXJuW19Bj SgjtLBmImyUk8mMH+OtYereMrdGlnD+QA077rob/yPiRMV8kYDaIX6LKL4yfTKaOAfUt m0SkV+hu80Cl876VUffFImEvZRXFRLJsJuwZFxou+npHa6cVyruf2fCkX9nYEzRN4om3 Zfit6UmZR+OBlzem0krzNLFIYTvc0uD3bKx2l8FkSrDDNQv+DQ32JX4dV3dAMQrxacxG Bcr9nJ/6yNUyTQyqNWdo8ghbqoJlyphayHsOdn3rzeTE46UkfVISiqOpHHt8OG90iCoQ QndQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=haV4HgajOuBZyaKR8WLf7rNEDHwvap87jZ2MipEC/AA=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=Ce66PXNL0KvKVi8m+VyIsj1Cemn8vuVzRuaUpCDRg88fpWEbjwgnBrw4BEt0zQjn1H jjemC4XUS1q4cyOac4oZM7m/JzBjQiTHi7s4zdk520HRPEvtrtanBnVnOLD8HvVe34ES wRcPpKu26RN2Sv2wi0Xe10BveF99eoQIEQn+sZ4omGEJjHh24jHP2TXYsrdfKbh0ezHr CGM+ECeQn9i/PvDEHq9+v05HxYxKTcGMgjqiAO6RuQC/uQTLndWOCKSQqUXPYgoqcu1x jPNGpEtgG34fIeY5kcJr5nlpVkIu/w9Ks2sCPS2sG+jHa88b6LjVg0Caka4yC8Ne1PJl mxNw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s1Aiu+VY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd8e8471sm226896305e9.4.2024.11.05.05.07.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:07:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 17/19] hw/microblaze: Support various endianness for s3adsp1800 machines Date: Tue, 5 Nov 2024 14:04:29 +0100 Message-ID: <20241105130431.22564-18-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce an abstract machine parent class which defines the 'little_endian' property. Duplicate the current machine, which endian is tied to the binary endianness, to one big endian and a little endian machine; updating the machine description. Keep the current default machine for each binary. 'petalogix-s3adsp1800' machine is aliased as: - 'petalogix-s3adsp1800-be' on big-endian binary, - 'petalogix-s3adsp1800-le' on little-endian one. Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 55 +++++++++++++++++++++--- 1 file changed, 48 insertions(+), 7 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 8407dbee12a..f5195327b76 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -55,8 +55,17 @@ #define ETHLITE_IRQ 1 #define UARTLITE_IRQ 3 +typedef struct PetalogixS3adsp1800MachineClass { + MachineClass parent_obj; + + bool little_endian; +} PetalogixS3adsp1800MachineClass; + #define TYPE_PETALOGIX_S3ADSP1800_MACHINE \ - MACHINE_TYPE_NAME("petalogix-s3adsp1800") + MACHINE_TYPE_NAME("petalogix-s3adsp1800-common") +DECLARE_CLASS_CHECKERS(PetalogixS3adsp1800MachineClass, + PETALOGIX_S3ADSP1800_MACHINE, + TYPE_PETALOGIX_S3ADSP1800_MACHINE) static void petalogix_s3adsp1800_init(MachineState *machine) @@ -71,11 +80,13 @@ petalogix_s3adsp1800_init(MachineState *machine) MemoryRegion *phys_ram = g_new(MemoryRegion, 1); qemu_irq irq[32]; MemoryRegion *sysmem = get_system_memory(); + PetalogixS3adsp1800MachineClass *pmc; + pmc = PETALOGIX_S3ADSP1800_MACHINE_GET_CLASS(machine); cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort); object_property_set_bool(OBJECT(cpu), "little-endian", - !TARGET_BIG_ENDIAN, &error_abort); + pmc->little_endian, &error_abort); qdev_realize(DEVICE(cpu), NULL, &error_abort); /* Attach emulated BRAM through the LMB. */ @@ -123,33 +134,63 @@ petalogix_s3adsp1800_init(MachineState *machine) qemu_configure_nic_device(dev, true, NULL); qdev_prop_set_uint32(dev, "tx-ping-pong", 0); qdev_prop_set_uint32(dev, "rx-ping-pong", 0); - qdev_prop_set_bit(dev, "access-little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "access-little-endian", pmc->little_endian); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000); - microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size, + microblaze_load_kernel(cpu, pmc->little_endian, ddr_base, ram_size, machine->initrd_filename, BINARY_DEVICE_TREE_FILE, NULL); } -static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void *data) +static void petalogix_s3adsp1800_machine_class_init_be(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + PetalogixS3adsp1800MachineClass *pmc = PETALOGIX_S3ADSP1800_MACHINE_CLASS(oc); - mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800"; + pmc->little_endian = false; + mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (big endian)"; mc->init = petalogix_s3adsp1800_init; +#if TARGET_BIG_ENDIAN mc->is_default = true; + mc->alias = "petalogix-s3adsp1800"; +#endif +} + +static void petalogix_s3adsp1800_machine_class_init_le(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + PetalogixS3adsp1800MachineClass *pmc = PETALOGIX_S3ADSP1800_MACHINE_CLASS(oc); + + pmc->little_endian = true; + mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (little endian)"; + mc->init = petalogix_s3adsp1800_init; +#if !TARGET_BIG_ENDIAN + mc->is_default = true; + mc->alias = "petalogix-s3adsp1800"; +#endif } static const TypeInfo petalogix_s3adsp1800_machine_types[] = { { .name = TYPE_PETALOGIX_S3ADSP1800_MACHINE, .parent = TYPE_MACHINE, - .class_init = petalogix_s3adsp1800_machine_class_init, + .abstract = true, + .class_size = sizeof(PetalogixS3adsp1800MachineClass), + }, + { + .name = MACHINE_TYPE_NAME("petalogix-s3adsp1800-be"), + .parent = TYPE_PETALOGIX_S3ADSP1800_MACHINE, + .class_init = petalogix_s3adsp1800_machine_class_init_be, + }, + { + .name = MACHINE_TYPE_NAME("petalogix-s3adsp1800-le"), + .parent = TYPE_PETALOGIX_S3ADSP1800_MACHINE, + .class_init = petalogix_s3adsp1800_machine_class_init_le, }, }; From patchwork Tue Nov 5 13:04:30 2024 Content-Type: text/plain; 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4327d5ac387sm194360095e9.1.2024.11.05.05.07.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:07:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 18/19] tests/functional: Explicit endianness of microblaze assets Date: Tue, 5 Nov 2024 14:04:30 +0100 Message-ID: <20241105130431.22564-19-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The archive used in test_microblaze_s3adsp1800.py (testing a big-endian target) contains a big-endian kernel. Rename using the _BE suffix. Similarly, the archive in test_microblazeel_s3adsp1800 (testing a little-endian target) contains a little-endian kernel. Rename using _LE suffix. These changes will help when adding cross-endian kernel tests. Signed-off-by: Philippe Mathieu-Daudé --- tests/functional/test_microblaze_s3adsp1800.py | 6 +++--- tests/functional/test_microblazeel_s3adsp1800.py | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index 4f692ffdb1a..2b2f7822707 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -17,14 +17,14 @@ class MicroblazeMachine(QemuSystemTest): timeout = 90 - ASSET_IMAGE = Asset( + ASSET_IMAGE_BE = Asset( ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/' 'day17.tar.xz'), '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057') - def test_microblaze_s3adsp1800(self): + def test_microblaze_s3adsp1800_be(self): self.set_machine('petalogix-s3adsp1800') - file_path = self.ASSET_IMAGE.fetch() + file_path = self.ASSET_IMAGE_BE.fetch() archive_extract(file_path, self.workdir) self.vm.set_console() self.vm.add_args('-kernel', self.workdir + '/day17/ballerina.bin') diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index faa3927f2e9..1aee5149fb1 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -17,14 +17,14 @@ class MicroblazeelMachine(QemuSystemTest): timeout = 90 - ASSET_IMAGE = Asset( + ASSET_IMAGE_LE = Asset( ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') - def test_microblazeel_s3adsp1800(self): + def test_microblazeel_s3adsp1800_le(self): self.require_netdev('user') self.set_machine('petalogix-s3adsp1800') - file_path = self.ASSET_IMAGE.fetch() + file_path = self.ASSET_IMAGE_LE.fetch() archive_extract(file_path, self.workdir) self.vm.set_console() self.vm.add_args('-kernel', self.workdir + '/day13/xmaton.bin') From patchwork Tue Nov 5 13:04:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 840810 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1ace:b0:37d:45d0:187 with SMTP id i14csp329987wry; Tue, 5 Nov 2024 05:08:28 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU9xVPNX/uu/dbL8lvkhGuZPmWEAZ4ki1q391SWpwZfcpdFLa1pRIDWON9SQoTIqx0TULM1ng==@linaro.org X-Google-Smtp-Source: AGHT+IEtpvOhBzuNRhEBjMq3cdljnPpBNl/6t9ZKwrSLGGNQh9G1dCljiGmcubJtf7T6y5MXvvcg X-Received: by 2002:a05:620a:4082:b0:7ac:d673:2057 with SMTP id af79cd13be357-7b2f24c51ffmr3486729485a.13.1730812108070; Tue, 05 Nov 2024 05:08:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730812108; cv=none; d=google.com; s=arc-20240605; b=ikb4ISQKM0vYuUZVI2/cG7rRPXYjeibXRTwcnZRxcX6HOOMNSqZLH+MI754ImNus00 CDMFlmOgMRhiE0dbMRs/HIZLCd3dVKDYVaLdUwIk1h9lJM9Lz8ylHPPURePslFn0/Qdo 0Z6WwjseF0JD0jfQLucXUU1gpZXSjopehjdruTGnXMx4vV3neSSguhEk9Jc8ADNbjRC9 QxdLkqmpEpjg1ATx1XiWqgp/DpnGMebdp2egPReZ+K2fg0n3fdKi2HhrYD+v2/0Azp20 NOFbOfmmC1rpjVV3Tarij0xmoBvesGOnCl5Wxw8+obuyUk/v3dEPxvez+j4Ag+6gMPFd d5sA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iGrQLs85iCO+ooJQZbg2Q0E0dHdOyXnWOUnrVx9dt/s=; fh=t3XyJLi79GAl74vwjx9CHyT1q7cQJdnSqFDS2FXNV/w=; b=fwAFozs0TLKUys9oixhqPPa5XJq1vQ+f2I2lJZisDitHa3wwDL3+Kj+CL62GZ5nSqQ HvqhTlAHfmBnfflHtv7qPrX7GFsdrua/nfu1ho5Hqhs+oKNelrAUMuWXGFPh8+b9i3oV +851aP/RFMAyJscIhjEh21utK5S9h6QFPUZ8iWyWqLasdkRj6y4S5PWKcXw11h9B9h26 pgaIDLCfseSjll3lxF3lGWmB/XLK60KIku9ccIgAO0uhdzCWsW8ZLqAFc3o5Aa55LCIU xiQjKKrip3INRMfuHlQh9hrLfSHqQca7siQyzDFhMfM3DKYdCzoVJb+uWm14+//jfjZH el+g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p7UplYso; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c10d439esm16225993f8f.44.2024.11.05.05.07.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:07:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?utf-8?q?Marc-Andr=C3=A9_Lur?= =?utf-8?q?eau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 19/19] tests/functional: Add microblaze cross-endianness tests Date: Tue, 5 Nov 2024 14:04:31 +0100 Message-ID: <20241105130431.22564-20-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Copy/paste the current tests, but call the opposite endianness machines, testing: - petalogix-s3adsp1800-le machine (little-endian CPU) on the qemu-system-microblaze binary (big-endian) - petalogix-s3adsp1800-be machine (big-endian CPU) on the qemu-system-microblazeel binary (little-endian). Signed-off-by: Philippe Mathieu-Daudé --- Clever refactor left for later --- .../functional/test_microblaze_s3adsp1800.py | 21 +++++++++++++++++++ .../test_microblazeel_s3adsp1800.py | 19 +++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index 2b2f7822707..7f5e8b6024f 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -36,5 +36,26 @@ def test_microblaze_s3adsp1800_be(self): # message, that's why we don't test for a later string here. This # needs some investigation by a microblaze wizard one day... + ASSET_IMAGE_LE = Asset( + ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), + 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') + + def test_microblaze_s3adsp1800_le(self): + self.require_netdev('user') + self.set_machine('petalogix-s3adsp1800-le') + file_path = self.ASSET_IMAGE_LE.fetch() + archive_extract(file_path, self.workdir) + self.vm.set_console() + self.vm.add_args('-kernel', self.workdir + '/day13/xmaton.bin') + self.vm.add_args('-nic', 'user,tftp=' + self.workdir + '/day13/') + self.vm.launch() + wait_for_console_pattern(self, 'QEMU Advent Calendar 2023') + time.sleep(0.1) + exec_command(self, 'root') + time.sleep(0.1) + exec_command_and_wait_for_pattern(self, + 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', + '821cd3cab8efd16ad6ee5acc3642a8ea') + if __name__ == '__main__': QemuSystemTest.main() diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index 1aee5149fb1..60543009bab 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -38,5 +38,24 @@ def test_microblazeel_s3adsp1800_le(self): 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', '821cd3cab8efd16ad6ee5acc3642a8ea') + ASSET_IMAGE_BE = Asset( + ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/' + 'day17.tar.xz'), + '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057') + + def test_microblazeel_s3adsp1800_be(self): + self.set_machine('petalogix-s3adsp1800-be') + file_path = self.ASSET_IMAGE_BE.fetch() + archive_extract(file_path, self.workdir) + self.vm.set_console() + self.vm.add_args('-kernel', self.workdir + '/day17/ballerina.bin') + self.vm.launch() + wait_for_console_pattern(self, 'This architecture does not have ' + 'kernel memory protection') + # Note: + # The kernel sometimes gets stuck after the "This architecture ..." + # message, that's why we don't test for a later string here. This + # needs some investigation by a microblaze wizard one day... + if __name__ == '__main__': QemuSystemTest.main()