From patchwork Tue Nov 5 20:04:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 840946 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2062.outbound.protection.outlook.com [40.107.244.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0B89215C50; Tue, 5 Nov 2024 20:04:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.62 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837099; cv=fail; b=Ts6cUCqprB46H6cHmtOax+HDKHfOt1m4taNsFl8JpsoznTkztOSVyBaPaPdaCXr1S+mEEUMvyxONB/Q4TCdxp3swTX0LcTV7x+/g25tP8akeqXK7lJGTP6jjBZA5dZz4F56fuBU6TjAWPBTbeogqp6a8M3s2IcBG7o7eeLIfCEs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837099; c=relaxed/simple; bh=7sPB15V/w4wInnTmw0ej6hMvg40uSiSj5vrqQcGoylU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mXHKjIFgC6rslveu9QFWx2gngatNJvJH8OLj5xpcVRYoOjOgdnvvMxVcrl+v83yIEKMWo9uYwpKWUy0GkQpmCgxZZXzQ2urH3AuL3CGqFSTcT9sPHV1WFmWFcbnGX+JcR1IpASfC/f2+LkKw+6YU3uzl2enkatwnZpt5w0J5ovc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=dL5j0/BT; arc=fail smtp.client-ip=40.107.244.62 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="dL5j0/BT" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=bKZVBpdZNR1drAUf2zOC+Fh+nSdN7IMC0GHe065IJyL1QJj6rKSAlvzQYtdjQWNV3aKoFDBE7hp1FjrPz/XaSLgedavwz8nk+Bb8EL/TsIGrtuYEBNUwECmSq1kHn+/8RO/Lb/YNA6gSK3+brKARYwDwUDVxjKXCe9YxycQPmDBGrbgg0wey3d5GnRloiom5M92mk7HQGkzIQ+E/y1e0/9sZteshP94bi+uEYUHK567bU2dUem/Z6SAsp1pDhTUPvdBjdaHyfT9AV58wJwMybUby86pwAHLidPwnD41KbQWWUXll01dDBTTM30umlziUVPOap0rwNnkzhSARbVBQ6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2m6/F+JKpnHyzJ1kxenJ++GEDw1KOY8ocDrGh1wzehw=; b=ozPwv9Ec1kGNF/j/d9GzdHKlv1qpjFjcwTzookxxb/5sJcblUV8x/EXw4MtgqzCiQ5SaQcG8q5cwv43nGE8LQzQDijzqmpHB6fcTRZ+1GYAPoVIGfjurKC2p1AIzM2ukV9VFnGRCpEI9bLKYyy+G2DnG1MxrUHiIYak+QZK9FuRW3xheOHdGHSKapn3NXLQQG2IeOQlLA3kMqbggGCdKP13MtYs1fgS3uECoRebr2aDx55NJlXLqbqhttbo1E/ehqvEoGcI72vDAkcDCYHAiIpsyZ/mK8NVCTeoABuwRNpBx17tqoPZUOFi/EZzGOPNSTlXBi4HeNEVNK2dwjD5EnQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2m6/F+JKpnHyzJ1kxenJ++GEDw1KOY8ocDrGh1wzehw=; b=dL5j0/BTPD3VBj0+KNEfNbJAuYJZMf2MdBmj7Lvnj1NUoU+p4GH+zJe3Mu2qfZV7PKaQBnFj5ZTM3BANXP9D1WK2OHH8Epg+kBpM5npKDYd1kF8skI9MpNUbiJCdMjGA4+sdltddFOA+PW9/mkWnNqkWCuzzAafCstNG0m/2YdVMf+MnH/hIffYcZ9Ft1Qz6ZvolDhFo1LJxspslm3bF5rZuYdXxmY6JZPcoJjH2P7YpedvO/ON8ep5a3eHQSoHG9zQJeb9FcPXY7JImuYIbtN0k5kY2fy2OzlpUf2fkK5fqoNijuhHZTWtV5S19+ZesANyVGDS7tHfbbBNm0bd7DQ== Received: from MN2PR04CA0021.namprd04.prod.outlook.com (2603:10b6:208:d4::34) by BL1PR12MB5874.namprd12.prod.outlook.com (2603:10b6:208:396::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.19; Tue, 5 Nov 2024 20:04:52 +0000 Received: from BL02EPF00029929.namprd02.prod.outlook.com (2603:10b6:208:d4:cafe::cf) by MN2PR04CA0021.outlook.office365.com (2603:10b6:208:d4::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.26 via Frontend Transport; Tue, 5 Nov 2024 20:04:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL02EPF00029929.mail.protection.outlook.com (10.167.249.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:04:52 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:39 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:39 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:37 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 01/13] iommufd: Move struct iommufd_object to public iommufd header Date: Tue, 5 Nov 2024 12:04:17 -0800 Message-ID: <54a43b0768089d690104530754f499ca05ce0074.1730836219.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00029929:EE_|BL1PR12MB5874:EE_ X-MS-Office365-Filtering-Correlation-Id: f3aaf95c-6830-4f77-5e46-08dcfdd51c72 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: rqucFVjrovnH5UtHqSSDvZ0kD00cyO//ACYHKDgioNzdmt+DTCOAoNCAZAGPdaXbhns+pyALzgRVXj3FLr1MMNjPPybg1EHoNaubN9SXl4r1/K7nvIZxEpS6634+g8PKHWnkGgEbuvZZBYGEJ0hfl2pq9a/dLHtuyiOvuq1ERHA7atuI1T7pvacx4+ZYVbdJdfg8/yOzkgBJq05Lhy2wniFBcMOE7KsZaedZm3WRyjFhNMA1sPY2EZwgzZJvvDnxTthJ+m6/TY8aANcfcrWhuVO28Uz7BO/WAP3ukbv1uCqEuY5028V9JHfdoCyFsz2AwDFXLRqvxPWl71rrapoUA+35edWkdtSFRZBa8OynTJUF8x3ENW7sHmW0qxEgNKsQMp91J4tL4eLZdwRmtGHUuZwR0bHJzlxaBiEi+GfLMgJt3/zsgOZ+trlwKYoWRGraJAYtPeGKgsNH1dEVTEquMQeWzfar5VI7UQvgKkL86wV6FRbB9QWhKi3PA/6rE7CxUYaQSYLZ0vvtPhmfUpPfrMBiwhK5MWmpeyCBp9epSFpWWGZJbB4b41suLNnFbrbRU/HJ8FrSVPN+BzfQuTVWqr9mgMxNRXljmw5Sufb+1HPr5AYfFscXFn982sZWowmxQ9ESw5goszxLqlyzA5oWBuYkP1eHIH+Em8WziPlsUbtRVfdxd9BGHWKD4qIuJzzbkdGo+lp9Q37NdtoDSS19cgDRSBrvEfF3xELMNJ8HFFSow8WC4jT6McRq91LerzoPaBVwJ3h9trh16G4B/tFvx8UtSVaslfci2jrhRiBwgkD5boW+1IIzf9ijJZpmZ4ZKREsRlBvGIFWmPGYXmUlclT3e3UZ1/noLbHvrI6mU0/XPvIEG6n+SV0NOhl/XOOcfjtN1gNeO2+D2o23cTGuntUbAB/m6T77aXfXsbu0sfpObQRtuAPYGhayJfkTnww8yhhWA6a3z+6uPWDuMByy95b6oFjq8lSE5JC3tmlZbBTMckxp7RWmBnAixCrDbExu0sAJG0ZOhBHO8raEou5WFDkMF0lN9DVw78YYSUKzygbpl27579+atCtsNmhZq2RAw/4W28tCpx6HF/m7aFJ4r3oSxn2jRFDdTKwKyshTYUNx0F0XGxuHokV+yPawvVrk0dl9N78cptjHi0h1q8HR/zFfBF1W1+/XuFbjktt8UPw7BPpkDnfHUsek6TyWzzvOW3J8I68FIUq0LMQpH18kWE7HCZ5ZlEd5kCjFzypeeRWKrJl4SAgOHwFiR0oxp5Q8R4j4RwDtk4OI6LBIXH8fuQvmOEoZj1mCwzxHBZKC5ECkeIhfLBGVbHm7SSipfCvrm5tDp8uceR0FoHHhpiEG1C7ePELWO9heraoJUBt/ivlNNBsJEOnhWxaNioktOcPCKy76cM4IP3Sjzng/ydL9c2Q== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:04:52.5323 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f3aaf95c-6830-4f77-5e46-08dcfdd51c72 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00029929.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5874 Prepare for an embedded structure design for driver-level iommufd_viommu objects: // include/linux/iommufd.h struct iommufd_viommu { struct iommufd_object obj; .... }; // Some IOMMU driver struct iommu_driver_viommu { struct iommufd_viommu core; .... }; It has to expose struct iommufd_object and enum iommufd_object_type from the core-level private header to the public iommufd header. Reviewed-by: Jason Gunthorpe Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_private.h | 25 +------------------------ include/linux/iommufd.h | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index 8f3c21a664bd..94cfcab7e9de 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -5,8 +5,8 @@ #define __IOMMUFD_PRIVATE_H #include +#include #include -#include #include #include #include @@ -126,29 +126,6 @@ static inline int iommufd_ucmd_respond(struct iommufd_ucmd *ucmd, return 0; } -enum iommufd_object_type { - IOMMUFD_OBJ_NONE, - IOMMUFD_OBJ_ANY = IOMMUFD_OBJ_NONE, - IOMMUFD_OBJ_DEVICE, - IOMMUFD_OBJ_HWPT_PAGING, - IOMMUFD_OBJ_HWPT_NESTED, - IOMMUFD_OBJ_IOAS, - IOMMUFD_OBJ_ACCESS, - IOMMUFD_OBJ_FAULT, -#ifdef CONFIG_IOMMUFD_TEST - IOMMUFD_OBJ_SELFTEST, -#endif - IOMMUFD_OBJ_MAX, -}; - -/* Base struct for all objects with a userspace ID handle. */ -struct iommufd_object { - refcount_t shortterm_users; - refcount_t users; - enum iommufd_object_type type; - unsigned int id; -}; - static inline bool iommufd_lock_obj(struct iommufd_object *obj) { if (!refcount_inc_not_zero(&obj->users)) diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 30f832a60ccb..22948dd03d67 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -8,6 +8,7 @@ #include #include +#include #include struct device; @@ -18,6 +19,29 @@ struct iommufd_ctx; struct iommufd_device; struct page; +enum iommufd_object_type { + IOMMUFD_OBJ_NONE, + IOMMUFD_OBJ_ANY = IOMMUFD_OBJ_NONE, + IOMMUFD_OBJ_DEVICE, + IOMMUFD_OBJ_HWPT_PAGING, + IOMMUFD_OBJ_HWPT_NESTED, + IOMMUFD_OBJ_IOAS, + IOMMUFD_OBJ_ACCESS, + IOMMUFD_OBJ_FAULT, +#ifdef CONFIG_IOMMUFD_TEST + IOMMUFD_OBJ_SELFTEST, +#endif + IOMMUFD_OBJ_MAX, +}; + +/* Base struct for all objects with a userspace ID handle. */ +struct iommufd_object { + refcount_t shortterm_users; + refcount_t users; + enum iommufd_object_type type; + unsigned int id; +}; + struct iommufd_device *iommufd_device_bind(struct iommufd_ctx *ictx, struct device *dev, u32 *id); void iommufd_device_unbind(struct iommufd_device *idev); From patchwork Tue Nov 5 20:04:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 841901 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2045.outbound.protection.outlook.com [40.107.244.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0BEC215C5D; Tue, 5 Nov 2024 20:04:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.45 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837099; cv=fail; b=hOkvITUJe2fiyZtn6E8Scv3m7nOMK99qQgcoJ6gIHGyPT6gm4cnsiy0XJ9g7QcDReL2z37ZZ63LvzQC/+qMtDZ5zYnzT5j1AtLl0szdpg/d0NMpm/mQvDmUfg/V3tt4JKDHzesh/mSVi3H9Q/98x6Pf2rxxVD20QxDXl1DqHfwk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837099; c=relaxed/simple; bh=+7G84GbJ1qm2SnmW+79pepnB/CPWxnn72/ACuXGmj9I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MrGhaFGwLoefsAOBgEV8z9QGRJt2oTjxTKyJDcm/x07pku1apDpXqVGcKbFv9jI1saVmSN+n/WTrTWZdKzpKURy0s+D6uc64GuQvLdCuUYEhRyI1v4Q1SV0bBGMWHLLr6tt8UYZK3AFpdN4Gf0HW7GhvS/IijfPeKI6uKDLYzek= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Rmh36dPF; arc=fail smtp.client-ip=40.107.244.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Rmh36dPF" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=AnD4NnhDY65iXDbowzMpFFNvBtIUAdt0uSavVguLkQEkGjL6EJrnLzySkBhuA1hiTkmxV7Du5hvu09Jy8NtKzovI6E16vwlUeEPRA0EIzSUngQAKTIYOrQPQmW9jKFrgfhVviDROrskC+zMB6nIBINz1LTEjUIDgKC6vzWPlniqyKVBFHgYOoOEjsQJ7US79DbTKKrrWmfIWIhgDww8ergBfSOyFr5ybMzwPn58TzTJwZxQu/0LviyUFWv/ZsPjoinqPnP4TFGJEMVhPyEzLWnA6sII+nXvUGvCuVe6NbUttvTpk7QL8q9l0yUpWnaraIUwVc/HuxmS8XbHw+/wAeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PpmAKFbTicc3QQsUhPxVbnnt92yo4QQil7k4I7tGIrQ=; b=jOV7F7FyfZ0tNLeH0cWY+P9u7PIrkhMJ+knFDNcJqL7jOkYptvM2m7bkd1QWHLC3nOLRfzvaL/qbgQuGcxRdeJbgXpvs/Wrl6DZuUg71NqEL+NlcgGujY2rEydwVGXwgYlsEn+Y/Et01d+XpPnrC05TN+IVliayUmSytFeAD2RIf6trVvIm57jDRqoHbLB/0rrn6TqNG2tO7U2FuQEyUf5eWxO+OHr7D+0iXc7eaVpiP7g+B8uugqoOVbIXoA2LPDpzy1EDKC8OwDAhkCCC1hZHSFzyBrVemGPy+/sZ7svDWDtttbujU1wpy0MuocXB9szDH00e4vV1wQV0j2wsnsA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PpmAKFbTicc3QQsUhPxVbnnt92yo4QQil7k4I7tGIrQ=; b=Rmh36dPFZSGOToifRnrmQ7qW3x5E78eOPkYYO5kDPzpVownTzHBDoPO3Vkr2BWnVkDuMS0hX5ANlQb0EOOdahHCAGU2Egu2DHvG0X7Aj0KZPfUvizGD56e9QIwK9TXqwW1aWsFxIBqzEMremvRzqtg04eIVu9ekXoqlJRmMbam+cz+7uWOc8oajZDR6apPzrjkOAYnI9iwZ46KfwqsYZPYjYPswVvDYxDa58rcLkdlEeSIuAGZ2yvy/KKdkorMfEh5kkHswIDrR+wn1p8hngvZyKoqAZ04K/ZDmx8f/+v9zqfaqxYbRlg4fN76N02FmVc2Za/O1xtb9mTv/QRT4Tug== Received: from BLAPR03CA0004.namprd03.prod.outlook.com (2603:10b6:208:32b::9) by CY5PR12MB6300.namprd12.prod.outlook.com (2603:10b6:930:f::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.18; Tue, 5 Nov 2024 20:04:53 +0000 Received: from BL02EPF00021F6D.namprd02.prod.outlook.com (2603:10b6:208:32b:cafe::3d) by BLAPR03CA0004.outlook.office365.com (2603:10b6:208:32b::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.31 via Frontend Transport; Tue, 5 Nov 2024 20:04:53 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00021F6D.mail.protection.outlook.com (10.167.249.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:04:53 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:41 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:41 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:39 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 02/13] iommufd: Move _iommufd_object_alloc helper to a sharable file Date: Tue, 5 Nov 2024 12:04:18 -0800 Message-ID: <2f4f6e116dc49ffb67ff6c5e8a7a8e789ab9e98e.1730836219.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6D:EE_|CY5PR12MB6300:EE_ X-MS-Office365-Filtering-Correlation-Id: f1e4483d-34bc-428c-7b97-08dcfdd51d0a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: gzpdkgTtMxlGU9euBxvtQ4LO7fsWkSUMpl0RPscwtZl06azUzpfudFSfCJBDqVwC0XIktyUUprFoIYe6vKwNoGgP/A62i16hUzDjQVtuHu/Rn7uPXovER0RRK6GABO4QZMEqLmtJnMq5qm0Yy4Ht5Tq3exWTrnVo8vj0hOU0trtspwG7o6Jhum2c9t93vZuvdHB1Lduj6fqgjEnW6OoyHoGOJPerMNB4EP14fNrLlzfWORxvV8ic4fr4R4qgN4qKa3NNVbgns4l+leF2JXBtTeyP9gSL2XgScVrXrv6EgEy7YM8Jb5T8EPl1BhwTU8xl6KMvRyTafz1Ev4sftcMKsDtyu5Ky18m50xyEs14ip365Q9SdQ+ot3hgtf8ih7ApaqoCDsAJ5XWWm4MN69mJDG0lBEAkFAr92OYp8ENQq6QLy3Lbx7Cgg3WeeCVPJFu/BU0ZTjMst8PkeIo0f940+KIUaIPzriGbaXIP/7EtojJpWJOkSoyar8tLcOQ2Vg4lajw8JrkdePEHo8NeuJoCvtasgL+3o+fEDdljfNdeS5wBP5Gnf1czjp8H9tJ/nNWQgsUKscymZa16C8DGi81/qVcvIAZTcx7lvvAajYdQnh2KmyJZgB1z0CeSXHcFaYS9J8+7XNNFiZKE2C4bZCIxgP9HFOtuM/W/yDDXn19gnic2pYEqMHgA4DiiHFmI9aVfd0/3xMWgZwtnC6FVDzoNloSm3G7pzhJFMMTRpkJOnA57EwvlwuPdxNPgIEBOwFxdf2xv9MrkbH0eO/7r9MSXRN01O7uQu/m6E7Bs2duUSMita2gkkTJ3pV2E2GjxlRdbyjGlQ5V1alwGGD5pX0EfcOlXOk7eoZr5/OnqFCqd3fOoWgwV27g1NOGuUUmOK/Pb8kbbwfaVltkMIdUyYoe1oZUzo4B/0Y34GXx8qHi4hZxW13Et9r7n0iAqkbm4/1+2tngLA1OuYbd3N1io05Eu/5V3NIllkt6tjKGnbVjP5u1M5xqNl0nNAb4Wh6H7unYDMsdxNNsfjV6AU2FJxz0XsylGe4UeHeNMnyRl4ymuaB8WEgL5Xayp/bURH6RbqcvGhhAEcGso59gLvN7Z+US1BokCcpqRuXuB0uQaMQpsBXzikL4SltLBm0gN3Afo/8tol5ge/x12TEa4DSSHkru9whg/WA05zor8iAj/z8ZtHAYmmUO0a3g39zVOlfNEjxmBQmhDboCqcQJAs8k7ng4cZph6iKJfYlQ43B3xlCwv26bn/Spma6Zmj/g9D2GjwmhgUCc8H3qjv0c3NVtPxlC+KdXScrVzai9wREPqzRnyqjvHa7dGzbSeCUobMX8ozbeULRLPYKo+HzW3Sx467PAw2PRiMi9ADEPBzkYdImo4yy7uTi9DlOgPTtfo2CyuULTM44NB4fBCrIU6SgegUxSEO6g== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:04:53.5292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1e4483d-34bc-428c-7b97-08dcfdd51d0a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6300 The following patch will add a new vIOMMU allocator that will require this _iommufd_object_alloc to be sharable with IOMMU drivers (and iommufd too). Add a new driver.c file that will be built with CONFIG_IOMMUFD_DRIVER_CORE selected by CONFIG_IOMMUFD, and put the CONFIG_DRIVER under that remaining to be selectable for drivers to build the existing iova_bitmap.c file. Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/Kconfig | 4 +++ drivers/iommu/iommufd/Makefile | 1 + drivers/iommu/iommufd/iommufd_private.h | 4 --- include/linux/iommufd.h | 13 ++++++++ drivers/iommu/iommufd/driver.c | 40 +++++++++++++++++++++++++ drivers/iommu/iommufd/main.c | 32 -------------------- 6 files changed, 58 insertions(+), 36 deletions(-) create mode 100644 drivers/iommu/iommufd/driver.c diff --git a/drivers/iommu/iommufd/Kconfig b/drivers/iommu/iommufd/Kconfig index 76656fe0470d..0a07f9449fd9 100644 --- a/drivers/iommu/iommufd/Kconfig +++ b/drivers/iommu/iommufd/Kconfig @@ -1,4 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only +config IOMMUFD_DRIVER_CORE + tristate + default (IOMMUFD_DRIVER || IOMMUFD) if IOMMUFD!=n + config IOMMUFD tristate "IOMMU Userspace API" select INTERVAL_TREE diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile index cf4605962bea..de675df52913 100644 --- a/drivers/iommu/iommufd/Makefile +++ b/drivers/iommu/iommufd/Makefile @@ -13,3 +13,4 @@ iommufd-$(CONFIG_IOMMUFD_TEST) += selftest.o obj-$(CONFIG_IOMMUFD) += iommufd.o obj-$(CONFIG_IOMMUFD_DRIVER) += iova_bitmap.o +obj-$(CONFIG_IOMMUFD_DRIVER_CORE) += driver.o diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index 94cfcab7e9de..be347f726fda 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -206,10 +206,6 @@ iommufd_object_put_and_try_destroy(struct iommufd_ctx *ictx, iommufd_object_remove(ictx, obj, obj->id, 0); } -struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx, - size_t size, - enum iommufd_object_type type); - #define __iommufd_object_alloc(ictx, ptr, type, obj) \ container_of(_iommufd_object_alloc( \ ictx, \ diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 22948dd03d67..94522d4029ca 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -135,4 +135,17 @@ static inline int iommufd_vfio_compat_set_no_iommu(struct iommufd_ctx *ictx) return -EOPNOTSUPP; } #endif /* CONFIG_IOMMUFD */ + +#if IS_ENABLED(CONFIG_IOMMUFD_DRIVER_CORE) +struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx, + size_t size, + enum iommufd_object_type type); +#else /* !CONFIG_IOMMUFD_DRIVER_CORE */ +static inline struct iommufd_object * +_iommufd_object_alloc(struct iommufd_ctx *ictx, size_t size, + enum iommufd_object_type type) +{ + return ERR_PTR(-EOPNOTSUPP); +} +#endif /* CONFIG_IOMMUFD_DRIVER_CORE */ #endif diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c new file mode 100644 index 000000000000..2bc47d92a0ab --- /dev/null +++ b/drivers/iommu/iommufd/driver.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES + */ +#include "iommufd_private.h" + +struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx, + size_t size, + enum iommufd_object_type type) +{ + struct iommufd_object *obj; + int rc; + + obj = kzalloc(size, GFP_KERNEL_ACCOUNT); + if (!obj) + return ERR_PTR(-ENOMEM); + obj->type = type; + /* Starts out bias'd by 1 until it is removed from the xarray */ + refcount_set(&obj->shortterm_users, 1); + refcount_set(&obj->users, 1); + + /* + * Reserve an ID in the xarray but do not publish the pointer yet since + * the caller hasn't initialized it yet. Once the pointer is published + * in the xarray and visible to other threads we can't reliably destroy + * it anymore, so the caller must complete all errorable operations + * before calling iommufd_object_finalize(). + */ + rc = xa_alloc(&ictx->objects, &obj->id, XA_ZERO_ENTRY, xa_limit_31b, + GFP_KERNEL_ACCOUNT); + if (rc) + goto out_free; + return obj; +out_free: + kfree(obj); + return ERR_PTR(rc); +} +EXPORT_SYMBOL_NS_GPL(_iommufd_object_alloc, IOMMUFD); + +MODULE_DESCRIPTION("iommufd code shared with builtin modules"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 826a2b2be52f..3c32b440471b 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -29,38 +29,6 @@ struct iommufd_object_ops { static const struct iommufd_object_ops iommufd_object_ops[]; static struct miscdevice vfio_misc_dev; -struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx, - size_t size, - enum iommufd_object_type type) -{ - struct iommufd_object *obj; - int rc; - - obj = kzalloc(size, GFP_KERNEL_ACCOUNT); - if (!obj) - return ERR_PTR(-ENOMEM); - obj->type = type; - /* Starts out bias'd by 1 until it is removed from the xarray */ - refcount_set(&obj->shortterm_users, 1); - refcount_set(&obj->users, 1); - - /* - * Reserve an ID in the xarray but do not publish the pointer yet since - * the caller hasn't initialized it yet. Once the pointer is published - * in the xarray and visible to other threads we can't reliably destroy - * it anymore, so the caller must complete all errorable operations - * before calling iommufd_object_finalize(). - */ - rc = xa_alloc(&ictx->objects, &obj->id, XA_ZERO_ENTRY, - xa_limit_31b, GFP_KERNEL_ACCOUNT); - if (rc) - goto out_free; - return obj; -out_free: - kfree(obj); - return ERR_PTR(rc); -} - /* * Allow concurrent access to the object. * From patchwork Tue Nov 5 20:04:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 840945 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2053.outbound.protection.outlook.com [40.107.244.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9154E215F57; Tue, 5 Nov 2024 20:05:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.53 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837104; cv=fail; b=b3loV+5fQYqOt6ApvcI7ER28W33qb+jqaQ4Q+SGTSXrQXf065+cors/lpADJlxXZGcqnukjJPZ+zZb4nXIxChBiiQX+N3oKLSKZHY6DSRqXe2FPzq/8GqHDEblSaTSXeFlNhEdVlnDPRlYI81jKiBavC+Kv22c+AQdT5vJ/QT6E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837104; c=relaxed/simple; bh=hCFev36SssAvNAj4ePzCjgjWEUTEU7hBmMoLdbzmq9I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tJQ38tcP7sAMUy784puYjfi4vh6wuuuaf95oYMeVqXPQYHc/NwleFTGF4NmpVeiLWJU/mkef76VHhtyZ6Z5bKk191wZOaQBAK4l1J651a/6XzrDh63IW3mX8uKimAbPwOLreZ4GVlB01OY2TugxPvX0rFg26UBFnOKoJafBfGGE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=hQ8SDEIw; arc=fail smtp.client-ip=40.107.244.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="hQ8SDEIw" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nL0KMy3trYRTjoJpE1VUgrsxS40LgN68f5uxCxhoLKi90LD5Z6BDsqsaG/VSTqBm+rQOzWSCYqZ7YuY2H0AfW6V4HytCbIP64DFN9Bvzv9CFlapWfa/JwihMT2ZfodaoleZhbCuJyM9eDXceNwdDoelZWjTHRrzYtiGVIWhJ7YSxh5iaFpz4HtVid+f/6F1E1Q0Z3zhT3oKw/GYxg2/yTFkt68jpH2SohtEThVvjzTFwIPbFpFsZYsrCt5P30i5iICNe2lCPpSb5H8kQUez9gZJJ3hr/D0c51hlTMk5qeACqYXzPMOkusiP9T9o8flNbPBrEU0GTGNS4usrusETLog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KeLwBl0Lzx6OjJFGG4jla+hnp4tMo9mXkAX5K9Oq5Rw=; b=cE/Y4BVpJZUEMDOd2w1HVtjAoelMHSoKxkWgshCpbKKHJO3hV0ASWlRWeWlbJrvJ6IZ8ihkFa/3KYGYmclNZgumgT2tiI36TkAmaly7dxoiKO//wE5hq5V3v5GMnWBxCrOjKS1Cd4EEkCfzb0tEhavOQVBZ/o4kz2dyB+f+L3dlydAoj6W9sYcpSG2aSyEFoB4BcCPcVtwuigp0AcH9g8DIvPlhoh3S5KhRH3aBN8tWNxj5pxIZEL+2ZES7H/cK1WcIymqplQH81x30CBLDHzKhjPpBTnO2yBvIQ8ErW32qyyAUYXvIsGvSiXuG2sW29dj5y+ufnc7+TpCJp1fxUSg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KeLwBl0Lzx6OjJFGG4jla+hnp4tMo9mXkAX5K9Oq5Rw=; b=hQ8SDEIw3pOhnj98sPdKbYIUrNJYhtLqbele/X5CYrjqmrHEGMejjLpUTA0VJcKnJQ7ByVpE2rjL56NDzgLiawVm5DGfMNsI7CuyQbSktp57ObiO/J1pebq1Ddwuo8811roRuiKQssao9ax8RMPLhqDI3rn6GWKzH6pL3k7CS3UvZJXFMXQiFuvSSjHaictxJt0YC4UufWSkIJYM71GFda9FJNccwFemjV/iGNrso6wql1RUjAZgsi1MqoExHcE6KLAQIEwX6+RIe0orZZPkBU+pICjwnRZQccMTyjwWf3M7Pi1c/KvkaSjm6ugtiFJf0COr/LKQIQvOiZn5ZrzvYQ== Received: from BL6PEPF00013E08.NAMP222.PROD.OUTLOOK.COM (2603:10b6:22e:400:0:1001:0:5) by LV8PR12MB9084.namprd12.prod.outlook.com (2603:10b6:408:18e::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.30; Tue, 5 Nov 2024 20:04:56 +0000 Received: from BL02EPF00021F6E.namprd02.prod.outlook.com (2a01:111:f403:f901::8) by BL6PEPF00013E08.outlook.office365.com (2603:1036:903:4::4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.20 via Frontend Transport; Tue, 5 Nov 2024 20:04:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00021F6E.mail.protection.outlook.com (10.167.249.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:04:56 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:43 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:42 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:41 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 03/13] iommufd: Introduce IOMMUFD_OBJ_VIOMMU and its related struct Date: Tue, 5 Nov 2024 12:04:19 -0800 Message-ID: <64685e2b79dea0f1dc56f6ede04809b72d578935.1730836219.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6E:EE_|LV8PR12MB9084:EE_ X-MS-Office365-Filtering-Correlation-Id: b60c9f2a-9ab3-4030-b254-08dcfdd51eaf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: wUYhZtFu7GaFjs793bVI6NTjxjjmhM1DnlV/L9mO6/Hzs9uQl2rAlL7h/9GG7TXyv9M08q97yeTjsfmDw//BZQpujgHv8cRoY925uyCPcb8F4djmik+ftX9uBdNAONlZvqoDeuwyhxE/hZExX/F+LEmKjSlk+8uqcHvNmK9/IPM8DJ637+vEDhsMvG80hzB5UdcoToC7WejgnPXyajsFziiPSJbi8+d+mGi5X/+dNbYjDkx987mGJiLStpo36zATuHJ/y+H+AkEkDOa9soII5m/1bfVbGdb1srTXD5Y9tl8FGafK6wuArXHTFj90v27tmk2LgiuWuRnYql5FenYro6zdaERmmBpGia2KI6lczbIBz3aCeDI5cHgjc4n+1PiIXRvF4MZa6O6jy6tfSu6sclEA5OyY/D+CnnvY1xid/wABkGYjvvCAUlY5qHinlxnqkUdh+VHr8btpCqNnxXlbKU5bORzIIX+KWHGTKIn3dJG911OC7yHmzX2wBGiy0CA0xTV6oTzdbVWSyxJhcfjVDXSk1HVEoWKI8kzWnl3S4YDeRzuK0/OvgI61DJxnFd9GlzUDhtJe42/yhV6WbKcRRNd+fitFcUUIWbNM3PfnjtWM4W6IpUkoWaq10xqWlzSp3+9epvhZJcEs3dn8og62ZR1GUW9jpzfIdmHNhY3UJMPR+2JdK9VUsv7XGdafyWaZL4mYbqmFf6UImbZVvmAdVdse+Sl4O9PFVXXov2QZgjBVkPC0pqmaueU7NlUqFJPF0dv9zLHev8/JIB55iZyIDIex6k5aoTF2k6tg1ipeJB2zLYX2gWSUbqbIEnC3FLdNsAuLu4HZK3e6Mai74BPctzURzftEvE0rp0j1qfyH0qml/WMReL/0I1O6lohbAZJGuDNFqn3ShvQhZHXTj5tUTSVRmFXPeRkV4KHtLXhUnVy2fMjLhRbI+YgXhuzjauFLKbTuDUHLrhEsbgt2hl9dF6gg735BhqQkiuOLYslMwCQRKaszOxpSBQOT5p0POsNuYtJNiHEUzQCux5xmBbO4YwKvvCXPRU5XlsOZ1ezLZMvvYYBHi2YRD8tdHdXl4ibl2EjKgeZPcNmKt9RPEZTNS+KphkcWo1fGELSvJNddGA9BjOf6Ik0PrKIdSEQOzRi8zbBtIpOPyEoNtwGtcRLKQ2UgHHtJTDZMEpVl/9sPQAe6CVpr5I7Dtty00dxcaZF/hKV+jb630Phwz8FQOtq3EU09BAgU+c1net4+n6ku0hjpeQNhR8EVA3KjVjQL2Srw2qfwxX0z/FO/nx2OoajcbHidvDwnYG8ASXmoRvJUfmnOGhuww6mI1ghWfk0DbnpqE0qtiPrC86xg5PPGUSDiEmpfyKWt7v45cR3NEMKx+JKOG5xZ/w908UT55/XLruJTRpNC3fKfv186Gt1Q49iYpQ== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(82310400026)(7416014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:04:56.2428 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b60c9f2a-9ab3-4030-b254-08dcfdd51eaf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9084 Add a new IOMMUFD_OBJ_VIOMMU with an iommufd_viommu structure to represent a slice of physical IOMMU device passed to or shared with a user space VM. This slice, now a vIOMMU object, is a group of virtualization resources of a physical IOMMU's, such as: - Security namespace for guest owned ID, e.g. guest-controlled cache tags - Non-device-affiliated event reporting, e.g. invalidation queue errors - Access to a sharable nesting parent pagetable across physical IOMMUs - Virtualization of various platforms IDs, e.g. RIDs and others - Delivery of paravirtualized invalidation - Direct assigned invalidation queues - Direct assigned interrupts Add a new viommu_alloc op in iommu_ops, for drivers to allocate their own vIOMMU structures. And this allocation also needs a free(), so add struct iommufd_viommu_ops. To simplify a vIOMMU allocation, provide a iommufd_viommu_alloc() helper. It's suggested that a driver should embed a core-level viommu structure in its driver-level viommu struct and call the iommufd_viommu_alloc() helper, meanwhile the driver can also implement a viommu ops: struct my_driver_viommu { struct iommufd_viommu core; /* driver-owned properties/features */ .... }; static const struct iommufd_viommu_ops my_driver_viommu_ops = { .free = my_driver_viommu_free, /* future ops for virtualization features */ .... }; static struct iommufd_viommu my_driver_viommu_alloc(...) { struct my_driver_viommu *my_viommu = iommufd_viommu_alloc(ictx, my_driver_viommu, core, my_driver_viommu_ops); /* Init my_viommu and related HW feature */ .... return &my_viommu->core; } static struct iommu_domain_ops my_driver_domain_ops = { .... .viommu_alloc = my_driver_viommu_alloc, }; Suggested-by: Jason Gunthorpe Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- include/linux/iommu.h | 14 ++++++++++++++ include/linux/iommufd.h | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index bd722f473635..2574fc8abaf2 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -42,6 +42,8 @@ struct notifier_block; struct iommu_sva; struct iommu_dma_cookie; struct iommu_fault_param; +struct iommufd_ctx; +struct iommufd_viommu; #define IOMMU_FAULT_PERM_READ (1 << 0) /* read */ #define IOMMU_FAULT_PERM_WRITE (1 << 1) /* write */ @@ -542,6 +544,14 @@ static inline int __iommu_copy_struct_from_user_array( * @remove_dev_pasid: Remove any translation configurations of a specific * pasid, so that any DMA transactions with this pasid * will be blocked by the hardware. + * @viommu_alloc: Allocate an iommufd_viommu on a physical IOMMU instance behind + * the @dev, as the set of virtualization resources shared/passed + * to user space IOMMU instance. And associate it with a nesting + * @parent_domain. The @viommu_type must be defined in the header + * include/uapi/linux/iommufd.h + * It is required to call iommufd_viommu_alloc() helper for + * a bundled allocation of the core and the driver structures, + * using the given @ictx pointer. * @pgsize_bitmap: bitmap of all possible supported page sizes * @owner: Driver module providing these ops * @identity_domain: An always available, always attachable identity @@ -591,6 +601,10 @@ struct iommu_ops { void (*remove_dev_pasid)(struct device *dev, ioasid_t pasid, struct iommu_domain *domain); + struct iommufd_viommu *(*viommu_alloc)( + struct device *dev, struct iommu_domain *parent_domain, + struct iommufd_ctx *ictx, unsigned int viommu_type); + const struct iommu_domain_ops *default_domain_ops; unsigned long pgsize_bitmap; struct module *owner; diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 94522d4029ca..4fc2ce332f10 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -17,6 +17,7 @@ struct iommu_group; struct iommufd_access; struct iommufd_ctx; struct iommufd_device; +struct iommufd_viommu_ops; struct page; enum iommufd_object_type { @@ -28,6 +29,7 @@ enum iommufd_object_type { IOMMUFD_OBJ_IOAS, IOMMUFD_OBJ_ACCESS, IOMMUFD_OBJ_FAULT, + IOMMUFD_OBJ_VIOMMU, #ifdef CONFIG_IOMMUFD_TEST IOMMUFD_OBJ_SELFTEST, #endif @@ -78,6 +80,26 @@ void iommufd_access_detach(struct iommufd_access *access); void iommufd_ctx_get(struct iommufd_ctx *ictx); +struct iommufd_viommu { + struct iommufd_object obj; + struct iommufd_ctx *ictx; + struct iommu_device *iommu_dev; + struct iommufd_hwpt_paging *hwpt; + + const struct iommufd_viommu_ops *ops; + + unsigned int type; +}; + +/** + * struct iommufd_viommu_ops - vIOMMU specific operations + * @destroy: Clean up all driver-specific parts of an iommufd_viommu. The memory + * of the vIOMMU will be free-ed by iommufd core after calling this op + */ +struct iommufd_viommu_ops { + void (*destroy)(struct iommufd_viommu *viommu); +}; + #if IS_ENABLED(CONFIG_IOMMUFD) struct iommufd_ctx *iommufd_ctx_from_file(struct file *file); struct iommufd_ctx *iommufd_ctx_from_fd(int fd); @@ -148,4 +170,22 @@ _iommufd_object_alloc(struct iommufd_ctx *ictx, size_t size, return ERR_PTR(-EOPNOTSUPP); } #endif /* CONFIG_IOMMUFD_DRIVER_CORE */ + +/* + * Helpers for IOMMU driver to allocate driver structures that will be freed by + * the iommufd core. The free op will be called prior to freeing the memory. + */ +#define iommufd_viommu_alloc(ictx, drv_struct, member, viommu_ops) \ + ({ \ + drv_struct *ret; \ + \ + static_assert(__same_type(struct iommufd_viommu, \ + ((drv_struct *)NULL)->member)); \ + static_assert(offsetof(drv_struct, member.obj) == 0); \ + ret = (drv_struct *)_iommufd_object_alloc( \ + ictx, sizeof(drv_struct), IOMMUFD_OBJ_VIOMMU); \ + if (!IS_ERR(ret)) \ + ret->member.ops = viommu_ops; \ + ret; \ + }) #endif From patchwork Tue Nov 5 20:04:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 841900 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2081.outbound.protection.outlook.com [40.107.101.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11A7E215F7B; Tue, 5 Nov 2024 20:05:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.101.81 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837104; cv=fail; b=krs/cYAZsfcWu0votgfYRG/lHdRpIK+S1a9DzZrIT/g4jkqohlTwBPiKm925Y0bK5b53GIqXH8jibK1p27JjNA1OE4i/4Lpuvpm68FskWDv0YnumA0VF7U9NqGNvc58RLOo+GJ9ukO2EYlqtag2q2ivNmx6ExOow40W3n0PrWf4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837104; c=relaxed/simple; bh=a1M6Xj+EOY5vqxY6NF5R7ZIef0s0hyjAALFMQRLuQmY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GRJgJww4VsyBGdLQgqJijCO7Yu7wapr/AuLpkak+ufdL6I2nmPkguGeheIVw3SPN+bRybDlNUsJRuBnXk54UEgRSXpFy/3assck2KBdid9hESsAiXmNGCGndcQs5YDF0ZW0AZa+hu8NL0ZJImu6KDuPmmaVthMJ2HKZDEzgIUn4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=hthQlDLg; arc=fail smtp.client-ip=40.107.101.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="hthQlDLg" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nxrKTFCy9oJDp1LilBJN9FLj+hsdf25jZ+WiWyG7iXYTC7QFbLxmQ+/vNM4EkUMqdLFCOSZyEWucIz0DY+LfaSwtAJg5RB2tn1Iik7ZlV2cWEccTtL0Df3BpWxfPdJr6PPX2OMPuh+KUgeF8wwYxlC6dSuArJ45k3O2pTN16AXJzNUj6/ZC8LpKIx8BLaIBdyv/6Zdw7wippKC7JSrpHb7b9uIxdDraoPjVE6TiFttQaC0rt+Quv9z7sIOPPofYn9cNvepTm+y+rlH2LfFxF2oQOBImXv74zaCV3/ftC/KZZpSlcsIgl6I3NsoSQdoq3FlacTyQDl7fMVcJD0aWN+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Uxl5BKf2cVFR686YBxEPCCNYlfJjglgJwFZ2tFWJnjQ=; b=e7qkoolhI2EFaftffKXlEgZC7UEBhxx1tt3tLYFRKKrf+0CK899GpJepXzUNijLWiH7twFOKuWKkzXGgCzE8VCe46lvEto12iIgAc1f/KixsnUIkEzpXxj89NjTZin+T8GohTcR5hLs1Ajzo4AsjdiG1Y0IYuuQ9Xc2NB8Hld+sICWbwo8G4b4Ae4CfgMRCCmcvvtdz/AKPg2qyYcSPl2sMVHgF36Y25CxXeb3930tXSJDXD0PfSyYCfAPYqqy/FLJt9TT2Ro/i1QhJxIZAo6fak8ok2mB2WEmsLMFxWrNgruzTrehxeLmZMDhJFTElg9W6MiuW6uBhcMlSoTPNKzA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Uxl5BKf2cVFR686YBxEPCCNYlfJjglgJwFZ2tFWJnjQ=; b=hthQlDLgLPjjX03l16x4LdInl6ocGoleOYxupWjR/V1uSB9h3aachuy8EyTFoRs9pnvKb6aq8qzFKNCXlWG86EK2StDFMuZwpT96JNEZDJQ8ZRidf1GeU2Uo+Ub+3qpDAVztTdconbnSIfY1ksjZAdBB1gnFWBQsOX1yY8rAbocXnmia8DDpa3IZiZImS4LTmmd2NvVhbn49oL1t7Y1gMbeJXdxC0xPCECA85vf7GZYz/pGs09xkXYoIhFvvp9UcL4TUqN3w0eI/ESzWx3AixtRoqIJ5BxKeHQz2c+hd0Fg0ZCenklVW7R5K+hs6f0IQxFQEX7V6MSHcgd/iB5rxLQ== Received: from BL6PEPF00013DF6.NAMP222.PROD.OUTLOOK.COM (2603:10b6:22e:400:0:1001:0:a) by PH7PR12MB5596.namprd12.prod.outlook.com (2603:10b6:510:136::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.18; Tue, 5 Nov 2024 20:04:59 +0000 Received: from BL02EPF00021F6E.namprd02.prod.outlook.com (2a01:111:f403:f901::8) by BL6PEPF00013DF6.outlook.office365.com (2603:1036:903:4::4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.26 via Frontend Transport; Tue, 5 Nov 2024 20:04:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00021F6E.mail.protection.outlook.com (10.167.249.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:04:59 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:45 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:44 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:43 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 04/13] iommufd: Verify object in iommufd_object_finalize/abort() Date: Tue, 5 Nov 2024 12:04:20 -0800 Message-ID: <334bd4dde8e0a88eb30fa67eeef61827cdb546f9.1730836219.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6E:EE_|PH7PR12MB5596:EE_ X-MS-Office365-Filtering-Correlation-Id: 5033ea0f-52bb-4443-ed6e-08dcfdd5206f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: JDUd2rgUKuUJiaxwA/HUFNzZP2VJv7LYoV6EUK/caJc86Ryc8cgz3vz882gdWhf4R6i7MLBnYlh098SPHS2GMWr5nGl2bl44lv+SvVhEoNjOBZUOpZMbvkqW7H4J1NFGCzNq7j5IpAIpc9ZCm14BVT5uSKqD4G1dAukANWPRE6K0ez2ahVs4+dIamCLgXQ9DKv83HxBVFB5mEYbj+t5gxTMbGEmOABsEGicOGjgl8DPcz6Wnvf5vgqt+/LSfwE55+z3a/aB/KHmJ1T8xxjpLdvh6xFwbLxTiJcfCGl96lF8QQN1tpZui1RQ9eTDefJCdKcUi2mnSyEiJhmYn0TzDAIcNyV7GmxUgMrzZl7qjyot8+8htcdpsNxm72vsf3GY+CWvo+C4fuQMfmOFJ6B2Gb32VqugXoiMklZ2795aVWasyhskEgwTWljJyykVc4OMOP8UGqAlooSFBZCwBLs8tLCwJOgpsJW/kTYDQ4OQR86EGp4ZNA8LLOorBrvhu73FDbKB+p41nR6N6st8q++KeSljCD4azz7+5UaHuzfvpLqBwGIWR8AEFrnmaAsLfoAFGx8+hkab7PG9mLkPlsCebwXqanXK55GoPeH5u9ha+ZBCAOBSKfqoTnXzFyowOVRlN7eSmD6/WlDzuvsga5YuZ269S3mKGIcQtDeVGISiVJK6cI5Y4fGEg4xUdFgu+5zzqP7oS9GiDOHvx25LwifQN1yW0URrthyenLKl7u7fgV2rUwCBxVGmHEDqMDO+4mrOOfZS7ET1VEt+4MYm2aBDNDHOr3oC2jrrtm3PkSwgJRg3vRVQ7ZVgrV/3qBRdWIamtGDf9QSJAadvvCgoXhWJ80VlnrIyfkMgr6erXToY7rfQZhAHWv7ij9JXPu73t0/9HkVTgM7R/WLd2aSM2gPzlIZQqYqn7ScIv3QUqsN2ZDeIPWT8oX/Jc9eWHDttNTpwrKhe+cOs2fqx1aHaLkXYjzk89P/RFhq9DTg6oDWMgASj8oscAigzbb20EUxcaYSwXCnPlFaYZLKUdm6TNGEqNaZmOj/WZLIA0m8ePW9tMRFad346SsARStQVTijW+AxAjwihZSkfFkBy+sur+WS5EC5mRNRUgiS6vMPan69w3KQt8f5ZrBBr6aF4vzAELOpstTDGbPoGB7XrINzVeIB/jTHqZQsr2cexBnJrruAJ2/hZorra4cZf7S6u/d5Ql092Vaid2+Kjdp0YwoEIBTlfDxvKH4veojFJcaO+CaI251igYiJlZoQnujGfbKkSjHW8lQSejmLpRf6GZajzbb3HpRvBJQqdMCfOgysZDjOjFou4s+OwND41MSkoGDH+/VA70DP6wEBF23qfI5u8uR4oGzDKAOvvmzKcT/Zp835Yan8afcCBLvWufVR4HWdDnaLdTv4MtxbPYXP1AnJf1AT9ByA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:04:59.1804 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5033ea0f-52bb-4443-ed6e-08dcfdd5206f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5596 To support driver-allocated vIOMMU objects, it's required for IOMMU driver to call the provided iommufd_viommu_alloc helper to embed the core struct. However, there is no guarantee that every driver will call it and allocate objects properly. Make the iommufd_object_finalize/abort functions more robust to verify if the xarray slot indexed by the input obj->id is having an XA_ZERO_ENTRY, which is the reserved value stored by xa_alloc via iommufd_object_alloc. Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/main.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 3c32b440471b..30e6c2af3b45 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -41,20 +41,26 @@ static struct miscdevice vfio_misc_dev; void iommufd_object_finalize(struct iommufd_ctx *ictx, struct iommufd_object *obj) { + XA_STATE(xas, &ictx->objects, obj->id); void *old; - old = xa_store(&ictx->objects, obj->id, obj, GFP_KERNEL); - /* obj->id was returned from xa_alloc() so the xa_store() cannot fail */ - WARN_ON(old); + xa_lock(&ictx->objects); + old = xas_store(&xas, obj); + xa_unlock(&ictx->objects); + /* obj->id was returned from xa_alloc() so the xas_store() cannot fail */ + WARN_ON(old != XA_ZERO_ENTRY); } /* Undo _iommufd_object_alloc() if iommufd_object_finalize() was not called */ void iommufd_object_abort(struct iommufd_ctx *ictx, struct iommufd_object *obj) { + XA_STATE(xas, &ictx->objects, obj->id); void *old; - old = xa_erase(&ictx->objects, obj->id); - WARN_ON(old); + xa_lock(&ictx->objects); + old = xas_store(&xas, NULL); + xa_unlock(&ictx->objects); + WARN_ON(old != XA_ZERO_ENTRY); kfree(obj); } From patchwork Tue Nov 5 20:04:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 841899 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2063.outbound.protection.outlook.com [40.107.94.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1248C215C7A; Tue, 5 Nov 2024 20:05:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.63 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837109; cv=fail; b=KvhztnJO3Bg9tv40zEqO8aXU/49kOqRFm1QvjxIcmPXqNoXuhBLFsX/PJIFEmIOTkETAGVoHMPfjyBVIbkZ0c7ldJm/XIKlbwDKOemVRhiNmmUx7MppgX54dx5Lr0RvYNJMZrho8vLnsCE72QqpdtHwAWop5cohXYFROCFAfdyc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837109; c=relaxed/simple; bh=tIFadCIZtR9rHxbbxoRX1CXGPDdeWzKo2pkk18HFys0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=naRR181yRKb5MPwy/MGdLV2rGAKj+wopt4wN4tWR84DqviwYuIy6722y4S9it1dPqlWtQBH9gk0ST8w53DDMbiVSJEVsfLcflQzJ9G/jy2hgyfgwdkAZT6jagwPUKrTchgQLNDSxco/QmF2DFgMH69TXsJPM4EpnaG6kB2ky0w8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=T8kXirZ2; arc=fail smtp.client-ip=40.107.94.63 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="T8kXirZ2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=jNNPBpupYxvDgya9ee86LJZDsGyB7KWHBxir+rzG6r/6NGxFuRgLJKv3CZwRjW8voa1TXr8c4vlRz46zumLgR/xTRvOgiecjtsV6IE7zzK5Tasq5dsFm0rTFm926QxnTxrnntgCZ9N7SaPJmLilRHtCWAQGWiVDFcZ4DxBTH9549uz7HMXdNMKTWuuI8UF5StPHHdz9M8K2OBjZ/SLS9Q0QvsUwIzCryaHno3iAHnA+1fUG6rJ81jO1HhwkHqt2hFMKAkiKDGpPEKw1OO0i0dkRRTWSLuzKz2BG/X5JsLJUcwdn0y/jcj9L7ViBCNfrCgL1CQjK0WAfciDBf5tn5TA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZOS47/eOsBy30CAGYZswnG/R+HoLPXvbTJ1xbqY66gI=; b=KQqCi9yAgqk4AKPWZhUbPc79sKHYPHuBSdKIX+E+j/zFqiTe+DSMstjnn64/W4eXNgtvHG29I8lCjWOzyyY6yhUbTaXN6SpFesOjjxLqXGv0GJDhJChqgazfqeKHjDQAM3Eb8CKyBf1LYxbrp3JhU7XErBdm8WwleIhd0sliOhjhu0W3VcmTDaY+rORme1bXdlvFybZp4ot1if87A9XzfricWecYSAffzrAIbEz3nBdFdMgtZO+p39X3LIUqg4g7OEJKibRzeZHlpJwubwBfS0K70/rvAnaulIL9QAy7/292C74QPRz5KtmCCLsyrfFS63JDd0UVoxeD0UxkCUSjlQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZOS47/eOsBy30CAGYZswnG/R+HoLPXvbTJ1xbqY66gI=; b=T8kXirZ2Fb1JvTF0KcmW6E6GWFvB9mAclXbdMBod+XPdkndObpXMhXmTkcisseCn3MHX8OGDROSA1WqeFL9mjhPTPyUOAyhwvijwKQbVpylRiVU/5aVXrwVg+b6CfVUqiwBVyzYOClMkNs2eopWCoui9HqKbQGCFxucOKpcGDLw4muog2kIu735w1wlMuWaoI5Z8ul9k3QsQFpGdRwqUwxRYZR92KgLuZYTzmD5zREH6MVgdbMagG8PakMQZp77MsMoKkjFftQGKq+HovAstt5FVTZ1UpGwVC1bMOJgp1SkX41eO7YWIT2sVCQKGwsGg+t5W/2D7fTaKhPv1EuOZVQ== Received: from BLAPR03CA0022.namprd03.prod.outlook.com (2603:10b6:208:32b::27) by DM4PR12MB7767.namprd12.prod.outlook.com (2603:10b6:8:100::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.18; Tue, 5 Nov 2024 20:05:01 +0000 Received: from BL02EPF00021F6D.namprd02.prod.outlook.com (2603:10b6:208:32b:cafe::55) by BLAPR03CA0022.outlook.office365.com (2603:10b6:208:32b::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.18 via Frontend Transport; Tue, 5 Nov 2024 20:05:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00021F6D.mail.protection.outlook.com (10.167.249.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:05:01 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:46 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:46 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:45 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 05/13] iommufd/viommu: Add IOMMU_VIOMMU_ALLOC ioctl Date: Tue, 5 Nov 2024 12:04:21 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6D:EE_|DM4PR12MB7767:EE_ X-MS-Office365-Filtering-Correlation-Id: c9282df3-f851-4ed2-bae4-08dcfdd5219a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: +bSDSN1B7AvQV2bDUlhFSag4RPKUVKbhqvApx6eI7eYYLYalqGi2GCXpzuNhL7wgSWm2eWwFid71HNXEJZUYu2IyhzW+7+djK9qn0Jp6BWPeBD6GcVXn0ZRKc4oDxoKnBDE38a5RW2qmPwVxL1yOhjwZwom5DqWxcybzpiJh77//Qed2xYnUkHjpGYNi2KEk7NqX6D+FPYA4PxUB7z5LzZjCePP7YrXFaLXP2t3XdUIxsgbHlMPDaQzzPmyrbyNjfrw1klszT6Qdp0zkDWu+aJKQzcCaIy9Lzf8kl4XFbd0OcyLjdxtlrnMheufO6DnCtTz9VP3kqdkw6e1rZSxVD6tPICCVFTpxzhxz4sUGssgKfnF+IiTHz8PQy9S9EJuk1RgjQL4CF1RRar3MUjoopRRfYPPRh4Gc9oJpxHw7wc6H9NSnBVXFhzJcgzPHRpjACGGXCt946HB4nsBvDEo+3Vm9NryuZjim5EnUnSu7FURacfY+MJue51RT0pyXBBWeV4A7yY4hYnKDLxvlxxROlIkBJuxJ/DeTumyKw8DMlcVA9dPJjlcAuS9uzyKExkkE2w18q6Sd7GEd5Jz8VT1AEVo+J3u6atJEZW9IHsIUJs5PcElq+S0QVOJk9NsXElXrteXixXyEWiuf2qr6buZ0rFrHNsLiiS3eNrxptGCdWo4o3zIfmDFTCZm2rdpV1azMbZwqFkfuYVTsKRfHfe1eL2uK6vakypo6d/tHncAK8ant19vsvuJjnI8VB18PaX0HPZySk9jrmvkWcVT3AnL2llDuEUW5wKwcqeWWKMR1OrB+WgPL+WlUgThSso4VQS3AZT5IDFOCnLzJ+IlKwpkwqk/p2lSgasqsrE+smGPIHqzdIfZ0hkEwLqaKHCqMN2hdOWgCpWu7ycnCOawHovgLj5pJmKh8Lj187C0DhExj5HX+48c7iunVvGcRdclZJOVJAGbXg1knfFORFt2I5PPS9e/OJKCbloTn7OLyyEh0/hYZG5zefr7+mtytHvM7YnPm/gR/ktVY8RPJQDS+0yaaETn8gzGo4p+yhI9AkUyTAweRNJcu0ZIaadpMBCOPIauqApWbDNyCt04w1psDKf/zbWuXTad46ZOAsUNaP5MT1GkFaZC6bgPNFUCXk01Ko113EkjjxGLV0n+PK2RPTK8Gw1xJk4u6DrZpEerDHfi5MZtV8CJoQRarFiuxmyublRqEysqkISx8IIx18k98AXOh1fLDz+1V1lCccqELGkg+DzcsMZ5rUITpD47qe40Na4667w+sU1W3GT4f7EhAi68B6VphiueEMiPPgbXm/33qqRS7SW8RijVdH6OW+pUl2eI5MPJFF/CX5LZHFUsJGEvn54z9fcMXy1cfd50yfkSdkVmdvXZpLV0kcxWmp7wDn/hh8BFa+DuUXXpInfsosTfznw== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(376014)(7416014)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:05:01.1386 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c9282df3-f851-4ed2-bae4-08dcfdd5219a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7767 Add a new ioctl for user space to do a vIOMMU allocation. It must be based on a nesting parent HWPT, so take its refcount. IOMMU driver wanting to support vIOMMUs must define its IOMMU_VIOMMU_TYPE_ in the uAPI header and implement a viommu_alloc op in its iommu_ops. Reviewed-by: Jason Gunthorpe Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/Makefile | 3 +- drivers/iommu/iommufd/iommufd_private.h | 3 + include/uapi/linux/iommufd.h | 40 ++++++++++++ drivers/iommu/iommufd/main.c | 6 ++ drivers/iommu/iommufd/viommu.c | 81 +++++++++++++++++++++++++ 5 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 drivers/iommu/iommufd/viommu.c diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile index de675df52913..9e321140cccd 100644 --- a/drivers/iommu/iommufd/Makefile +++ b/drivers/iommu/iommufd/Makefile @@ -7,7 +7,8 @@ iommufd-y := \ ioas.o \ main.o \ pages.o \ - vfio_compat.o + vfio_compat.o \ + viommu.o iommufd-$(CONFIG_IOMMUFD_TEST) += selftest.o diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index be347f726fda..a8104d9d4cef 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -506,6 +506,9 @@ static inline int iommufd_hwpt_replace_device(struct iommufd_device *idev, return iommu_group_replace_domain(idev->igroup->group, hwpt->domain); } +int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucmd); +void iommufd_viommu_destroy(struct iommufd_object *obj); + #ifdef CONFIG_IOMMUFD_TEST int iommufd_test(struct iommufd_ucmd *ucmd); void iommufd_selftest_destroy(struct iommufd_object *obj); diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 41b1a01e9293..302844136b02 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -52,6 +52,7 @@ enum { IOMMUFD_CMD_HWPT_INVALIDATE = 0x8d, IOMMUFD_CMD_FAULT_QUEUE_ALLOC = 0x8e, IOMMUFD_CMD_IOAS_MAP_FILE = 0x8f, + IOMMUFD_CMD_VIOMMU_ALLOC = 0x90, }; /** @@ -822,4 +823,43 @@ struct iommu_fault_alloc { __u32 out_fault_fd; }; #define IOMMU_FAULT_QUEUE_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_FAULT_QUEUE_ALLOC) + +/** + * enum iommu_viommu_type - Virtual IOMMU Type + * @IOMMU_VIOMMU_TYPE_DEFAULT: Reserved for future use + */ +enum iommu_viommu_type { + IOMMU_VIOMMU_TYPE_DEFAULT = 0, +}; + +/** + * struct iommu_viommu_alloc - ioctl(IOMMU_VIOMMU_ALLOC) + * @size: sizeof(struct iommu_viommu_alloc) + * @flags: Must be 0 + * @type: Type of the virtual IOMMU. Must be defined in enum iommu_viommu_type + * @dev_id: The device's physical IOMMU will be used to back the virtual IOMMU + * @hwpt_id: ID of a nesting parent HWPT to associate to + * @out_viommu_id: Output virtual IOMMU ID for the allocated object + * + * Allocate a virtual IOMMU object, representing the underlying physical IOMMU's + * virtualization support that is a security-isolated slice of the real IOMMU HW + * that is unique to a specific VM. Operations global to the IOMMU are connected + * to the vIOMMU, such as: + * - Security namespace for guest owned ID, e.g. guest-controlled cache tags + * - Non-device-affiliated event reporting, e.g. invalidation queue errors + * - Access to a sharable nesting parent pagetable across physical IOMMUs + * - Virtualization of various platforms IDs, e.g. RIDs and others + * - Delivery of paravirtualized invalidation + * - Direct assigned invalidation queues + * - Direct assigned interrupts + */ +struct iommu_viommu_alloc { + __u32 size; + __u32 flags; + __u32 type; + __u32 dev_id; + __u32 hwpt_id; + __u32 out_viommu_id; +}; +#define IOMMU_VIOMMU_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VIOMMU_ALLOC) #endif diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 30e6c2af3b45..cc514f9bc3e6 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -307,6 +307,7 @@ union ucmd_buffer { struct iommu_ioas_unmap unmap; struct iommu_option option; struct iommu_vfio_ioas vfio_ioas; + struct iommu_viommu_alloc viommu; #ifdef CONFIG_IOMMUFD_TEST struct iommu_test_cmd test; #endif @@ -360,6 +361,8 @@ static const struct iommufd_ioctl_op iommufd_ioctl_ops[] = { val64), IOCTL_OP(IOMMU_VFIO_IOAS, iommufd_vfio_ioas, struct iommu_vfio_ioas, __reserved), + IOCTL_OP(IOMMU_VIOMMU_ALLOC, iommufd_viommu_alloc_ioctl, + struct iommu_viommu_alloc, out_viommu_id), #ifdef CONFIG_IOMMUFD_TEST IOCTL_OP(IOMMU_TEST_CMD, iommufd_test, struct iommu_test_cmd, last), #endif @@ -495,6 +498,9 @@ static const struct iommufd_object_ops iommufd_object_ops[] = { [IOMMUFD_OBJ_FAULT] = { .destroy = iommufd_fault_destroy, }, + [IOMMUFD_OBJ_VIOMMU] = { + .destroy = iommufd_viommu_destroy, + }, #ifdef CONFIG_IOMMUFD_TEST [IOMMUFD_OBJ_SELFTEST] = { .destroy = iommufd_selftest_destroy, diff --git a/drivers/iommu/iommufd/viommu.c b/drivers/iommu/iommufd/viommu.c new file mode 100644 index 000000000000..888239b78667 --- /dev/null +++ b/drivers/iommu/iommufd/viommu.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES + */ +#include "iommufd_private.h" + +void iommufd_viommu_destroy(struct iommufd_object *obj) +{ + struct iommufd_viommu *viommu = + container_of(obj, struct iommufd_viommu, obj); + + if (viommu->ops && viommu->ops->destroy) + viommu->ops->destroy(viommu); + refcount_dec(&viommu->hwpt->common.obj.users); +} + +int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucmd) +{ + struct iommu_viommu_alloc *cmd = ucmd->cmd; + struct iommufd_hwpt_paging *hwpt_paging; + struct iommufd_viommu *viommu; + struct iommufd_device *idev; + const struct iommu_ops *ops; + int rc; + + if (cmd->flags || cmd->type == IOMMU_VIOMMU_TYPE_DEFAULT) + return -EOPNOTSUPP; + + idev = iommufd_get_device(ucmd, cmd->dev_id); + if (IS_ERR(idev)) + return PTR_ERR(idev); + + ops = dev_iommu_ops(idev->dev); + if (!ops->viommu_alloc) { + rc = -EOPNOTSUPP; + goto out_put_idev; + } + + hwpt_paging = iommufd_get_hwpt_paging(ucmd, cmd->hwpt_id); + if (IS_ERR(hwpt_paging)) { + rc = PTR_ERR(hwpt_paging); + goto out_put_idev; + } + + if (!hwpt_paging->nest_parent) { + rc = -EINVAL; + goto out_put_hwpt; + } + + viommu = ops->viommu_alloc(idev->dev, hwpt_paging->common.domain, + ucmd->ictx, cmd->type); + if (IS_ERR(viommu)) { + rc = PTR_ERR(viommu); + goto out_put_hwpt; + } + + viommu->type = cmd->type; + viommu->ictx = ucmd->ictx; + viommu->hwpt = hwpt_paging; + refcount_inc(&viommu->hwpt->common.obj.users); + /* + * It is the most likely case that a physical IOMMU is unpluggable. A + * pluggable IOMMU instance (if exists) is responsible for refcounting + * on its own. + */ + viommu->iommu_dev = __iommu_get_iommu_dev(idev->dev); + + cmd->out_viommu_id = viommu->obj.id; + rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd)); + if (rc) + goto out_abort; + iommufd_object_finalize(ucmd->ictx, &viommu->obj); + goto out_put_hwpt; + +out_abort: + iommufd_object_abort_and_destroy(ucmd->ictx, &viommu->obj); +out_put_hwpt: + iommufd_put_object(ucmd->ictx, &hwpt_paging->common.obj); +out_put_idev: + iommufd_put_object(ucmd->ictx, &idev->obj); + return rc; +} From patchwork Tue Nov 5 20:04:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 840944 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2088.outbound.protection.outlook.com [40.107.92.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6E5C216217; Tue, 5 Nov 2024 20:05:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.88 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837109; cv=fail; b=IMF/GwzidD++dbd+3bTZ4YbpO3JfdGVQ/w3BIMOFIJMzUVfHz/Us8pMbdfV7lUMYc/tixPOz7pvwpSBUe+Dg6U0v0dK9/9Od8mLHKLrUaG97V216ITPfE9rnqbHILBV/ZKd0gCO49Khap8lBvnzGsBeEy2EycGlCAbWnC0rf9yY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837109; c=relaxed/simple; bh=u5pZzL4rN7BY1cRxnreaxEMpsmZzqNVt8WwikkvaCC8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mztd+My9z/UszGKpt354Hq0AMgaB6nCxV/HOPWmVZj8NI2tsbOqYod5a/Uj1cvpFSCZpqWVujj1UYBR8k+guB5nDZuVGKml5LgtYJo+5ZA3vQDFyG8F4NNygxsXKb4kRFMZVMBzWhndrQvP9jgeWEIbyd+o9NABuopSLuX6tJXo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=i4dnxJ1E; arc=fail smtp.client-ip=40.107.92.88 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="i4dnxJ1E" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=VSnMMEOu3Gy1QBCilUgk7F0TcbHrycLRfbAPRukSb6mD8vvzn6c8GhCNGUrNr4uLUyq/2H2d/kpbSwb+xPX+qLW8I1HnxsTuftggUcM7VICyuPrZvBnvW7FwEWDeTClBbwt79HDiD5kNcVeEzb8KNgDt4Qi+mzFvff1xWopHrRQdVHCv17mUVFXB8JXA3wMAFgbRYGffP2gAlTXvdWDPaVzop+cLEgc+Z9EbcGQX28KosRxgIsFPCRdKVamTM6rVjqYCELO760Jd2vr2RqFXzDjWw17q8M4ZzXHSunE3HqI8rUKnNwASoCLHwZaCY5fZ90sxLCG7asPtT31KNhK15w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=AA2gBV2134LitfJvCPpvY/fpiZHb96l7kAYadyzY41U=; b=auqnSmyqmLuPbHSQwCYjSBcOHZh7iyWlBh8aTPTTvrHyWcsnUDM7sZtWqtF0mo/wHxR0Uu55al1p8GfMDh75p6DHAzZVMbLZVaF1SPvzNp4cCfyf/cVHCE2kpyNY0+c3QKj2fHNQxgBzpaWQn7UDJUjeShqrkSh2LlhEItIRSlLH+wBU0MOS4m1FEd2WGwmMhlulhi5+Zze1uAaPA1dOxUetcsUDC6oAuV+oHPh98xvjZQvjrh49rM4bmCGgt0HpX4i62bcO0NnpUoqLapGc8/UVk18SI0ya2nkLHfz590N0aPD0z4qxjO11vktDVEsb7XAlQDwhO19AXvc/1UnGSQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AA2gBV2134LitfJvCPpvY/fpiZHb96l7kAYadyzY41U=; b=i4dnxJ1EqXbfp5DVdEr6MxiR0qhy6l/fuC4PWnZHlaFq4mmVIPi+D389+BEl0P8k2COQ3Ig9PxUtl53l0abL0NNe+EBSRT8OdjYbu7NmJbcjfNGpK9+vfeOANzGlkVAc5KyANDSEyGNd1UVzynxV99EmQOgOVVdKkI+DtHAVn6J3GL+uCI0LqZi2UEW3CGGIm8lVUlA6YATTv0FWl+shqLWSlE4q8mmYfihf+k31Nn6H4dAfQUVKs72snxtSvtbdTPK+CqiAf5X7xpHosY6DToIdn+UExz5kLbjbhfNGSqV4nb6UjTdWmGBCYGW5RL6lNzWmQ36TfTa3vnY6L/itxA== Received: from LV3P220CA0014.NAMP220.PROD.OUTLOOK.COM (2603:10b6:408:234::14) by DM4PR12MB5819.namprd12.prod.outlook.com (2603:10b6:8:63::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.18; Tue, 5 Nov 2024 20:05:04 +0000 Received: from BL02EPF00021F6E.namprd02.prod.outlook.com (2603:10b6:408:234:cafe::4b) by LV3P220CA0014.outlook.office365.com (2603:10b6:408:234::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.18 via Frontend Transport; Tue, 5 Nov 2024 20:05:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00021F6E.mail.protection.outlook.com (10.167.249.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:05:03 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:48 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:48 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:46 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 06/13] iommufd: Add alloc_domain_nested op to iommufd_viommu_ops Date: Tue, 5 Nov 2024 12:04:22 -0800 Message-ID: <2dcdb5e405dc0deb68230564530d989d285d959c.1730836219.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6E:EE_|DM4PR12MB5819:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c73714f-0456-406a-449c-08dcfdd5232f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: tTZ6V0W6YgXXVQGmLZ6YqAB+Y+Q2hZEIwtlugmvV4lNTFcQDnPq5wiB4ebyn/3dxyo+OG0x5X4Ps6fB4P3Avr8cmgXD4PqIelOk516neZIP3Re+wIbfUPUKrN3HB96r5PHE3O9JxaU7o8OaQmhgmnOQhC1KVQ4I9ki87U1fOyMLm4RbGVNgBWEygxhrptyNteCFK5iqShSA6eW82gK8tbzyhB5clgCOS3o7n7QZ4sGpH08KclWyHX9iFQajPfEy6SqMmyW68NxpaJ5KXl7TzvhQ/UuUlSj1pgJFckE0TaJt+QgRpNNxPe3WB3e8V/ZuPwq6U5qBigvI43fhHXnvpOPWtG6D/0aDA6mmVT3U1AcW4iAv283O69O8eHFuPsvV2CxPmDMeqEq2bFGu/HNzayKATFrB14V3GZGEntaO2enGv1i3bNVesVJFkHOn3/V3HCymDyymW94jOoH5/NvaONiekXndZumG2Kr+HeKecZO7aOsrhRwjui5vOZ901eBoIuTFsM6//57oZhHCyOjB8neLgjBErExxmFV/TdeUvH80N5zIgN/3BSTPteJ/twWfcJzTzyxtpYyNSUrbkoW9V9NtXKfzg3UiY6M9QbLxvojv4uYZAmfZlWyGRQB1VawSdZaefqtT33I1ZRwVa5EsC0ZpfCO9bqnh7TXC1S85YpLr7mIET0l9kbT3KBtQElWA2bDH2u9EXmnt3j3sHIwGptMp8jHANzTU2jrD1a+He/Fsi6QO5JvbumfGmzxT9e/5S7lSywyjTutO/pPXfy7nQQY678FkMwre+qgxK+WuhpGpUOKPYFtVPJVQ7MpouE5HEGu9ZoccJ+UtfPkJEG0vSf3pWYGxzT3LCynb5uHryJNCEvgOLhxrzlHiZPiOyDTSQi7M0zbcyV6Y3Ws0/88ZzC36ZYJFkaglFCru6YsOGt2yg9cYg97aJnQYXMlcHofXLKQBPbIzcMMmUkyTp/I6kTOkyuI3fv3MvfvMoRaxE9eKatr/CHII4kCIUObb4r+f4NsQaaf8vnfJUS7TYcMQFTadVWzJENI9T/irDKUwHmwvGVgwX4q5XdxCigtVTaHkrQUm8nxgUiQ3xjuGYc4vN9YRT+JkpAuxwpmVBUHLIRKfDVvnt1KCW5EB3Gc4ZWfVotSmjHnOrn8UNR9uiNU7UrNnp9PNrYKf/2nvlU4cJfLzXeWYdSugbQhqSDPCA7JMVho+jE2BrCOEj5uZpTWbjV4Ui7QRsbDQPxwGgh6W+YwcCzOtXsHG5twdgiCKcT+B8DbEttCSJWa3+LGskF7BfjgAVsTWt7aSOkQYWfrAmfaVyLK72bOlUPgnqgZTV0XQuT+jWvCR27CTZNqCkpuq/igkls/2DoH7hCDMZ++5x93GRWAfeFPYtymv1NT4nDBiSrq/EB9UTParUZKQcqjA6Sg== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:05:03.8054 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c73714f-0456-406a-449c-08dcfdd5232f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5819 Allow IOMMU driver to use a vIOMMU object that holds a nesting parent hwpt/domain to allocate a nested domain. Suggested-by: Jason Gunthorpe Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- include/linux/iommufd.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 4fc2ce332f10..de9b56265c9c 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -14,6 +14,7 @@ struct device; struct file; struct iommu_group; +struct iommu_user_data; struct iommufd_access; struct iommufd_ctx; struct iommufd_device; @@ -95,9 +96,17 @@ struct iommufd_viommu { * struct iommufd_viommu_ops - vIOMMU specific operations * @destroy: Clean up all driver-specific parts of an iommufd_viommu. The memory * of the vIOMMU will be free-ed by iommufd core after calling this op + * @alloc_domain_nested: Allocate a IOMMU_DOMAIN_NESTED on a vIOMMU that holds a + * nesting parent domain (IOMMU_DOMAIN_PAGING). @user_data + * must be defined in include/uapi/linux/iommufd.h. + * It must fully initialize the new iommu_domain before + * returning. Upon failure, ERR_PTR must be returned. */ struct iommufd_viommu_ops { void (*destroy)(struct iommufd_viommu *viommu); + struct iommu_domain *(*alloc_domain_nested)( + struct iommufd_viommu *viommu, u32 flags, + const struct iommu_user_data *user_data); }; #if IS_ENABLED(CONFIG_IOMMUFD) From patchwork Tue Nov 5 20:04:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 840943 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2068.outbound.protection.outlook.com [40.107.244.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C258216435; Tue, 5 Nov 2024 20:05:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.68 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837112; cv=fail; b=bmg/mJXO0J/5MRJHJoYCBOeTTAu17N7+XL6cdgUqow+6B0jggBBUhLYtzJeLdHw+TEx3Geow9W+Lphr9n9fOmaiFzkzB9fCZK6dLY4o0GeV3YJ9Mh512e3wW1gl3gnDMIR2EZQez1LU7k0JxV6HlgQx+W9zEJbKJ8ifrZcqMsyg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837112; c=relaxed/simple; bh=5gPEZtyyDhyM2EjvMAHDyzSrnjeQcuInTegKAjl6Qic=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SYhCc/7x63ynqFiP+REw/3RXvK1vZWDa3pXcLd/JJc9SMDcMsme3xcKuCFEHFftUYA3V5/nqct7a9SJEnNDhEU1wGK7BARKRsFxyl5CMzkk6br64Li+7yzvKOFNOYmqmBaZzMteDonbEFqmgXcU8iUE6e++aUxERR+GDu+JoiVo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=m7ebJnwB; arc=fail smtp.client-ip=40.107.244.68 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="m7ebJnwB" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=l2WnVVg4kWT2rBjubfKYv1jJBKoEHLKrTJpMLo7g3upW9lUTHCbNwNZb/HHKwSreoy9aCNxXW+oazYzHBnGleQczsydeEuIC5LWt7JJzjCtB/vOenZp0WhTfjk/IdZt/rfmPqC+bAKBZXSHNGAaXd9T/SFSYzTr17ZLicN7bzOpAt3NpjuyHlGlHlC+Ow2/Zrk+eMUA/SEJ+Ou336ywCQzZp8RTWwuy5T3bm5ODnY9/rbb2VNL/65xmrHGmCWVulnyWlDqHwziYShMQtq12BWE0qApAjOmMMiaHcIPksgPykV61bmmplJjjgjaJwFPfWxdwj/7Y5P+VNgTXOzuHQMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0Gd0uG/1jtFeNxS3+PkXSFAp4PEfyqYU+G9occHIIPY=; b=zLLgXIdJmGbMqCDHKKzwaNasWmZwTJZdHzWwYUYmISxU4XpovlQQ29J1r7s5En5Zz/Dde1E6u3uFrQ7LK9McoaTGB/yjJUCHdrWUXswpCDkoEtasVVieGGduvUJQ/wudzzA5sjE2Q96oPI6qphj72Ah7iBI3K9lo98i2djbV9qiMuA2FhbKsxiRKxUn5HJj8n1pXYiQH34J97Wd7masFeY4QeTn6MYb5gJl+4+17uBegey1RRMkOn1WAjlTw337b+HMej6lOkvs+7wMEv/g7NM9/k+kMZP/maypGkrW76UTuLv5fEzgKYSaLSL0GF9Tlp4ToKads646u3LFvo2WxxA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0Gd0uG/1jtFeNxS3+PkXSFAp4PEfyqYU+G9occHIIPY=; b=m7ebJnwBj7O8FyMjYKHeqwzhr19hQPkIfz5aRenfGhzD6oCvWeJUEX38B2WsKZlkB1JwKLFFFzcRE56JaVRMWGfAdxMevHKGnfP7uvSALMhb3kiGEn0cRveoyb4xsFAjbaAH5HXyUy1kSxffcZ/GKCmwYLvxx8v9rKcxs37vGo8Tc3bw5FHFcpeTnH0WZzJTi5HRpcN+ZQJIVQAQ4ltOMEAK9wB1VdLrtTy5yWnO0BecjHyaJ061QXg9y0jnoSMuP0eT86nNxObAdjsInvzVQ15vF6I6mJJQWEKgnukXwK9eexoqTASvLoMXJOchESPO0WreRUtesd1+z4bNAvQgnw== Received: from BN9P222CA0028.NAMP222.PROD.OUTLOOK.COM (2603:10b6:408:10c::33) by SJ2PR12MB8718.namprd12.prod.outlook.com (2603:10b6:a03:540::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.19; Tue, 5 Nov 2024 20:05:06 +0000 Received: from BL02EPF0002992C.namprd02.prod.outlook.com (2603:10b6:408:10c:cafe::47) by BN9P222CA0028.outlook.office365.com (2603:10b6:408:10c::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.31 via Frontend Transport; Tue, 5 Nov 2024 20:05:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0002992C.mail.protection.outlook.com (10.167.249.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:05:05 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:50 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:50 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:48 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 07/13] iommufd: Allow pt_id to carry viommu_id for IOMMU_HWPT_ALLOC Date: Tue, 5 Nov 2024 12:04:23 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992C:EE_|SJ2PR12MB8718:EE_ X-MS-Office365-Filtering-Correlation-Id: cd402134-4741-4eed-473a-08dcfdd52474 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: KhOAhdfdo8sOPK21sjWErSj+sdTB/a6dBuwVvc32QMhRBwVLM/1PeR+MHuol+z34+efBkfpYpy//6k4sWhhtymEl2hPJ9ayM40YZw/YYZyszy31bjJHNnR0/5es35g2Obzc1wUWnoQ2ODa5mw0FrtJHOgD4E13XXwiKggNth9kcT75pZA9GV9LblY9RDpN1TeyfqVYiYxwLNN7OYcRZHRDBBpO4KUoOmZmTx05udJeiJ132M9QXR1NL9+0MEolMiA/P/KwYfXqZ93u0KTuS035gytETGddjmIgGnx51odp+PGp4EC0SSudSA3E+4WLGZhKyBza1hIdlxYjpRmkZZoMDwCpvQf/mDpCDx0bIQEvJLFzDqMS7w5tdHpjepBaUKZkT31PDilw9pkg4Ivxhm0ydN096FgHoEzuYBWD48xgXtunuibDtJP02kNALNwZN9uY62fNbd5jl5RkC0mX1MiISBS1N7fWlwyQUHDBzaZdIhrsVcgdVEVn6RZrbDPB8oBPUrZp+FZ99dIFuyzITI8mOFQ3sxYRhxWqy1on8d2C8U77gqsYUj2xId4Coz9XFve4NIRMHFuKL6TzEP7ciVvxQRZ29DOiJb1QQCYRDnhKtni1mi8zjdKlGdmyUWV7nvLTS9WBIKIDam5ZVod8x8z4EIXegsA9i/eknhKKKyDSvn/TmlIir5w78xy6Crk/b/dJ/NETM/AsUK8fFoUf9U8ARNMBpozAAghF/sne+BkI9uNAteVQ7/+DDjOTxFEwz4SGaQeyzslc8Ysy4ZqXzTgzD08EfSlf0T80n8rBU5wpNTGoD2wLak8E71jLlx4vTCc0KVNJUeDDgo46GITZwnbtUEaln9JI2BCu8G8lSzQH446lPrSW3rpSUWTVGeXvyGlegc0vUfnNr9OMmBHfiGlmMUJ7HJGVMrYL7w7C8YCdEObnOKn6FPGTtgkRrL7VudeX3aFLGKcLHOvtv6twDjxvH8Sc4vS+C0lJa9aIasJQlraYyPkAF58imDC11rikUuIMJfSo0ww0GsLdUnSunQWOuH/BAws59KtkbzQwpxHucguEhlL/mw2pXvqst5xtiVRVkRiCJzo/PA76I7JyUPkXq3K6p24QO+jlk4wjYUVBe8frcidlfLGCN1p+MrKYcjiV6KqZwi5KX+F7zMOgEM/mxs3zYPn+ey6jYYjmVNMXhKc5hzd8ZRaHCiWjoArLdwuKoDG/l/b9Odt1wBDaI2qnCFa2mz+GkG993EkTOhxApHSE0b5QPOp8SaO93ormdaR1REr7cx/n7FrrKFhorBs5gpWNDxTI5nOEwlii7ZkhoCbBq0jpD6Ey4ekN1HQb9lRnh65RKKfQsXeVUY9aga6taNU/YNfpKdPcuAjioOqGCedxvmLbM1WlanXSpjiNj0lOH10JY44GwIfSlBO4XGyw== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:05:05.9198 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd402134-4741-4eed-473a-08dcfdd52474 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8718 Now a vIOMMU holds a shareable nesting parent HWPT. So, it can act like that nesting parent HWPT to allocate a nested HWPT. Support that in the IOMMU_HWPT_ALLOC ioctl handler, and update its kdoc. Also, add an iommufd_viommu_alloc_hwpt_nested helper to allocate a nested HWPT for a vIOMMU object. Since a vIOMMU object holds the parent hwpt's refcount already, increase the refcount of the vIOMMU only. Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_private.h | 1 + include/uapi/linux/iommufd.h | 14 +++-- drivers/iommu/iommufd/hw_pagetable.c | 73 ++++++++++++++++++++++++- 3 files changed, 81 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index a8104d9d4cef..e8f5ef550cc9 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -290,6 +290,7 @@ struct iommufd_hwpt_paging { struct iommufd_hwpt_nested { struct iommufd_hw_pagetable common; struct iommufd_hwpt_paging *parent; + struct iommufd_viommu *viommu; }; static inline bool hwpt_is_paging(struct iommufd_hw_pagetable *hwpt) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 302844136b02..a498d4838f9a 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -435,7 +435,7 @@ enum iommu_hwpt_data_type { * @size: sizeof(struct iommu_hwpt_alloc) * @flags: Combination of enum iommufd_hwpt_alloc_flags * @dev_id: The device to allocate this HWPT for - * @pt_id: The IOAS or HWPT to connect this HWPT to + * @pt_id: The IOAS or HWPT or vIOMMU to connect this HWPT to * @out_hwpt_id: The ID of the new HWPT * @__reserved: Must be 0 * @data_type: One of enum iommu_hwpt_data_type @@ -454,11 +454,13 @@ enum iommu_hwpt_data_type { * IOMMU_HWPT_DATA_NONE. The HWPT can be allocated as a parent HWPT for a * nesting configuration by passing IOMMU_HWPT_ALLOC_NEST_PARENT via @flags. * - * A user-managed nested HWPT will be created from a given parent HWPT via - * @pt_id, in which the parent HWPT must be allocated previously via the - * same ioctl from a given IOAS (@pt_id). In this case, the @data_type - * must be set to a pre-defined type corresponding to an I/O page table - * type supported by the underlying IOMMU hardware. + * A user-managed nested HWPT will be created from a given vIOMMU (wrapping a + * parent HWPT) or a parent HWPT via @pt_id, in which the parent HWPT must be + * allocated previously via the same ioctl from a given IOAS (@pt_id). In this + * case, the @data_type must be set to a pre-defined type corresponding to an + * I/O page table type supported by the underlying IOMMU hardware. The device + * via @dev_id and the vIOMMU via @pt_id must be associated to the same IOMMU + * instance. * * If the @data_type is set to IOMMU_HWPT_DATA_NONE, @data_len and * @data_uptr should be zero. Otherwise, both @data_len and @data_uptr diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/hw_pagetable.c index d06bf6e6c19f..982bf4a35a2b 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -57,7 +57,10 @@ void iommufd_hwpt_nested_destroy(struct iommufd_object *obj) container_of(obj, struct iommufd_hwpt_nested, common.obj); __iommufd_hwpt_destroy(&hwpt_nested->common); - refcount_dec(&hwpt_nested->parent->common.obj.users); + if (hwpt_nested->viommu) + refcount_dec(&hwpt_nested->viommu->obj.users); + else + refcount_dec(&hwpt_nested->parent->common.obj.users); } void iommufd_hwpt_nested_abort(struct iommufd_object *obj) @@ -260,6 +263,58 @@ iommufd_hwpt_nested_alloc(struct iommufd_ctx *ictx, return ERR_PTR(rc); } +/** + * iommufd_viommu_alloc_hwpt_nested() - Get a hwpt_nested for a vIOMMU + * @viommu: vIOMMU ojbect to associate the hwpt_nested/domain with + * @flags: Flags from userspace + * @user_data: user_data pointer. Must be valid + * + * Allocate a new IOMMU_DOMAIN_NESTED for a vIOMMU and return it as a NESTED + * hw_pagetable. + */ +static struct iommufd_hwpt_nested * +iommufd_viommu_alloc_hwpt_nested(struct iommufd_viommu *viommu, u32 flags, + const struct iommu_user_data *user_data) +{ + struct iommufd_hwpt_nested *hwpt_nested; + struct iommufd_hw_pagetable *hwpt; + int rc; + + if (!user_data->len) + return ERR_PTR(-EOPNOTSUPP); + if (!viommu->ops || !viommu->ops->alloc_domain_nested) + return ERR_PTR(-EOPNOTSUPP); + + hwpt_nested = __iommufd_object_alloc( + viommu->ictx, hwpt_nested, IOMMUFD_OBJ_HWPT_NESTED, common.obj); + if (IS_ERR(hwpt_nested)) + return ERR_CAST(hwpt_nested); + hwpt = &hwpt_nested->common; + + hwpt_nested->viommu = viommu; + refcount_inc(&viommu->obj.users); + hwpt_nested->parent = viommu->hwpt; + + hwpt->domain = + viommu->ops->alloc_domain_nested(viommu, flags, user_data); + if (IS_ERR(hwpt->domain)) { + rc = PTR_ERR(hwpt->domain); + hwpt->domain = NULL; + goto out_abort; + } + hwpt->domain->owner = viommu->iommu_dev->ops; + + if (WARN_ON_ONCE(hwpt->domain->type != IOMMU_DOMAIN_NESTED)) { + rc = -EINVAL; + goto out_abort; + } + return hwpt_nested; + +out_abort: + iommufd_object_abort_and_destroy(viommu->ictx, &hwpt->obj); + return ERR_PTR(rc); +} + int iommufd_hwpt_alloc(struct iommufd_ucmd *ucmd) { struct iommu_hwpt_alloc *cmd = ucmd->cmd; @@ -316,6 +371,22 @@ int iommufd_hwpt_alloc(struct iommufd_ucmd *ucmd) goto out_unlock; } hwpt = &hwpt_nested->common; + } else if (pt_obj->type == IOMMUFD_OBJ_VIOMMU) { + struct iommufd_hwpt_nested *hwpt_nested; + struct iommufd_viommu *viommu; + + viommu = container_of(pt_obj, struct iommufd_viommu, obj); + if (viommu->iommu_dev != __iommu_get_iommu_dev(idev->dev)) { + rc = -EINVAL; + goto out_unlock; + } + hwpt_nested = iommufd_viommu_alloc_hwpt_nested( + viommu, cmd->flags, &user_data); + if (IS_ERR(hwpt_nested)) { + rc = PTR_ERR(hwpt_nested); + goto out_unlock; + } + hwpt = &hwpt_nested->common; } else { rc = -EINVAL; goto out_put_pt; From patchwork Tue Nov 5 20:04:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 841897 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2073.outbound.protection.outlook.com [40.107.93.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 778B21FF7B3; Tue, 5 Nov 2024 20:05:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.73 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837117; cv=fail; b=YYfp/0LMFhEVd2OAAVaYZ10IzOJP33xL/FSeowhpsMMNTtl3V1RoMCl8qVVYwLGATOsnTjukdjwlPOLBYCQP3KgcD3bygR8wNhggifaaSr2eHRtxfe7sfUAwA8xPjES6ouKiU3YFCWtF5/4Td3hT1qf58iBs8EAqVdLv5a5lFCY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837117; c=relaxed/simple; bh=ju5HyEZzFfmDYHxRYjKrj8DcYQoamkrIU8iuQIhWIUo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=vEjdUbn6Oy687gtbZh4MY6BuUX4tWUoIDNE7NqhClH7lg/6xyqBueJXP2wwLm1+X6ILylB6I47V+AEJUdhKZN1Q2dWL8CXjFi5OtI/VxKYfv4pkbgvETMt8esT0qsTEn9unihDTcil2fUUF1sFCQwIyNPzv2K0ZnSDdujqwRllc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=bTOr/O5b; arc=fail smtp.client-ip=40.107.93.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="bTOr/O5b" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=vW7NbkTY96mY2q1b7N9D/x9gT95u1DafmK6pFSkZ1U5fQkP2SiY88slAkwVC1lg+vyYiLQ19wbryqZMmrmrit5cUFbRdA6QM/n1UD9YjB1nKqlfHPZWQYlrj7HAjQ90vFALqkaEBzlyjiKMh5yClD2aqow07ZqYjeXK21Y5klrMZnjqSlLPyLqBChNYp7r9L3aOVFWR0VZZxjHXxHY1FiRiyh/+T66u8lSqnHsf3XQQuHrdF7PJkB5NFZw1rvNEU6EoA+DCkoplw3+DUFuamZkZnpbzbdG0raKVhkoc/pDYLF8JNNb5UldNzUzfR97lKiioG+7PuZBuYBwiyAuJXvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ae3NYYj8Mb/IQHqia9NXSz9x6kihsiTvFqB6gqoxl+Y=; b=UBm9+5kfgOvKWmuUYbzfGHKPas7RYA7C8XHt+5pbdSzAV6SRKFYRS+vpZNe7DamXBCw3H3J20hWUcvjjeZm9mbMTcQQeOMZcJJNb95VhoxnqjVvVsGvOL9XFWR2EVKzyVHBJVv0Ghf5H9yFgDwizxklBrCjY2HHhLonNqhzaKQxrD3Of19ts5+wk0U9y4QC1TJQ9AXY235gSVEN5UkdEl9vzZ7zUoHIADVeESOzBB7500OmTqKOXE0AWdj0E3Rfduc4fp+n7Cu2HJsD2LSPA1gJMb2VlG0H3PuHkj+x42HydMo4MR7BaEl6R5sUMKTOkJFNTqZwrg4Kdd610kLqKjg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ae3NYYj8Mb/IQHqia9NXSz9x6kihsiTvFqB6gqoxl+Y=; b=bTOr/O5b7uk0kxM2X6u2ZnY9oUCH8BdblikIsmXrcerLtKTG3EDcPWUBkO2FRw3eznYuN+K9d9lrLnLBkDwPLhTIyksS3OC2DsukEiz9X56l2r+rstzD3/HX+drNrS9F5IO45L1yZVMhHNVJyc6v6pmzWkPGgdWUjtBos3cAnjX4KBkUeB37MiQlRqdmtWCe4wiMSBJk/oA8I/qROiZ5pMrwZo7CImnXB88Ni31dV2MUER1F5TI+PgBqXZxxdXaciYhFNnfc0GYQf/HzzQLgx5MJjeXgDENDJOpMivxrU0EwqCbCdT594eE7V3J0j7u5m/JUvG7/Byj5aVGY8S2g9w== Received: from LV3P220CA0001.NAMP220.PROD.OUTLOOK.COM (2603:10b6:408:234::33) by PH8PR12MB7352.namprd12.prod.outlook.com (2603:10b6:510:214::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.28; Tue, 5 Nov 2024 20:05:06 +0000 Received: from BL02EPF00021F6E.namprd02.prod.outlook.com (2603:10b6:408:234:cafe::f9) by LV3P220CA0001.outlook.office365.com (2603:10b6:408:234::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.31 via Frontend Transport; Tue, 5 Nov 2024 20:05:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00021F6E.mail.protection.outlook.com (10.167.249.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:05:05 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:52 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:52 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:50 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 08/13] iommufd/selftest: Add container_of helpers Date: Tue, 5 Nov 2024 12:04:24 -0800 Message-ID: <518ec64dae2e814eb29fd9f170f58a3aad56c81c.1730836219.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6E:EE_|PH8PR12MB7352:EE_ X-MS-Office365-Filtering-Correlation-Id: 0fe2a915-a9c9-4565-9a53-08dcfdd52448 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|7416014|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: 0Hdb4RCo3sTaNKjeiJwfxIkMh85OX0oM9iDku6b9+wVHIMcwP0ayPbj0msWSgP+dmGlksL8ZwPGRPYxO7VhSN/t75TEnljxz8cs6OWhPy2vFeYSC8tko0wqRoUa3YwHpykgOOozaXRMW5FdjGjS0qaMZWOLRRE8KMFmNR3fMePKGye1rr3MM8zqClsTkv3cHnz/ofNvHdhyTV8K9GqjPrvbI3bTwCMcvptqa7efi6kYoIGkvD3fH6e61PyKga1EMP6/IKweTOw4EUff7tGHH5MduAiYYGevYgn+nAdNDzEZdej9dHaevAfEKtTwjR0l1Ci98XRM7li6KBV7ZceV6dC2uVtaL6My605ECl5gGbZMmuiZhgIrRNb2+Ez43j/l8fKH5rAOQytkscXWY06OO5uCM5LPRHminRACw9IEHzuS0O/VCzSuDDuMrDvBhyRJFJlWYEVXv3oiJFOLvK7ZHJ7pUG3GqYwSMsIkOVYnn4GrDEb4qJ7o/DmaB2R3jsVOWtS8OhlkXORi69VWbxpmmtBPu3w//xR6IKvVcYki7uAF1ejPD8NJZJ6ItbAxDW5sc+tAuiYS/n6rL0+wj0ETYR4KyF23tjCAe4ab+mHeR5xizxv57dWnl3+jE240lDQ9YTinwvmUFpn9AO/4fUOxgAsRneor9AkH9Ki0i/bvUzqeXWJX/s6jT+SYNC9b0Kmx3ORa6XNibxQ114ywPEkEswL/9Vg0csHYOK712KCCxTZBsHPwR58WWQ4iM2h0JVswKZq9gbh+XgVpbPwUIcLqmGitkhO/EYyZHdlKhM7PCvX9Okp0OXyaOcmVUJ3AFk7S37NqUqtMGErU6k1B+MtXsFPHQo0nMredZ2Biaqyn0+SI3RnJFXkvDOqvpRYlhVHSwtG3l4H6chamX8ljpYaXNECsbBQRo4xIwiAchsE8TatiSRY2V6LZb0qf5j2ndOFB0rEccsysbdV070QMQoq2FDKFzrMKTdBofYU8SRMl1muab3VxIEk2s9Sjp0F3qMP9geSIm4i9fz5y6FN8ctihPV2axBZWRLiSQ50uynPvEIeLh4qtTtIOiJRwxJzXHl/dG5AVPaMtBdgk1VbM61zaJklLwMzae/mXysvRW+551+pZmbX/B0rmHyKhXtrlPQSz+xNbbbE16N9Lm78L69VMns1/NJAVkArUBUcEchtlcqMpWWort2+yF3yjoyWp1l7Tjpeq/HWY+w9gxHrmP3HSfP/sxJkIC/PZBkg8/kPfFZSeg8lHK8eyShr8EdhYPoQ7ndXawvEwvjE88vOtEFPpjhKXo7ojFUOauNol2env8/K36I66MmE/Ix6P11Fo3Ok+nbzAGosjosCDgCUV0+ekFbW+/XFxfO58QqZojSBE32hohgxAuq0sdgeBR7/XJGY0OPiFF6cwPazyWhRtgQIuExg== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:05:05.6335 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0fe2a915-a9c9-4565-9a53-08dcfdd52448 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7352 Use these inline helpers to shorten those container_of lines. Note that one of them goes back and forth between iommu_domain and mock_iommu_domain, which isn't necessary. So drop its container_of. Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/selftest.c | 75 ++++++++++++++++++-------------- 1 file changed, 42 insertions(+), 33 deletions(-) diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c index 540437be168a..322e57ff3605 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -126,12 +126,24 @@ struct mock_iommu_domain { struct xarray pfns; }; +static inline struct mock_iommu_domain * +to_mock_domain(struct iommu_domain *domain) +{ + return container_of(domain, struct mock_iommu_domain, domain); +} + struct mock_iommu_domain_nested { struct iommu_domain domain; struct mock_iommu_domain *parent; u32 iotlb[MOCK_NESTED_DOMAIN_IOTLB_NUM]; }; +static inline struct mock_iommu_domain_nested * +to_mock_nested(struct iommu_domain *domain) +{ + return container_of(domain, struct mock_iommu_domain_nested, domain); +} + enum selftest_obj_type { TYPE_IDEV, }; @@ -142,6 +154,11 @@ struct mock_dev { int id; }; +static inline struct mock_dev *to_mock_dev(struct device *dev) +{ + return container_of(dev, struct mock_dev, dev); +} + struct selftest_obj { struct iommufd_object obj; enum selftest_obj_type type; @@ -155,10 +172,15 @@ struct selftest_obj { }; }; +static inline struct selftest_obj *to_selftest_obj(struct iommufd_object *obj) +{ + return container_of(obj, struct selftest_obj, obj); +} + static int mock_domain_nop_attach(struct iommu_domain *domain, struct device *dev) { - struct mock_dev *mdev = container_of(dev, struct mock_dev, dev); + struct mock_dev *mdev = to_mock_dev(dev); if (domain->dirty_ops && (mdev->flags & MOCK_FLAGS_DEVICE_NO_DIRTY)) return -EINVAL; @@ -193,8 +215,7 @@ static void *mock_domain_hw_info(struct device *dev, u32 *length, u32 *type) static int mock_domain_set_dirty_tracking(struct iommu_domain *domain, bool enable) { - struct mock_iommu_domain *mock = - container_of(domain, struct mock_iommu_domain, domain); + struct mock_iommu_domain *mock = to_mock_domain(domain); unsigned long flags = mock->flags; if (enable && !domain->dirty_ops) @@ -243,8 +264,7 @@ static int mock_domain_read_and_clear_dirty(struct iommu_domain *domain, unsigned long flags, struct iommu_dirty_bitmap *dirty) { - struct mock_iommu_domain *mock = - container_of(domain, struct mock_iommu_domain, domain); + struct mock_iommu_domain *mock = to_mock_domain(domain); unsigned long end = iova + size; void *ent; @@ -281,7 +301,7 @@ static const struct iommu_dirty_ops dirty_ops = { static struct iommu_domain *mock_domain_alloc_paging(struct device *dev) { - struct mock_dev *mdev = container_of(dev, struct mock_dev, dev); + struct mock_dev *mdev = to_mock_dev(dev); struct mock_iommu_domain *mock; mock = kzalloc(sizeof(*mock), GFP_KERNEL); @@ -327,7 +347,7 @@ mock_domain_alloc_user(struct device *dev, u32 flags, /* must be mock_domain */ if (!parent) { - struct mock_dev *mdev = container_of(dev, struct mock_dev, dev); + struct mock_dev *mdev = to_mock_dev(dev); bool has_dirty_flag = flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING; bool no_dirty_ops = mdev->flags & MOCK_FLAGS_DEVICE_NO_DIRTY; struct iommu_domain *domain; @@ -341,8 +361,7 @@ mock_domain_alloc_user(struct device *dev, u32 flags, if (!domain) return ERR_PTR(-ENOMEM); if (has_dirty_flag) - container_of(domain, struct mock_iommu_domain, domain) - ->domain.dirty_ops = &dirty_ops; + domain->dirty_ops = &dirty_ops; return domain; } @@ -352,7 +371,7 @@ mock_domain_alloc_user(struct device *dev, u32 flags, if (!parent || parent->ops != mock_ops.default_domain_ops) return ERR_PTR(-EINVAL); - mock_parent = container_of(parent, struct mock_iommu_domain, domain); + mock_parent = to_mock_domain(parent); if (!mock_parent) return ERR_PTR(-EINVAL); @@ -366,8 +385,7 @@ mock_domain_alloc_user(struct device *dev, u32 flags, static void mock_domain_free(struct iommu_domain *domain) { - struct mock_iommu_domain *mock = - container_of(domain, struct mock_iommu_domain, domain); + struct mock_iommu_domain *mock = to_mock_domain(domain); WARN_ON(!xa_empty(&mock->pfns)); kfree(mock); @@ -378,8 +396,7 @@ static int mock_domain_map_pages(struct iommu_domain *domain, size_t pgsize, size_t pgcount, int prot, gfp_t gfp, size_t *mapped) { - struct mock_iommu_domain *mock = - container_of(domain, struct mock_iommu_domain, domain); + struct mock_iommu_domain *mock = to_mock_domain(domain); unsigned long flags = MOCK_PFN_START_IOVA; unsigned long start_iova = iova; @@ -430,8 +447,7 @@ static size_t mock_domain_unmap_pages(struct iommu_domain *domain, size_t pgcount, struct iommu_iotlb_gather *iotlb_gather) { - struct mock_iommu_domain *mock = - container_of(domain, struct mock_iommu_domain, domain); + struct mock_iommu_domain *mock = to_mock_domain(domain); bool first = true; size_t ret = 0; void *ent; @@ -479,8 +495,7 @@ static size_t mock_domain_unmap_pages(struct iommu_domain *domain, static phys_addr_t mock_domain_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) { - struct mock_iommu_domain *mock = - container_of(domain, struct mock_iommu_domain, domain); + struct mock_iommu_domain *mock = to_mock_domain(domain); void *ent; WARN_ON(iova % MOCK_IO_PAGE_SIZE); @@ -491,7 +506,7 @@ static phys_addr_t mock_domain_iova_to_phys(struct iommu_domain *domain, static bool mock_domain_capable(struct device *dev, enum iommu_cap cap) { - struct mock_dev *mdev = container_of(dev, struct mock_dev, dev); + struct mock_dev *mdev = to_mock_dev(dev); switch (cap) { case IOMMU_CAP_CACHE_COHERENCY: @@ -571,18 +586,14 @@ static const struct iommu_ops mock_ops = { static void mock_domain_free_nested(struct iommu_domain *domain) { - struct mock_iommu_domain_nested *mock_nested = - container_of(domain, struct mock_iommu_domain_nested, domain); - - kfree(mock_nested); + kfree(to_mock_nested(domain)); } static int mock_domain_cache_invalidate_user(struct iommu_domain *domain, struct iommu_user_data_array *array) { - struct mock_iommu_domain_nested *mock_nested = - container_of(domain, struct mock_iommu_domain_nested, domain); + struct mock_iommu_domain_nested *mock_nested = to_mock_nested(domain); struct iommu_hwpt_invalidate_selftest inv; u32 processed = 0; int i = 0, j; @@ -657,7 +668,7 @@ get_md_pagetable(struct iommufd_ucmd *ucmd, u32 mockpt_id, iommufd_put_object(ucmd->ictx, &hwpt->obj); return ERR_PTR(-EINVAL); } - *mock = container_of(hwpt->domain, struct mock_iommu_domain, domain); + *mock = to_mock_domain(hwpt->domain); return hwpt; } @@ -675,14 +686,13 @@ get_md_pagetable_nested(struct iommufd_ucmd *ucmd, u32 mockpt_id, iommufd_put_object(ucmd->ictx, &hwpt->obj); return ERR_PTR(-EINVAL); } - *mock_nested = container_of(hwpt->domain, - struct mock_iommu_domain_nested, domain); + *mock_nested = to_mock_nested(hwpt->domain); return hwpt; } static void mock_dev_release(struct device *dev) { - struct mock_dev *mdev = container_of(dev, struct mock_dev, dev); + struct mock_dev *mdev = to_mock_dev(dev); ida_free(&mock_dev_ida, mdev->id); kfree(mdev); @@ -813,7 +823,7 @@ static int iommufd_test_mock_domain_replace(struct iommufd_ucmd *ucmd, if (IS_ERR(dev_obj)) return PTR_ERR(dev_obj); - sobj = container_of(dev_obj, struct selftest_obj, obj); + sobj = to_selftest_obj(dev_obj); if (sobj->type != TYPE_IDEV) { rc = -EINVAL; goto out_dev_obj; @@ -951,8 +961,7 @@ static int iommufd_test_md_check_iotlb(struct iommufd_ucmd *ucmd, if (IS_ERR(hwpt)) return PTR_ERR(hwpt); - mock_nested = container_of(hwpt->domain, - struct mock_iommu_domain_nested, domain); + mock_nested = to_mock_nested(hwpt->domain); if (iotlb_id > MOCK_NESTED_DOMAIN_IOTLB_ID_MAX || mock_nested->iotlb[iotlb_id] != iotlb) @@ -1431,7 +1440,7 @@ static int iommufd_test_trigger_iopf(struct iommufd_ucmd *ucmd, void iommufd_selftest_destroy(struct iommufd_object *obj) { - struct selftest_obj *sobj = container_of(obj, struct selftest_obj, obj); + struct selftest_obj *sobj = to_selftest_obj(obj); switch (sobj->type) { case TYPE_IDEV: From patchwork Tue Nov 5 20:04:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 840941 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2059.outbound.protection.outlook.com [40.107.220.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33728216A13; Tue, 5 Nov 2024 20:05:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.59 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837119; cv=fail; b=fa78ClbViAIy3ALO62GjhHl8MkfwNuLrGSeeX+xakwsFimzR5kiSkB0laav9Y25J7ELdNb9skr/q7mCaQSfcyQh67DG2vN53wuFMd810KOrA467cRlBtGmwTwCQcaW8tj726NfVzNPFDs8Et8ohZSb/jdENpxo7fEg7AI5RDyBE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837119; c=relaxed/simple; bh=gGhsKUAuS3tN+ZVvOMxcUVmYnU4xo6EcIIjj8fa0HYQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pjUvhnvspjgz1FUCZ+AtPm7W+hHc/BJ/bev2kXauFY5KbRoxspjZsySzn4pj+xtmplYnZlc8tUPRWFcfdG/R7AZVbEIKwKLa8ujHFZUgYOZ6HLj5el8ioWyri+1/yOqlArZqUN68eXLNTj4efqJwW62ThrofUKYRsf+7XET5PNA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=COGz5N9Z; arc=fail smtp.client-ip=40.107.220.59 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="COGz5N9Z" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=dH7leVxJYmI0C0AtZtsmmnM45iiCUiz9w6T/Pbg7+gbiNd8jhcfAM1JEW8Hq4//MLBhMGqDex5HmowS7WNM2BCxM/ap5o2ogV0zbj/QDlWsldzDfOZOnpYZOaR1ytgc3qS1+34GA5zzY5h6uxjNeCHlBx8sBY4bNidRUzooY5/a78Bfsn21ecRqDCQ8oObDmqQUzIhKUtD0TEzuCDVtuGsWAe2kiJLWxzQLdGQPkC36X1kSZitd45tfiZ5M85IogmK8Z5VReRw0veEgB66uk//ISCZjwdBxKcQJolvA5yT9/DMbkxdV8IHe4wB2SxCH4dA1W+3Xp8HWLmN4n9DPg6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PUbjJXnib9EiC6H9vV18C3nn1EiLRyVYUNzy8Y9BqNA=; b=Mj4pKCxg7rKU/UKFIiqy4j4L4VqFdb3aPR1/sEXgpPmoCOaqTIJRIKj6A4QTcP2JTLJckcOpzjRWx9A8TpYZG33Gg0njQpFPdkvp/yv6LVZByrL1nUz3uQyIyaxGh4gXmoAcA2QABGFgHmAa25gMqMgUhf/T8LMSwH7UuNiUkTSp7w2K1Dy/S0wPjNzw9Y4Tv9/EAgwZY4grB6H9DyTxQN1FtjsbaYOs2IusnchM06Ay6N6iJc1suUWtyIJrOT5NX3ceOUCkC7nfmwqMqRQ07fAcT6TXFZBQflAe0SpwOdlFbCoKSqyYnd+u6xzTGECdDyFn2jNh3VaauxchhGHvLQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PUbjJXnib9EiC6H9vV18C3nn1EiLRyVYUNzy8Y9BqNA=; b=COGz5N9ZiFEOes4MUcjQIbAAwHmVVzTBrQL9VmtUfDg8cXFY9hjNdMyY3ryzdifd8ayok7e8Ms79dXdtpSMZ/h6BPyhsaRLGuPPR9wqbxyj9vcrJHe3vsvGJVr1hglpW+phkfywm68It/EjfD7984Zo3W3F2NdFvT4YuSxwZap8gg0Kc+QyJ6yWxXW0c0rMIZNxb9ho834axJVb/GWn/5uWz8/0CuhbfQz2Bc+HzkHO0cT2iLO1W2zT67v8SSxGyBWEhwtwmHRIXUI1iPn7ZMDApIExMnTgvj3wYRnUZPb+iGU1ERnm5ISYabR4eYukmdd2czQ2/YRPYJOQxrEKJTg== Received: from BN9PR03CA0069.namprd03.prod.outlook.com (2603:10b6:408:fc::14) by CH3PR12MB9028.namprd12.prod.outlook.com (2603:10b6:610:123::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.36; Tue, 5 Nov 2024 20:05:10 +0000 Received: from BL02EPF0002992A.namprd02.prod.outlook.com (2603:10b6:408:fc:cafe::16) by BN9PR03CA0069.outlook.office365.com (2603:10b6:408:fc::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.19 via Frontend Transport; Tue, 5 Nov 2024 20:05:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0002992A.mail.protection.outlook.com (10.167.249.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:05:10 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:54 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:54 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:52 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 09/13] iommufd/selftest: Prepare for mock_viommu_alloc_domain_nested() Date: Tue, 5 Nov 2024 12:04:25 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992A:EE_|CH3PR12MB9028:EE_ X-MS-Office365-Filtering-Correlation-Id: 86fe7baf-c359-4098-7a58-08dcfdd52715 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|7416014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: sIrdTAd3tBws+qTBcsyW6qPxgmNLmxTN2uHY6ckyGn/ZZF7UfzfShCZsvL4X15De4xwVNg5OfcjojdldSYLKaltmJP454WuIVC1szx+nnqflcNv+KnzaV7lm5SyKklPKDw2/1oKtoVom2S61I76fiiTwVIBGqgL6bpjmxkV3vV7zRO8rd52pHZcGiK0MSJOH7yYi4XwgyeU5fb66kO/aop98N10sfx03R0OJNN2fzDK5hVn4aW26WyrznM/Nbl/wVMBh3OW4RZxz462Wz1iqA/38I3SFM8+ZvQg52V8Ta2aXHDk7xq6zToP2SDugXTBBS6ScqV11X97fOZLcUa7Lw9q2qdY42dWxyLpDZLxTGXceFVbndY6i9QpMn3MR0HLqNZZ/Ub+ju5clnoTzMwaIg9enMoudQh9pFu2KUd5Mtx45j/MRGFQve/uVX1MH7xnF1P4YS54xwC9P3JJk0iZTT+zs6SYXQhTfkDWbY8jAO3kTGModnLndLE+4njlXNgfjCDYiy3eMQdtenGdYTpeCvYsW0ByBmg5dVc+TfBAICg5WuDkl6+EW8KGrU+3RgvKbnA72jMBMUWkEZmckeOHfWlPv8K+Gp/lL3r/BPkBhayd34ucoe2AekMn7PV9rwqBryvn1G6vUhp16aabU/M9PaCMqsmNq1yAcZERWdQZ2V8ChZelvGwbuaSvt3ofDD+dJOwMWoEQ1sdbda5I3/YvleGg1WV2jKb9Nfc+2P1AresM5Ech68ge6fXaV5ytkimW4rUgZFF4nAnF22dM/Qfk89lyyoqWTg3CzS7G72yDsMxpho3yoIxQQ+ra4ai5Kf04nHehE298p5NwrJaEt2k0gkapY6Jh2aNBhmDA/RwAO0K2jLSFYLt52veOUW2+7VYs7tqEIw/o+hLFoWKdzWo2U9+vnE4+x+7K1/7KCECDvRmRIbltRmThhmJs4rY0KkHd1G+CzA1DkHD9lTuU2Y3EoaErHVxV0IQakyUF1r05qrvmlUPtNYFP0JlWILSxWhNBo8qUgAjyQtvIXBsY2Ah9tojspAm5EpNfggy65/CcAnEK0SrELSZuw2+erdYhL0wyp37P7ZoyXmR2dJIQsUZ6Hmng5Ou5qORsz6WA4aTDV2/hHE2bM4/OXgPsbt3+DY5XohUQgyTRT+XA5EjFg89CJWrn+BZpruQ7sNuRdCB1TUS50YGQXdPcpDGi6YQTNf0iNDJjGD/Ty9LUx35/eapAAAXKLehOfDvwI0/F2zsfyfStdR2U42kX08HmmwLuCK7ybv+YM/eeiUd5blS+BL/pnAef21ikpzTp5nUQqbRgHegUD7OeVy3ezmN6Id0uUCxqmtyQl9uUnH+xkYCEAtqWjFo432tROdysnl6Ni9olpe5qej901UtiAWK5g4nQh6OYedjCVYzkiXhBPv2KKF/9z+w== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:05:10.3316 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86fe7baf-c359-4098-7a58-08dcfdd52715 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9028 A nested domain now can be allocated for a parent domain or for a vIOMMU object. Rework the existing allocators to prepare for the latter case. Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/selftest.c | 89 ++++++++++++++++++-------------- 1 file changed, 50 insertions(+), 39 deletions(-) diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c index 322e57ff3605..92d753985640 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -318,55 +318,39 @@ static struct iommu_domain *mock_domain_alloc_paging(struct device *dev) return &mock->domain; } -static struct iommu_domain * -__mock_domain_alloc_nested(struct mock_iommu_domain *mock_parent, - const struct iommu_hwpt_selftest *user_cfg) +static struct mock_iommu_domain_nested * +__mock_domain_alloc_nested(const struct iommu_user_data *user_data) { struct mock_iommu_domain_nested *mock_nested; - int i; + struct iommu_hwpt_selftest user_cfg; + int rc, i; + + if (user_data->type != IOMMU_HWPT_DATA_SELFTEST) + return ERR_PTR(-EOPNOTSUPP); + + rc = iommu_copy_struct_from_user(&user_cfg, user_data, + IOMMU_HWPT_DATA_SELFTEST, iotlb); + if (rc) + return ERR_PTR(rc); mock_nested = kzalloc(sizeof(*mock_nested), GFP_KERNEL); if (!mock_nested) return ERR_PTR(-ENOMEM); - mock_nested->parent = mock_parent; mock_nested->domain.ops = &domain_nested_ops; mock_nested->domain.type = IOMMU_DOMAIN_NESTED; for (i = 0; i < MOCK_NESTED_DOMAIN_IOTLB_NUM; i++) - mock_nested->iotlb[i] = user_cfg->iotlb; - return &mock_nested->domain; + mock_nested->iotlb[i] = user_cfg.iotlb; + return mock_nested; } static struct iommu_domain * -mock_domain_alloc_user(struct device *dev, u32 flags, - struct iommu_domain *parent, - const struct iommu_user_data *user_data) +mock_domain_alloc_nested(struct iommu_domain *parent, u32 flags, + const struct iommu_user_data *user_data) { + struct mock_iommu_domain_nested *mock_nested; struct mock_iommu_domain *mock_parent; - struct iommu_hwpt_selftest user_cfg; - int rc; - - /* must be mock_domain */ - if (!parent) { - struct mock_dev *mdev = to_mock_dev(dev); - bool has_dirty_flag = flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING; - bool no_dirty_ops = mdev->flags & MOCK_FLAGS_DEVICE_NO_DIRTY; - struct iommu_domain *domain; - - if (flags & (~(IOMMU_HWPT_ALLOC_NEST_PARENT | - IOMMU_HWPT_ALLOC_DIRTY_TRACKING))) - return ERR_PTR(-EOPNOTSUPP); - if (user_data || (has_dirty_flag && no_dirty_ops)) - return ERR_PTR(-EOPNOTSUPP); - domain = mock_domain_alloc_paging(dev); - if (!domain) - return ERR_PTR(-ENOMEM); - if (has_dirty_flag) - domain->dirty_ops = &dirty_ops; - return domain; - } - /* must be mock_domain_nested */ - if (user_data->type != IOMMU_HWPT_DATA_SELFTEST || flags) + if (flags) return ERR_PTR(-EOPNOTSUPP); if (!parent || parent->ops != mock_ops.default_domain_ops) return ERR_PTR(-EINVAL); @@ -375,12 +359,39 @@ mock_domain_alloc_user(struct device *dev, u32 flags, if (!mock_parent) return ERR_PTR(-EINVAL); - rc = iommu_copy_struct_from_user(&user_cfg, user_data, - IOMMU_HWPT_DATA_SELFTEST, iotlb); - if (rc) - return ERR_PTR(rc); + mock_nested = __mock_domain_alloc_nested(user_data); + if (IS_ERR(mock_nested)) + return ERR_CAST(mock_nested); + mock_nested->parent = mock_parent; + return &mock_nested->domain; +} + +static struct iommu_domain * +mock_domain_alloc_user(struct device *dev, u32 flags, + struct iommu_domain *parent, + const struct iommu_user_data *user_data) +{ + bool has_dirty_flag = flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING; + const u32 PAGING_FLAGS = IOMMU_HWPT_ALLOC_DIRTY_TRACKING | + IOMMU_HWPT_ALLOC_NEST_PARENT; + bool no_dirty_ops = to_mock_dev(dev)->flags & + MOCK_FLAGS_DEVICE_NO_DIRTY; + struct iommu_domain *domain; + + if (parent) + return mock_domain_alloc_nested(parent, flags, user_data); - return __mock_domain_alloc_nested(mock_parent, &user_cfg); + if (user_data) + return ERR_PTR(-EOPNOTSUPP); + if ((flags & ~PAGING_FLAGS) || (has_dirty_flag && no_dirty_ops)) + return ERR_PTR(-EOPNOTSUPP); + + domain = mock_domain_alloc_paging(dev); + if (!domain) + return ERR_PTR(-ENOMEM); + if (has_dirty_flag) + domain->dirty_ops = &dirty_ops; + return domain; } static void mock_domain_free(struct iommu_domain *domain) From patchwork Tue Nov 5 20:04:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 841898 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2089.outbound.protection.outlook.com [40.107.92.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD6B8216A01; Tue, 5 Nov 2024 20:05:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.89 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837115; cv=fail; b=WAniLyErFXNtynC1uoQxjkH5hYwbqbkxEYV3cJ4kINB9r8Yw51B9nS40Phnb8uULlgwjdPCL09OGU0COTxVMCFkzwaKi5uM1AqibRZcZTvXyTkmVIW/Zev5wUT19fVYu7grXmIPoH057GyqkjAwQm+sbdLqaYSJ53inaJIf2lL0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837115; c=relaxed/simple; bh=+iScv+JPH5qZd8WJf8hN+2Zy1gN2CgRyr1NqLkHDIe8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ul5D7Z+/Dj52HLNsX95QOLcPrEtlKSZKcE/KTyWySMdFUfGoOfPWGU8vXNTH/SIOxC8sq35+Lu2hMOY79HxQbpaRlG5ZBzml0zlZwTKMzxU2kGuXX5tLBYjgtEsS3/1Q7F+rqCyo6+wtR1TSRR6x177nEspYN+HYdYy2Ncpe14Y= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=LqH2aDV2; arc=fail smtp.client-ip=40.107.92.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="LqH2aDV2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZPWSTfC95OyAbRplIccjFNBa9zIk8369g4K2lwwKZNtx9rpa2k4ZUo2ALYx7XANFkwhCP5/L/nY6K4AQ8Ub9kbq6sYpGdlz9MZB1u1qK31jEfRGi1T1o5bgu+TQwIGApy1P/DTHZ28wVk6WwX9pr1BmXDsV3SGUKafyX8PcsUP4TXdQvv6qlae1tAj5Pa7Rcfwj76grhkrvxUSC70zSIhgGr7yq9mNKIgPW4Bn0EK6Eu0fDDljN4qWSn1uRg25+7U1G/M/mYl6Y8KcAP8DJ63LGGOzRfWB1/CR84eZapu0cydd64cJtAvnI0jRqwJHr83v5UajxeoIhRmgfdFLobXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=37CS+mIDQfL06j1QvVP3AC2sA04PpVCXgVs/EoL/36Q=; b=vF1JtEcUbihGtJWA/Cd7F5RECL//wQEpz4Zuc5t5eEWCwkDofTW+41q0bXkTG/g39TC28kJkNO74nKEa9yZ4XwIy40Q5bCxJ/YnnRLyx+GR5Xz0M08NNhDE+9belA1PmpoWOdxxIdFik/lEdQfKQKIiEtVHTGX3re3JK5b1g6XE2AVl/rUGE/9ptXVc7aQc77qqhNBIRPU5WyBHI8Vywi5DaUO1dcQVy/yR5zdIw7NJ6nLerrAcnG8MIjSKQNzpJghXdNPfPV7gIkdS/1nkvSN43fovypXM16Yz4TJt3JbAKlEgHdb/OiCzdZVo33NrDopDxR9uO4h7P3A7warY2aQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=37CS+mIDQfL06j1QvVP3AC2sA04PpVCXgVs/EoL/36Q=; b=LqH2aDV2+1dtGtAcIhgbiHVT4gamj4o52sTbdV/WN5m2vGP4AbuC9xpw8EGjnuBngBHUrVSrXziwCsyfU4HbxHAH4l+piEqpATjiCzLmtmUyDK5Og7noJnwjJGAaKrN33dgaad0LBwLGj3a9fpRdhObJZKSNeveWJwUzC6xVtd433ybcBDJ69XMtDEaNQz0UIcVrAfSBPe0nL5Aymzms+wFL78GRhINzZutfphGFVdjVFeeLdl7qedpjXd11SuxVNZ9Oosbb5jUWK3Q5q7IAGQjxCbwieRyBfiZZx3J0rGy8A5zt3miSZWvcemlneVhnPvItT3adad3M1DTc3ZSyTA== Received: from BLAPR05CA0011.namprd05.prod.outlook.com (2603:10b6:208:36e::26) by SN7PR12MB7131.namprd12.prod.outlook.com (2603:10b6:806:2a3::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.30; Tue, 5 Nov 2024 20:05:09 +0000 Received: from BL02EPF00021F6C.namprd02.prod.outlook.com (2603:10b6:208:36e:cafe::fa) by BLAPR05CA0011.outlook.office365.com (2603:10b6:208:36e::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:05:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00021F6C.mail.protection.outlook.com (10.167.249.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:05:08 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:56 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:55 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:54 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 10/13] iommufd/selftest: Add refcount to mock_iommu_device Date: Tue, 5 Nov 2024 12:04:26 -0800 Message-ID: <33f28d64841b497eebef11b49a571e03103c5d24.1730836219.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6C:EE_|SN7PR12MB7131:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e6871cf-2b42-4526-c1fd-08dcfdd52611 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: oHHduxOXQEZCCnq/QGGJFnoVKOssNKkw+bwX7eLcciDDg3hRR8gjdjJJZYNDgYpNjY8pWO9K6kb0nAi1ZpzPBX7PBBpKUrjryW8MtmexuGTjy1INFTHo0AtIwOBcxQP5u3QYBVXWM3Ec4ycuCgXKhgrc+WliT1AgFLSSvkFb6Hd0ipYb9gYW7asEjID/NTBtwsf5TCHDCUG6FR7EQtDT/wEPeLE0kcC/cMvVwC2h9gL9TosP4ls8e1aD2GUDad9E+v3nnQ63sNTKAGjqfyH0TcEH3K/oEuTWWYx2gYgJl2vytOwO4G7MBSiAjVWeuQ2dSLnO6Y2sZsYCNaQwnZ5fJcAbIKCYdkuEl32iNTK7yO4aSTY5h8W00XgDeSjiDovYeecQv0rQzZMPCveP8rFAJh6lt4sfouri5HbGGkWVFNj7Uv2cIPIcaHpbe3mOctpqQ9vZhZLw1udstLy9nYvgGpbzt19JX80olxIX7cseD8TuRRjg75H1X4cCG5l0UJMHX+n+B76I+1kQbj3CT05wQk7nOq/M7grsbw6/7NLDv5rk7GLCnOhixIA2zhTFpq1VpTk3W8sai3VPA4gvMi6wxuuYNjqrpWKiAbTlci0DY3bUu/wbVayo1H4GkBtixy9t0xfQdZLyQ67Tblh7RP8VPsdJZ9D30JAGehoLKSOwACiS28qBVLz35T9EM0GVIdJDHwnAkFcpXMNK0LsTSHlSphqF2nx+o07wlG+YcN67uGkNhBYsuBuRCdtUQLJHYPuHPffS9LGFGwMgk1bFrpWte0gTfhuv79D4YOBQGuMUQdojw6Ljtp/SefN9N6XUGQwYjtKHVABe5NqJf9roHewxANZtYpYNHZ4snD4IAmstcWOMiLT4e/5RkaUBKmf4ueMk4dK/UWl+VukjgSy2aQd3saKrPHnfljpzOncfAZsffEYDj33zbDPTD2VfnDTxK7/cshouEadGJRS8414UPbnybqyCVk2aDJgSeId+TTzLsDwzapilD8ERjvE+YNeATHnQYbYKZCy6vPZkGmIkJ8nGLqHFEVxHZrKJycEy9vO5YvjDUM6n7vHy7/RcrgnTZab2HCfHfJuXSZc+fZVWBoDjoDUaKV5uBE6pvUZcyf7Hwnqr9BMT23THUMZfTuRNjqEwPh5dv95WfoLHXKbrg3QPKw8SsJsfoTBBCPUgbrGmWZVBUaP7M1b4pqSRhJndn76YOFF/RB95lovCbAYwCvYFyeivU0tG+EpNSgfmO1NgvrmvBPvVaU+nqoqEm9y0UEttDOBU+IiCmC3rqICDggKCT0y2yb1cWMJvpyeKRsiBzCjdwfGvhsevM1P3n26vQ1LU9jqVxLAHRQRF3WDEkEdqDHwJWQmudlC5FNFX9UkEferh8LKqLw2m0EzwP1OdGi4J0Z2gNyhGtUvNWvkDyJboMA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:05:08.6295 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e6871cf-2b42-4526-c1fd-08dcfdd52611 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7131 For an iommu_dev that can unplug (so far only this selftest does so), the viommu->iommu_dev pointer has no guarantee of its life cycle after it is copied from the idev->dev->iommu->iommu_dev. Track the user count of the iommu_dev. Postpone the exit routine using a completion, if refcount is unbalanced. The refcount inc/dec will be added in the following patch. Suggested-by: Jason Gunthorpe Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/selftest.c | 39 +++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c index 92d753985640..4f67a83f667a 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -533,14 +533,17 @@ static bool mock_domain_capable(struct device *dev, enum iommu_cap cap) static struct iopf_queue *mock_iommu_iopf_queue; -static struct iommu_device mock_iommu_device = { -}; +static struct mock_iommu_device { + struct iommu_device iommu_dev; + struct completion complete; + refcount_t users; +} mock_iommu; static struct iommu_device *mock_probe_device(struct device *dev) { if (dev->bus != &iommufd_mock_bus_type.bus) return ERR_PTR(-ENODEV); - return &mock_iommu_device; + return &mock_iommu.iommu_dev; } static void mock_domain_page_response(struct device *dev, struct iopf_fault *evt, @@ -1556,24 +1559,27 @@ int __init iommufd_test_init(void) if (rc) goto err_platform; - rc = iommu_device_sysfs_add(&mock_iommu_device, + rc = iommu_device_sysfs_add(&mock_iommu.iommu_dev, &selftest_iommu_dev->dev, NULL, "%s", dev_name(&selftest_iommu_dev->dev)); if (rc) goto err_bus; - rc = iommu_device_register_bus(&mock_iommu_device, &mock_ops, + rc = iommu_device_register_bus(&mock_iommu.iommu_dev, &mock_ops, &iommufd_mock_bus_type.bus, &iommufd_mock_bus_type.nb); if (rc) goto err_sysfs; + refcount_set(&mock_iommu.users, 1); + init_completion(&mock_iommu.complete); + mock_iommu_iopf_queue = iopf_queue_alloc("mock-iopfq"); return 0; err_sysfs: - iommu_device_sysfs_remove(&mock_iommu_device); + iommu_device_sysfs_remove(&mock_iommu.iommu_dev); err_bus: bus_unregister(&iommufd_mock_bus_type.bus); err_platform: @@ -1583,6 +1589,22 @@ int __init iommufd_test_init(void) return rc; } +static void iommufd_test_wait_for_users(void) +{ + if (refcount_dec_and_test(&mock_iommu.users)) + return; + /* + * Time out waiting for iommu device user count to become 0. + * + * Note that this is just making an example here, since the selftest is + * built into the iommufd module, i.e. it only unplugs the iommu device + * when unloading the module. So, it is expected that this WARN_ON will + * not trigger, as long as any iommufd FDs are open. + */ + WARN_ON(!wait_for_completion_timeout(&mock_iommu.complete, + msecs_to_jiffies(10000))); +} + void iommufd_test_exit(void) { if (mock_iommu_iopf_queue) { @@ -1590,8 +1612,9 @@ void iommufd_test_exit(void) mock_iommu_iopf_queue = NULL; } - iommu_device_sysfs_remove(&mock_iommu_device); - iommu_device_unregister_bus(&mock_iommu_device, + iommufd_test_wait_for_users(); + iommu_device_sysfs_remove(&mock_iommu.iommu_dev); + iommu_device_unregister_bus(&mock_iommu.iommu_dev, &iommufd_mock_bus_type.bus, &iommufd_mock_bus_type.nb); bus_unregister(&iommufd_mock_bus_type.bus); From patchwork Tue Nov 5 20:04:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 840942 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2054.outbound.protection.outlook.com [40.107.100.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B669216A0A; Tue, 5 Nov 2024 20:05:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.100.54 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837116; cv=fail; b=TtjWVcoM4tutGrXY8cwvVB7lK4o3mPul77fpb/dwTCynxFjLkXj1RU5ckl5Z5SIGmrYTRykpZPGiE/uWAWTG3fpGiYWPVrNgDJ3e7nNoj9oym6LrbZwNt5SsOCh4UthpytodlJW3EMa5PDCHo+IHKrBpj3PtpH3HgMMsA4KBc08= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837116; c=relaxed/simple; bh=XAnHHsXmfB9omCBKJVEBuBtMUpCwsE2Iax9K1of39lY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WP4H1eux8ynne/4v0vbVg5V39t4fjbn8EnR5EzsBH+ORmnPZoS0k9UN+AvwkOpe2CV32Q5bUMUVGLS9gC+a9UcYJE/qhmvdFcr3LHQlI9OM6U+fXw3+kAlRncrz2rbTPfAa+gjpfr4nhbMWnTKJfPGNSjAmRUB4TvyldOwykPkU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=YXdH6RTK; arc=fail smtp.client-ip=40.107.100.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="YXdH6RTK" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=u3jAqIYZKLRUwQtqVrDfErdrYhlIYYNkBRGx/qMZ2Sfqpsvd8qZriLXuhvcJRJcbHkudUM1N5XQs6Y7HTElVx34nJmfo/2UbCrYFeUWNlJY1KcepUxxeDtqEYwDj1Rqfzq3tPCWIzzdQs04gn3bio3W0yZI/9PSQybt1tIOHRBhOmk/2a+6He9GLtiEuDKLFwdSU2lpLguAI2hIIyLuqyDDBFGNV62P5dDj9RogIUCbgkIi59ilSbL9sSoIaca75ZT+TiwUwV9CQy8SO7vIUm7VWTBHxir8UJLl/D0Ydn2lPJcZvKuIiTWEyqTaPFikdiMBWsHQDiO6N3e1ajJilCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8KzkVgcFO0ftegl7pn6y2UsVmj7zwEHZ8Ed8lJfivy8=; b=Nf17FhKG6HZvUKiC/dtjtCRsdDzJJSWYG6y1VXTL8+NW1AiVQVWxwpkGfTPxzJY77/91koOwH79ytYMubwsy2p7CaqvipNTxYqwKL66Hk1m2rorGYs3vdFSfbwwNND14ffR+dBA8GFlSNjxXQzXRINcc+v04yGDL76QHdJVu/oquXG2TaiBKAW8YXCEgLmlhTAw0GnuLW0E/HPHZKjCCuJlv518EsW1S/sCuMqEb8Oe6xY1rM4UkSkSvLCZg3AXhADWZdPAPpz/WNRVReB/Wil6/vpoVlLIHdgQocCcz2yrTJmLw+WJFfXL/yDJnoNbBCoTlyJhHovlfjwgwyx4DSA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8KzkVgcFO0ftegl7pn6y2UsVmj7zwEHZ8Ed8lJfivy8=; b=YXdH6RTKiUW2SEgYHUl0wgvG7haYYnldkIbP6h+5lxoZFVH9t+gvWctNmSd2ibsH1I5XsoqneV/4yCU07liBrnTHDOl32vOJEM/YOVe7rVpRNiXFkjqL9c9XuRa2zQ63rWe3fM30vsxxk073oWt0IPxsVKQeKnxqdxi/qAeBG/2gJxmMZNWJwAiY8AWUW7LRkDv0YlgYtMHDmfcuqAnACokABjNKqtZbIr1CKiVoENxWxyxU9KKMtBTONPL3hu4ke8aKKQPWTcK7nvHsnc1xAfrPvD4yv9P5pziczGxUlgl9tO8BRTrR6fBmZ6uj0Oqt2g7UEGlasp7m/aYFLxF2EQ== Received: from LV3P220CA0023.NAMP220.PROD.OUTLOOK.COM (2603:10b6:408:234::24) by DM6PR12MB4297.namprd12.prod.outlook.com (2603:10b6:5:211::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.31; Tue, 5 Nov 2024 20:05:10 +0000 Received: from BL02EPF00021F6E.namprd02.prod.outlook.com (2603:10b6:408:234:cafe::8d) by LV3P220CA0023.outlook.office365.com (2603:10b6:408:234::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.18 via Frontend Transport; Tue, 5 Nov 2024 20:05:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00021F6E.mail.protection.outlook.com (10.167.249.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:05:09 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:58 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:57 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:56 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 11/13] iommufd/selftest: Add IOMMU_VIOMMU_TYPE_SELFTEST Date: Tue, 5 Nov 2024 12:04:27 -0800 Message-ID: <9d755a215a3007d4d8d1c2513846830332db62aa.1730836219.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6E:EE_|DM6PR12MB4297:EE_ X-MS-Office365-Filtering-Correlation-Id: 353d9e5d-1826-48c1-ba48-08dcfdd526af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: p0Zvd+x+eAtIXY3R5grbqwjyEmmoNY272PH1Hh/EFmndYV+IOmEwxcfx/OAuDHbYxPXMDQ95Ap5Mpf1H8mTdx4fa1XEpohBG8EHuaZt7hy1OCOzCE0DdjJf+hTbWCjnRebcAzurNopSDVtmcq4gpXA1ck+qPRUnSdWLKXxd8oY1GDKmjbuvHW1fKnER/QwtyMuntBtfyrx5oPh+EBmwnsIr2X4Xfcz+XT+8NmnR3xa7BCxVZsrRVx3aSZ3wLhxVPqYWOy2lo/LynoU4Kprp777DSa3hxaBPbLMDbCNqjgHzCVmslfbM5Y6yllZloXyYYZxpCwB1kyMo7NPobcuqi9q6Dh+tGy42c5y7XvaNVOxZbFeTVV0HW76QCtIVKjV5S5GmN3W44MYh+/F/jAPbPW13uPHVprwYaMhiRTXEUgxKItoFPrqhmnWdoYXrlPUATDUyAg1PONnBGG6gtgUz2cnwpKwYD60D8q8aeIavj+mx7e5+QVxby2+AC4oIlKTJH60f4CSEKlFEKGhsB/WcGd9jn/oZMxDEZwkv79st1G0RU5wqgb6tBMU+uqqFUaagJOkoFsEoia30ZAyC9K66gBuvthgpXuV/32fQ6kDq3p2vINsatzjrUPDWZAOxRe8vjjvhUUJ7zZpzvRFjwOxB5Ri9PouOl98hkpc/YV7JhuhRST9OqmWuNm3NMb3Qb42T4OqNjX7QDu5r0hKTYZoklHwmlC/vd4rOwwNg4LurdZrJnik6levyInCd61j06lAhEPTKKFnZxUaph5WBC46Vp496l196lBsf7TXVwmP6mRnZK9IRmEZR7a/agQW/gNUOwS/poSKUvy/jV6oLruPkSQBTIBBRZqN2XzddXfpjxxrTVn9MIIJrakFprruQAHTEyTY4X3hzXeucalqkFPNDh+suqe3STcaqhFavwGZlhyu8kd1/E0wGU6zute0V7RWvezWhtdwQSqiYxq3gEaedm+80mdBpPPMQzIo2vOhJ5SItePoxwH6XifTpoUAnqUmQ5KfHtdRckNE1uxbf5xSkAK9L22pTqBkiCncBf6Ng6cWFEPN2KIj9tyt9ba5n/3yPySjbxgzBNK6nqqPJ2q5HJbg9k0teFtKOIc3DvAd61RbGIOPozwzKLbJUNQ6YhiCPI1KHmUgBchHf7KMIfKq0ejxd2gRxWbG8eOZMj3OXHOFy3VCDGyHKxq/p8aZSPiz2xRYgsO4jdyJf4mj4qhdGkkhK2PuD0a8YQJ8kHr9rj4wi03NebjDnOBC9R1vfJIin36XP8hPjXpLLYioIP4gV0lsCMLe6IMFtcJZiLoJuNpQAnk3gO16ebM4gMl9/r2Ni7crP69FCIz5Vl5ZWCGU/391CRwx7ymf6HYjfhdbpDxwph07+49y4ZThS+sLK6VBJxbeL5kCq2s4xaN/raUWwMAg== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:05:09.7117 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 353d9e5d-1826-48c1-ba48-08dcfdd526af X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4297 Implement the viommu alloc/free functions to increase/reduce refcount of its dependent mock iommu device. User space can verify this loop via the IOMMU_VIOMMU_TYPE_SELFTEST. Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_test.h | 2 + drivers/iommu/iommufd/selftest.c | 67 ++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/drivers/iommu/iommufd/iommufd_test.h b/drivers/iommu/iommufd/iommufd_test.h index f4bc23a92f9a..edced4ac7cd3 100644 --- a/drivers/iommu/iommufd/iommufd_test.h +++ b/drivers/iommu/iommufd/iommufd_test.h @@ -180,4 +180,6 @@ struct iommu_hwpt_invalidate_selftest { __u32 iotlb_id; }; +#define IOMMU_VIOMMU_TYPE_SELFTEST 0xdeadbeef + #endif diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c index 4f67a83f667a..31c8f78a3a66 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -134,6 +134,7 @@ to_mock_domain(struct iommu_domain *domain) struct mock_iommu_domain_nested { struct iommu_domain domain; + struct mock_viommu *mock_viommu; struct mock_iommu_domain *parent; u32 iotlb[MOCK_NESTED_DOMAIN_IOTLB_NUM]; }; @@ -144,6 +145,16 @@ to_mock_nested(struct iommu_domain *domain) return container_of(domain, struct mock_iommu_domain_nested, domain); } +struct mock_viommu { + struct iommufd_viommu core; + struct mock_iommu_domain *s2_parent; +}; + +static inline struct mock_viommu *to_mock_viommu(struct iommufd_viommu *viommu) +{ + return container_of(viommu, struct mock_viommu, core); +} + enum selftest_obj_type { TYPE_IDEV, }; @@ -569,6 +580,61 @@ static int mock_dev_disable_feat(struct device *dev, enum iommu_dev_features fea return 0; } +static void mock_viommu_destroy(struct iommufd_viommu *viommu) +{ + struct mock_iommu_device *mock_iommu = container_of( + viommu->iommu_dev, struct mock_iommu_device, iommu_dev); + + if (refcount_dec_and_test(&mock_iommu->users)) + complete(&mock_iommu->complete); + + /* iommufd core frees mock_viommu and viommu */ +} + +static struct iommu_domain * +mock_viommu_alloc_domain_nested(struct iommufd_viommu *viommu, u32 flags, + const struct iommu_user_data *user_data) +{ + struct mock_viommu *mock_viommu = to_mock_viommu(viommu); + struct mock_iommu_domain_nested *mock_nested; + + if (flags & ~IOMMU_HWPT_FAULT_ID_VALID) + return ERR_PTR(-EOPNOTSUPP); + + mock_nested = __mock_domain_alloc_nested(user_data); + if (IS_ERR(mock_nested)) + return ERR_CAST(mock_nested); + mock_nested->mock_viommu = mock_viommu; + mock_nested->parent = mock_viommu->s2_parent; + return &mock_nested->domain; +} + +static struct iommufd_viommu_ops mock_viommu_ops = { + .destroy = mock_viommu_destroy, + .alloc_domain_nested = mock_viommu_alloc_domain_nested, +}; + +static struct iommufd_viommu *mock_viommu_alloc(struct device *dev, + struct iommu_domain *domain, + struct iommufd_ctx *ictx, + unsigned int viommu_type) +{ + struct mock_iommu_device *mock_iommu = + iommu_get_iommu_dev(dev, struct mock_iommu_device, iommu_dev); + struct mock_viommu *mock_viommu; + + if (viommu_type != IOMMU_VIOMMU_TYPE_SELFTEST) + return ERR_PTR(-EOPNOTSUPP); + + mock_viommu = iommufd_viommu_alloc(ictx, struct mock_viommu, core, + &mock_viommu_ops); + if (IS_ERR(mock_viommu)) + return ERR_CAST(mock_viommu); + + refcount_inc(&mock_iommu->users); + return &mock_viommu->core; +} + static const struct iommu_ops mock_ops = { /* * IOMMU_DOMAIN_BLOCKED cannot be returned from def_domain_type() @@ -588,6 +654,7 @@ static const struct iommu_ops mock_ops = { .dev_enable_feat = mock_dev_enable_feat, .dev_disable_feat = mock_dev_disable_feat, .user_pasid_table = true, + .viommu_alloc = mock_viommu_alloc, .default_domain_ops = &(struct iommu_domain_ops){ .free = mock_domain_free, From patchwork Tue Nov 5 20:04:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 840940 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2076.outbound.protection.outlook.com [40.107.244.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AC2C215C6C; Tue, 5 Nov 2024 20:05:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.76 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837121; cv=fail; b=aZN6hB5x6pTtX+spbBp06bQ1xQbhIfOVYItbNeZfKztoQAiqU3fsNYhnGkCthDCp9/p20MbM3adTXyWUfZ49kiYePdEjeLjZufjlxhhTuZJ43wmoc6HZalJi0dMTqhpxEUvYvHhvHwcP098qntudPSmpWwUPilURVXGbaaIzMBc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837121; c=relaxed/simple; bh=UFeNtUCfE3Sycpaa1cglfzuNKH62h+f73QJE7bmmOg4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hZJbOdY1/nCHMFz3vuBEaIpJv49mpQbwpjMM6CJGmGVFJEMcBOxEcqdGagx8f31yPsJ7yrAvA+doRjlPz7BJjGMmhjjsKZ29abiI/JQlNg0YAh0QJaG8tJ/49DNeTPhXoz1deV/6Bybi/FaNLSAxJi7kOZUM1s86sORaKruMqIQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=g5lvnbj0; arc=fail smtp.client-ip=40.107.244.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="g5lvnbj0" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DpRoU583KBDGUoHoCqwupx26wIlEqUbv5gqE78/yV/pp+Myy97FGUZ/gm8XW3Ov7hZ9Ks2R2bI+GvZzjv8fnRpKHyvwD4NHaQAqCvjOEqqmFuBJ4nXITPVspQDm6qgt0Yu3kNHqMnhy9cAX0+zWhM5+lhbqoQqJE6Q8GRaaw4lSlpi0RmozU2fKfXU2h2qQBRgZjrHioMDURUIRIyBy6AIFLpuvBa8Mv/Zkg7A+OLz/iVPucS1zSaZFZVeQnB0SFpwMpU9v7ZF45saZM335bGdPCOzwhTYzXvwdBNfmnsC4yAWGih+E2a9j7CO/SXSlL9nrs6pFbFzZmG30f/Gb1tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=B5BUJhxm/I2QYALcz0voEjRrzsULOrrfaKjMZN/4xEs=; b=k27xFgv/Zzzbcxu/aa0Mw0NCZ2ONr4db1vr4f8zfqixr5C43pQDFyow1nFvnsHIP61WQq35IfZzCT9Jtf2MRX6ya+LvHw5AEp5f9z5wypkgc+tf0JnQ9hkM6Lsxh06znEejhyP0dYWHR+WRXzlqaiLhfOoSY8uzuXmeM3T1cjQWmMk9buSWa81v0GsVA7C5dp35eSkWt5F2HdVKbLzIFb4ZtNI5KYCvj6YcvsVpy4vAQKxCUreNZN11HvnALZ74+axkSNpaV05OdrH6K6VqSEb3qLgiTlM3jdft8Bipa+ySEj3mAu1Y5qgrYJTk9KlJmt8vgePSpzz7iMr/K3S7jFg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=B5BUJhxm/I2QYALcz0voEjRrzsULOrrfaKjMZN/4xEs=; b=g5lvnbj03NKozNTu9jB5gaGKZXBagFtba9hV9lWlSUVbx8/igOi8ixVBB7e8jOsTWva2ZtUj/v6L2plYKl1gppAxBEz/duH1Tt4/RG9qTDPS5f7DS8iyn7Zt7SCqxDF9qzpKD7MyNBypriRPsoGbVtVAJjjY4t+YCLjOdFe6S363XNTjBHeR2Vh8o84PYyw1wqWXJFBLPnFFubfATBDtsmGvK6qa+xG6WKHcEdbJsbGZk/jVX++BMbK/wf8IBD05drhBpyQecPij4UkPtccTzDbaR/mqS5c1obE5n2wKb++lVxzDE+yeWsSkI3xF/AfLojVhx5sCLuV2iWbJBMSNhw== Received: from BN9P222CA0016.NAMP222.PROD.OUTLOOK.COM (2603:10b6:408:10c::21) by BN5PR12MB9461.namprd12.prod.outlook.com (2603:10b6:408:2a8::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.30; Tue, 5 Nov 2024 20:05:13 +0000 Received: from BL02EPF0002992C.namprd02.prod.outlook.com (2603:10b6:408:10c:cafe::c5) by BN9P222CA0016.outlook.office365.com (2603:10b6:408:10c::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.30 via Frontend Transport; Tue, 5 Nov 2024 20:05:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0002992C.mail.protection.outlook.com (10.167.249.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:05:13 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:59 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:04:59 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:58 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 12/13] iommufd/selftest: Add IOMMU_VIOMMU_ALLOC test coverage Date: Tue, 5 Nov 2024 12:04:28 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992C:EE_|BN5PR12MB9461:EE_ X-MS-Office365-Filtering-Correlation-Id: f4907721-3aea-40ce-eba1-08dcfdd528c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|7416014|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: 5z3icSKAqRqZHCkn8Mdqh4gAUbxxP3HCrnuRt8Adn851dY7LzBqyjl8XSVD3JBXyrdT+mWSLWjWk11KVw1YQ021EQGARXmiHGTIInLyH/lzUXBICKUWsU8uJIh4OwT/IxE3MYzBSk3P0VOqEAnL8i+LroHgWy7MS+eGIcjN2P196+G3xu5Gy/3ULXtNPwn30oQEi3FSvhMLLqzswwQqtbPhqDfWd2VMGmTkSM+LlBB6heqhYAX/AMy0S5e18kCCepszO17PctgdNHAG1dWoX0GUax80mImdHVSB69Mqsw30w4fPP99PCEoQ+5OjtxPVjqORywpiqRB7fy/uCe1frS/eRuyLF/lV8oJi5qoyRPj4hMS6etyCk4UL7VFWS2JQlvyC220cO12zqaAN6RvUEycSRF96riFDona0woRGSr65cVdnJpJvAziPLCn49TZAqisR9Kc4hKCInC2Wrl8pWyUIW8ZIXGv/NPQ5/L05tRsroklIWK3hoVNUSG4wxeufs/4convdKzPzW8S/fUGrtO0FXerHZOXbGcMNuwCtP20iJeGWRJw9AoGsBQjk6eyozypOKDuZq+7V1D6SX0FN3vVeh8FI5v2OvuEXgzBIzsRdkjGT0DxrBhjVQ7/hg/j/uGHUdNkLTMaDT6nvS2mnWGcjwbajsCTLgBF8vwUDFaUdSxrHxMOvOy9nzheVp2JCpFneDuu58LsSspo0KQ+GzexXelnvb3SGVCASyuHJrVgE1/pAwEJp+cxLHQ4J3P8DBjGGdfhoZky+8/lXoTZXAfPXVHDNnmeRJJPgTwJQYYFTTrlraq3/lxQfytOBuWiTpSYEBIHdlcgfWizOY91HySUSp0wFbGo+frjjzUFE+aJcdusbzo9Ku9owtxsznncvkQzpq/s2TThoGHnybU06ORdUrEqroZ7wydfXiOeKssoCOCu4QuNDTk/Vrwp4TCDSJ2+PgJ0iDoK9mUtAeBGKZz8Cuht8SiM5vbDK/3nzSsHWkNW2ZJRG1Ml/aX9b6uMTz2YZg0N3dYHDWxeoRwskfRT/2EE4R4mkJP01d24fWkv/R/wLQOvFMZjaClPilRQv8YVTTfT6/TlEI6ggaGSLnZCJaOPConmW2uLwLmF8c69bz+EOsbSMWoc+0FhPEVPyJJh3TCspKpxJ9O+bzA4MxowwaAIIl976UvHMFwB9g+zXXv8CRnXeGStmgVfhMfWWQTp6JIErWiU4W0wA+TQp4wF6O6gepn1iDHEXVHRyI+9wJ4BAdk2rFi6k4XhYy9Gvk0Q44c5AyPFo7/0+LLDaZQbSGmX/JSpQdVEPVxddAl0byxCbXB/UkUtWiX8f/F0/vVHJUh8VAgweqYx5CDezKp85mlmDmQqOMaxXAfIpDvyl1Vf+QiQ6CDRko/wdTSxrysdeGczGDkui6jrOTViEpUA== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:05:13.1697 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4907721-3aea-40ce-eba1-08dcfdd528c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9461 Add a new iommufd_viommu FIXTURE and setup it up with a vIOMMU object. Any new vIOMMU feature will be added as a TEST_F under that. Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen --- tools/testing/selftests/iommu/iommufd_utils.h | 28 ++++ tools/testing/selftests/iommu/iommufd.c | 137 ++++++++++++++++++ .../selftests/iommu/iommufd_fail_nth.c | 11 ++ 3 files changed, 176 insertions(+) diff --git a/tools/testing/selftests/iommu/iommufd_utils.h b/tools/testing/selftests/iommu/iommufd_utils.h index 6a11c26370f3..7dabc261fae2 100644 --- a/tools/testing/selftests/iommu/iommufd_utils.h +++ b/tools/testing/selftests/iommu/iommufd_utils.h @@ -819,3 +819,31 @@ static int _test_cmd_trigger_iopf(int fd, __u32 device_id, __u32 fault_fd) #define test_cmd_trigger_iopf(device_id, fault_fd) \ ASSERT_EQ(0, _test_cmd_trigger_iopf(self->fd, device_id, fault_fd)) + +static int _test_cmd_viommu_alloc(int fd, __u32 device_id, __u32 hwpt_id, + __u32 type, __u32 flags, __u32 *viommu_id) +{ + struct iommu_viommu_alloc cmd = { + .size = sizeof(cmd), + .flags = flags, + .type = type, + .dev_id = device_id, + .hwpt_id = hwpt_id, + }; + int ret; + + ret = ioctl(fd, IOMMU_VIOMMU_ALLOC, &cmd); + if (ret) + return ret; + if (viommu_id) + *viommu_id = cmd.out_viommu_id; + return 0; +} + +#define test_cmd_viommu_alloc(device_id, hwpt_id, type, viommu_id) \ + ASSERT_EQ(0, _test_cmd_viommu_alloc(self->fd, device_id, hwpt_id, \ + type, 0, viommu_id)) +#define test_err_viommu_alloc(_errno, device_id, hwpt_id, type, viommu_id) \ + EXPECT_ERRNO(_errno, \ + _test_cmd_viommu_alloc(self->fd, device_id, hwpt_id, \ + type, 0, viommu_id)) diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selftests/iommu/iommufd.c index 88b92bb69756..37c7da283824 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -133,6 +133,7 @@ TEST_F(iommufd, cmd_length) TEST_LENGTH(iommu_option, IOMMU_OPTION, val64); TEST_LENGTH(iommu_vfio_ioas, IOMMU_VFIO_IOAS, __reserved); TEST_LENGTH(iommu_ioas_map_file, IOMMU_IOAS_MAP_FILE, iova); + TEST_LENGTH(iommu_viommu_alloc, IOMMU_VIOMMU_ALLOC, out_viommu_id); #undef TEST_LENGTH } @@ -2480,4 +2481,140 @@ TEST_F(vfio_compat_mock_domain, huge_map) } } +FIXTURE(iommufd_viommu) +{ + int fd; + uint32_t ioas_id; + uint32_t stdev_id; + uint32_t hwpt_id; + uint32_t nested_hwpt_id; + uint32_t device_id; + uint32_t viommu_id; +}; + +FIXTURE_VARIANT(iommufd_viommu) +{ + unsigned int viommu; +}; + +FIXTURE_SETUP(iommufd_viommu) +{ + self->fd = open("/dev/iommu", O_RDWR); + ASSERT_NE(-1, self->fd); + test_ioctl_ioas_alloc(&self->ioas_id); + test_ioctl_set_default_memory_limit(); + + if (variant->viommu) { + struct iommu_hwpt_selftest data = { + .iotlb = IOMMU_TEST_IOTLB_DEFAULT, + }; + + test_cmd_mock_domain(self->ioas_id, &self->stdev_id, NULL, + &self->device_id); + + /* Allocate a nesting parent hwpt */ + test_cmd_hwpt_alloc(self->device_id, self->ioas_id, + IOMMU_HWPT_ALLOC_NEST_PARENT, + &self->hwpt_id); + + /* Allocate a vIOMMU taking refcount of the parent hwpt */ + test_cmd_viommu_alloc(self->device_id, self->hwpt_id, + IOMMU_VIOMMU_TYPE_SELFTEST, + &self->viommu_id); + + /* Allocate a regular nested hwpt */ + test_cmd_hwpt_alloc_nested(self->device_id, self->viommu_id, 0, + &self->nested_hwpt_id, + IOMMU_HWPT_DATA_SELFTEST, &data, + sizeof(data)); + } +} + +FIXTURE_TEARDOWN(iommufd_viommu) +{ + teardown_iommufd(self->fd, _metadata); +} + +FIXTURE_VARIANT_ADD(iommufd_viommu, no_viommu) +{ + .viommu = 0, +}; + +FIXTURE_VARIANT_ADD(iommufd_viommu, mock_viommu) +{ + .viommu = 1, +}; + +TEST_F(iommufd_viommu, viommu_auto_destroy) +{ +} + +TEST_F(iommufd_viommu, viommu_negative_tests) +{ + uint32_t device_id = self->device_id; + uint32_t ioas_id = self->ioas_id; + uint32_t hwpt_id; + + if (self->device_id) { + /* Negative test -- invalid hwpt (hwpt_id=0) */ + test_err_viommu_alloc(ENOENT, device_id, 0, + IOMMU_VIOMMU_TYPE_SELFTEST, NULL); + + /* Negative test -- not a nesting parent hwpt */ + test_cmd_hwpt_alloc(device_id, ioas_id, 0, &hwpt_id); + test_err_viommu_alloc(EINVAL, device_id, hwpt_id, + IOMMU_VIOMMU_TYPE_SELFTEST, NULL); + test_ioctl_destroy(hwpt_id); + + /* Negative test -- unsupported viommu type */ + test_err_viommu_alloc(EOPNOTSUPP, device_id, self->hwpt_id, + 0xdead, NULL); + EXPECT_ERRNO(EBUSY, + _test_ioctl_destroy(self->fd, self->hwpt_id)); + EXPECT_ERRNO(EBUSY, + _test_ioctl_destroy(self->fd, self->viommu_id)); + } else { + test_err_viommu_alloc(ENOENT, self->device_id, self->hwpt_id, + IOMMU_VIOMMU_TYPE_SELFTEST, NULL); + } +} + +TEST_F(iommufd_viommu, viommu_alloc_nested_iopf) +{ + struct iommu_hwpt_selftest data = { + .iotlb = IOMMU_TEST_IOTLB_DEFAULT, + }; + uint32_t viommu_id = self->viommu_id; + uint32_t dev_id = self->device_id; + uint32_t iopf_hwpt_id; + uint32_t fault_id; + uint32_t fault_fd; + + if (self->device_id) { + test_ioctl_fault_alloc(&fault_id, &fault_fd); + test_err_hwpt_alloc_iopf( + ENOENT, dev_id, viommu_id, UINT32_MAX, + IOMMU_HWPT_FAULT_ID_VALID, &iopf_hwpt_id, + IOMMU_HWPT_DATA_SELFTEST, &data, sizeof(data)); + test_err_hwpt_alloc_iopf( + EOPNOTSUPP, dev_id, viommu_id, fault_id, + IOMMU_HWPT_FAULT_ID_VALID | (1 << 31), &iopf_hwpt_id, + IOMMU_HWPT_DATA_SELFTEST, &data, sizeof(data)); + test_cmd_hwpt_alloc_iopf( + dev_id, viommu_id, fault_id, IOMMU_HWPT_FAULT_ID_VALID, + &iopf_hwpt_id, IOMMU_HWPT_DATA_SELFTEST, &data, + sizeof(data)); + + test_cmd_mock_domain_replace(self->stdev_id, iopf_hwpt_id); + EXPECT_ERRNO(EBUSY, + _test_ioctl_destroy(self->fd, iopf_hwpt_id)); + test_cmd_trigger_iopf(dev_id, fault_fd); + + test_cmd_mock_domain_replace(self->stdev_id, self->ioas_id); + test_ioctl_destroy(iopf_hwpt_id); + close(fault_fd); + test_ioctl_destroy(fault_id); + } +} + TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/iommu/iommufd_fail_nth.c b/tools/testing/selftests/iommu/iommufd_fail_nth.c index 2d7d01638be8..fb618485d7ca 100644 --- a/tools/testing/selftests/iommu/iommufd_fail_nth.c +++ b/tools/testing/selftests/iommu/iommufd_fail_nth.c @@ -621,6 +621,7 @@ TEST_FAIL_NTH(basic_fail_nth, device) uint32_t stdev_id; uint32_t idev_id; uint32_t hwpt_id; + uint32_t viommu_id; __u64 iova; self->fd = open("/dev/iommu", O_RDWR); @@ -663,6 +664,16 @@ TEST_FAIL_NTH(basic_fail_nth, device) if (_test_cmd_mock_domain_replace(self->fd, stdev_id, hwpt_id, NULL)) return -1; + + if (_test_cmd_hwpt_alloc(self->fd, idev_id, ioas_id, 0, + IOMMU_HWPT_ALLOC_NEST_PARENT, &hwpt_id, + IOMMU_HWPT_DATA_NONE, 0, 0)) + return -1; + + if (_test_cmd_viommu_alloc(self->fd, idev_id, hwpt_id, + IOMMU_VIOMMU_TYPE_SELFTEST, 0, &viommu_id)) + return -1; + return 0; } From patchwork Tue Nov 5 20:04:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 841896 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2054.outbound.protection.outlook.com [40.107.101.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D041216DF5; Tue, 5 Nov 2024 20:05:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.101.54 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837121; cv=fail; b=LC7UB8sJeMsBkLJu6/L0v7+QR9mZhNlj7wTcDVf7tL/Heedyx2dKnAOuABS1ae/9CzCDzlZAYiuaLkN8qWqYxUNEwL5h6YbqC+JkSdQgmC9nxN6ZekPtDFUIKXY3PKsFS/tW1fyCnteugz6KzIgzBWFMiMgVAwvo59NkbgqpANc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730837121; c=relaxed/simple; bh=Bc7irgx/6rjjEyhgYWm5e4HG/xlq3Zz6q1tfakfeWrM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GFzIVlHs8ykTqSVv5YWMxWfCrrtJUY6ai30Nu5UntpECDbNR5TrjnWpLDOlR2Gun3wLKn2nph/5mMHMmHo7l4klx6VuzHHSI0nD1ZUVOF/t6WkLL2pRNEGCz2i2Gy72r/X8S1Qk9+kKJaWOTd4Gt//Z7EjPRJevPTpkhwxUAFCs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=FM4pZHyt; arc=fail smtp.client-ip=40.107.101.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="FM4pZHyt" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=cW/DybCJ8WyO1gMd47FZcieCRvS+xh5RZsxlKOQYCIX7wyr15W6df+6OLw4rK2N+bshlaQEhXD0aem/z1W3naKVfs1cmZJpfFhbLAgrfUFdLw0WY8muMrykn81+ptzU8p7gvX8j1/x/y7K2pnei+OcqZCikNB7zMf37mlc/ZekQeULaYRqO7Hp5f++o7eE5/bVBy3mJef4/J7qlAopVUsLhd2DeFTmTrlBZDxg6b+S3n25cnubyq7zP9VwNxr23NQyrKIZWFOIMJMmdY5S8Fsdeo9goAp0LvCUeJlO6q39/K/I0D5ODS+Lnb5TA37bOZgrqZ9lSUWOGHoUy89KvESQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=LEMmgACXamRJHRJ8k8PHyMQpZBwcJXQxMazWsnOea9A=; b=jsUg87QzWLC/Rt3wJKsNMNrHiPv7i4+AvmuRwWGTjANU2cfImAVD65H2MCbdvfFekPRuWsJtXXsjBJGpkeU0ektVhIVqz5Sxc3zZZZF7ZcJey023qK1TxJGys/aR23CWhp6BZYGmIS3fTPqBqTE1SqPuuTk4ItzdHQqRxGkh9fZjPp3M860Wtu/vKTTfPR370MupmQXuH+luOTEka/faipAd4Bh9E5miscmfiIG8vJXH93skMvuS61tFiwaJs8ATaxWtnlbS7m45+IyKwVtQK8RvU3HuNo7X0MFBKGgHaDdtECRjHzuNd2DpMdrxn184NfjMATiBSddY8bhVFI16LA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LEMmgACXamRJHRJ8k8PHyMQpZBwcJXQxMazWsnOea9A=; b=FM4pZHyt9mpAxXsMJ/Z2Fp/Ixto6XRmnPfDYgNt4BiiG5I1Z66eOp9PRrN5Iu4n9PVaxJs9LL+FYRXLl9Kz5Ouuol6DECciYAV/4QRIMbkVfkUoNcrY8WeMP+cgrkuDH0HjlNsRKBOdPzRxBHuPQgCdvy7fYLTFa15XzLtId9Guv/Y36SXWl+S3s2FBMBh2kNRj3+j0EyaOLbEp1/y+T07kZVRnkZ0T1MF9Tm6x+x+rFCSdQI0BfIMinxfJIgssHKF8F73cYhSP3uH3FFyC850zi8JNLXOH6R/0uaH7j7uptXAOyog0P0HuvTtUJCmLzI2D8hQnPhFM3wlcTyAt+Vg== Received: from BLAPR05CA0014.namprd05.prod.outlook.com (2603:10b6:208:36e::18) by DS7PR12MB8292.namprd12.prod.outlook.com (2603:10b6:8:e2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.30; Tue, 5 Nov 2024 20:05:13 +0000 Received: from BL02EPF00021F6C.namprd02.prod.outlook.com (2603:10b6:208:36e:cafe::37) by BLAPR05CA0014.outlook.office365.com (2603:10b6:208:36e::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:05:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00021F6C.mail.protection.outlook.com (10.167.249.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Tue, 5 Nov 2024 20:05:12 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:05:01 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 12:05:01 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 12:04:59 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 13/13] Documentation: userspace-api: iommufd: Update vIOMMU Date: Tue, 5 Nov 2024 12:04:29 -0800 Message-ID: <7e4302064e0d02137c1b1e139342affc0485ed3f.1730836219.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6C:EE_|DS7PR12MB8292:EE_ X-MS-Office365-Filtering-Correlation-Id: 563c5146-2f93-483b-e013-08dcfdd52897 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: ImQ5HBOh/WqiW8iecn03QkosyRHVdFRNrUaM0r8OuTjX9NI565/JTqgnxxCh8OeX3yH0xtUxRAg38r7C1HOpEiFnRKhKH9SNGrbdcS9YU6L8mcFBKAyoGO21Gwtp+kvlUb4fRsYP7WZwzc5/FOrnBHYRaqDgh2I2kgNamZ98pzLKscZcH4VdUakf4lbajv/v1sSJIWI+b3l1DiZ73IkUsAVDwKUtn898D0ujzm5rP7kVRG9GJphBw+6jd5M9T2qghtGkGzzVrUt9gkxEBUw+v3B61zHDhsGy63zpnpJ9yC46wVBefmi63GI8w407erP1ssNY1RBPLPyeM5KDli93LMxA3NLeduoZfqwAcvcTyw/XG10JE5vwhYTTxATu7JI6qi6rYzfc+mgZ1JZZRZOZidgASGPmcI46JH8wJVWYlGhNrr0Izu5xAq7HlZHLTM11KmdnM+scq6+xjaH+MN5oXeE0F+8xurm634DFhE26WpAfeJQSLQZvXD0fylW0ZdfIRzBTzE70x2nv8GLjBu2BzT0iBRpGlJNFUYyxirS+Ip1Nsn1HoKuYWdqTGIRxtWYnMnVVYh5pflR5pQjHzGscftxyPoFNxoyITvEW+ibmNFSNxeiHdqFpm1oZ90/lMvPXivPho5OoPe5ZuSjcGW9GWLGK+3MKw7O9YQe4L27VzOzEzeo9LMhNkwKuIiLg0fNv91dgifwWqZywfS3Pp09xjst8kLue34pBSFDdDhTlXdLaAeu7Cq5WYfejBK9plOl9rPsBQzrY7FwP9pHkuJL7OA3hoancF5Yf5BkZnkErxuKfMQGDbrQaytJ3QWtL02VekTIov8RvziOUAw1bMsqICw1SvE2MXxwwbyZG5t4Ti1zpmMt/0OfPtPOjEafsVgdvvRWxlYto4GEORkudN5pMUHx7gp0aqHp5o12EJflBZancvMytBhpx3B6E0mz2H3ErfWfv+cYzZqlT9AwfdK8qj6XL7AOo5QohTaKM/s9NQJvXwpk9b+X18CZRfHvsPSgp9zJ3UqVVOVe/MMmSq7L11axrhvMQU7uemrIXgC5mulhoQteq8z+Be68qLX7DOZ+8Am24Hh4lx+dK1rgd+A45/bppt6NaMmKzbZlXCXIxmn7EBQlt/Gkq+2NKnN4BpCXgDwU5wZ3y2Kz18j+9Sp3ICKGpgdSEZNffXMYZSMP1b3ELYvuq9js1UD567wIGjVO9GYjUikhQTRvtAe0knUZ2gaJKcywywxd1LokF5el4Lcg6N/dSzxYXtg0OquMeNfcciqSJHTHyQvTrGJxgjUzxFKZcuOQJHDmRByvZNgTUH3Y02ov7Lt6ZNWKcvc94aJNkYafKV0mS1FXkkbcOTJElO6PiRQeP4j0q0i/x1JRxAb6s2672m3jK3+q1qo3bCkE1PgGAarW/ZVORVJj+2tEJ4w== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 20:05:12.8639 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 563c5146-2f93-483b-e013-08dcfdd52897 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8292 With the introduction of the new object and its infrastructure, update the doc to reflect that and add a new graph. Reviewed-by: Jason Gunthorpe Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen --- Documentation/userspace-api/iommufd.rst | 69 ++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/Documentation/userspace-api/iommufd.rst b/Documentation/userspace-api/iommufd.rst index 2deba93bf159..a8b7766c2849 100644 --- a/Documentation/userspace-api/iommufd.rst +++ b/Documentation/userspace-api/iommufd.rst @@ -63,6 +63,37 @@ Following IOMMUFD objects are exposed to userspace: space usually has mappings from guest-level I/O virtual addresses to guest- level physical addresses. +- IOMMUFD_OBJ_VIOMMU, representing a slice of the physical IOMMU instance, + passed to or shared with a VM. It may be some HW-accelerated virtualization + features and some SW resources used by the VM. For examples: + * Security namespace for guest owned ID, e.g. guest-controlled cache tags + * Non-device-affiliated event reporting, e.g. invalidation queue errors + * Access to a sharable nesting parent pagetable across physical IOMMUs + * Virtualization of various platforms IDs, e.g. RIDs and others + * Delivery of paravirtualized invalidation + * Direct assigned invalidation queues + * Direct assigned interrupts + Such a vIOMMU object generally has the access to a nesting parent pagetable + to support some HW-accelerated virtualization features. So, a vIOMMU object + must be created given a nesting parent HWPT_PAGING object, and then it would + encapsulate that HWPT_PAGING object. Therefore, a vIOMMU object can be used + to allocate an HWPT_NESTED object in place of the encapsulated HWPT_PAGING. + + .. note:: + + The name "vIOMMU" isn't necessarily identical to a virtualized IOMMU in a + VM. A VM can have one giant virtualized IOMMU running on a machine having + multiple physical IOMMUs, in which case the VMM will dispatch the requests + or configurations from this single virtualized IOMMU instance to multiple + vIOMMU objects created for individual slices of different physical IOMMUs. + In other words, a vIOMMU object is always a representation of one physical + IOMMU, not necessarily of a virtualized IOMMU. For VMMs that want the full + virtualization features from physical IOMMUs, it is suggested to build the + same number of virtualized IOMMUs as the number of physical IOMMUs, so the + passed-through devices would be connected to their own virtualized IOMMUs + backed by corresponding vIOMMU objects, in which case a guest OS would do + the "dispatch" naturally instead of VMM trappings. + All user-visible objects are destroyed via the IOMMU_DESTROY uAPI. The diagrams below show relationships between user-visible objects and kernel @@ -101,6 +132,28 @@ creating the objects and links:: |------------>|iommu_domain|<----|iommu_domain|<----|device| |____________| |____________| |______| + _______________________________________________________________________ + | iommufd (with vIOMMU) | + | | + | [5] | + | _____________ | + | | | | + | |----------------| vIOMMU | | + | | | | | + | | | | | + | | [1] | | [4] [2] | + | | ______ | | _____________ ________ | + | | | | | [3] | | | | | | + | | | IOAS |<---|(HWPT_PAGING)|<---| HWPT_NESTED |<--| DEVICE | | + | | |______| |_____________| |_____________| |________| | + | | | | | | | + |______|________|______________|__________________|_______________|_____| + | | | | | + ______v_____ | ______v_____ ______v_____ ___v__ + | struct | | PFN | (paging) | | (nested) | |struct| + |iommu_device| |------>|iommu_domain|<----|iommu_domain|<----|device| + |____________| storage|____________| |____________| |______| + 1. IOMMUFD_OBJ_IOAS is created via the IOMMU_IOAS_ALLOC uAPI. An iommufd can hold multiple IOAS objects. IOAS is the most generic object and does not expose interfaces that are specific to single IOMMU drivers. All operations @@ -132,7 +185,8 @@ creating the objects and links:: flag is set. 4. IOMMUFD_OBJ_HWPT_NESTED can be only manually created via the IOMMU_HWPT_ALLOC - uAPI, provided an hwpt_id via @pt_id to associate the new HWPT_NESTED object + uAPI, provided an hwpt_id or a viommu_id of a vIOMMU object encapsulating a + nesting parent HWPT_PAGING via @pt_id to associate the new HWPT_NESTED object to the corresponding HWPT_PAGING object. The associating HWPT_PAGING object must be a nesting parent manually allocated via the same uAPI previously with an IOMMU_HWPT_ALLOC_NEST_PARENT flag, otherwise the allocation will fail. The @@ -149,6 +203,18 @@ creating the objects and links:: created via the same IOMMU_HWPT_ALLOC uAPI. The difference is at the type of the object passed in via the @pt_id field of struct iommufd_hwpt_alloc. +5. IOMMUFD_OBJ_VIOMMU can be only manually created via the IOMMU_VIOMMU_ALLOC + uAPI, provided a dev_id (for the device's physical IOMMU to back the vIOMMU) + and an hwpt_id (to associate the vIOMMU to a nesting parent HWPT_PAGING). The + iommufd core will link the vIOMMU object to the struct iommu_device that the + struct device is behind. And an IOMMU driver can implement a viommu_alloc op + to allocate its own vIOMMU data structure embedding the core-level structure + iommufd_viommu and some driver-specific data. If necessary, the driver can + also configure its HW virtualization feature for that vIOMMU (and thus for + the VM). Successful completion of this operation sets up the linkages between + the vIOMMU object and the HWPT_PAGING, then this vIOMMU object can be used + as a nesting parent object to allocate an HWPT_NESTED object described above. + A device can only bind to an iommufd due to DMA ownership claim and attach to at most one IOAS object (no support of PASID yet). @@ -161,6 +227,7 @@ User visible objects are backed by following datastructures: - iommufd_device for IOMMUFD_OBJ_DEVICE. - iommufd_hwpt_paging for IOMMUFD_OBJ_HWPT_PAGING. - iommufd_hwpt_nested for IOMMUFD_OBJ_HWPT_NESTED. +- iommufd_viommu for IOMMUFD_OBJ_VIOMMU. Several terminologies when looking at these datastructures: