From patchwork Sat Nov 9 11:00:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 842622 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4D621474BC; Sat, 9 Nov 2024 11:00:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731150022; cv=none; b=mitKPQgi0Kd102t9yUQSIqijDc3UqYC+XwSrG/BPQTXN8kuhrWgITG8tc7D0920A2hOpKW18iAYBlYTXp3GR5pJuEaHicNPYKGtmbBkl7BW77P+ulojW9yMjJpMlAzgFs6SwftFs0wgWoy5gFejiJKDJYaCFt2dU/VhLwOC8oUI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731150022; c=relaxed/simple; bh=nH5ZbJEfnNtqpVAJdxQPimoXQFIYYcfa/hUchSNyuLA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GtInFj7J9xRXpCUV7cPOVtDrYbwixES2m58Mhtx0n43cjtpiQnZ/svmefBmD6oe3FhCMKu7EiYTdQVteUkHr6EvzCbgXZskgBsBrfGrv9KfpG/dR9fkUmlj0KhZplIqgXwjVhqss9QL1RlHmd1DiMz04FuNZGnFU3E6yHoOY7yE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U4xVwyUG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U4xVwyUG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A602CC4CED4; Sat, 9 Nov 2024 11:00:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731150022; bh=nH5ZbJEfnNtqpVAJdxQPimoXQFIYYcfa/hUchSNyuLA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=U4xVwyUGntD3G401bT/ozIj63X6LlJgvaSVu0IK8x0DvAFTZd2MZg6PlnZ+E+7hHM Gy6Sz/zz6gmAv1F+Fj6JJKx6gQkrikkuOTCm5xdlm/4JyU3JLqWF72sfwYenLHKEFV //XLYHzIQfoboob9TOBQBoDEYNwWeuL4XB3lfrdqQBRtUk9m5FXG5iCXVg2vmXGd9e N9wG5kU04pLP2UZjjEYTfgEoUSs39xhWMZ9vgE9XWNYJBAhLW/ncdcyD9YZm+YHYR9 xH+Ofb2eCmThCI7PyTi+sxXUYwvr1t06Bld/lJ/X1AT0g4JSRH1oohHnviDgM30SGE sj4WpHTGLKKtg== From: Roger Quadros Date: Sat, 09 Nov 2024 13:00:07 +0200 Subject: [PATCH net-next v3 1/2] net: ethernet: ti: am65-cpsw: update pri_thread_map as per IEEE802.1Q-2014 Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241109-am65-cpsw-multi-rx-dscp-v3-1-1cfb76928490@kernel.org> References: <20241109-am65-cpsw-multi-rx-dscp-v3-0-1cfb76928490@kernel.org> In-Reply-To: <20241109-am65-cpsw-multi-rx-dscp-v3-0-1cfb76928490@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman Cc: linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, srk@ti.com, Pekka Varis , Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2982; i=rogerq@kernel.org; h=from:subject:message-id; bh=nH5ZbJEfnNtqpVAJdxQPimoXQFIYYcfa/hUchSNyuLA=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBnL0C/ZvSqh4fZ5XX1yNqY7iyl1erdOCyhClcLe tqTz85Ya3uJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZy9AvwAKCRDSWmvTvnYw kxd0D/4hHEBWHfFKqqEJrX6ibTbuep29SUU1LYdC/W/eic0dn8tBX8ccKFWKyiSo0hVQQFM/Ezn fQUZYQ2Ms1uuQ7RqGIHWpCGJKZbLNHFF8K40gpY+5WvHHu0Q0pNsNSsCkh66gyJhyRrM4RFvVsx LKlgF4zuRzOWhl57aEZVEJq5K5wvJWgl7Hnhwx7wQ9KjTyKIZuwjIKj3uJYnHJJxWV46EZYVTS/ f3mUSpiHZLYDuJWvPoukiVjOlavlUXoDLwZx3mklsACdIgx6e21t8ilAkpmuEf1EMaIqYYfYlR+ upwfJLF9euR6jTe0ClONa+K1ngITYT0ZxixUPLowR+Qeo8ZVmdZc4uYVty4E0cOn9q2P4b7W+eZ I64sIHuoIrqh1ZberjFDAO87tcndZm7cTK+bUDFQ5kKmEorLnJmtY3MQHUvQNc/NZxCTpoBzMxi EAa5sFOai5PT4/T6UMfgW8ola1bJt/nsA1q+d8DrrxBOrX1zDzYz+zTx2Y4+VGUTgQn0sYsIATg GGkkFK8veV1U3BQ8SgjDBYdTE4jpp9pss1M6+nEti5uS9dryltqNPp6SmXqggW0U/qxbEi1vHdK 8jbeqS5ixQWa1bTplC0IhGM4CtyJytznvYKXFbIBSob6mzsPvYudPbv+SqRiTHrOKgbFoqf68sF uglAwpG/77sRvAw== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 IEEE802.1Q-2014 supersedes IEEE802.1D-2004. Now Priority Code Point (PCP) 2 is no longer at a lower priority than PCP 0. PCP 1 (Background) is still at a lower priority than PCP 0 (Best Effort). Reference: IEEE802.1Q-2014, Standard for Local and metropolitan area networks Table I-2 - Traffic type acronyms Table I-3 - Defining traffic types Signed-off-by: Roger Quadros Reviewed-by: Siddharth Vadapalli --- drivers/net/ethernet/ti/cpsw_ale.c | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 8d02d2b21429..9f79056b3f48 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1692,26 +1692,34 @@ static void cpsw_ale_policer_reset(struct cpsw_ale *ale) void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch) { int pri, idx; - /* IEEE802.1D-2004, Standard for Local and metropolitan area networks - * Table G-2 - Traffic type acronyms - * Table G-3 - Defining traffic types - * User priority values 1 and 2 effectively communicate a lower - * priority than 0. In the below table 0 is assigned to higher priority - * thread than 1 and 2 wherever possible. - * The below table maps which thread the user priority needs to be + + /* Reference: + * IEEE802.1Q-2014, Standard for Local and metropolitan area networks + * Table I-2 - Traffic type acronyms + * Table I-3 - Defining traffic types + * Section I.4 Traffic types and priority values, states: + * "0 is thus used both for default priority and for Best Effort, and + * Background is associated with a priority value of 1. This means + * that the value 1 effectively communicates a lower priority than 0." + * + * In the table below, Priority Code Point (PCP) 0 is assigned + * to a higher priority thread than PCP 1 wherever possible. + * The table maps which thread the PCP traffic needs to be * sent to for a given number of threads (RX channels). Upper threads * have higher priority. * e.g. if number of threads is 8 then user priority 0 will map to - * pri_thread_map[8-1][0] i.e. thread 2 + * pri_thread_map[8-1][0] i.e. thread 1 */ - int pri_thread_map[8][8] = { { 0, 0, 0, 0, 0, 0, 0, 0, }, + + int pri_thread_map[8][8] = { /* BK,BE,EE,CA,VI,VO,IC,NC */ + { 0, 0, 0, 0, 0, 0, 0, 0, }, { 0, 0, 0, 0, 1, 1, 1, 1, }, { 0, 0, 0, 0, 1, 1, 2, 2, }, - { 1, 0, 0, 1, 2, 2, 3, 3, }, - { 1, 0, 0, 1, 2, 3, 4, 4, }, - { 1, 0, 0, 2, 3, 4, 5, 5, }, - { 1, 0, 0, 2, 3, 4, 5, 6, }, - { 2, 0, 1, 3, 4, 5, 6, 7, } }; + { 0, 0, 1, 1, 2, 2, 3, 3, }, + { 0, 0, 1, 1, 2, 2, 3, 4, }, + { 1, 0, 2, 2, 3, 3, 4, 5, }, + { 1, 0, 2, 3, 4, 4, 5, 6, }, + { 1, 0, 2, 3, 4, 5, 6, 7 } }; cpsw_ale_policer_reset(ale); From patchwork Sat Nov 9 11:00:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 842267 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24C461714A1; Sat, 9 Nov 2024 11:00:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731150026; cv=none; b=tIaMJsumOGa/9ntxp0Q9TG2lY3YEU4LjQq+fOSj+KovbMsmAzItOux88sGfE+mZrUt92jy0b6V8Yk1LuFOZj4uH4dYqvoKx8Lrf83yxNypdU3Wln4UDXQmtOP3rhDvXsgTvRxFLYWnZvVN0iUdlqWWbvlpbOI1CTvvhU9Gh5FY4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731150026; c=relaxed/simple; bh=C2Ggr7/lBmMYcsEocbkbo4QN88kd46oS6nv6gv/iEgA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Tdk/dATG25qZsglyCT58Eah/YnxsKARFmIPTJjIJ7bcjxWSt+heubNXQegR7RfBFXrym2p8Cgqt9rbePWhd/dMoFCDea+8diu5XmimP5/uizJpvVfQq1tIbRTQEkzQHqQkt8fPxwFAmTILMe7zoSgmLzD1bS63oRBbiOq4dcjdY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CNbBIdwA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CNbBIdwA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EAA51C4CECE; Sat, 9 Nov 2024 11:00:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731150025; bh=C2Ggr7/lBmMYcsEocbkbo4QN88kd46oS6nv6gv/iEgA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CNbBIdwAm3xS6s+wZ3pr+GNj3QD0NVrazS5bSRsfAn+kui58+vt57tSGgYlTJtj3p vxwpUW65Hu6ebxD/Gq5RA1ja2++m7Qz6dUgNWtByqvIHCrdlbkY3nm0Zj5u6az5JcS T4VAuRyZIaQ+WW8Ap2UDf3aiY7pDHOUV+aH6qb4ZxUbjeX5xoLeQFi2N91APv/y7Ot v2ZgVYMQ87KaBDAelMcPqHK30BqWFXJ6Vx6IjC0Tspm1wPfxKpzxQU1/EHLVTwgoTl 9VzGA7WQ4b6W1tsdgRBDUGl6VDfK0YjNUP7pVr0l/CeiFcYpAllI+H50sPEU4JLGXH xI3XfRRrG+a4g== From: Roger Quadros Date: Sat, 09 Nov 2024 13:00:08 +0200 Subject: [PATCH net-next v3 2/2] net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241109-am65-cpsw-multi-rx-dscp-v3-2-1cfb76928490@kernel.org> References: <20241109-am65-cpsw-multi-rx-dscp-v3-0-1cfb76928490@kernel.org> In-Reply-To: <20241109-am65-cpsw-multi-rx-dscp-v3-0-1cfb76928490@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman Cc: linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, srk@ti.com, Pekka Varis , Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3478; i=rogerq@kernel.org; h=from:subject:message-id; bh=C2Ggr7/lBmMYcsEocbkbo4QN88kd46oS6nv6gv/iEgA=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBnL0C/p93EJarGcx0+FJBWemE0yLPM2z20HXQIa aYHJxbEwvSJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZy9AvwAKCRDSWmvTvnYw k29bEADKJNXfzn+YvxF+JuefXvuYT2LJBi7Qms8XonKOcs3hnOQsdAwJoFZV3fLHrIWN9PLvJel tMc58bXPRsgZ8nRGAKCV8zReWoVIx97bXBqpiPlMpW4KbiiqqjvL+2f4zkkXP8mer2NWN8m2Vvv UqSzHonhYSLvf17laJQLzbo8T6B22v9hS4GMZip63e42+AfkbWM0ORyuScnOhZh/Ec7JZQttq2I aQb97TRzCgeOIZ1g3sRllJfxTlbxhpeZ+pi/70BhoqVg0vf55sZEg58HBkfp10OG8jnETAFc+y8 hH8ijX8Voeyu/Eifakh+sDdOWmX+Jr6VlE9kYugmr3VMWfASRzdI4+6A5NWhSz6RhKkC1sweZpn fq7kiEePmyavQBXJzy69mlurNdcLikgM29Z25OipCk31Izk46dl9OmB6Of9f2dHmOXD13LJZX5A 52fpub8Z8ri3oZGOX4uZ/GDH3bYrs+BchP4wAaWlKQfg0nrMdCH4FcgPObgfIMD+lj07mzrdBaZ +M5QuG5oKKeNBR1qI/GDUzOgSifXvRlzxQup0y9tMzrypVmmDC4eWMY9L7bZJFjc8U/QYqX5lvX vAEoQaAu0OJVlDYr2JkJVi+u4jmCQjwyF5R2uN5jgZ3Rrkr+o3ghDnH8aM7jls2lshKETSQ5+iE SKsV2xB6qP+9x0Q== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 AM65 CPSW hardware can map the 6-bit DSCP/TOS field to appropriate priority queue via DSCP to Priority mapping registers (CPSW_PN_RX_PRI_MAP_REG). We use the upper 3 bits of the DSCP field that indicate IP Precedence to map traffic to 8 priority queues. Signed-off-by: Roger Quadros Reviewed-by: Siddharth Vadapalli --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 54 ++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 0520e9f4bea7..fab35e6aac7f 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -71,6 +71,8 @@ #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 +#define AM65_CPSW_PORTN_REG_CTL 0x004 +#define AM65_CPSW_PORTN_REG_DSCP_MAP 0x120 #define AM65_CPSW_PORTN_REG_SA_L 0x308 #define AM65_CPSW_PORTN_REG_SA_H 0x30c #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 @@ -94,6 +96,10 @@ /* AM65_CPSW_PORT_REG_PRI_CTL */ #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) +/* AM65_CPSW_PN_REG_CTL */ +#define AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN BIT(1) +#define AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN BIT(2) + /* AM65_CPSW_PN_TS_CTL register fields */ #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) @@ -176,6 +182,53 @@ static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); } +#define AM65_CPSW_DSCP_MAX GENMASK(5, 0) +#define AM65_CPSW_PRI_MAX GENMASK(2, 0) +#define AM65_CPSW_DSCP_PRI_PER_REG 8 +#define AM65_CPSW_DSCP_PRI_SIZE 4 /* in bits */ +static int am65_cpsw_port_set_dscp_map(struct am65_cpsw_port *slave, u8 dscp, u8 pri) +{ + int reg_ofs; + int bit_ofs; + u32 val; + + if (dscp > AM65_CPSW_DSCP_MAX) + return -EINVAL; + + if (pri > AM65_CPSW_PRI_MAX) + return -EINVAL; + + /* 32-bit register offset to this dscp */ + reg_ofs = (dscp / AM65_CPSW_DSCP_PRI_PER_REG) * 4; + /* bit field offset to this dscp */ + bit_ofs = AM65_CPSW_DSCP_PRI_SIZE * (dscp % AM65_CPSW_DSCP_PRI_PER_REG); + + val = readl(slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); + val &= ~(AM65_CPSW_PRI_MAX << bit_ofs); /* clear */ + val |= pri << bit_ofs; /* set */ + writel(val, slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); + + return 0; +} + +static void am65_cpsw_port_enable_dscp_map(struct am65_cpsw_port *slave) +{ + int dscp, pri; + u32 val; + + /* Map IP Precedence field to Priority */ + for (dscp = 0; dscp <= AM65_CPSW_DSCP_MAX; dscp++) { + pri = dscp >> 3; /* Extract IP Precedence */ + am65_cpsw_port_set_dscp_map(slave, dscp, pri); + } + + /* enable port IPV4 and IPV6 DSCP for this port */ + val = readl(slave->port_base + AM65_CPSW_PORTN_REG_CTL); + val |= AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN | + AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN; + writel(val, slave->port_base + AM65_CPSW_PORTN_REG_CTL); +} + static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) { cpsw_sl_reset(port->slave.mac_sl, 100); @@ -921,6 +974,7 @@ static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) common->usage_count++; am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); + am65_cpsw_port_enable_dscp_map(port); if (common->is_emac_mode) am65_cpsw_init_port_emac_ale(port);