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Tue, 19 Nov 2024 17:13:43 -0500 (EST) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Sakari Ailus , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Laurent Pinchart , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH 1/4] media: dt-bindings: Add property to describe CSI-2 C-PHY line orders Date: Tue, 19 Nov 2024 23:12:46 +0100 Message-ID: <20241119221249.539610-2-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241119221249.539610-1-niklas.soderlund+renesas@ragnatech.se> References: <20241119221249.539610-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Each data lane on a CSI-2 C-PHY bus uses three phase encoding and is constructed from three physical wires. The wires are referred to as A, B and C and their default order is ABC. However to ease hardware design the specification allows for the wires to be switched in any order. Add a vendor neutral property to describe the line order used. The property name 'line-orders', the possible values it can be assigned and there names are taken from the MIPI Discovery and Configuration (DisCo) Specification for Imaging. Signed-off-by: Niklas Söderlund --- .../bindings/media/video-interfaces.yaml | 20 +++++++++++++++++++ include/dt-bindings/media/video-interfaces.h | 7 +++++++ 2 files changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/media/video-interfaces.yaml b/Documentation/devicetree/bindings/media/video-interfaces.yaml index 26e3e7d7c67b..95491e5779ba 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.yaml +++ b/Documentation/devicetree/bindings/media/video-interfaces.yaml @@ -210,6 +210,26 @@ properties: lane-polarities property is omitted, the value must be interpreted as 0 (normal). This property is valid for serial busses only. + line-orders: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + enum: + - 0 # ABC + - 1 # ACB + - 2 # BAC + - 3 # BCA + - 4 # CAB + - 5 # CBA + description: + An array of line orders of the CSI-2 C-PHY data lanes. The order of the + lanes are the same as in data-lanes property. Valid values are 0-5 as + defined in the MIPI Discovery and Configuration (DisCo) Specification for + Imaging. The length of the array should be the same length as the + data-lanes property. If the line-orders property is omitted, the value + must be interpreted as 0 (ABC). This property is valid for CSI-2 C-PHY + busses only. + strobe: $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 0, 1 ] diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h index 68ac4e05e37f..88b9d05d8075 100644 --- a/include/dt-bindings/media/video-interfaces.h +++ b/include/dt-bindings/media/video-interfaces.h @@ -13,4 +13,11 @@ #define MEDIA_BUS_TYPE_PARALLEL 5 #define MEDIA_BUS_TYPE_BT656 6 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC 0 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ACB 1 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BAC 2 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BCA 3 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CAB 4 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CBA 5 + #endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */ From patchwork Tue Nov 19 22:12:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 844388 Received: from fhigh-a1-smtp.messagingengine.com (fhigh-a1-smtp.messagingengine.com [103.168.172.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 869A01D4177; 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Tue, 19 Nov 2024 17:13:48 -0500 (EST) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Sakari Ailus , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Laurent Pinchart , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH 3/4] arm64: dts: renesas: white-hawk-csi-dsi: Define CSI-2 data line orders Date: Tue, 19 Nov 2024 23:12:48 +0100 Message-ID: <20241119221249.539610-4-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241119221249.539610-1-niklas.soderlund+renesas@ragnatech.se> References: <20241119221249.539610-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The second CSI-2 C-PHY data-lane have a different line order (BCA) then the two other data-lanes (ABC) for both connected CSI-2 receivers, describe this in the device tree. This have worked in the past as the R-Car CSI-2 driver did not have documentation for the line order configuration and a magic value was written to the register for this specific setup. Now the registers involved are documented and the hardware description as well as the driver needs to be corrected. Signed-off-by: Niklas Söderlund --- arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi index 3006b0a64f41..a5d1c1008e7e 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi @@ -21,6 +21,9 @@ csi40_in: endpoint { bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3>; + line-orders = ; remote-endpoint = <&max96712_out0>; }; }; @@ -41,6 +44,9 @@ csi41_in: endpoint { bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3>; + line-orders = ; remote-endpoint = <&max96712_out1>; }; };