From patchwork Sun Nov 24 19:17:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845197 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841258wru; Sun, 24 Nov 2024 11:18:00 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVDNEYB62ugeax0AfEoc+QRdKYsth7kPRA7+tbsS8TWFkho1nsLneYG2K2LoH6S6mtbIaQNpA==@linaro.org X-Google-Smtp-Source: AGHT+IEhLqgDVZjt2Ij7c/cpSMQlXqoyeb72/Gb6+DWf04RcRhWJogfKJYlOVACDL3KC1K0z60dg X-Received: by 2002:a05:6402:40d2:b0:5cf:c188:81be with SMTP id 4fb4d7f45d1cf-5d0205de24bmr10333438a12.13.1732475880584; Sun, 24 Nov 2024 11:18:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475880; cv=none; d=google.com; s=arc-20240605; b=E7kvL+9nCmORNNwJCSq/dW48E49a6+5P6w02GRdCiGpNxnSX2K4dW9KIZTFXahb476 lHMiTFAhFiOSfB6q71UkXtSRSPeiONM8jqkceMIU599SeurYbXwUfGDPlIY4i76rf9M0 bNQfm2PA/aNLQTFvX9FG9kXGh3c4rAr8ze3sFeEur/wqeAd5pDGJsABWks8E8PhUC+nC vbcPzzj+f5W04QzeWKG3eqrRQeiQepOJW1ZdmBGLnVzDKPtlzUiNlzhuV2KIsW+W73uJ VAKxSiPWoJe2ZH0yeBWOwv12N6S85kgt5iC+lZCjxcqAQ8Li0ykMeyBhoiI9xTKoCU9X sj+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=brqqZKykrMuZoa1LdNYB8vuSNcJr6464qwcR4yIsGyw=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=EL4jJRR544WMVQQwc6psHUyJHv5Vn/ohDCyqZuRZip/TUe33I3LDynW4Z31fE+zpLr wXSKAst7U5gfJVTfMe3rmWJmIoxIHdmPDZxfSDWXfMcpswwsJiciCQOPZk8OlQF/p/8E G6Gtl1TzLbo/viD5G0t4koytDNN+w0PV/KpSwvv/AKZawVpJnjfj5F5l3POX3AGBy1sn DyMepXBhIch2d7nRccH7Q5beccI4iFYubHyuxCL1KTUKFz+T9ctFbyrdrb/itdziiqZL oO1dnJAQluouJ71EVlnXoT38820Pwy28Q2uLwZPvfqH2d77/XLBYxSJlFChouKAkKxSe kpRQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C25RpgA6; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id 4fb4d7f45d1cf-5d01d41da3asi3829785a12.307.2024.11.24.11.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:18:00 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C25RpgA6; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E5B59896A0; Sun, 24 Nov 2024 20:17:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="C25RpgA6"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 63EB989580; Sun, 24 Nov 2024 20:17:50 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3355A8953A for ; Sun, 24 Nov 2024 20:17:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-aa52bb7beceso208163066b.3 for ; Sun, 24 Nov 2024 11:17:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475868; x=1733080668; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=brqqZKykrMuZoa1LdNYB8vuSNcJr6464qwcR4yIsGyw=; b=C25RpgA6whGMq1I3MEA8TboI3s85oNqg4XSTlqEqD52p94zo48fSoaYNdW7wjlq+xU paEckPH4h6iZDhPWOrfzXwb9hnTInqeCEQ1ZXutcCfBTqfU3TpBlikE0Ils0MgJUKA3R PuXbx+/zVt8GxpjGmmXsHmbbrb5USyOiehYf1BJYyqx5ffcATUEItHsGKl96EB+k71mK hCDZzzH5wTzHHJ6X3vgNH7HF9xDbChBBOGgEmOST1/fppRZOvZeEInAsOkmFQLQCkeOl Nz47VLUmjJe0Ih1YJlyW2fMNeGpClpPbE4Rh7ot/aQZGatBkrhd4KR6VKKXZwsveCJ1D bsPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475868; x=1733080668; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=brqqZKykrMuZoa1LdNYB8vuSNcJr6464qwcR4yIsGyw=; b=t1GHqfF6h9lSitOgh4CIId/Z7gp3te3LPA4MPR6rkUtpPYyOTuPdfqah6WljXjVC8d w8HSGeiXTkrVk2Rv4FP7gpuPFvI7Cz6ziH8o/DTkqse6VsCyv8RFyCROQ4sgynXLr4YF LCBQSGF7YztUo133R5lw3PYkPozmHBTM87AVSJgCZxiRKUqwmNHurJ5yndWEFl+6aYGZ vSTWPTx0PrqM90wHR/5Vt11srpCncyXqIVe5cY8pjLV1cxNzT2OySCkoI21hJgxxXW7N 1J5AOE/BNLlGB+dmFpD/6WyVtEALDdawHe/1yqUTGmBWHcBtMzEKJxuZVrA14XdLVa5L cnYw== X-Gm-Message-State: AOJu0YwJR2SUmvD09SoOODLyMTLhkjL5gQfy0ynDTnHU7tZuPSdi7a58 1PdMFcPLh4RJxsWIy4/AGuUStPCh2hn83UzP29AcM/IfwivWcjWUxjW+w8rMPDTmUrC+WM+RxW1 fnjU= X-Gm-Gg: ASbGncvv7ced7n+N85g6sjQdA5bBnD55jYkmddoHnoIlqyrtzO/9eR8h4CWkYQnI8u6 dG+tj0S2XRCnCtld776J3NIQLkxe9TQBldvCKAKjNF5PkLc13Nkx7ieKlKblPpuTghttfjk5/xD pohHqOvOeDuG4jA7NVUDKSNLKzD4ECWQRHts4g5wAu3YZiBgorNN4n7bzDZp9VnboPu9yXuTm3A 8gyMtTZYPXaL3jCEvqSa2tOrCn89pf3ojTQsx8oa2xJ+Dq0rROsTmSJVsCP4Ab9Pdwj X-Received: by 2002:a17:906:3caa:b0:aa5:451c:ce1e with SMTP id a640c23a62f3a-aa5451cd0cemr303962066b.32.1732475867648; Sun, 24 Nov 2024 11:17:47 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:47 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:43 +0100 Subject: [PATCH 01/15] Revert "dm: SMEM (Shared memory) uclass" MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-1-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=8318; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=gP75Ots5RFaUWiObk7tC3qWRGvUFUcSl3q31p9RYwy8=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6huTD/96kTRFu/j7tECndc6NrOWPJUR+HlBVM0wqL XsXtUqko5SFQZCDQVZMkUX8xDLLprWX7TW2L7gAM4eVCWQIAxenAExE+wHD/9htZirfpS/lTlty +fYbtsOrngQ/3aJst/J94onWZte4VE6Gf0Zzv8+JvjWDzbJsYmZYX8v/j12hkpOXup5/oRvuZal i2wEA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean SMEM is a highly Qualcomm specific interface, while having a dedicated UCLASS for it offers a nice abstraction, for things like memory layout parsing we need to use it before the driver model is available. Therefore, it doesn't make sense to fit SMEM into the driver model. Instead let's adopt a model closer to Linux, and parse SMEM really early during boot (as soon as we have the FDT). This reverts commit 7b384eccc785b596f68448b155cbda26df57fb23. Signed-off-by: Caleb Connolly --- arch/arm/Kconfig | 1 - drivers/Kconfig | 2 -- drivers/Makefile | 1 - drivers/smem/Kconfig | 24 ------------- drivers/smem/Makefile | 7 ---- drivers/smem/smem-uclass.c | 46 ------------------------ include/dm/uclass-id.h | 1 - include/smem.h | 90 ---------------------------------------------- 8 files changed, 172 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7282c4123b08..dc44ea1e6c9f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1091,9 +1091,8 @@ config ARCH_SNAPDRAGON select GPIO_EXTRA_HEADER select MSM_SMEM select OF_CONTROL select OF_SEPARATE - select SMEM select SPMI select BOARD_LATE_INIT select OF_BOARD select SAVE_PREV_BL_FDT_ADDR diff --git a/drivers/Kconfig b/drivers/Kconfig index a073230c26dd..6dbbc3172076 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -119,10 +119,8 @@ source "drivers/scsi/Kconfig" source "drivers/serial/Kconfig" source "drivers/sm/Kconfig" -source "drivers/smem/Kconfig" - source "drivers/sound/Kconfig" source "drivers/soc/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 9440af1b09bc..385ea3b7918b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -113,9 +113,8 @@ obj-y += pwm/ obj-y += reset/ obj-y += input/ obj-y += iommu/ # SOC specific infrastructure drivers. -obj-y += smem/ obj-y += thermal/ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_ARM_FFA_TRANSPORT) += firmware/arm-ffa/ obj-y += axi/ diff --git a/drivers/smem/Kconfig b/drivers/smem/Kconfig deleted file mode 100644 index 73d51b3a7a48..000000000000 --- a/drivers/smem/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -menuconfig SMEM - bool "SMEM (Shared Memory mamanger) support" - -if SMEM - -config SANDBOX_SMEM - bool "Sandbox Shared Memory Manager (SMEM)" - depends on SANDBOX && DM - help - enable SMEM support for sandbox. This is an emulation of a real SMEM - manager. - The sandbox driver allocates a shared memory from the heap and - initialzies it on start. - -config MSM_SMEM - bool "Qualcomm Shared Memory Manager (SMEM)" - depends on DM - depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX - help - Enable support for the Qualcomm Shared Memory Manager. - The driver provides an interface to items in a heap shared among all - processors in a Qualcomm platform. - -endif # menu "SMEM Support" diff --git a/drivers/smem/Makefile b/drivers/smem/Makefile deleted file mode 100644 index af3e9b50883c..000000000000 --- a/drivers/smem/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Makefile for the U-Boot SMEM interface drivers - -obj-$(CONFIG_SANDBOX_SMEM) += sandbox_smem.o -obj-$(CONFIG_SMEM) += smem-uclass.o -obj-$(CONFIG_MSM_SMEM) += msm_smem.o diff --git a/drivers/smem/smem-uclass.c b/drivers/smem/smem-uclass.c deleted file mode 100644 index 4dea5cc4bf1c..000000000000 --- a/drivers/smem/smem-uclass.c +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2018 Ramon Fried - */ - -#define LOG_CATEGORY UCLASS_SMEM - -#include -#include - -int smem_alloc(struct udevice *dev, unsigned int host, - unsigned int item, size_t size) -{ - struct smem_ops *ops = smem_get_ops(dev); - - if (!ops->alloc) - return -ENOSYS; - - return ops->alloc(host, item, size); -} - -void *smem_get(struct udevice *dev, unsigned int host, - unsigned int item, size_t *size) -{ - struct smem_ops *ops = smem_get_ops(dev); - - if (!ops->get) - return NULL; - - return ops->get(host, item, size); -} - -int smem_get_free_space(struct udevice *dev, unsigned int host) -{ - struct smem_ops *ops = smem_get_ops(dev); - - if (!ops->get_free_space) - return -ENOSYS; - - return ops->get_free_space(host); -} - -UCLASS_DRIVER(smem) = { - .id = UCLASS_SMEM, - .name = "smem", -}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 270088ad94f7..281abe99acf1 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -128,9 +128,8 @@ enum uclass_id { UCLASS_SCMI_BASE, /* Interface for SCMI Base protocol */ UCLASS_SCSI, /* SCSI device */ UCLASS_SERIAL, /* Serial UART */ UCLASS_SIMPLE_BUS, /* Bus with child devices */ - UCLASS_SMEM, /* Shared memory interface */ UCLASS_SOC, /* SOC Device */ UCLASS_SOUND, /* Playing simple sounds */ UCLASS_SPI, /* SPI bus */ UCLASS_SPI_FLASH, /* SPI flash */ diff --git a/include/smem.h b/include/smem.h deleted file mode 100644 index b19c534ebc43..000000000000 --- a/include/smem.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * The shared memory system is an allocate-only heap structure that - * consists of one of more memory areas that can be accessed by the processors - * in the SoC. - * - * Allocation can be done globally for all processors or to an individual processor. - * This is controlled by the @host parameter. - * - * Allocation and management of heap can be implemented in various ways, - * The @item parameter should be used as an index/hash to the memory region. - * - * Copyright (c) 2018 Ramon Fried - */ - -#ifndef _smemh_ -#define _smemh_ - -/* struct smem_ops: Operations for the SMEM uclass */ -struct smem_ops { - /** - * alloc() - allocate space for a smem item - * - * @host: remote processor id, or -1 for all processors. - * @item: smem item handle - * @size: number of bytes to be allocated - * @return 0 if OK, -ve on error - */ - int (*alloc)(unsigned int host, - unsigned int item, size_t size); - - /** - * get() - Resolve ptr of size of a smem item - * - * @host: the remote processor, of -1 for all processors. - * @item: smem item handle - * @size: pointer to be filled out with the size of the item - * @return pointer on success, NULL on error - */ - void *(*get)(unsigned int host, - unsigned int item, size_t *size); - - /** - * get_free_space() - Get free space in smem in bytes - * - * @host: the remote processor identifying a partition, or -1 - * for all processors. - * @return free space, -ve on error - */ - int (*get_free_space)(unsigned int host); -}; - -#define smem_get_ops(dev) ((struct smem_ops *)(dev)->driver->ops) - -/** - * smem_alloc() - allocate space for a smem item - * @host: remote processor id, or -1 - * @item: smem item handle - * @size: number of bytes to be allocated - * Return: 0 if OK, -ve on error - * - * Allocate space for a given smem item of size @size, given that the item is - * not yet allocated. - */ -int smem_alloc(struct udevice *dev, unsigned int host, unsigned int item, size_t size); - -/** - * smem_get() - resolve ptr of size of a smem item - * @host: the remote processor, or -1 for all processors. - * @item: smem item handle - * @size: pointer to be filled out with size of the item - * Return: pointer on success, NULL on error - * - * Looks up smem item and returns pointer to it. Size of smem - * item is returned in @size. - */ -void *smem_get(struct udevice *dev, unsigned int host, unsigned int item, size_t *size); - -/** - * smem_get_free_space() - retrieve amount of free space in a partition - * @host: the remote processor identifying a partition, or -1 - * for all processors. - * Return: size in bytes, -ve on error - * - * To be used by smem clients as a quick way to determine if any new - * allocations has been made. - */ -int smem_get_free_space(struct udevice *dev, unsigned int host); - -#endif /* _smem_h_ */ From patchwork Sun Nov 24 19:17:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845198 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841318wru; Sun, 24 Nov 2024 11:18:10 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUxLnP4u0mKN4hX6HNNhjLB4pyfTdpXEFFqEwEuHzNM3L3kNODJYOxPkcOW7FToCSgHOYQsOQ==@linaro.org X-Google-Smtp-Source: AGHT+IGJzUJDLxTEZgSP3ybYnxjVv8V7woiheA/HKteOKH2u58YrkzmSjmeYlR61kMsp6ZJWcrYM X-Received: by 2002:a17:906:1da2:b0:aa4:a853:a65 with SMTP id a640c23a62f3a-aa5099c393emr785875766b.21.1732475890504; Sun, 24 Nov 2024 11:18:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475890; cv=none; d=google.com; s=arc-20240605; b=T4wrGE8H0rtqBF1d8eDufOGt/dNfWPhVO/Tx5w225iEWsb+m+58XE8/VJ9AmYe1PA+ MZ4KPvHo3KRSFY5sYzqMqRjVoIy87MEVmfTOc5w8J0G2Wf2I66d3n13fSLJMr6RpgQU2 NppwYX5ssZyuXCVSwDuyczSXcf7RC8F+1vG0FTvci2GFcE1f2c20Vgo/5Z8f15uWPYy1 AnJfx1QI4vkLAGn3MfU/2NfWuYhHTR1G1UOYJecelZ45H60coRUZ/oLV1Ezm8RNEhngC jnTCvlFz4illm6gAbIUrrw3HTPZPv2oG6iyA7aNmlc4kKXgLan2OxcFgMTKzIICy0QxK 0GPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=kWPv/d3iBtRzqvr7SJ0aXQ9TlvQ2UoKOQwDcqdjZYJU=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=fJ8Y0+y2xPOeTIZAbl17Renj+xWlSFq60+r1TMvZ7ONd6T3fpx6ciIt0Y61GE8ESqS WCxfwBYgEysFJ8wEt47CFCV0O77+H8Tq0j+tJX4TMFL7IP5vGTDD1Vuc4DQ3iUEBa/Y9 r35kvYVXkZHNGZu4qYosGSKI26vKHbBgr8qoWDqGOVx/wZO8Ds2Wtcp8J2kJQkxHJa1Z q2sU+xdIrop4sjlq++/N/cuL/qC2GWHaS9ZVeVr7STZ4gXgH4l5LM73qBFrNckL/F61E r534uUr3w8uciikb9zAlRU9pfQWsjS8OT2BsFTyXy96G9SyjR0KJfdgm4GuHXhMuvGu/ Jrqw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NBwo7mXD; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id a640c23a62f3a-aa53633fd29si200657566b.948.2024.11.24.11.18.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:18:10 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NBwo7mXD; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 463A289574; Sun, 24 Nov 2024 20:17:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="NBwo7mXD"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 62FD88975F; Sun, 24 Nov 2024 20:17:52 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 37C838956D for ; Sun, 24 Nov 2024 20:17:49 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-aa51bf95ce1so339207266b.3 for ; Sun, 24 Nov 2024 11:17:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475869; x=1733080669; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kWPv/d3iBtRzqvr7SJ0aXQ9TlvQ2UoKOQwDcqdjZYJU=; b=NBwo7mXDikVRM8Yv/1AK7QOZ3HGWSiyCNsInon4GRxBDhQB/QUicR+MwMVqh8dWb4U xsBa6cdQdCk9dfB19yEPb5ypeovX4fBIkk1Cij8lfRBLNNVeYXxSmznSQ46/CGdRaVPf whu8QkiB0ruqYT72RT0rz64AnyGQItZ7qjALY51TNSs5clp8mXrHuzId9AIZNk2g0u4M irGd14m8NHPyu42l1lBUXqKLF0P4gRChDzhB9QSa4u0tmfXflA4+J6Aqc7uX8C7IKfaI KH3yukHa66Fh95Bup7K2ddTQAXC09/swZDJZv1m4rY1AKduMhsHpy0HerUFWoh0JeGLV ygpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475869; x=1733080669; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kWPv/d3iBtRzqvr7SJ0aXQ9TlvQ2UoKOQwDcqdjZYJU=; b=klWonknhNQ27C31naKxkYGbeWrXa8dVTWD1ZB6VCRGeIqmj9tNP8REl0V88kV7EI1s u12I+LQQ5pOavTji6r/hsMjfJnClzGdvr15e4AL8WNzLsf5KhwP17ueYw7CW476ASJ4u 6+6vS7NNn9988R3UWTdqLGgvFr7kgNZcti8FRnJaetvq0PxwperpZLXZ+nKZNjCiWzqx Ahw68Dmi8smslpcYnfcrcTwzr6iAQ+F8SK03jot0qW7UmhDIkEx+XH/J5SXH63BQ6EMm RDjtMoFJFrHlAQg99dG3pXT7d5lBoQLhixWiBAGq6ROhCOTDBzAsCVvTzV+NjX9FCtLa 4uTA== X-Gm-Message-State: AOJu0YxSQ7J7WtLHQ56dmrXfsZnDxoiuDB3+W4Wfh2KF+cVIyKM0b5Yy qPbQ/3ZSne5/BBfmg6J15938MTp/TiXEG6TsEKatwuqnIH8zk94TXaZwvzmPyBo= X-Gm-Gg: ASbGncs7ju0/oJHLxGy6vzO+CHTW97vDXT3BtH83EoC0N51lfvgTUlt9uhID0S2VryG e7S0zgEuo2v2dNgXTSMfZL9kELLjNakJlpRW2OJr3RnqYPa73XJZKvjzL0KL9rFjBDrjORT2i8x MAwZT2rxqwVvyfcljnL2mWlkU229VaGtFjX/t3lb4jrmOO8njyc4whd3YRBwb0X0dsRXkTKtbXY eRNpngaWTEFUJGb99LEoLPF69rc5zNRDEepCMPuzVBz4W0BhI+UEd4ZwZvREfN1QABE X-Received: by 2002:a17:906:3111:b0:aa5:2f8a:b94f with SMTP id a640c23a62f3a-aa52f8ac9c8mr537535966b.54.1732475868597; Sun, 24 Nov 2024 11:17:48 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:48 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:44 +0100 Subject: [PATCH 02/15] smem: drop drivers/smem MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-2-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=28721; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=DYcZjup17k8JsbWYsyF/fJR5OJ/xY6AaQ0Zz3uHneYs=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6hvN9jO3y/Q+KeoV/WbR4fuMnXsf68MClWc5DQpn8 3xsSpg7SlkYBDkYZMUUWcRPLLNsWnvZXmP7ggswc1iZQIYwcHEKwETYrzEyLNnmZHhd71ZnU7fY +wuVaYcVP6y8z+I52+Lxs/PMvfMnH2dk2MvfqZX35Xv9vpI5OosWBny215XqD2MN62Yq31K0sHl HKQA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Remove the old qcom SMEM driver port and the sandbox stub implementation. Signed-off-by: Caleb Connolly --- arch/arm/Kconfig | 1 - drivers/smem/msm_smem.c | 937 -------------------------------------------- drivers/smem/sandbox_smem.c | 44 --- 3 files changed, 982 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dc44ea1e6c9f..66b773b0b7f4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1088,9 +1088,8 @@ config ARCH_SNAPDRAGON select DM_SERIAL select DM_RESET select POWER_DOMAIN select GPIO_EXTRA_HEADER - select MSM_SMEM select OF_CONTROL select OF_SEPARATE select SPMI select BOARD_LATE_INIT diff --git a/drivers/smem/msm_smem.c b/drivers/smem/msm_smem.c deleted file mode 100644 index ccd145f9afbb..000000000000 --- a/drivers/smem/msm_smem.c +++ /dev/null @@ -1,937 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2015, Sony Mobile Communications AB. - * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. - * Copyright (c) 2018, Ramon Fried - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * The Qualcomm shared memory system is an allocate-only heap structure that - * consists of one of more memory areas that can be accessed by the processors - * in the SoC. - * - * All systems contains a global heap, accessible by all processors in the SoC, - * with a table of contents data structure (@smem_header) at the beginning of - * the main shared memory block. - * - * The global header contains meta data for allocations as well as a fixed list - * of 512 entries (@smem_global_entry) that can be initialized to reference - * parts of the shared memory space. - * - * - * In addition to this global heap, a set of "private" heaps can be set up at - * boot time with access restrictions so that only certain processor pairs can - * access the data. - * - * These partitions are referenced from an optional partition table - * (@smem_ptable), that is found 4kB from the end of the main smem region. The - * partition table entries (@smem_ptable_entry) lists the involved processors - * (or hosts) and their location in the main shared memory region. - * - * Each partition starts with a header (@smem_partition_header) that identifies - * the partition and holds properties for the two internal memory regions. The - * two regions are cached and non-cached memory respectively. Each region - * contain a link list of allocation headers (@smem_private_entry) followed by - * their data. - * - * Items in the non-cached region are allocated from the start of the partition - * while items in the cached region are allocated from the end. The free area - * is hence the region between the cached and non-cached offsets. The header of - * cached items comes after the data. - * - * Version 12 (SMEM_GLOBAL_PART_VERSION) changes the item alloc/get procedure - * for the global heap. A new global partition is created from the global heap - * region with partition type (SMEM_GLOBAL_HOST) and the max smem item count is - * set by the bootloader. - * - */ - -/* - * The version member of the smem header contains an array of versions for the - * various software components in the SoC. We verify that the boot loader - * version is a valid version as a sanity check. - */ -#define SMEM_MASTER_SBL_VERSION_INDEX 7 -#define SMEM_GLOBAL_HEAP_VERSION 11 -#define SMEM_GLOBAL_PART_VERSION 12 - -/* - * The first 8 items are only to be allocated by the boot loader while - * initializing the heap. - */ -#define SMEM_ITEM_LAST_FIXED 8 - -/* Highest accepted item number, for both global and private heaps */ -#define SMEM_ITEM_COUNT 512 - -/* Processor/host identifier for the application processor */ -#define SMEM_HOST_APPS 0 - -/* Processor/host identifier for the global partition */ -#define SMEM_GLOBAL_HOST 0xfffe - -/* Max number of processors/hosts in a system */ -#define SMEM_HOST_COUNT 10 - -/** - * struct smem_proc_comm - proc_comm communication struct (legacy) - * @command: current command to be executed - * @status: status of the currently requested command - * @params: parameters to the command - */ -struct smem_proc_comm { - __le32 command; - __le32 status; - __le32 params[2]; -}; - -/** - * struct smem_global_entry - entry to reference smem items on the heap - * @allocated: boolean to indicate if this entry is used - * @offset: offset to the allocated space - * @size: size of the allocated space, 8 byte aligned - * @aux_base: base address for the memory region used by this unit, or 0 for - * the default region. bits 0,1 are reserved - */ -struct smem_global_entry { - __le32 allocated; - __le32 offset; - __le32 size; - __le32 aux_base; /* bits 1:0 reserved */ -}; -#define AUX_BASE_MASK 0xfffffffc - -/** - * struct smem_header - header found in beginning of primary smem region - * @proc_comm: proc_comm communication interface (legacy) - * @version: array of versions for the various subsystems - * @initialized: boolean to indicate that smem is initialized - * @free_offset: index of the first unallocated byte in smem - * @available: number of bytes available for allocation - * @reserved: reserved field, must be 0 - * toc: array of references to items - */ -struct smem_header { - struct smem_proc_comm proc_comm[4]; - __le32 version[32]; - __le32 initialized; - __le32 free_offset; - __le32 available; - __le32 reserved; - struct smem_global_entry toc[SMEM_ITEM_COUNT]; -}; - -/** - * struct smem_ptable_entry - one entry in the @smem_ptable list - * @offset: offset, within the main shared memory region, of the partition - * @size: size of the partition - * @flags: flags for the partition (currently unused) - * @host0: first processor/host with access to this partition - * @host1: second processor/host with access to this partition - * @cacheline: alignment for "cached" entries - * @reserved: reserved entries for later use - */ -struct smem_ptable_entry { - __le32 offset; - __le32 size; - __le32 flags; - __le16 host0; - __le16 host1; - __le32 cacheline; - __le32 reserved[7]; -}; - -/** - * struct smem_ptable - partition table for the private partitions - * @magic: magic number, must be SMEM_PTABLE_MAGIC - * @version: version of the partition table - * @num_entries: number of partitions in the table - * @reserved: for now reserved entries - * @entry: list of @smem_ptable_entry for the @num_entries partitions - */ -struct smem_ptable { - u8 magic[4]; - __le32 version; - __le32 num_entries; - __le32 reserved[5]; - struct smem_ptable_entry entry[]; -}; - -static const u8 SMEM_PTABLE_MAGIC[] = { 0x24, 0x54, 0x4f, 0x43 }; /* "$TOC" */ - -/** - * struct smem_partition_header - header of the partitions - * @magic: magic number, must be SMEM_PART_MAGIC - * @host0: first processor/host with access to this partition - * @host1: second processor/host with access to this partition - * @size: size of the partition - * @offset_free_uncached: offset to the first free byte of uncached memory in - * this partition - * @offset_free_cached: offset to the first free byte of cached memory in this - * partition - * @reserved: for now reserved entries - */ -struct smem_partition_header { - u8 magic[4]; - __le16 host0; - __le16 host1; - __le32 size; - __le32 offset_free_uncached; - __le32 offset_free_cached; - __le32 reserved[3]; -}; - -static const u8 SMEM_PART_MAGIC[] = { 0x24, 0x50, 0x52, 0x54 }; - -/** - * struct smem_private_entry - header of each item in the private partition - * @canary: magic number, must be SMEM_PRIVATE_CANARY - * @item: identifying number of the smem item - * @size: size of the data, including padding bytes - * @padding_data: number of bytes of padding of data - * @padding_hdr: number of bytes of padding between the header and the data - * @reserved: for now reserved entry - */ -struct smem_private_entry { - u16 canary; /* bytes are the same so no swapping needed */ - __le16 item; - __le32 size; /* includes padding bytes */ - __le16 padding_data; - __le16 padding_hdr; - __le32 reserved; -}; -#define SMEM_PRIVATE_CANARY 0xa5a5 - -/** - * struct smem_info - smem region info located after the table of contents - * @magic: magic number, must be SMEM_INFO_MAGIC - * @size: size of the smem region - * @base_addr: base address of the smem region - * @reserved: for now reserved entry - * @num_items: highest accepted item number - */ -struct smem_info { - u8 magic[4]; - __le32 size; - __le32 base_addr; - __le32 reserved; - __le16 num_items; -}; - -static const u8 SMEM_INFO_MAGIC[] = { 0x53, 0x49, 0x49, 0x49 }; /* SIII */ - -/** - * struct smem_region - representation of a chunk of memory used for smem - * @aux_base: identifier of aux_mem base - * @virt_base: virtual base address of memory with this aux_mem identifier - * @size: size of the memory region - */ -struct smem_region { - u32 aux_base; - void __iomem *virt_base; - size_t size; -}; - -/** - * struct qcom_smem - device data for the smem device - * @dev: device pointer - * @global_partition: pointer to global partition when in use - * @global_cacheline: cacheline size for global partition - * @partitions: list of pointers to partitions affecting the current - * processor/host - * @cacheline: list of cacheline sizes for each host - * @item_count: max accepted item number - * @num_regions: number of @regions - * @regions: list of the memory regions defining the shared memory - */ -struct qcom_smem { - struct udevice *dev; - - struct smem_partition_header *global_partition; - size_t global_cacheline; - struct smem_partition_header *partitions[SMEM_HOST_COUNT]; - size_t cacheline[SMEM_HOST_COUNT]; - u32 item_count; - - unsigned int num_regions; - struct smem_region regions[0]; -}; - -static struct smem_private_entry * -phdr_to_last_uncached_entry(struct smem_partition_header *phdr) -{ - void *p = phdr; - - return p + le32_to_cpu(phdr->offset_free_uncached); -} - -static void *phdr_to_first_cached_entry(struct smem_partition_header *phdr, - size_t cacheline) -{ - void *p = phdr; - - return p + le32_to_cpu(phdr->size) - ALIGN(sizeof(*phdr), cacheline); -} - -static void *phdr_to_last_cached_entry(struct smem_partition_header *phdr) -{ - void *p = phdr; - - return p + le32_to_cpu(phdr->offset_free_cached); -} - -static struct smem_private_entry * -phdr_to_first_uncached_entry(struct smem_partition_header *phdr) -{ - void *p = phdr; - - return p + sizeof(*phdr); -} - -static struct smem_private_entry * -uncached_entry_next(struct smem_private_entry *e) -{ - void *p = e; - - return p + sizeof(*e) + le16_to_cpu(e->padding_hdr) + - le32_to_cpu(e->size); -} - -static struct smem_private_entry * -cached_entry_next(struct smem_private_entry *e, size_t cacheline) -{ - void *p = e; - - return p - le32_to_cpu(e->size) - ALIGN(sizeof(*e), cacheline); -} - -static void *uncached_entry_to_item(struct smem_private_entry *e) -{ - void *p = e; - - return p + sizeof(*e) + le16_to_cpu(e->padding_hdr); -} - -static void *cached_entry_to_item(struct smem_private_entry *e) -{ - void *p = e; - - return p - le32_to_cpu(e->size); -} - -/* Pointer to the one and only smem handle */ -static struct qcom_smem *__smem; - -static int qcom_smem_alloc_private(struct qcom_smem *smem, - struct smem_partition_header *phdr, - unsigned int item, - size_t size) -{ - struct smem_private_entry *hdr, *end; - size_t alloc_size; - void *cached; - - hdr = phdr_to_first_uncached_entry(phdr); - end = phdr_to_last_uncached_entry(phdr); - cached = phdr_to_last_cached_entry(phdr); - - while (hdr < end) { - if (hdr->canary != SMEM_PRIVATE_CANARY) { - dev_err(smem->dev, - "Found invalid canary in hosts %d:%d partition\n", - phdr->host0, phdr->host1); - return -EINVAL; - } - - if (le16_to_cpu(hdr->item) == item) - return -EEXIST; - - hdr = uncached_entry_next(hdr); - } - - /* Check that we don't grow into the cached region */ - alloc_size = sizeof(*hdr) + ALIGN(size, 8); - if ((void *)hdr + alloc_size >= cached) { - dev_err(smem->dev, "Out of memory\n"); - return -ENOSPC; - } - - hdr->canary = SMEM_PRIVATE_CANARY; - hdr->item = cpu_to_le16(item); - hdr->size = cpu_to_le32(ALIGN(size, 8)); - hdr->padding_data = cpu_to_le16(le32_to_cpu(hdr->size) - size); - hdr->padding_hdr = 0; - - /* - * Ensure the header is written before we advance the free offset, so - * that remote processors that does not take the remote spinlock still - * gets a consistent view of the linked list. - */ - dmb(); - le32_add_cpu(&phdr->offset_free_uncached, alloc_size); - - return 0; -} - -static int qcom_smem_alloc_global(struct qcom_smem *smem, - unsigned int item, - size_t size) -{ - struct smem_global_entry *entry; - struct smem_header *header; - - header = smem->regions[0].virt_base; - entry = &header->toc[item]; - if (entry->allocated) - return -EEXIST; - - size = ALIGN(size, 8); - if (WARN_ON(size > le32_to_cpu(header->available))) - return -ENOMEM; - - entry->offset = header->free_offset; - entry->size = cpu_to_le32(size); - - /* - * Ensure the header is consistent before we mark the item allocated, - * so that remote processors will get a consistent view of the item - * even though they do not take the spinlock on read. - */ - dmb(); - entry->allocated = cpu_to_le32(1); - - le32_add_cpu(&header->free_offset, size); - le32_add_cpu(&header->available, -size); - - return 0; -} - -/** - * qcom_smem_alloc() - allocate space for a smem item - * @host: remote processor id, or -1 - * @item: smem item handle - * @size: number of bytes to be allocated - * - * Allocate space for a given smem item of size @size, given that the item is - * not yet allocated. - */ -static int qcom_smem_alloc(unsigned int host, unsigned int item, size_t size) -{ - struct smem_partition_header *phdr; - int ret; - - if (!__smem) - return -ENOMEM; - - if (item < SMEM_ITEM_LAST_FIXED) { - dev_err(__smem->dev, - "Rejecting allocation of static entry %d\n", item); - return -EINVAL; - } - - if (WARN_ON(item >= __smem->item_count)) - return -EINVAL; - - if (host < SMEM_HOST_COUNT && __smem->partitions[host]) { - phdr = __smem->partitions[host]; - ret = qcom_smem_alloc_private(__smem, phdr, item, size); - } else if (__smem->global_partition) { - phdr = __smem->global_partition; - ret = qcom_smem_alloc_private(__smem, phdr, item, size); - } else { - ret = qcom_smem_alloc_global(__smem, item, size); - } - - return ret; -} - -static void *qcom_smem_get_global(struct qcom_smem *smem, - unsigned int item, - size_t *size) -{ - struct smem_header *header; - struct smem_region *area; - struct smem_global_entry *entry; - u32 aux_base; - unsigned int i; - - header = smem->regions[0].virt_base; - entry = &header->toc[item]; - if (!entry->allocated) - return ERR_PTR(-ENXIO); - - aux_base = le32_to_cpu(entry->aux_base) & AUX_BASE_MASK; - - for (i = 0; i < smem->num_regions; i++) { - area = &smem->regions[i]; - - if (area->aux_base == aux_base || !aux_base) { - if (size != NULL) - *size = le32_to_cpu(entry->size); - return area->virt_base + le32_to_cpu(entry->offset); - } - } - - return ERR_PTR(-ENOENT); -} - -static void *qcom_smem_get_private(struct qcom_smem *smem, - struct smem_partition_header *phdr, - size_t cacheline, - unsigned int item, - size_t *size) -{ - struct smem_private_entry *e, *end; - - e = phdr_to_first_uncached_entry(phdr); - end = phdr_to_last_uncached_entry(phdr); - - while (e < end) { - if (e->canary != SMEM_PRIVATE_CANARY) - goto invalid_canary; - - if (le16_to_cpu(e->item) == item) { - if (size != NULL) - *size = le32_to_cpu(e->size) - - le16_to_cpu(e->padding_data); - - return uncached_entry_to_item(e); - } - - e = uncached_entry_next(e); - } - - /* Item was not found in the uncached list, search the cached list */ - - e = phdr_to_first_cached_entry(phdr, cacheline); - end = phdr_to_last_cached_entry(phdr); - - while (e > end) { - if (e->canary != SMEM_PRIVATE_CANARY) - goto invalid_canary; - - if (le16_to_cpu(e->item) == item) { - if (size != NULL) - *size = le32_to_cpu(e->size) - - le16_to_cpu(e->padding_data); - - return cached_entry_to_item(e); - } - - e = cached_entry_next(e, cacheline); - } - - return ERR_PTR(-ENOENT); - -invalid_canary: - dev_err(smem->dev, "Found invalid canary in hosts %d:%d partition\n", - phdr->host0, phdr->host1); - - return ERR_PTR(-EINVAL); -} - -/** - * qcom_smem_get() - resolve ptr of size of a smem item - * @host: the remote processor, or -1 - * @item: smem item handle - * @size: pointer to be filled out with size of the item - * - * Looks up smem item and returns pointer to it. Size of smem - * item is returned in @size. - */ -static void *qcom_smem_get(unsigned int host, unsigned int item, size_t *size) -{ - struct smem_partition_header *phdr; - size_t cacheln; - void *ptr = ERR_PTR(-ENOMEM); - - if (!__smem) - return ptr; - - if (WARN_ON(item >= __smem->item_count)) - return ERR_PTR(-EINVAL); - - if (host < SMEM_HOST_COUNT && __smem->partitions[host]) { - phdr = __smem->partitions[host]; - cacheln = __smem->cacheline[host]; - ptr = qcom_smem_get_private(__smem, phdr, cacheln, item, size); - } else if (__smem->global_partition) { - phdr = __smem->global_partition; - cacheln = __smem->global_cacheline; - ptr = qcom_smem_get_private(__smem, phdr, cacheln, item, size); - } else { - ptr = qcom_smem_get_global(__smem, item, size); - } - - return ptr; - -} - -/** - * qcom_smem_get_free_space() - retrieve amount of free space in a partition - * @host: the remote processor identifying a partition, or -1 - * - * To be used by smem clients as a quick way to determine if any new - * allocations has been made. - */ -static int qcom_smem_get_free_space(unsigned int host) -{ - struct smem_partition_header *phdr; - struct smem_header *header; - unsigned int ret; - - if (!__smem) - return -ENOMEM; - - if (host < SMEM_HOST_COUNT && __smem->partitions[host]) { - phdr = __smem->partitions[host]; - ret = le32_to_cpu(phdr->offset_free_cached) - - le32_to_cpu(phdr->offset_free_uncached); - } else if (__smem->global_partition) { - phdr = __smem->global_partition; - ret = le32_to_cpu(phdr->offset_free_cached) - - le32_to_cpu(phdr->offset_free_uncached); - } else { - header = __smem->regions[0].virt_base; - ret = le32_to_cpu(header->available); - } - - return ret; -} - -static int qcom_smem_get_sbl_version(struct qcom_smem *smem) -{ - struct smem_header *header; - __le32 *versions; - - header = smem->regions[0].virt_base; - versions = header->version; - - return le32_to_cpu(versions[SMEM_MASTER_SBL_VERSION_INDEX]); -} - -static struct smem_ptable *qcom_smem_get_ptable(struct qcom_smem *smem) -{ - struct smem_ptable *ptable; - u32 version; - - ptable = smem->regions[0].virt_base + smem->regions[0].size - SZ_4K; - if (memcmp(ptable->magic, SMEM_PTABLE_MAGIC, sizeof(ptable->magic))) - return ERR_PTR(-ENOENT); - - version = le32_to_cpu(ptable->version); - if (version != 1) { - dev_err(smem->dev, - "Unsupported partition header version %d\n", version); - return ERR_PTR(-EINVAL); - } - return ptable; -} - -static u32 qcom_smem_get_item_count(struct qcom_smem *smem) -{ - struct smem_ptable *ptable; - struct smem_info *info; - - ptable = qcom_smem_get_ptable(smem); - if (IS_ERR_OR_NULL(ptable)) - return SMEM_ITEM_COUNT; - - info = (struct smem_info *)&ptable->entry[ptable->num_entries]; - if (memcmp(info->magic, SMEM_INFO_MAGIC, sizeof(info->magic))) - return SMEM_ITEM_COUNT; - - return le16_to_cpu(info->num_items); -} - -static int qcom_smem_set_global_partition(struct qcom_smem *smem) -{ - struct smem_partition_header *header; - struct smem_ptable_entry *entry = NULL; - struct smem_ptable *ptable; - u32 host0, host1, size; - int i; - - ptable = qcom_smem_get_ptable(smem); - if (IS_ERR(ptable)) - return PTR_ERR(ptable); - - for (i = 0; i < le32_to_cpu(ptable->num_entries); i++) { - entry = &ptable->entry[i]; - host0 = le16_to_cpu(entry->host0); - host1 = le16_to_cpu(entry->host1); - - if (host0 == SMEM_GLOBAL_HOST && host0 == host1) - break; - } - - if (!entry) { - dev_err(smem->dev, "Missing entry for global partition\n"); - return -EINVAL; - } - - if (!le32_to_cpu(entry->offset) || !le32_to_cpu(entry->size)) { - dev_err(smem->dev, "Invalid entry for global partition\n"); - return -EINVAL; - } - - if (smem->global_partition) { - dev_err(smem->dev, "Already found the global partition\n"); - return -EINVAL; - } - - header = smem->regions[0].virt_base + le32_to_cpu(entry->offset); - host0 = le16_to_cpu(header->host0); - host1 = le16_to_cpu(header->host1); - - if (memcmp(header->magic, SMEM_PART_MAGIC, sizeof(header->magic))) { - dev_err(smem->dev, "Global partition has invalid magic\n"); - return -EINVAL; - } - - if (host0 != SMEM_GLOBAL_HOST && host1 != SMEM_GLOBAL_HOST) { - dev_err(smem->dev, "Global partition hosts are invalid\n"); - return -EINVAL; - } - - if (le32_to_cpu(header->size) != le32_to_cpu(entry->size)) { - dev_err(smem->dev, "Global partition has invalid size\n"); - return -EINVAL; - } - - size = le32_to_cpu(header->offset_free_uncached); - if (size > le32_to_cpu(header->size)) { - dev_err(smem->dev, - "Global partition has invalid free pointer\n"); - return -EINVAL; - } - - smem->global_partition = header; - smem->global_cacheline = le32_to_cpu(entry->cacheline); - - return 0; -} - -static int qcom_smem_enumerate_partitions(struct qcom_smem *smem, - unsigned int local_host) -{ - struct smem_partition_header *header; - struct smem_ptable_entry *entry; - struct smem_ptable *ptable; - unsigned int remote_host; - u32 host0, host1; - int i; - - ptable = qcom_smem_get_ptable(smem); - if (IS_ERR(ptable)) - return PTR_ERR(ptable); - - for (i = 0; i < le32_to_cpu(ptable->num_entries); i++) { - entry = &ptable->entry[i]; - host0 = le16_to_cpu(entry->host0); - host1 = le16_to_cpu(entry->host1); - - if (host0 != local_host && host1 != local_host) - continue; - - if (!le32_to_cpu(entry->offset)) - continue; - - if (!le32_to_cpu(entry->size)) - continue; - - if (host0 == local_host) - remote_host = host1; - else - remote_host = host0; - - if (remote_host >= SMEM_HOST_COUNT) { - dev_err(smem->dev, - "Invalid remote host %d\n", - remote_host); - return -EINVAL; - } - - if (smem->partitions[remote_host]) { - dev_err(smem->dev, - "Already found a partition for host %d\n", - remote_host); - return -EINVAL; - } - - header = smem->regions[0].virt_base + le32_to_cpu(entry->offset); - host0 = le16_to_cpu(header->host0); - host1 = le16_to_cpu(header->host1); - - if (memcmp(header->magic, SMEM_PART_MAGIC, - sizeof(header->magic))) { - dev_err(smem->dev, - "Partition %d has invalid magic\n", i); - return -EINVAL; - } - - if (host0 != local_host && host1 != local_host) { - dev_err(smem->dev, - "Partition %d hosts are invalid\n", i); - return -EINVAL; - } - - if (host0 != remote_host && host1 != remote_host) { - dev_err(smem->dev, - "Partition %d hosts are invalid\n", i); - return -EINVAL; - } - - if (le32_to_cpu(header->size) != le32_to_cpu(entry->size)) { - dev_err(smem->dev, - "Partition %d has invalid size\n", i); - return -EINVAL; - } - - if (le32_to_cpu(header->offset_free_uncached) > le32_to_cpu(header->size)) { - dev_err(smem->dev, - "Partition %d has invalid free pointer\n", i); - return -EINVAL; - } - - smem->partitions[remote_host] = header; - smem->cacheline[remote_host] = le32_to_cpu(entry->cacheline); - } - - return 0; -} - -static int qcom_smem_map_memory(struct qcom_smem *smem, struct udevice *dev, - const char *name, int i) -{ - struct fdt_resource r; - int ret; - int node = dev_of_offset(dev); - - ret = fdtdec_lookup_phandle(gd->fdt_blob, node, name); - if (ret < 0) { - dev_err(dev, "No %s specified\n", name); - return -EINVAL; - } - - ret = fdt_get_resource(gd->fdt_blob, ret, "reg", 0, &r); - if (ret) - return ret; - - smem->regions[i].aux_base = (u32)r.start; - smem->regions[i].size = fdt_resource_size(&r); - smem->regions[i].virt_base = devm_ioremap(dev, r.start, fdt_resource_size(&r)); - if (!smem->regions[i].virt_base) - return -ENOMEM; - - return 0; -} - -static int qcom_smem_probe(struct udevice *dev) -{ - struct smem_header *header; - struct qcom_smem *smem; - size_t array_size; - int num_regions; - u32 version; - int ret; - int node = dev_of_offset(dev); - - num_regions = 1; - if (fdtdec_lookup_phandle(gd->fdt_blob, node, "qcomrpm-msg-ram") >= 0) - num_regions++; - - array_size = num_regions * sizeof(struct smem_region); - smem = devm_kzalloc(dev, sizeof(*smem) + array_size, GFP_KERNEL); - if (!smem) - return -ENOMEM; - - smem->dev = dev; - smem->num_regions = num_regions; - - ret = qcom_smem_map_memory(smem, dev, "memory-region", 0); - if (ret) - return ret; - - if (num_regions > 1) { - ret = qcom_smem_map_memory(smem, dev, - "qcom,rpm-msg-ram", 1); - if (ret) - return ret; - } - - header = smem->regions[0].virt_base; - if (le32_to_cpu(header->initialized) != 1 || - le32_to_cpu(header->reserved)) { - dev_err(dev, "SMEM is not initialized by SBL\n"); - return -EINVAL; - } - - version = qcom_smem_get_sbl_version(smem); - switch (version >> 16) { - case SMEM_GLOBAL_PART_VERSION: - ret = qcom_smem_set_global_partition(smem); - if (ret < 0) - return ret; - smem->item_count = qcom_smem_get_item_count(smem); - break; - case SMEM_GLOBAL_HEAP_VERSION: - smem->item_count = SMEM_ITEM_COUNT; - break; - default: - dev_err(dev, "Unsupported SMEM version 0x%x\n", version); - return -EINVAL; - } - - ret = qcom_smem_enumerate_partitions(smem, SMEM_HOST_APPS); - if (ret < 0 && ret != -ENOENT) - return ret; - - __smem = smem; - - return 0; -} - -static int qcom_smem_remove(struct udevice *dev) -{ - __smem = NULL; - - return 0; -} - -const struct udevice_id qcom_smem_of_match[] = { - { .compatible = "qcom,smem" }, - { } -}; - -static const struct smem_ops msm_smem_ops = { - .alloc = qcom_smem_alloc, - .get = qcom_smem_get, - .get_free_space = qcom_smem_get_free_space, -}; - -U_BOOT_DRIVER(qcom_smem) = { - .name = "qcom_smem", - .id = UCLASS_SMEM, - .of_match = qcom_smem_of_match, - .ops = &msm_smem_ops, - .probe = qcom_smem_probe, - .remove = qcom_smem_remove, -}; diff --git a/drivers/smem/sandbox_smem.c b/drivers/smem/sandbox_smem.c deleted file mode 100644 index fec98e5611d6..000000000000 --- a/drivers/smem/sandbox_smem.c +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2018 Ramon Fried - */ - -#include -#include -#include -#include - -static int sandbox_smem_alloc(unsigned int host, - unsigned int item, size_t size) -{ - return 0; -} - -static void *sandbox_smem_get(unsigned int host, - unsigned int item, size_t *size) -{ - return NULL; -} - -static int sandbox_smem_get_free_space(unsigned int host) -{ - return 0; -} - -static const struct smem_ops sandbox_smem_ops = { - .alloc = sandbox_smem_alloc, - .get = sandbox_smem_get, - .get_free_space = sandbox_smem_get_free_space, -}; - -static const struct udevice_id sandbox_smem_ids[] = { - { .compatible = "sandbox,smem" }, - { } -}; - -U_BOOT_DRIVER(smem_sandbox) = { - .name = "smem_sandbox", - .id = UCLASS_SMEM, - .of_match = sandbox_smem_ids, - .ops = &sandbox_smem_ops, -}; From patchwork Sun Nov 24 19:17:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845199 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841353wru; Sun, 24 Nov 2024 11:18:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWiYtYC4Ub+u5FdKVRW2pvDtUSjYGGnpT+0qF4NsuQj1tOggjYfoBdxHctAbJu54kOmaiLC/Q==@linaro.org X-Google-Smtp-Source: AGHT+IF69PwpGuNPyF4oXFvejwsc5nSqDMnSvDYgtidUE22nnDrPuSnp+F1xz8H+0R3tG23i7JEY X-Received: by 2002:a17:906:2189:b0:aa5:3663:64c5 with SMTP id a640c23a62f3a-aa5366368f8mr422314866b.22.1732475898843; Sun, 24 Nov 2024 11:18:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475898; cv=none; d=google.com; s=arc-20240605; b=cUlQfRdLYAp5YLaaXooTttHJXsqqUKcMV9OTqrcX80wdbpEckfdJg9phjjQ28lFnMD L6EEMduJwT/CEgrn8FzGXmeqMkYH+YkLiRnhzZvL3Q/hVkWm6sxS8ZyyJx7Fx4iKwhGk joRKzAhFYLDTzvy+olR546qOQ9zIeiDkc6XHTujsqgIM9Bdt1slNEbhLldnt6d79Lwz+ +9fB3AXGdDVzZ3pkgswK6+qwmo4K/r6jGz4f1IXOJmLgI5VpdA6bfFsY/b83ihq9LWbx KjGB30IfULyvCgwN4uCtb6JNp+GGzMmAfomlb1dZp/SBzGvb3KUHkQxejehNBXYWK8mE VuaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=VTBN0T0NznHzWnwiBTAiquqo2zKIhRnGeV9ZDwdMjZQ=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=lmsXfHDmS/ED4vzktVckycjyiNjVrOVMfiY9SiBmkKCz39DXrGP93QGECcKt2kppFy CIQwldFlCU2ubmH9NX1qx1reOrglfswd+AuY6sB34t7Yozp0kKbtaODY8bDL8MHVlq6d MumKooLn/8nCVp0IK/eDhdvIBMppweSL7XIf+xQtuajaqd97RAE+gemEhcs2hg0eyq/n NRgwZ4Qcj4icPD4Uy6m/NDVhmDjHSE8ZNotVXwzHz9zvS8KPCbFMqj3f1JLvq5bgHkq0 1lHMKO4qAVDh74J39ZkRCiCesVIIgvucuxp7r8BYJ1vA7oBYEoh+tmyOEHuuGjvAXwq5 w3Mg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ngDVMWBr; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id a640c23a62f3a-aa53a146fc5si192061166b.668.2024.11.24.11.18.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:18:18 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ngDVMWBr; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A18E58976E; Sun, 24 Nov 2024 20:17:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ngDVMWBr"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6D9D38956D; Sun, 24 Nov 2024 20:17:52 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 526C489574 for ; Sun, 24 Nov 2024 20:17:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-aa52edbcb63so256095766b.1 for ; Sun, 24 Nov 2024 11:17:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475870; x=1733080670; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VTBN0T0NznHzWnwiBTAiquqo2zKIhRnGeV9ZDwdMjZQ=; b=ngDVMWBrr5vmfJPMhp8AMfD79b3f6g9pstuUaGYWOFW7WivWh2aEUYyuUatsOOKk5H 5PVtO0yVC16z6cnINZC8B82JXA8cX1F1BsS+6q+Xuj9TKJ4aGzlMksDZ+BzFw/3wQ6EM 259lL7LbpH/efwvx/McJtodW7qyofn8T151wusbqHaJ+jvumkZ1nreQN+UboE9Rl33Yy wMqP19SSHxAvGXN/tLfOeb3CBtTGnF9TWR22aYfJklYBh8wrwzOHrCOL0/wgfZ+hO7ql Nk2n4avik+FLx6cxV2etEV909BVGx+13Di2shOlI2Q56smHo2ReFWVq03Pi7UkX+Bw7t Qpfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475870; x=1733080670; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VTBN0T0NznHzWnwiBTAiquqo2zKIhRnGeV9ZDwdMjZQ=; b=hm3qXqnXcjp5tqRA/dnYIsrj5Jd+zc/dwmTOWQtiNxkcpXVZiYtVlUlt/o68cc9Ta9 Kc1y/Cg4nUXrOjM3UN/C2o7FPS6AXiarpLfzOoTTUsHichu3JEwmENhCfeGaR9TuwnFo LU+53HmdX9Vei+T02jcNHXG/HYe5q/Du5OhV7Ttf7QwJtMvsHQ9UecjxSvQLyRSFKM5e YudXzQn3cPKN8SyHjMS4cVsN7AngW6VYvWYo9N9Cp55HcF83+1/U/hccK3MagulmNO5x COE2IhZyscLggtv0fBbTjpMVZYvuS43uJaP0GmES1lrt8q+Id9N46uDOIkLLOi86Z076 FZ+g== X-Gm-Message-State: AOJu0Yy5oB/T7lFBzX3aK4f9v7mVwb36TYs32fHyXSvQNVDR0gmMW+jT iRw5lw0IXUPXOHEU2u06cPyf/F/fdF/PNgY8mnr48flINSHt2FGWAJdJ00hQTdw= X-Gm-Gg: ASbGncvbJTAtl1nvl4uszknRpGFCI+HiN//yRb2zyaBv5k49AjWQd3LZulEbvWK9HUc c/F/syLrJQGxa7WrTksr9pIW2pzEGNAjD388L5niaEWERZw9z2/5UVTUqLvXe7a4k7lRq/eKsCJ bvFlwCAwumWYOiIExqyzcg1Yh+m5AGIT/9SBdGzH3uPFnQvmqyNM6HlTQHm4XodtzNGjAUtQHPm Z6eaxjpVwgKwOcNIQJcQd0l8fo0DmPrHTmUn+tUabXcvWYFdlzoc4XjqRIesaCwl6pc X-Received: by 2002:a17:906:3194:b0:aa5:27da:104a with SMTP id a640c23a62f3a-aa527da111amr904411466b.15.1732475869629; Sun, 24 Nov 2024 11:17:49 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:49 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:45 +0100 Subject: [PATCH 03/15] Revert "test: smem: add basic smem test" MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-3-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1551; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=ScIrVBolsK+rc+s+hhVdbr0CQ2XjXUgWo4F27F8iFlg=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6hs3SwRnBq+de+2Y21FRkUpFidYptTyfP7zc8X72l Ofxz1l/dJSyMAhyMMiKKbKIn1hm2bT2sr3G9gUXYOawMoEMYeDiFICJNC5hZNhaKsz25nPtgVy7 jZu9ec3yFS9z/1GNtXj0dqHXSX+Nv28Y/pnWBq+5vWOuW+nqy4dXCzrr1/g2lB0PfR7oUZWkLrv uaB0A X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This reverts commit 20e7705764c4e5ea924f1ea54bb36ebbbeffffe7. --- test/dm/Makefile | 1 - test/dm/smem.c | 26 -------------------------- 2 files changed, 27 deletions(-) diff --git a/test/dm/Makefile b/test/dm/Makefile index bcb52ef1067b..c7511d072716 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -111,9 +111,8 @@ obj-$(CONFIG_SCSI) += scsi.o obj-$(CONFIG_DM_SERIAL) += serial.o obj-$(CONFIG_DM_SPI_FLASH) += sf.o obj-$(CONFIG_SIMPLE_BUS) += simple-bus.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o -obj-$(CONFIG_SMEM) += smem.o obj-$(CONFIG_SOC_DEVICE) += soc.o obj-$(CONFIG_SOUND) += sound.o obj-$(CONFIG_DM_SPI) += spi.o obj-$(CONFIG_SPMI) += spmi.o diff --git a/test/dm/smem.c b/test/dm/smem.c deleted file mode 100644 index 89e74cccc574..000000000000 --- a/test/dm/smem.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Ramon Fried - */ - -#include -#include -#include -#include -#include - -/* Basic test of the smem uclass */ -static int dm_test_smem_base(struct unit_test_state *uts) -{ - struct udevice *dev; - size_t size; - - ut_assertok(uclass_get_device(UCLASS_SMEM, 0, &dev)); - ut_assertnonnull(dev); - ut_assertok(smem_alloc(dev, -1, 0, 16)); - ut_asserteq(0, smem_get_free_space(dev, -1)); - ut_assertnull(smem_get(dev, -1, 0, &size)); - - return 0; -} -DM_TEST(dm_test_smem_base, UTF_SCAN_PDATA | UTF_SCAN_FDT); From patchwork Sun Nov 24 19:17:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845200 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841404wru; Sun, 24 Nov 2024 11:18:26 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW2AZtA4Z/FkZ9E30ryptw76ymNLFVV9/1iUhMWwROZFNgwpzSrkXGTHgjl4sD0DEEGIxYMwA==@linaro.org X-Google-Smtp-Source: AGHT+IHfwykY5uoex8WxlDA7q9ZQG/EOX7bvhlN3m5azlXN8YMwuYo9p4YDNUVGwRAxt9cQShjjx X-Received: by 2002:a05:6402:909:b0:5cf:af26:3da9 with SMTP id 4fb4d7f45d1cf-5d007ca476cmr12813233a12.12.1732475906771; Sun, 24 Nov 2024 11:18:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475906; cv=none; d=google.com; s=arc-20240605; b=acZmtiLaopaxJHyifT68DKJuba8N4v/OEnyF+le3nQdcU1cxRYiZNYzFIG4j040vTc uX2af9IcMoBv+Sq0SllVPyWfEQcTBHv23A8SWDUCkoPjaJ+485j+zbW6s7y0G9IzOEnG ckmE0j6JwSyxFSY5WZD3Ooav2Iwvmfeqk9kDrFa3prBXa5+ir3RyNHnpEoqaRuvC5iam OuJRieAUwQh+Vd9kahqIeahEOt5sjo/vaoggpjl0ha3V5x/+g2XWoA701h5dKSj8NhrS s1z8aQ2L3uoXmMVt2VlVWle/pcnwzFuIyV3lMe4pzlpsmCCKrHipQwv3Dq+MxVHD+R6y Od1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=+OTbGvErowKXK3MSvlRU9/eK38YsCQAJ5+qw4mqKLK4=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=DtLw4pKAADLqAY66be5scTz00De3cLdhAx5ah+vw4y9WhPXMastF9NNvhzx/QkbvBZ 9ILM1hJj1FHgm8sckkyE+g4F8vgd2TEsfbGy9pf4KWYWfv/VHtSDzLR0+rRCy4m3pmWP Gh/23OuVbGL0xTFjasW1nesDwD0ejQthnegwlULFz8Ew17if801e2cimS21KqzXFAUmL b41Lsip/VNgMaSS73hHep5FSkbG6rDrUZcqXxzMtmphyJR/UtRYjzL5vkWvqFli/oihz 0h+5MZXUUCGXkvn+qi8+eMKeLwNFcJiEEY3k3PJBBfb4dkJFFZRFWXOU0oOII8tqBmF0 lReA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ggqO1Nyi; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id 4fb4d7f45d1cf-5d03c2c7e17si1875268a12.292.2024.11.24.11.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:18:26 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ggqO1Nyi; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 02CBA895B5; Sun, 24 Nov 2024 20:17:57 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ggqO1Nyi"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 504298958E; Sun, 24 Nov 2024 20:17:53 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 47E24895B2 for ; Sun, 24 Nov 2024 20:17:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-aa4d257eb68so702151066b.0 for ; Sun, 24 Nov 2024 11:17:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475871; x=1733080671; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+OTbGvErowKXK3MSvlRU9/eK38YsCQAJ5+qw4mqKLK4=; b=ggqO1NyigPb44zwYdjfoUZko27gCV4M7JA5cOIx2vgjBFEKFmtdtU/21213TBiGT2e j+fckrDYLeyXDcE6P9yxP1xZX4vM8/l+l9nMBpGxCtS9FWoI8rw5I0FBf0VMgW+yxEKO zkCn1unMsKrTYqOY1jzcLA4vlIbp7JPkMl29VDUqPqQC4/N5srR5WMzhgZ6YjBVrovB9 wkrl8J329ZLElMAwO3LwnI4amhf6FEeoTPZgLA1SW6F9qm3P5HZeCPgooifyYIpxFgVd XrVxURL2cr56TWqadLVkfRqAGY3h1O02a/FMXuvfCizHFWOPoEJ5jXMa+5fMW3se38RT 8xEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475871; x=1733080671; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+OTbGvErowKXK3MSvlRU9/eK38YsCQAJ5+qw4mqKLK4=; b=CrzLjq3eTVwFaVGmoyDyvRmWUxx9Yd4R8r0TBXywxhFc7YRDkapbZGKUxkK7l50Sqn cK95L9sHwYesVFtSATXrWuj/BfT9Nt9AMtx1axThNrksN0dpmIFoCKsT1uEzZU/t8NPf 3jaRXGUDWdaBW5WRv8iVcjtmq6l3dWEOzCBza0eUfhSzQB/+AMQ8+qhh+uv00iwtbnCK zn8QY7oBqWLNE8r84Lb5Xc4LHb737jk++8MRgboZenylYwCbZRym/JBxFRbD5ANCIbE5 /WqPbhtYeWF/jLIrLKvEPpaHI9e+e7S7j013rOjnTKl6XXMfeIjVcIcmpCjNkr8uLcbs yAXw== X-Gm-Message-State: AOJu0YxKmO2QRAok7jg7Qi7YJokKYlWB3UpfoZfCgfhVlICAEZ9GEH9u v2U5GZk4sPGLvvYztZJbQ4qeuBHct8ZPuu+IZdEWCEIogPGF7WR3i1cNYCD2a+Y= X-Gm-Gg: ASbGncvYr2pCBI3+oAT7jjX/32VxFQCR80u2EmqnDrLlWZ5tPlqgZ9W8F3WTtg8ktDj Wq221UJJtJgDrzx169mnXDX8TCdY7Lu0d+tjcB2qbXPj5OXOVFuIEGlOPRjs90YpNKpYsLhCeet imgEtz5KEvAtyAXHeobLN7RGurykkQY06BilcQQdittJldO5CwvJZJfvlldXnSUHzzkx6hsjdtA qmeRapjDPsOgghqVCkhw0FXG3jaHgtwF+sakkYyLSU4wxKF2g6c/WxiHjIlN6JXwAF7 X-Received: by 2002:a17:907:9622:b0:aa5:4a38:174d with SMTP id a640c23a62f3a-aa54a381849mr246869566b.29.1732475870754; Sun, 24 Nov 2024 11:17:50 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:50 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:46 +0100 Subject: [PATCH 04/15] Revert "drivers: smem: sandbox" MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-4-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1509; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=t8/nTIl8Vup687vgc5fbWUSkZ0ZrFTPTE0N0GbnNtYI=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6htzNh77ovJj76NyD4E9Mb0O67smbnQ+VrFH7+b5+ u+NhsvVOkpZGAQ5GGTFFFnETyyzbFp72V5j+4ILMHNYmUCGMHBxCsBEDlQw/JXPl5RY++56zf2P ew0v1ri18a3K0uFyLdutVGex/MZK12JGhnner8qnqMhv/3vt5OR3DpaNuk7fbkx4Yx2Yy3ms6LH WbSkA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This reverts commit 7fd7e2cf339ea2ec570f6dae1cdfaf8e066eb4af. --- arch/sandbox/dts/test.dts | 4 ---- configs/sandbox64_defconfig | 2 -- configs/sandbox_defconfig | 2 -- 3 files changed, 8 deletions(-) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index dee280184b1b..1c1f148d5b5c 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1357,12 +1357,8 @@ compatible = "sandbox,scsi"; sandbox,filepath = "scsi.img"; }; - smem@0 { - compatible = "sandbox,smem"; - }; - sound { compatible = "sandbox,sound"; cpu { sound-dai = <&i2s 0>; diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 7960b2ef42e7..62a4fb80e2cb 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -228,10 +228,8 @@ CONFIG_SANDBOX_RESET=y CONFIG_DM_RTC=y CONFIG_RTC_RV8803=y CONFIG_SCSI=y CONFIG_SANDBOX_SERIAL=y -CONFIG_SMEM=y -CONFIG_SANDBOX_SMEM=y CONFIG_SOUND=y CONFIG_SOUND_SANDBOX=y CONFIG_SOC_DEVICE=y CONFIG_SANDBOX_SPI=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 718e4a8283c8..1428d8e4b411 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -297,10 +297,8 @@ CONFIG_RTC_RV8803=y CONFIG_RTC_HT1380=y CONFIG_SCSI=y CONFIG_SANDBOX_SERIAL=y CONFIG_SM=y -CONFIG_SMEM=y -CONFIG_SANDBOX_SMEM=y CONFIG_SOUND=y CONFIG_SOUND_DA7219=y CONFIG_SOUND_MAX98357A=y CONFIG_SOUND_SANDBOX=y From patchwork Sun Nov 24 19:17:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845202 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841501wru; Sun, 24 Nov 2024 11:18:43 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUn1KFl9CO2mV76mUcKe4DXaF8perKri6hW+U3tIubPN3X+bK4B7jriMYC0cihhUoJXi3KfBw==@linaro.org X-Google-Smtp-Source: AGHT+IHN14GiG2UZsQza6wx+W3P4lkRRvGVh0cTcuNXtGPFMB4qmm/1ZjIrlEJfQ2uvZRuHx7i2p X-Received: by 2002:a17:907:6e8b:b0:aa4:9ab1:1985 with SMTP id a640c23a62f3a-aa509d7a7d0mr1035735066b.51.1732475923281; Sun, 24 Nov 2024 11:18:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475923; cv=none; d=google.com; s=arc-20240605; b=NIC7e56KKqnENJXDMRARO1Hbr+RCSxgb0uU1pmIuQeB5tZNcMEh9/hgIQ4hh61Fue+ xr1DZOVKbWpPtB4Nv5gFb6r5KCPTyfYW/FIOkYR9manupo3zltjA7z0Qmxk4pfnOd4yA vzlkCftEnlI2+NLcEK7MuN6N0K4JY6CX8I32hp3TJgVgIKIuJeV71tpJNWTpxQa3m/Aa fy3LJJKA+ZFplwEOmxKkUIaWFEGHCtbJ1lFaK33rU5DFmlMrCFqcXOgBhAVSk8JUeEQs QN6Xg8oggHLL4HTSP3WKFmoiZ3eEBFG59nVcHne3p/Ww4yX85fTMGIUbtEWA4FPV+VC9 uv1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=cqb6KcLWKmcgMwozq7ibPo753UC3S+1X9c7zVrt5ZOg=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=LobMpopV/L/4qV0pKP7GOwlLOo4AH071PzLk/Xu06S7wJSZwyVsru4JiFEu5+iae6c PcwitzkLAidsjOnsN8P7gz/m1ggKnDc6LN9uq086AqrZB2MzeGob+hP8Uqdv3ZWEhPeA n0Q48Q+HitTAdWhhrdaK5qid74NkrWuXure5eRYH0dvdl6EPipiVgTI68lIMdj4EjKgo kImmzRC7SUvG4m5pknzvGTXlgPioCEusb+nwgmxvBK9+Nz4GX88uAKqgM9Cj8xac8FkM 2HYoPi/opMJLz9VYe8OStPMK83+x7VU6KWgDdBh4SMG+SYNXmUGoP3xiM5Fva0+JNsP3 itBQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MdXqxTDb; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id a640c23a62f3a-aa536815c4esi214102466b.114.2024.11.24.11.18.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:18:43 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MdXqxTDb; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A617689915; Sun, 24 Nov 2024 20:17:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="MdXqxTDb"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6AA5F89578; Sun, 24 Nov 2024 20:17:56 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 401A48953A for ; Sun, 24 Nov 2024 20:17:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-a9f1d76dab1so622914766b.0 for ; Sun, 24 Nov 2024 11:17:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475873; x=1733080673; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cqb6KcLWKmcgMwozq7ibPo753UC3S+1X9c7zVrt5ZOg=; b=MdXqxTDbiiBftICEEg+nEirkWyFVkVn3w8ottO2TLvnZEwksk5lO68alHw0q1UQzd0 9yTG6L//YkA8pRSKUNq00sQ0UFRyE9OQYzMP87r79wuVYOX1lrm5iFtlDXXRUXOXSfqH xMuhwY9n/FJ8BA9Zy0sFtTRar1okQBRifdfgY9634x081PMR6j61XrTD3IvK/D9YSA/C zi3SuHReHTZZbc2HHl3S/S8FFE8+1f4VIMDkmBdt3FtWP50wxEcg3eTAlKbEj6VB1c2b HMl0VRo1Kzx75Xr7So3L44fsL4Gh4q1eSmbQqzHw7GeA8KwBmpr+yOceK2vRQ7VUdVmb WcSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475873; x=1733080673; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cqb6KcLWKmcgMwozq7ibPo753UC3S+1X9c7zVrt5ZOg=; b=CRFcqVMxw/UvuyTGRt9jhffsbx4b7THozbZ6i8CP5twvaql9gv0l7pE2whWJYJQcXi 4cvQ/eBDk4Sva2y8CC1QRwF/+0mWty51l1OokSUDuhGkIy6vZuDVF8ovov73lOwBLWtO Url0orZo8Zn/HpzCautgUi8uP6x58eKqh9KFRBGIP3zWC9stKakmHhyKe4CjDS2NA/MX dVsZc+nTTwCRGEYLzTkeR3R5sz5vBI15Qf8E1XJCSp9UFnskF73VnKyExXylIiA0q1Vg YZ4+gew0pzf6YOLygcjwcFGgo1oF4AyLW7t0aidOa6Qg47/gesa1D9XIEynTx0fh4sZF k0YA== X-Gm-Message-State: AOJu0YyUIsXpCkVNz18RudD5UZyxawuSUw3AL11lclRgylzfh5h5DhDj WUWOcHyhmoCW0ht4mQwmRxoZtwIEsBQ5Sz6ILQFUrLStW8MnvP9ou/4OBgvZoic= X-Gm-Gg: ASbGnctRRmeDlnxOCVC5uBSVeQZVTdZE3gKb576EJ3wUe3v3Pn4xJ0VsVTc/3n1+G1x DQsobKxYG2fDiwZEI/Ai3sbRxGUt43NBvhsXrGNysZT9gOWlFiFWKWEvwpLEPH7R6leCr1762Ut KekNClOg6TraSL2Vhfr9T2/b7/O74IWtwYxeuL6GU3eAXOE2Y/CSExP6kNbbRWuN9HLyWqYzUO2 W4Lajxjvv6A1rUA1gptrPcLv9CjycK7baITMCOgj0ahI76nmLbLK3vMQnFC7NR17hcT X-Received: by 2002:a17:906:1bb1:b0:aa5:1ec3:b96f with SMTP id a640c23a62f3a-aa51ec3be89mr765094566b.17.1732475872555; Sun, 24 Nov 2024 11:17:52 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:52 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:47 +0100 Subject: [PATCH 05/15] soc: qcom: import smem from Linux 6.11-rc2 MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-5-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=40564; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=7Q9qDL1Nl3tB3jOmavMu5xzRgm86V1t3I12eMDq/y8U=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6hsF6S8eMq3h2OPtvLC5r8jrVHrZg/fLj2or3drUf qLp0uH/HaUsDIIcDLJiiiziJ5ZZNq29bK+xfcEFmDmsTCBDGLg4BWAizvKMDI0PjYL3pNubLtFJ mbvwTZ1cGN+ii2f11C/5p7zkWnEv9RQjQ98ib6Z8zt0dz9deZHhvz/rj1+/D/VdWbktdpf6jpC3 83zsA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Import the SMEM driver from Linux. Signed-off-by: Caleb Connolly --- drivers/soc/qcom/smem.c | 1279 ++++++++++++++++++++++++++++++++++++++++++++ include/soc/qcom/smem.h | 20 + include/soc/qcom/socinfo.h | 111 ++++ 3 files changed, 1410 insertions(+) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c new file mode 100644 index 000000000000..8515b8ae7777 --- /dev/null +++ b/drivers/soc/qcom/smem.c @@ -0,0 +1,1279 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, Sony Mobile Communications AB. + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The Qualcomm shared memory system is a allocate only heap structure that + * consists of one of more memory areas that can be accessed by the processors + * in the SoC. + * + * All systems contains a global heap, accessible by all processors in the SoC, + * with a table of contents data structure (@smem_header) at the beginning of + * the main shared memory block. + * + * The global header contains meta data for allocations as well as a fixed list + * of 512 entries (@smem_global_entry) that can be initialized to reference + * parts of the shared memory space. + * + * + * In addition to this global heap a set of "private" heaps can be set up at + * boot time with access restrictions so that only certain processor pairs can + * access the data. + * + * These partitions are referenced from an optional partition table + * (@smem_ptable), that is found 4kB from the end of the main smem region. The + * partition table entries (@smem_ptable_entry) lists the involved processors + * (or hosts) and their location in the main shared memory region. + * + * Each partition starts with a header (@smem_partition_header) that identifies + * the partition and holds properties for the two internal memory regions. The + * two regions are cached and non-cached memory respectively. Each region + * contain a link list of allocation headers (@smem_private_entry) followed by + * their data. + * + * Items in the non-cached region are allocated from the start of the partition + * while items in the cached region are allocated from the end. The free area + * is hence the region between the cached and non-cached offsets. The header of + * cached items comes after the data. + * + * Version 12 (SMEM_GLOBAL_PART_VERSION) changes the item alloc/get procedure + * for the global heap. A new global partition is created from the global heap + * region with partition type (SMEM_GLOBAL_HOST) and the max smem item count is + * set by the bootloader. + * + * To synchronize allocations in the shared memory heaps a remote spinlock must + * be held - currently lock number 3 of the sfpb or tcsr is used for this on all + * platforms. + * + */ + +/* + * The version member of the smem header contains an array of versions for the + * various software components in the SoC. We verify that the boot loader + * version is a valid version as a sanity check. + */ +#define SMEM_MASTER_SBL_VERSION_INDEX 7 +#define SMEM_GLOBAL_HEAP_VERSION 11 +#define SMEM_GLOBAL_PART_VERSION 12 + +/* + * The first 8 items are only to be allocated by the boot loader while + * initializing the heap. + */ +#define SMEM_ITEM_LAST_FIXED 8 + +/* Highest accepted item number, for both global and private heaps */ +#define SMEM_ITEM_COUNT 512 + +/* Processor/host identifier for the application processor */ +#define SMEM_HOST_APPS 0 + +/* Processor/host identifier for the global partition */ +#define SMEM_GLOBAL_HOST 0xfffe + +/* Max number of processors/hosts in a system */ +#define SMEM_HOST_COUNT 20 + +/** + * struct smem_proc_comm - proc_comm communication struct (legacy) + * @command: current command to be executed + * @status: status of the currently requested command + * @params: parameters to the command + */ +struct smem_proc_comm { + __le32 command; + __le32 status; + __le32 params[2]; +}; + +/** + * struct smem_global_entry - entry to reference smem items on the heap + * @allocated: boolean to indicate if this entry is used + * @offset: offset to the allocated space + * @size: size of the allocated space, 8 byte aligned + * @aux_base: base address for the memory region used by this unit, or 0 for + * the default region. bits 0,1 are reserved + */ +struct smem_global_entry { + __le32 allocated; + __le32 offset; + __le32 size; + __le32 aux_base; /* bits 1:0 reserved */ +}; +#define AUX_BASE_MASK 0xfffffffc + +/** + * struct smem_header - header found in beginning of primary smem region + * @proc_comm: proc_comm communication interface (legacy) + * @version: array of versions for the various subsystems + * @initialized: boolean to indicate that smem is initialized + * @free_offset: index of the first unallocated byte in smem + * @available: number of bytes available for allocation + * @reserved: reserved field, must be 0 + * @toc: array of references to items + */ +struct smem_header { + struct smem_proc_comm proc_comm[4]; + __le32 version[32]; + __le32 initialized; + __le32 free_offset; + __le32 available; + __le32 reserved; + struct smem_global_entry toc[SMEM_ITEM_COUNT]; +}; + +/** + * struct smem_ptable_entry - one entry in the @smem_ptable list + * @offset: offset, within the main shared memory region, of the partition + * @size: size of the partition + * @flags: flags for the partition (currently unused) + * @host0: first processor/host with access to this partition + * @host1: second processor/host with access to this partition + * @cacheline: alignment for "cached" entries + * @reserved: reserved entries for later use + */ +struct smem_ptable_entry { + __le32 offset; + __le32 size; + __le32 flags; + __le16 host0; + __le16 host1; + __le32 cacheline; + __le32 reserved[7]; +}; + +/** + * struct smem_ptable - partition table for the private partitions + * @magic: magic number, must be SMEM_PTABLE_MAGIC + * @version: version of the partition table + * @num_entries: number of partitions in the table + * @reserved: for now reserved entries + * @entry: list of @smem_ptable_entry for the @num_entries partitions + */ +struct smem_ptable { + u8 magic[4]; + __le32 version; + __le32 num_entries; + __le32 reserved[5]; + struct smem_ptable_entry entry[]; +}; + +static const u8 SMEM_PTABLE_MAGIC[] = { 0x24, 0x54, 0x4f, 0x43 }; /* "$TOC" */ + +/** + * struct smem_partition_header - header of the partitions + * @magic: magic number, must be SMEM_PART_MAGIC + * @host0: first processor/host with access to this partition + * @host1: second processor/host with access to this partition + * @size: size of the partition + * @offset_free_uncached: offset to the first free byte of uncached memory in + * this partition + * @offset_free_cached: offset to the first free byte of cached memory in this + * partition + * @reserved: for now reserved entries + */ +struct smem_partition_header { + u8 magic[4]; + __le16 host0; + __le16 host1; + __le32 size; + __le32 offset_free_uncached; + __le32 offset_free_cached; + __le32 reserved[3]; +}; + +/** + * struct smem_partition - describes smem partition + * @virt_base: starting virtual address of partition + * @phys_base: starting physical address of partition + * @cacheline: alignment for "cached" entries + * @size: size of partition + */ +struct smem_partition { + void __iomem *virt_base; + phys_addr_t phys_base; + size_t cacheline; + size_t size; +}; + +static const u8 SMEM_PART_MAGIC[] = { 0x24, 0x50, 0x52, 0x54 }; + +/** + * struct smem_private_entry - header of each item in the private partition + * @canary: magic number, must be SMEM_PRIVATE_CANARY + * @item: identifying number of the smem item + * @size: size of the data, including padding bytes + * @padding_data: number of bytes of padding of data + * @padding_hdr: number of bytes of padding between the header and the data + * @reserved: for now reserved entry + */ +struct smem_private_entry { + u16 canary; /* bytes are the same so no swapping needed */ + __le16 item; + __le32 size; /* includes padding bytes */ + __le16 padding_data; + __le16 padding_hdr; + __le32 reserved; +}; +#define SMEM_PRIVATE_CANARY 0xa5a5 + +/** + * struct smem_info - smem region info located after the table of contents + * @magic: magic number, must be SMEM_INFO_MAGIC + * @size: size of the smem region + * @base_addr: base address of the smem region + * @reserved: for now reserved entry + * @num_items: highest accepted item number + */ +struct smem_info { + u8 magic[4]; + __le32 size; + __le32 base_addr; + __le32 reserved; + __le16 num_items; +}; + +static const u8 SMEM_INFO_MAGIC[] = { 0x53, 0x49, 0x49, 0x49 }; /* SIII */ + +/** + * struct smem_region - representation of a chunk of memory used for smem + * @aux_base: identifier of aux_mem base + * @virt_base: virtual base address of memory with this aux_mem identifier + * @size: size of the memory region + */ +struct smem_region { + phys_addr_t aux_base; + void __iomem *virt_base; + size_t size; +}; + +/** + * struct qcom_smem - device data for the smem device + * @dev: device pointer + * @hwlock: reference to a hwspinlock + * @ptable: virtual base of partition table + * @global_partition: describes for global partition when in use + * @partitions: list of partitions of current processor/host + * @item_count: max accepted item number + * @socinfo: platform device pointer + * @num_regions: number of @regions + * @regions: list of the memory regions defining the shared memory + */ +struct qcom_smem { + struct device *dev; + + struct hwspinlock *hwlock; + + u32 item_count; + struct platform_device *socinfo; + struct smem_ptable *ptable; + struct smem_partition global_partition; + struct smem_partition partitions[SMEM_HOST_COUNT]; + + unsigned num_regions; + struct smem_region regions[] __counted_by(num_regions); +}; + +static void * +phdr_to_last_uncached_entry(struct smem_partition_header *phdr) +{ + void *p = phdr; + + return p + le32_to_cpu(phdr->offset_free_uncached); +} + +static struct smem_private_entry * +phdr_to_first_cached_entry(struct smem_partition_header *phdr, + size_t cacheline) +{ + void *p = phdr; + struct smem_private_entry *e; + + return p + le32_to_cpu(phdr->size) - ALIGN(sizeof(*e), cacheline); +} + +static void * +phdr_to_last_cached_entry(struct smem_partition_header *phdr) +{ + void *p = phdr; + + return p + le32_to_cpu(phdr->offset_free_cached); +} + +static struct smem_private_entry * +phdr_to_first_uncached_entry(struct smem_partition_header *phdr) +{ + void *p = phdr; + + return p + sizeof(*phdr); +} + +static struct smem_private_entry * +uncached_entry_next(struct smem_private_entry *e) +{ + void *p = e; + + return p + sizeof(*e) + le16_to_cpu(e->padding_hdr) + + le32_to_cpu(e->size); +} + +static struct smem_private_entry * +cached_entry_next(struct smem_private_entry *e, size_t cacheline) +{ + void *p = e; + + return p - le32_to_cpu(e->size) - ALIGN(sizeof(*e), cacheline); +} + +static void *uncached_entry_to_item(struct smem_private_entry *e) +{ + void *p = e; + + return p + sizeof(*e) + le16_to_cpu(e->padding_hdr); +} + +static void *cached_entry_to_item(struct smem_private_entry *e) +{ + void *p = e; + + return p - le32_to_cpu(e->size); +} + +/* Pointer to the one and only smem handle */ +static struct qcom_smem *__smem; + +/* Timeout (ms) for the trylock of remote spinlocks */ +#define HWSPINLOCK_TIMEOUT 1000 + +/* The qcom hwspinlock id is always plus one from the smem host id */ +#define SMEM_HOST_ID_TO_HWSPINLOCK_ID(__x) ((__x) + 1) + +/** + * qcom_smem_bust_hwspin_lock_by_host() - bust the smem hwspinlock for a host + * @host: remote processor id + * + * Busts the hwspin_lock for the given smem host id. This helper is intended + * for remoteproc drivers that manage remoteprocs with an equivalent smem + * driver instance in the remote firmware. Drivers can force a release of the + * smem hwspin_lock if the rproc unexpectedly goes into a bad state. + * + * Context: Process context. + * + * Returns: 0 on success, otherwise negative errno. + */ +int qcom_smem_bust_hwspin_lock_by_host(unsigned int host) +{ + /* This function is for remote procs, so ignore SMEM_HOST_APPS */ + if (host == SMEM_HOST_APPS || host >= SMEM_HOST_COUNT) + return -EINVAL; + + return hwspin_lock_bust(__smem->hwlock, SMEM_HOST_ID_TO_HWSPINLOCK_ID(host)); +} +EXPORT_SYMBOL_GPL(qcom_smem_bust_hwspin_lock_by_host); + +/** + * qcom_smem_is_available() - Check if SMEM is available + * + * Return: true if SMEM is available, false otherwise. + */ +bool qcom_smem_is_available(void) +{ + return !!__smem; +} +EXPORT_SYMBOL_GPL(qcom_smem_is_available); + +static int qcom_smem_alloc_private(struct qcom_smem *smem, + struct smem_partition *part, + unsigned item, + size_t size) +{ + struct smem_private_entry *hdr, *end; + struct smem_partition_header *phdr; + size_t alloc_size; + void *cached; + void *p_end; + + phdr = (struct smem_partition_header __force *)part->virt_base; + p_end = (void *)phdr + part->size; + + hdr = phdr_to_first_uncached_entry(phdr); + end = phdr_to_last_uncached_entry(phdr); + cached = phdr_to_last_cached_entry(phdr); + + if (WARN_ON((void *)end > p_end || cached > p_end)) + return -EINVAL; + + while (hdr < end) { + if (hdr->canary != SMEM_PRIVATE_CANARY) + goto bad_canary; + if (le16_to_cpu(hdr->item) == item) + return -EEXIST; + + hdr = uncached_entry_next(hdr); + } + + if (WARN_ON((void *)hdr > p_end)) + return -EINVAL; + + /* Check that we don't grow into the cached region */ + alloc_size = sizeof(*hdr) + ALIGN(size, 8); + if ((void *)hdr + alloc_size > cached) { + dev_err(smem->dev, "Out of memory\n"); + return -ENOSPC; + } + + hdr->canary = SMEM_PRIVATE_CANARY; + hdr->item = cpu_to_le16(item); + hdr->size = cpu_to_le32(ALIGN(size, 8)); + hdr->padding_data = cpu_to_le16(le32_to_cpu(hdr->size) - size); + hdr->padding_hdr = 0; + + /* + * Ensure the header is written before we advance the free offset, so + * that remote processors that does not take the remote spinlock still + * gets a consistent view of the linked list. + */ + wmb(); + le32_add_cpu(&phdr->offset_free_uncached, alloc_size); + + return 0; +bad_canary: + dev_err(smem->dev, "Found invalid canary in hosts %hu:%hu partition\n", + le16_to_cpu(phdr->host0), le16_to_cpu(phdr->host1)); + + return -EINVAL; +} + +static int qcom_smem_alloc_global(struct qcom_smem *smem, + unsigned item, + size_t size) +{ + struct smem_global_entry *entry; + struct smem_header *header; + + header = smem->regions[0].virt_base; + entry = &header->toc[item]; + if (entry->allocated) + return -EEXIST; + + size = ALIGN(size, 8); + if (WARN_ON(size > le32_to_cpu(header->available))) + return -ENOMEM; + + entry->offset = header->free_offset; + entry->size = cpu_to_le32(size); + + /* + * Ensure the header is consistent before we mark the item allocated, + * so that remote processors will get a consistent view of the item + * even though they do not take the spinlock on read. + */ + wmb(); + entry->allocated = cpu_to_le32(1); + + le32_add_cpu(&header->free_offset, size); + le32_add_cpu(&header->available, -size); + + return 0; +} + +/** + * qcom_smem_alloc() - allocate space for a smem item + * @host: remote processor id, or -1 + * @item: smem item handle + * @size: number of bytes to be allocated + * + * Allocate space for a given smem item of size @size, given that the item is + * not yet allocated. + */ +int qcom_smem_alloc(unsigned host, unsigned item, size_t size) +{ + struct smem_partition *part; + unsigned long flags; + int ret; + + if (!__smem) + return -EPROBE_DEFER; + + if (item < SMEM_ITEM_LAST_FIXED) { + dev_err(__smem->dev, + "Rejecting allocation of static entry %d\n", item); + return -EINVAL; + } + + if (WARN_ON(item >= __smem->item_count)) + return -EINVAL; + + ret = hwspin_lock_timeout_irqsave(__smem->hwlock, + HWSPINLOCK_TIMEOUT, + &flags); + if (ret) + return ret; + + if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) { + part = &__smem->partitions[host]; + ret = qcom_smem_alloc_private(__smem, part, item, size); + } else if (__smem->global_partition.virt_base) { + part = &__smem->global_partition; + ret = qcom_smem_alloc_private(__smem, part, item, size); + } else { + ret = qcom_smem_alloc_global(__smem, item, size); + } + + hwspin_unlock_irqrestore(__smem->hwlock, &flags); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_smem_alloc); + +static void *qcom_smem_get_global(struct qcom_smem *smem, + unsigned item, + size_t *size) +{ + struct smem_header *header; + struct smem_region *region; + struct smem_global_entry *entry; + u64 entry_offset; + u32 e_size; + u32 aux_base; + unsigned i; + + header = smem->regions[0].virt_base; + entry = &header->toc[item]; + if (!entry->allocated) + return ERR_PTR(-ENXIO); + + aux_base = le32_to_cpu(entry->aux_base) & AUX_BASE_MASK; + + for (i = 0; i < smem->num_regions; i++) { + region = &smem->regions[i]; + + if ((u32)region->aux_base == aux_base || !aux_base) { + e_size = le32_to_cpu(entry->size); + entry_offset = le32_to_cpu(entry->offset); + + if (WARN_ON(e_size + entry_offset > region->size)) + return ERR_PTR(-EINVAL); + + if (size != NULL) + *size = e_size; + + return region->virt_base + entry_offset; + } + } + + return ERR_PTR(-ENOENT); +} + +static void *qcom_smem_get_private(struct qcom_smem *smem, + struct smem_partition *part, + unsigned item, + size_t *size) +{ + struct smem_private_entry *e, *end; + struct smem_partition_header *phdr; + void *item_ptr, *p_end; + u32 padding_data; + u32 e_size; + + phdr = (struct smem_partition_header __force *)part->virt_base; + p_end = (void *)phdr + part->size; + + e = phdr_to_first_uncached_entry(phdr); + end = phdr_to_last_uncached_entry(phdr); + + while (e < end) { + if (e->canary != SMEM_PRIVATE_CANARY) + goto invalid_canary; + + if (le16_to_cpu(e->item) == item) { + if (size != NULL) { + e_size = le32_to_cpu(e->size); + padding_data = le16_to_cpu(e->padding_data); + + if (WARN_ON(e_size > part->size || padding_data > e_size)) + return ERR_PTR(-EINVAL); + + *size = e_size - padding_data; + } + + item_ptr = uncached_entry_to_item(e); + if (WARN_ON(item_ptr > p_end)) + return ERR_PTR(-EINVAL); + + return item_ptr; + } + + e = uncached_entry_next(e); + } + + if (WARN_ON((void *)e > p_end)) + return ERR_PTR(-EINVAL); + + /* Item was not found in the uncached list, search the cached list */ + + e = phdr_to_first_cached_entry(phdr, part->cacheline); + end = phdr_to_last_cached_entry(phdr); + + if (WARN_ON((void *)e < (void *)phdr || (void *)end > p_end)) + return ERR_PTR(-EINVAL); + + while (e > end) { + if (e->canary != SMEM_PRIVATE_CANARY) + goto invalid_canary; + + if (le16_to_cpu(e->item) == item) { + if (size != NULL) { + e_size = le32_to_cpu(e->size); + padding_data = le16_to_cpu(e->padding_data); + + if (WARN_ON(e_size > part->size || padding_data > e_size)) + return ERR_PTR(-EINVAL); + + *size = e_size - padding_data; + } + + item_ptr = cached_entry_to_item(e); + if (WARN_ON(item_ptr < (void *)phdr)) + return ERR_PTR(-EINVAL); + + return item_ptr; + } + + e = cached_entry_next(e, part->cacheline); + } + + if (WARN_ON((void *)e < (void *)phdr)) + return ERR_PTR(-EINVAL); + + return ERR_PTR(-ENOENT); + +invalid_canary: + dev_err(smem->dev, "Found invalid canary in hosts %hu:%hu partition\n", + le16_to_cpu(phdr->host0), le16_to_cpu(phdr->host1)); + + return ERR_PTR(-EINVAL); +} + +/** + * qcom_smem_get() - resolve ptr of size of a smem item + * @host: the remote processor, or -1 + * @item: smem item handle + * @size: pointer to be filled out with size of the item + * + * Looks up smem item and returns pointer to it. Size of smem + * item is returned in @size. + */ +void *qcom_smem_get(unsigned host, unsigned item, size_t *size) +{ + struct smem_partition *part; + void *ptr = ERR_PTR(-EPROBE_DEFER); + + if (!__smem) + return ptr; + + if (WARN_ON(item >= __smem->item_count)) + return ERR_PTR(-EINVAL); + + if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) { + part = &__smem->partitions[host]; + ptr = qcom_smem_get_private(__smem, part, item, size); + } else if (__smem->global_partition.virt_base) { + part = &__smem->global_partition; + ptr = qcom_smem_get_private(__smem, part, item, size); + } else { + ptr = qcom_smem_get_global(__smem, item, size); + } + + return ptr; +} +EXPORT_SYMBOL_GPL(qcom_smem_get); + +/** + * qcom_smem_get_free_space() - retrieve amount of free space in a partition + * @host: the remote processor identifying a partition, or -1 + * + * To be used by smem clients as a quick way to determine if any new + * allocations has been made. + */ +int qcom_smem_get_free_space(unsigned host) +{ + struct smem_partition *part; + struct smem_partition_header *phdr; + struct smem_header *header; + unsigned ret; + + if (!__smem) + return -EPROBE_DEFER; + + if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) { + part = &__smem->partitions[host]; + phdr = part->virt_base; + ret = le32_to_cpu(phdr->offset_free_cached) - + le32_to_cpu(phdr->offset_free_uncached); + + if (ret > le32_to_cpu(part->size)) + return -EINVAL; + } else if (__smem->global_partition.virt_base) { + part = &__smem->global_partition; + phdr = part->virt_base; + ret = le32_to_cpu(phdr->offset_free_cached) - + le32_to_cpu(phdr->offset_free_uncached); + + if (ret > le32_to_cpu(part->size)) + return -EINVAL; + } else { + header = __smem->regions[0].virt_base; + ret = le32_to_cpu(header->available); + + if (ret > __smem->regions[0].size) + return -EINVAL; + } + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_smem_get_free_space); + +static bool addr_in_range(void __iomem *base, size_t size, void *addr) +{ + return base && ((void __iomem *)addr >= base && (void __iomem *)addr < base + size); +} + +/** + * qcom_smem_virt_to_phys() - return the physical address associated + * with an smem item pointer (previously returned by qcom_smem_get() + * @p: the virtual address to convert + * + * Returns 0 if the pointer provided is not within any smem region. + */ +phys_addr_t qcom_smem_virt_to_phys(void *p) +{ + struct smem_partition *part; + struct smem_region *area; + u64 offset; + u32 i; + + for (i = 0; i < SMEM_HOST_COUNT; i++) { + part = &__smem->partitions[i]; + + if (addr_in_range(part->virt_base, part->size, p)) { + offset = p - part->virt_base; + + return (phys_addr_t)part->phys_base + offset; + } + } + + part = &__smem->global_partition; + + if (addr_in_range(part->virt_base, part->size, p)) { + offset = p - part->virt_base; + + return (phys_addr_t)part->phys_base + offset; + } + + for (i = 0; i < __smem->num_regions; i++) { + area = &__smem->regions[i]; + + if (addr_in_range(area->virt_base, area->size, p)) { + offset = p - area->virt_base; + + return (phys_addr_t)area->aux_base + offset; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_smem_virt_to_phys); + +/** + * qcom_smem_get_soc_id() - return the SoC ID + * @id: On success, we return the SoC ID here. + * + * Look up SoC ID from HW/SW build ID and return it. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_smem_get_soc_id(u32 *id) +{ + struct socinfo *info; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); + if (IS_ERR(info)) + return PTR_ERR(info); + + *id = __le32_to_cpu(info->id); + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_smem_get_soc_id); + +/** + * qcom_smem_get_feature_code() - return the feature code + * @code: On success, return the feature code here. + * + * Look up the feature code identifier from SMEM and return it. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_smem_get_feature_code(u32 *code) +{ + struct socinfo *info; + u32 raw_code; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); + if (IS_ERR(info)) + return PTR_ERR(info); + + /* This only makes sense for socinfo >= 16 */ + if (__le32_to_cpu(info->fmt) < SOCINFO_VERSION(0, 16)) + return -EOPNOTSUPP; + + raw_code = __le32_to_cpu(info->feature_code); + + /* Ensure the value makes sense */ + if (raw_code > SOCINFO_FC_INT_MAX) + raw_code = SOCINFO_FC_UNKNOWN; + + *code = raw_code; + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_smem_get_feature_code); + +static int qcom_smem_get_sbl_version(struct qcom_smem *smem) +{ + struct smem_header *header; + __le32 *versions; + + header = smem->regions[0].virt_base; + versions = header->version; + + return le32_to_cpu(versions[SMEM_MASTER_SBL_VERSION_INDEX]); +} + +static struct smem_ptable *qcom_smem_get_ptable(struct qcom_smem *smem) +{ + struct smem_ptable *ptable; + u32 version; + + ptable = smem->ptable; + if (memcmp(ptable->magic, SMEM_PTABLE_MAGIC, sizeof(ptable->magic))) + return ERR_PTR(-ENOENT); + + version = le32_to_cpu(ptable->version); + if (version != 1) { + dev_err(smem->dev, + "Unsupported partition header version %d\n", version); + return ERR_PTR(-EINVAL); + } + return ptable; +} + +static u32 qcom_smem_get_item_count(struct qcom_smem *smem) +{ + struct smem_ptable *ptable; + struct smem_info *info; + + ptable = qcom_smem_get_ptable(smem); + if (IS_ERR_OR_NULL(ptable)) + return SMEM_ITEM_COUNT; + + info = (struct smem_info *)&ptable->entry[ptable->num_entries]; + if (memcmp(info->magic, SMEM_INFO_MAGIC, sizeof(info->magic))) + return SMEM_ITEM_COUNT; + + return le16_to_cpu(info->num_items); +} + +/* + * Validate the partition header for a partition whose partition + * table entry is supplied. Returns a pointer to its header if + * valid, or a null pointer otherwise. + */ +static struct smem_partition_header * +qcom_smem_partition_header(struct qcom_smem *smem, + struct smem_ptable_entry *entry, u16 host0, u16 host1) +{ + struct smem_partition_header *header; + u32 phys_addr; + u32 size; + + phys_addr = smem->regions[0].aux_base + le32_to_cpu(entry->offset); + header = devm_ioremap_wc(smem->dev, phys_addr, le32_to_cpu(entry->size)); + + if (!header) + return NULL; + + if (memcmp(header->magic, SMEM_PART_MAGIC, sizeof(header->magic))) { + dev_err(smem->dev, "bad partition magic %4ph\n", header->magic); + return NULL; + } + + if (host0 != le16_to_cpu(header->host0)) { + dev_err(smem->dev, "bad host0 (%hu != %hu)\n", + host0, le16_to_cpu(header->host0)); + return NULL; + } + if (host1 != le16_to_cpu(header->host1)) { + dev_err(smem->dev, "bad host1 (%hu != %hu)\n", + host1, le16_to_cpu(header->host1)); + return NULL; + } + + size = le32_to_cpu(header->size); + if (size != le32_to_cpu(entry->size)) { + dev_err(smem->dev, "bad partition size (%u != %u)\n", + size, le32_to_cpu(entry->size)); + return NULL; + } + + if (le32_to_cpu(header->offset_free_uncached) > size) { + dev_err(smem->dev, "bad partition free uncached (%u > %u)\n", + le32_to_cpu(header->offset_free_uncached), size); + return NULL; + } + + return header; +} + +static int qcom_smem_set_global_partition(struct qcom_smem *smem) +{ + struct smem_partition_header *header; + struct smem_ptable_entry *entry; + struct smem_ptable *ptable; + bool found = false; + int i; + + if (smem->global_partition.virt_base) { + dev_err(smem->dev, "Already found the global partition\n"); + return -EINVAL; + } + + ptable = qcom_smem_get_ptable(smem); + if (IS_ERR(ptable)) + return PTR_ERR(ptable); + + for (i = 0; i < le32_to_cpu(ptable->num_entries); i++) { + entry = &ptable->entry[i]; + if (!le32_to_cpu(entry->offset)) + continue; + if (!le32_to_cpu(entry->size)) + continue; + + if (le16_to_cpu(entry->host0) != SMEM_GLOBAL_HOST) + continue; + + if (le16_to_cpu(entry->host1) == SMEM_GLOBAL_HOST) { + found = true; + break; + } + } + + if (!found) { + dev_err(smem->dev, "Missing entry for global partition\n"); + return -EINVAL; + } + + header = qcom_smem_partition_header(smem, entry, + SMEM_GLOBAL_HOST, SMEM_GLOBAL_HOST); + if (!header) + return -EINVAL; + + smem->global_partition.virt_base = (void __iomem *)header; + smem->global_partition.phys_base = smem->regions[0].aux_base + + le32_to_cpu(entry->offset); + smem->global_partition.size = le32_to_cpu(entry->size); + smem->global_partition.cacheline = le32_to_cpu(entry->cacheline); + + return 0; +} + +static int +qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host) +{ + struct smem_partition_header *header; + struct smem_ptable_entry *entry; + struct smem_ptable *ptable; + u16 remote_host; + u16 host0, host1; + int i; + + ptable = qcom_smem_get_ptable(smem); + if (IS_ERR(ptable)) + return PTR_ERR(ptable); + + for (i = 0; i < le32_to_cpu(ptable->num_entries); i++) { + entry = &ptable->entry[i]; + if (!le32_to_cpu(entry->offset)) + continue; + if (!le32_to_cpu(entry->size)) + continue; + + host0 = le16_to_cpu(entry->host0); + host1 = le16_to_cpu(entry->host1); + if (host0 == local_host) + remote_host = host1; + else if (host1 == local_host) + remote_host = host0; + else + continue; + + if (remote_host >= SMEM_HOST_COUNT) { + dev_err(smem->dev, "bad host %u\n", remote_host); + return -EINVAL; + } + + if (smem->partitions[remote_host].virt_base) { + dev_err(smem->dev, "duplicate host %u\n", remote_host); + return -EINVAL; + } + + header = qcom_smem_partition_header(smem, entry, host0, host1); + if (!header) + return -EINVAL; + + smem->partitions[remote_host].virt_base = (void __iomem *)header; + smem->partitions[remote_host].phys_base = smem->regions[0].aux_base + + le32_to_cpu(entry->offset); + smem->partitions[remote_host].size = le32_to_cpu(entry->size); + smem->partitions[remote_host].cacheline = le32_to_cpu(entry->cacheline); + } + + return 0; +} + +static int qcom_smem_map_toc(struct qcom_smem *smem, struct smem_region *region) +{ + u32 ptable_start; + + /* map starting 4K for smem header */ + region->virt_base = devm_ioremap_wc(smem->dev, region->aux_base, SZ_4K); + ptable_start = region->aux_base + region->size - SZ_4K; + /* map last 4k for toc */ + smem->ptable = devm_ioremap_wc(smem->dev, ptable_start, SZ_4K); + + if (!region->virt_base || !smem->ptable) + return -ENOMEM; + + return 0; +} + +static int qcom_smem_map_global(struct qcom_smem *smem, u32 size) +{ + u32 phys_addr; + + phys_addr = smem->regions[0].aux_base; + + smem->regions[0].size = size; + smem->regions[0].virt_base = devm_ioremap_wc(smem->dev, phys_addr, size); + + if (!smem->regions[0].virt_base) + return -ENOMEM; + + return 0; +} + +static int qcom_smem_resolve_mem(struct qcom_smem *smem, const char *name, + struct smem_region *region) +{ + struct device *dev = smem->dev; + struct device_node *np; + struct resource r; + int ret; + + np = of_parse_phandle(dev->of_node, name, 0); + if (!np) { + dev_err(dev, "No %s specified\n", name); + return -EINVAL; + } + + ret = of_address_to_resource(np, 0, &r); + of_node_put(np); + if (ret) + return ret; + + region->aux_base = r.start; + region->size = resource_size(&r); + + return 0; +} + +static int qcom_smem_probe(struct platform_device *pdev) +{ + struct smem_header *header; + struct reserved_mem *rmem; + struct qcom_smem *smem; + unsigned long flags; + int num_regions; + int hwlock_id; + u32 version; + u32 size; + int ret; + int i; + + if (__smem) + return 0; + + num_regions = 1; + if (of_property_present(pdev->dev.of_node, "qcom,rpm-msg-ram")) + num_regions++; + + smem = devm_kzalloc(&pdev->dev, struct_size(smem, regions, num_regions), + GFP_KERNEL); + if (!smem) + return -ENOMEM; + + smem->dev = &pdev->dev; + smem->num_regions = num_regions; + + rmem = of_reserved_mem_lookup(pdev->dev.of_node); + if (rmem) { + smem->regions[0].aux_base = rmem->base; + smem->regions[0].size = rmem->size; + } else { + /* + * Fall back to the memory-region reference, if we're not a + * reserved-memory node. + */ + ret = qcom_smem_resolve_mem(smem, "memory-region", &smem->regions[0]); + if (ret) + return ret; + } + + if (num_regions > 1) { + ret = qcom_smem_resolve_mem(smem, "qcom,rpm-msg-ram", &smem->regions[1]); + if (ret) + return ret; + } + + + ret = qcom_smem_map_toc(smem, &smem->regions[0]); + if (ret) + return ret; + + for (i = 1; i < num_regions; i++) { + smem->regions[i].virt_base = devm_ioremap_wc(&pdev->dev, + smem->regions[i].aux_base, + smem->regions[i].size); + if (!smem->regions[i].virt_base) { + dev_err(&pdev->dev, "failed to remap %pa\n", &smem->regions[i].aux_base); + return -ENOMEM; + } + } + + header = smem->regions[0].virt_base; + if (le32_to_cpu(header->initialized) != 1 || + le32_to_cpu(header->reserved)) { + dev_err(&pdev->dev, "SMEM is not initialized by SBL\n"); + return -EINVAL; + } + + hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); + if (hwlock_id < 0) { + if (hwlock_id != -EPROBE_DEFER) + dev_err(&pdev->dev, "failed to retrieve hwlock\n"); + return hwlock_id; + } + + smem->hwlock = hwspin_lock_request_specific(hwlock_id); + if (!smem->hwlock) + return -ENXIO; + + ret = hwspin_lock_timeout_irqsave(smem->hwlock, HWSPINLOCK_TIMEOUT, &flags); + if (ret) + return ret; + size = readl_relaxed(&header->available) + readl_relaxed(&header->free_offset); + hwspin_unlock_irqrestore(smem->hwlock, &flags); + + version = qcom_smem_get_sbl_version(smem); + /* + * smem header mapping is required only in heap version scheme, so unmap + * it here. It will be remapped in qcom_smem_map_global() when whole + * partition is mapped again. + */ + devm_iounmap(smem->dev, smem->regions[0].virt_base); + switch (version >> 16) { + case SMEM_GLOBAL_PART_VERSION: + ret = qcom_smem_set_global_partition(smem); + if (ret < 0) + return ret; + smem->item_count = qcom_smem_get_item_count(smem); + break; + case SMEM_GLOBAL_HEAP_VERSION: + qcom_smem_map_global(smem, size); + smem->item_count = SMEM_ITEM_COUNT; + break; + default: + dev_err(&pdev->dev, "Unsupported SMEM version 0x%x\n", version); + return -EINVAL; + } + + BUILD_BUG_ON(SMEM_HOST_APPS >= SMEM_HOST_COUNT); + ret = qcom_smem_enumerate_partitions(smem, SMEM_HOST_APPS); + if (ret < 0 && ret != -ENOENT) + return ret; + + __smem = smem; + + smem->socinfo = platform_device_register_data(&pdev->dev, "qcom-socinfo", + PLATFORM_DEVID_NONE, NULL, + 0); + if (IS_ERR(smem->socinfo)) + dev_dbg(&pdev->dev, "failed to register socinfo device\n"); + + return 0; +} + +static void qcom_smem_remove(struct platform_device *pdev) +{ + platform_device_unregister(__smem->socinfo); + + hwspin_lock_free(__smem->hwlock); + __smem = NULL; +} + +static const struct of_device_id qcom_smem_of_match[] = { + { .compatible = "qcom,smem" }, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_smem_of_match); + +static struct platform_driver qcom_smem_driver = { + .probe = qcom_smem_probe, + .remove_new = qcom_smem_remove, + .driver = { + .name = "qcom-smem", + .of_match_table = qcom_smem_of_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init qcom_smem_init(void) +{ + return platform_driver_register(&qcom_smem_driver); +} +arch_initcall(qcom_smem_init); + +static void __exit qcom_smem_exit(void) +{ + platform_driver_unregister(&qcom_smem_driver); +} +module_exit(qcom_smem_exit) + +MODULE_AUTHOR("Bjorn Andersson "); +MODULE_DESCRIPTION("Qualcomm Shared Memory Manager"); +MODULE_LICENSE("GPL v2"); diff --git a/include/soc/qcom/smem.h b/include/soc/qcom/smem.h new file mode 100644 index 000000000000..f946e3beca21 --- /dev/null +++ b/include/soc/qcom/smem.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __QCOM_SMEM_H__ +#define __QCOM_SMEM_H__ + +#define QCOM_SMEM_HOST_ANY -1 + +bool qcom_smem_is_available(void); +int qcom_smem_alloc(unsigned host, unsigned item, size_t size); +void *qcom_smem_get(unsigned host, unsigned item, size_t *size); + +int qcom_smem_get_free_space(unsigned host); + +phys_addr_t qcom_smem_virt_to_phys(void *p); + +int qcom_smem_get_soc_id(u32 *id); +int qcom_smem_get_feature_code(u32 *code); + +int qcom_smem_bust_hwspin_lock_by_host(unsigned int host); + +#endif diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h new file mode 100644 index 000000000000..608950443eee --- /dev/null +++ b/include/soc/qcom/socinfo.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __QCOM_SOCINFO_H__ +#define __QCOM_SOCINFO_H__ + +#include + +/* + * SMEM item id, used to acquire handles to respective + * SMEM region. + */ +#define SMEM_HW_SW_BUILD_ID 137 + +#define SMEM_SOCINFO_BUILD_ID_LENGTH 32 +#define SMEM_SOCINFO_CHIP_ID_LENGTH 32 + +/* + * SoC version type with major number in the upper 16 bits and minor + * number in the lower 16 bits. + */ +#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff) +#define SOCINFO_MINOR(ver) ((ver) & 0xffff) +#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff)) + +/* Socinfo SMEM item structure */ +struct socinfo { + __le32 fmt; + __le32 id; + __le32 ver; + char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH]; + /* Version 2 */ + __le32 raw_id; + __le32 raw_ver; + /* Version 3 */ + __le32 hw_plat; + /* Version 4 */ + __le32 plat_ver; + /* Version 5 */ + __le32 accessory_chip; + /* Version 6 */ + __le32 hw_plat_subtype; + /* Version 7 */ + __le32 pmic_model; + __le32 pmic_die_rev; + /* Version 8 */ + __le32 pmic_model_1; + __le32 pmic_die_rev_1; + __le32 pmic_model_2; + __le32 pmic_die_rev_2; + /* Version 9 */ + __le32 foundry_id; + /* Version 10 */ + __le32 serial_num; + /* Version 11 */ + __le32 num_pmics; + __le32 pmic_array_offset; + /* Version 12 */ + __le32 chip_family; + __le32 raw_device_family; + __le32 raw_device_num; + /* Version 13 */ + __le32 nproduct_id; + char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH]; + /* Version 14 */ + __le32 num_clusters; + __le32 ncluster_array_offset; + __le32 num_subset_parts; + __le32 nsubset_parts_array_offset; + /* Version 15 */ + __le32 nmodem_supported; + /* Version 16 */ + __le32 feature_code; + __le32 pcode; + __le32 npartnamemap_offset; + __le32 nnum_partname_mapping; + /* Version 17 */ + __le32 oem_variant; + /* Version 18 */ + __le32 num_kvps; + __le32 kvps_offset; + /* Version 19 */ + __le32 num_func_clusters; + __le32 boot_cluster; + __le32 boot_core; +}; + +/* Internal feature codes */ +enum qcom_socinfo_feature_code { + /* External feature codes */ + SOCINFO_FC_UNKNOWN = 0x0, + SOCINFO_FC_AA, + SOCINFO_FC_AB, + SOCINFO_FC_AC, + SOCINFO_FC_AD, + SOCINFO_FC_AE, + SOCINFO_FC_AF, + SOCINFO_FC_AG, + SOCINFO_FC_AH, +}; + +/* Internal feature codes */ +/* Valid values: 0 <= n <= 0xf */ +#define SOCINFO_FC_Yn(n) (0xf1 + (n)) +#define SOCINFO_FC_INT_MAX SOCINFO_FC_Yn(0xf) + +/* Product codes */ +#define SOCINFO_PC_UNKNOWN 0 +#define SOCINFO_PCn(n) ((n) + 1) +#define SOCINFO_PC_RESERVE (BIT(31) - 1) + +#endif From patchwork Sun Nov 24 19:17:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845201 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841461wru; Sun, 24 Nov 2024 11:18:34 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVaI22Evx2COnFPnDwl+J9+mharLNYyqHyPw1uvWnn6pMnh/NFIRnPDNU2Da3f1OBPwEoNUwA==@linaro.org X-Google-Smtp-Source: AGHT+IHsUTI58DXTTXJRUPsMy+5BJQh9vHJQa1C2NtQ117Z241Fqsa+u63FUKj9nJ6/JAL9AO6sy X-Received: by 2002:a17:906:2192:b0:aa5:1a00:5189 with SMTP id a640c23a62f3a-aa51a0059edmr864213166b.28.1732475914761; Sun, 24 Nov 2024 11:18:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475914; cv=none; d=google.com; s=arc-20240605; b=ZPmzpd1L5VL409UA0lSuKkSqzWP5CtlV5DIv7eF1nNTUKYl7Uh7Fx7xpk6AGcct7oQ DlZcLymDDTWMgNBIiMjYXCMlwaAq1tM3YTySRxPUqM/tKv5dWw3y2BYrqvkW3raQkTUI ucffwpJ0ic990hxAQjGwYojBrtAYb1ffUTDNF0JhL2yc2uawRLw3UN8SsONF3Wa/sFcZ 7Kp/JaUlIBK2pkYOmjE1PiYAemyHfl5fJsB5kKv4fV1CCOFWtUSooyYJRQbKTagTBiof ZUqkr3cocNenxNXpUEHqlL2oIW3GcxI5WiVbLjPsxy8kQz4da5ogXHJkOaWLECmw8H3G bmtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=ZhiZzlhanjmoy/ixJ4Go/EF0N+6n3Z+6cx+gDfMUfLY=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=Jir8Xrgb1r+OPgaZi8EoAo1gr0XLr62qFXsAVOOTaC0VzwE3/V89/jdtexVRGE02P0 Wc27S6rf8oF+9GGLyTv5bG68wKbF7lwdhv696Y8ct96biCJXV8WtQd6Zulja5jvg6TIl x3axhw3ucw5GAWJGVzy9eECLvYr0TyJuNj7aSjqljm2F/C8rIg9YBcQsv+20z1lnFnHx yOEqsxmDorqD5lp4qAewfhUc63tSnCZUAA7Cp1a0sXEld0X45FqOabIigOtnHTKMTf0E ziU3Ys+NlWQzVkvnp/BK0gFOWQYMpBP191O28OuHqh9Jcy/wZmdMInfIBkIhyvwziAVm HzzA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RgrI1GPH; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id a640c23a62f3a-aa5168ee81asi365822666b.718.2024.11.24.11.18.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:18:34 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RgrI1GPH; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4E5F98999A; Sun, 24 Nov 2024 20:17:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="RgrI1GPH"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0E98689578; Sun, 24 Nov 2024 20:17:56 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0ED0C8985F for ; Sun, 24 Nov 2024 20:17:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-5cfc035649bso5142523a12.2 for ; Sun, 24 Nov 2024 11:17:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475873; x=1733080673; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ZhiZzlhanjmoy/ixJ4Go/EF0N+6n3Z+6cx+gDfMUfLY=; b=RgrI1GPHDNT+BoKQ46ZJdUjJOwEEbxCfp9mD8oXMYStINPQuoXlUHQ/TpeB6yQi+Ow emrRDqLy0KqvkxBY8ZA2eCdthvSU6ISwLe9ffUvZzzYQoKqQdWvdyDSdYAEiTGjCg8e7 oV2MqaY/t+LamJZY8c7l1wHhv60xFus01kRwnfnYaj4MF3Dl8YTG1sXlbuJIGWo7UQvV nzfu9KNk/UDHVgwvnbA9FCD/hUMSopRWkqXf+/Cd8CFCFyGEf+J35eIKi/Wc0OMHD/8h edjol1htPTDpCCb0xxCocFl2/NYkgrbeAZHJmiNLYM3rxKct5SPMdPqLabHKO9DE9WGL oQvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475873; x=1733080673; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZhiZzlhanjmoy/ixJ4Go/EF0N+6n3Z+6cx+gDfMUfLY=; b=afUE3KFgBh8WBDydLZIm/PY8fAKtS/gYZtYQZza8nTJLfaBLh8wtnPfgCAaVZYx+xE sTwoFP/gTmeyRKwJGDaWkh9Y09wXzoTBmzQpmOIrtbHdQwbxpEznPnjRqjSS0S3ukhNP Lt8S9zemX+HU/rexElvE0RX8vocJlCZd4g5w/GBO9MQO0tomPfQr/vthHhyynQviScUR KA2evCZzl28Mpfq0qL9Ly0oten2zvnsWD+oaa/ZZhXAYtvRbnsmQ0rH/MH+wmeJnBFHp Oea08bBEmY4iupu6EghE/9ojTveI/PR3pECHz70mgxlsagIu0uDB5eHksd6k0s8oAns+ 32Ww== X-Gm-Message-State: AOJu0Yxnv9WzS828Ox1+CUQIJlzGIo7s/OZ6k0H1gJvtKOYv0TIdGEgI lbCaDm9uBaCMJ5Hq5pY3O3fE2orfO1oZbXIZ6E+HIzfZQpR5h+8EHbxc/G3VCe4= X-Gm-Gg: ASbGncus9ZOG2iluyfIEeIcsnPjuR3KUDVhmjJddH/4gTTkw3lBry7SgqJNrh5QNc7o 8S7ewVKvu/BN/npca0uqEyHqZ/hVUInRAegoUtTaGtYBLRV5FYySvUArnXSUiN/8Np1/q7ItKfS YpQ8P29aRl1AcQcXd3d2yKg+mUYw7TwHeZYpv9RGqeCw5x+uFfRrA+eL9fiVnct/Ge9Kbajwvw2 L1VhNhaReCAwiy8dVlLvxgOHsExq3gJbaeNiopuDzL+pUGODMZU5RWdFvn2EBiEZibn X-Received: by 2002:a17:906:1da9:b0:aa5:4d72:6dd7 with SMTP id a640c23a62f3a-aa54d7270bfmr179327166b.29.1732475873411; Sun, 24 Nov 2024 11:17:53 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:53 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:48 +0100 Subject: [PATCH 06/15] soc: qcom: smem: adjust headers for U-Boot MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-6-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1249; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=GQ1J51ZFIFNTHz0+gEMUUTu+0fC1jmMmL7XJDNL8JQs=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6hv/pffmzdGR2nlJa9UhCZsp8UsfmAmWb+daecPzj wjTtg37O0pZGAQ5GGTFFFnETyyzbFp72V5j+4ILMHNYmUCGMHBxCsBEorcx/M9UvPF072txxamH BGwq/7M+FDCV+tThoV305NtZMxaBtCZGhp0TKxeeM1rV+W+bYIyZVv1rsSmtKVruWof/L2Zjnqq 7NQsA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Drop Linux headers for the U-Boot ones. Signed-off-by: Caleb Connolly --- drivers/soc/qcom/smem.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 8515b8ae7777..7143856e85c3 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -3,19 +3,17 @@ * Copyright (c) 2015, Sony Mobile Communications AB. * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. */ -#include +#include +#include +#include +#include #include -#include -#include -#include -#include -#include +#include #include -#include -#include -#include +#include +#include /* * The Qualcomm shared memory system is a allocate only heap structure that * consists of one of more memory areas that can be accessed by the processors From patchwork Sun Nov 24 19:17:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845203 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841554wru; Sun, 24 Nov 2024 11:18:54 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVjsQZ/w+ciZu/ynjyejbtyzVGXQWT2vuWDhtCPtg0sFEbEU4hmkVq1BfHxyWJ5Ip740vhq5w==@linaro.org X-Google-Smtp-Source: AGHT+IED7mcjrW0V/4OYJw4IkUiPFxqnBla6KBtl2gHlzPuhtE/4yKCav0LdJ8zhqIMrjaVFmGVO X-Received: by 2002:a17:906:310b:b0:aa5:2237:67af with SMTP id a640c23a62f3a-aa522376878mr527020766b.9.1732475934306; Sun, 24 Nov 2024 11:18:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475934; cv=none; d=google.com; s=arc-20240605; b=MrMNIF4VSxizVn2UVi8Ky0zrRQLdpFgimPYYyvu2Wt2yOXPquyX5CcWPv062zEudNH QkT1k1iHfHTDzPv0F57b+uMNEFz13CSMn5NFEi2+7JGhf7MnNneiO2uMneCu9qpCCBuz 1o8htZ61r2WukZCBvW3fXeyEK/0KK4p1oO4695XRA5DUPWbWxby6fQv66Dfzl/Ym5/wt 9yv9nvvpnyu6KzFR/AnaR9oOchRhpEKe4X0VCd+3s1FGUxi7/1Vnd0LR7t7gZMufA/nk H9VllL5U0A1r8Q/IcnoRul1vq1O2G25Udlni3nMIKyKtJHmw/nZrfclk2wefJYYK5cbu /G8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=vMTNM8Wxw3yHIqudFos625gRJbJSmUlRgS4x2gT55mA=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=UCBmjOdGUas1hmEZb/6RvPrEjd6/fiYOx9ujXwaBJBMIpCFiKvUjWOO9ngUyE0Oubq uqDRvJO2ddu/xrAu4ifLjhzqeKCc1llxARI6FtzGVChF/i7N0MLeABI3oHFKqkKdXNEC jKs4wAl+YrJ2bzj+dILT9flv0bZf/XEABAwf8C3/zWAcXpCEy2abHqSg5i2qeT1Drq5i Itztf2iEMTfMN/OsIvxBz18zao7XxrbcsMIedMBOOBRPD32kJTi124plv3DYI6RjZhhH mr1EWyfwQHibkcUzTLrRZF4sTMQZxMh7/zX7V/LL4zijNqcNuD9kPCTIfozvIp4waHLp nY+w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O7cUUQMO; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id a640c23a62f3a-aa54fe8fa58si50843866b.22.2024.11.24.11.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:18:54 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O7cUUQMO; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 228A689924; Sun, 24 Nov 2024 20:18:01 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="O7cUUQMO"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D62F989924; Sun, 24 Nov 2024 20:17:58 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id F17EC8958F for ; Sun, 24 Nov 2024 20:17:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-aa545dc7105so119192466b.3 for ; Sun, 24 Nov 2024 11:17:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475874; x=1733080674; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vMTNM8Wxw3yHIqudFos625gRJbJSmUlRgS4x2gT55mA=; b=O7cUUQMOyJWM09putsxq+50IlCYzIIIzhiiGvzvQr5VCXczY0ewaTA6qTo73vy+JIS gAw+i9l4F19+lnkTGmcw8GdEhZqPJzkniV76umxZJJufEUXBPFGFad6C2W4wy/UE9OVt qguUkCGK2agvF37DtHGFtsK1DEEPy8P3UJtbXBy8dY3MGnNluVbt8dgoZ5cAWaS0I9gm 3YkQWFBSeE1wxevLppvxZf6uGOdWedQIVQjO3476m129fvQC6jcXjTvhdcoZ5ax0xujJ swG6pDwbtGohFQdmhZ6qk5YL4D3/30+pbeE/OmnJ/gOljUBlMvWwbQAj66JRDFN6ZVti 7z/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475874; x=1733080674; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vMTNM8Wxw3yHIqudFos625gRJbJSmUlRgS4x2gT55mA=; b=DUcdIP6ctWDaMMSY7uupvYd4Hs+pI6fbWC71qYEF70GxIKRZiWE9QtJawIDpLYqUso 3Ws7uasCbl7PsjBEIc0hXbRM1O9XrpGFfOPjpnT4dBI1L/BH7sqKCUbSQYGBfiWA00S4 NguEIRxbox1gwe1EK8bUkbkOadA4VECbyiFoBAvWoI3L5W9gcwJW42oei56btBGtWu93 CxCSJmiQegI/B7uuil2V6Z2GmTYPMqVKILUGiezC/4A1yZFM9RxSFiQE3dWpgWT0chgH HOWvopd1kC1X5GCu8eXGCKbuELyQISaao3rjvl/+uEIykpLgeWN2wcUsboHjGql67j35 QKdA== X-Gm-Message-State: AOJu0YwxlDzPCysPXq/L/NQ7mxWJov5NTPEwB1PJwAroRsVIU70HXXm+ jod0HKGv4JCB15qxsFRMWiGpIsPe3l9Tx8NlayJkUrXq4cdi9yqdrALDO0zoT/0= X-Gm-Gg: ASbGncvKTULPsaLtkS9JrhdH42zccDxe52A1Vbw97U0oa+hr4YvQ+0pOo739o0HWg3v fergcGeuqJQ0ev4hlvq9bJc3vCfAY4VDx2wSWVUwkawPRFgHxootioXZ+nRYezX4b/8sz/YraQM Uvqhjy3jJDQpJYUpJtgG/c8Rj2IopQyY88qkXNuvtuceZT1taKjG6dSBUXy7f5ruswTB4sse1u2 8M7GqikQdVnAFqY4S39yu5z5JP8qdGA2jacoVpVzrf+wXcMiYKg4Lvw1XsO+9Bqh5wX X-Received: by 2002:a17:906:2929:b0:aa5:1661:1949 with SMTP id a640c23a62f3a-aa516611a79mr739920066b.40.1732475874357; Sun, 24 Nov 2024 11:17:54 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:53 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:49 +0100 Subject: [PATCH 07/15] soc: qcom: smem: adjust for U-Boot MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-7-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=18900; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=6Io/+B5XjS8J5lBvCIePD30blJmgsuFGDVwPqeqtrTA=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6psXXPQLQu2+xv5si9MSveN5IzxeOLdXiDf68dJnH nufMLzoKGVhEORgkBVTZBE/scyyae1le43tCy7AzGFlAhnCwMUpABOJusHwv17iyzVp3vvfM/h/ iBjKyPv3Lk1/L3xqQci0deGeD+xUJRn+O22/1Xu1wOPXDK5TXtE/zxnViziXKzAsfv+tW9wl+NA 0PwA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Port over the smem code to U-Boot and remove socinfo. Signed-off-by: Caleb Connolly --- drivers/soc/qcom/smem.c | 320 +++++++++--------------------------------------- include/soc/qcom/smem.h | 9 +- 2 files changed, 63 insertions(+), 266 deletions(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 7143856e85c3..5166f289dfb6 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -3,17 +3,18 @@ * Copyright (c) 2015, Sony Mobile Communications AB. * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. */ +#define pr_fmt(fmt) "smem: " fmt + #include #include #include #include #include #include #include #include -#include /* * The Qualcomm shared memory system is a allocate only heap structure that * consists of one of more memory areas that can be accessed by the processors @@ -260,31 +261,23 @@ struct smem_region { }; /** * struct qcom_smem - device data for the smem device - * @dev: device pointer - * @hwlock: reference to a hwspinlock * @ptable: virtual base of partition table * @global_partition: describes for global partition when in use * @partitions: list of partitions of current processor/host * @item_count: max accepted item number - * @socinfo: platform device pointer * @num_regions: number of @regions * @regions: list of the memory regions defining the shared memory */ struct qcom_smem { - struct device *dev; - - struct hwspinlock *hwlock; - u32 item_count; - struct platform_device *socinfo; struct smem_ptable *ptable; struct smem_partition global_partition; struct smem_partition partitions[SMEM_HOST_COUNT]; unsigned num_regions; - struct smem_region regions[] __counted_by(num_regions); + struct smem_region regions[]; }; static void * phdr_to_last_uncached_entry(struct smem_partition_header *phdr) @@ -351,38 +344,9 @@ static void *cached_entry_to_item(struct smem_private_entry *e) return p - le32_to_cpu(e->size); } /* Pointer to the one and only smem handle */ -static struct qcom_smem *__smem; - -/* Timeout (ms) for the trylock of remote spinlocks */ -#define HWSPINLOCK_TIMEOUT 1000 - -/* The qcom hwspinlock id is always plus one from the smem host id */ -#define SMEM_HOST_ID_TO_HWSPINLOCK_ID(__x) ((__x) + 1) - -/** - * qcom_smem_bust_hwspin_lock_by_host() - bust the smem hwspinlock for a host - * @host: remote processor id - * - * Busts the hwspin_lock for the given smem host id. This helper is intended - * for remoteproc drivers that manage remoteprocs with an equivalent smem - * driver instance in the remote firmware. Drivers can force a release of the - * smem hwspin_lock if the rproc unexpectedly goes into a bad state. - * - * Context: Process context. - * - * Returns: 0 on success, otherwise negative errno. - */ -int qcom_smem_bust_hwspin_lock_by_host(unsigned int host) -{ - /* This function is for remote procs, so ignore SMEM_HOST_APPS */ - if (host == SMEM_HOST_APPS || host >= SMEM_HOST_COUNT) - return -EINVAL; - - return hwspin_lock_bust(__smem->hwlock, SMEM_HOST_ID_TO_HWSPINLOCK_ID(host)); -} -EXPORT_SYMBOL_GPL(qcom_smem_bust_hwspin_lock_by_host); +static struct qcom_smem *__smem __section(".data") = NULL; /** * qcom_smem_is_available() - Check if SMEM is available * @@ -429,9 +393,9 @@ static int qcom_smem_alloc_private(struct qcom_smem *smem, /* Check that we don't grow into the cached region */ alloc_size = sizeof(*hdr) + ALIGN(size, 8); if ((void *)hdr + alloc_size > cached) { - dev_err(smem->dev, "Out of memory\n"); + log_err("Out of memory\n"); return -ENOSPC; } hdr->canary = SMEM_PRIVATE_CANARY; @@ -449,9 +413,9 @@ static int qcom_smem_alloc_private(struct qcom_smem *smem, le32_add_cpu(&phdr->offset_free_uncached, alloc_size); return 0; bad_canary: - dev_err(smem->dev, "Found invalid canary in hosts %hu:%hu partition\n", + log_err("Found invalid canary in hosts %hu:%hu partition\n", le16_to_cpu(phdr->host0), le16_to_cpu(phdr->host1)); return -EINVAL; } @@ -500,29 +464,21 @@ static int qcom_smem_alloc_global(struct qcom_smem *smem, */ int qcom_smem_alloc(unsigned host, unsigned item, size_t size) { struct smem_partition *part; - unsigned long flags; int ret; if (!__smem) return -EPROBE_DEFER; if (item < SMEM_ITEM_LAST_FIXED) { - dev_err(__smem->dev, - "Rejecting allocation of static entry %d\n", item); + log_err("Rejecting allocation of static entry %d\n", item); return -EINVAL; } if (WARN_ON(item >= __smem->item_count)) return -EINVAL; - ret = hwspin_lock_timeout_irqsave(__smem->hwlock, - HWSPINLOCK_TIMEOUT, - &flags); - if (ret) - return ret; - if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) { part = &__smem->partitions[host]; ret = qcom_smem_alloc_private(__smem, part, item, size); } else if (__smem->global_partition.virt_base) { @@ -531,10 +487,8 @@ int qcom_smem_alloc(unsigned host, unsigned item, size_t size) } else { ret = qcom_smem_alloc_global(__smem, item, size); } - hwspin_unlock_irqrestore(__smem->hwlock, &flags); - return ret; } EXPORT_SYMBOL_GPL(qcom_smem_alloc); @@ -660,9 +614,9 @@ static void *qcom_smem_get_private(struct qcom_smem *smem, return ERR_PTR(-ENOENT); invalid_canary: - dev_err(smem->dev, "Found invalid canary in hosts %hu:%hu partition\n", + log_err("Found invalid canary in hosts %hu:%hu partition\n", le16_to_cpu(phdr->host0), le16_to_cpu(phdr->host1)); return ERR_PTR(-EINVAL); } @@ -796,63 +750,8 @@ phys_addr_t qcom_smem_virt_to_phys(void *p) return 0; } EXPORT_SYMBOL_GPL(qcom_smem_virt_to_phys); -/** - * qcom_smem_get_soc_id() - return the SoC ID - * @id: On success, we return the SoC ID here. - * - * Look up SoC ID from HW/SW build ID and return it. - * - * Return: 0 on success, negative errno on failure. - */ -int qcom_smem_get_soc_id(u32 *id) -{ - struct socinfo *info; - - info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); - if (IS_ERR(info)) - return PTR_ERR(info); - - *id = __le32_to_cpu(info->id); - - return 0; -} -EXPORT_SYMBOL_GPL(qcom_smem_get_soc_id); - -/** - * qcom_smem_get_feature_code() - return the feature code - * @code: On success, return the feature code here. - * - * Look up the feature code identifier from SMEM and return it. - * - * Return: 0 on success, negative errno on failure. - */ -int qcom_smem_get_feature_code(u32 *code) -{ - struct socinfo *info; - u32 raw_code; - - info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); - if (IS_ERR(info)) - return PTR_ERR(info); - - /* This only makes sense for socinfo >= 16 */ - if (__le32_to_cpu(info->fmt) < SOCINFO_VERSION(0, 16)) - return -EOPNOTSUPP; - - raw_code = __le32_to_cpu(info->feature_code); - - /* Ensure the value makes sense */ - if (raw_code > SOCINFO_FC_INT_MAX) - raw_code = SOCINFO_FC_UNKNOWN; - - *code = raw_code; - - return 0; -} -EXPORT_SYMBOL_GPL(qcom_smem_get_feature_code); - static int qcom_smem_get_sbl_version(struct qcom_smem *smem) { struct smem_header *header; __le32 *versions; @@ -873,10 +772,9 @@ static struct smem_ptable *qcom_smem_get_ptable(struct qcom_smem *smem) return ERR_PTR(-ENOENT); version = le32_to_cpu(ptable->version); if (version != 1) { - dev_err(smem->dev, - "Unsupported partition header version %d\n", version); + log_err("Unsupported partition header version %d\n", version); return ERR_PTR(-EINVAL); } return ptable; } @@ -906,42 +804,42 @@ static struct smem_partition_header * qcom_smem_partition_header(struct qcom_smem *smem, struct smem_ptable_entry *entry, u16 host0, u16 host1) { struct smem_partition_header *header; - u32 phys_addr; + u64 phys_addr; u32 size; phys_addr = smem->regions[0].aux_base + le32_to_cpu(entry->offset); - header = devm_ioremap_wc(smem->dev, phys_addr, le32_to_cpu(entry->size)); + header = (void *)phys_addr; // devm_ioremap_wc() if (!header) return NULL; if (memcmp(header->magic, SMEM_PART_MAGIC, sizeof(header->magic))) { - dev_err(smem->dev, "bad partition magic %4ph\n", header->magic); + log_err("bad partition magic %4ph\n", header->magic); return NULL; } if (host0 != le16_to_cpu(header->host0)) { - dev_err(smem->dev, "bad host0 (%hu != %hu)\n", - host0, le16_to_cpu(header->host0)); + log_err("bad host0 (%hu != %hu)\n", + host0, le16_to_cpu(header->host0)); return NULL; } if (host1 != le16_to_cpu(header->host1)) { - dev_err(smem->dev, "bad host1 (%hu != %hu)\n", - host1, le16_to_cpu(header->host1)); + log_err("bad host1 (%hu != %hu)\n", + host1, le16_to_cpu(header->host1)); return NULL; } size = le32_to_cpu(header->size); if (size != le32_to_cpu(entry->size)) { - dev_err(smem->dev, "bad partition size (%u != %u)\n", + log_err("bad partition size (%u != %u)\n", size, le32_to_cpu(entry->size)); return NULL; } if (le32_to_cpu(header->offset_free_uncached) > size) { - dev_err(smem->dev, "bad partition free uncached (%u > %u)\n", + log_err("bad partition free uncached (%u > %u)\n", le32_to_cpu(header->offset_free_uncached), size); return NULL; } @@ -956,9 +854,9 @@ static int qcom_smem_set_global_partition(struct qcom_smem *smem) bool found = false; int i; if (smem->global_partition.virt_base) { - dev_err(smem->dev, "Already found the global partition\n"); + log_err("Already found the global partition\n"); return -EINVAL; } ptable = qcom_smem_get_ptable(smem); @@ -981,9 +879,9 @@ static int qcom_smem_set_global_partition(struct qcom_smem *smem) } } if (!found) { - dev_err(smem->dev, "Missing entry for global partition\n"); + log_err("Missing entry for global partition\n"); return -EINVAL; } header = qcom_smem_partition_header(smem, entry, @@ -1030,14 +928,14 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host) else continue; if (remote_host >= SMEM_HOST_COUNT) { - dev_err(smem->dev, "bad host %u\n", remote_host); + log_err("bad host %u\n", remote_host); return -EINVAL; } if (smem->partitions[remote_host].virt_base) { - dev_err(smem->dev, "duplicate host %u\n", remote_host); + log_err("duplicate host %u\n", remote_host); return -EINVAL; } header = qcom_smem_partition_header(smem, entry, host0, host1); @@ -1058,12 +956,12 @@ static int qcom_smem_map_toc(struct qcom_smem *smem, struct smem_region *region) { u32 ptable_start; /* map starting 4K for smem header */ - region->virt_base = devm_ioremap_wc(smem->dev, region->aux_base, SZ_4K); + region->virt_base = (void *)region->aux_base; ptable_start = region->aux_base + region->size - SZ_4K; /* map last 4k for toc */ - smem->ptable = devm_ioremap_wc(smem->dev, ptable_start, SZ_4K); + smem->ptable = (struct smem_ptable *)(u64)ptable_start; if (!region->virt_base || !smem->ptable) return -ENOMEM; @@ -1071,54 +969,29 @@ static int qcom_smem_map_toc(struct qcom_smem *smem, struct smem_region *region) } static int qcom_smem_map_global(struct qcom_smem *smem, u32 size) { - u32 phys_addr; + u64 phys_addr; phys_addr = smem->regions[0].aux_base; smem->regions[0].size = size; - smem->regions[0].virt_base = devm_ioremap_wc(smem->dev, phys_addr, size); + smem->regions[0].virt_base = (void *)phys_addr; if (!smem->regions[0].virt_base) return -ENOMEM; return 0; } -static int qcom_smem_resolve_mem(struct qcom_smem *smem, const char *name, - struct smem_region *region) -{ - struct device *dev = smem->dev; - struct device_node *np; - struct resource r; - int ret; - - np = of_parse_phandle(dev->of_node, name, 0); - if (!np) { - dev_err(dev, "No %s specified\n", name); - return -EINVAL; - } - - ret = of_address_to_resource(np, 0, &r); - of_node_put(np); - if (ret) - return ret; - - region->aux_base = r.start; - region->size = resource_size(&r); - - return 0; -} - -static int qcom_smem_probe(struct platform_device *pdev) +int qcom_smem_init(void) { struct smem_header *header; - struct reserved_mem *rmem; struct qcom_smem *smem; - unsigned long flags; int num_regions; - int hwlock_id; + fdt_size_t reg_size = 0; + u32 phandle; + ofnode node, mem_node; u32 version; u32 size; int ret; int i; @@ -1126,85 +999,58 @@ static int qcom_smem_probe(struct platform_device *pdev) if (__smem) return 0; num_regions = 1; - if (of_property_present(pdev->dev.of_node, "qcom,rpm-msg-ram")) - num_regions++; - smem = devm_kzalloc(&pdev->dev, struct_size(smem, regions, num_regions), + node = ofnode_by_compatible(ofnode_root(), "qcom,smem"); + if (!ofnode_valid(node)) + return -ENODEV; + + if (ofnode_has_property(node, "memory-region")) { + ofnode_read_u32(node, "memory-region", &phandle); + mem_node = ofnode_get_by_phandle(phandle); + } else { + mem_node = node; + } + + smem = kzalloc(sizeof(struct smem_region) * num_regions + + sizeof(struct qcom_smem), GFP_KERNEL); - if (!smem) + if (!smem) { + log_err("Failed to allocate memory for smem\n"); return -ENOMEM; + } - smem->dev = &pdev->dev; smem->num_regions = num_regions; - rmem = of_reserved_mem_lookup(pdev->dev.of_node); - if (rmem) { - smem->regions[0].aux_base = rmem->base; - smem->regions[0].size = rmem->size; - } else { - /* - * Fall back to the memory-region reference, if we're not a - * reserved-memory node. - */ - ret = qcom_smem_resolve_mem(smem, "memory-region", &smem->regions[0]); - if (ret) - return ret; + smem->regions[0].aux_base = ofnode_get_addr(mem_node); + reg_size = ofnode_get_size(mem_node); + if (smem->regions[0].aux_base == FDT_ADDR_T_NONE) { + log_err("Failed to get base address\n"); + return -EINVAL; } - - if (num_regions > 1) { - ret = qcom_smem_resolve_mem(smem, "qcom,rpm-msg-ram", &smem->regions[1]); - if (ret) - return ret; - } - + smem->regions[0].size = reg_size; ret = qcom_smem_map_toc(smem, &smem->regions[0]); - if (ret) + if (ret) { + log_err("Failed to map toc\n"); return ret; + } for (i = 1; i < num_regions; i++) { - smem->regions[i].virt_base = devm_ioremap_wc(&pdev->dev, - smem->regions[i].aux_base, - smem->regions[i].size); - if (!smem->regions[i].virt_base) { - dev_err(&pdev->dev, "failed to remap %pa\n", &smem->regions[i].aux_base); - return -ENOMEM; - } + smem->regions[i].virt_base = (void *)smem->regions[i].aux_base; } header = smem->regions[0].virt_base; if (le32_to_cpu(header->initialized) != 1 || le32_to_cpu(header->reserved)) { - dev_err(&pdev->dev, "SMEM is not initialized by SBL\n"); + log_err("SMEM is not initialized by SBL\n"); return -EINVAL; } - hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); - if (hwlock_id < 0) { - if (hwlock_id != -EPROBE_DEFER) - dev_err(&pdev->dev, "failed to retrieve hwlock\n"); - return hwlock_id; - } - - smem->hwlock = hwspin_lock_request_specific(hwlock_id); - if (!smem->hwlock) - return -ENXIO; - - ret = hwspin_lock_timeout_irqsave(smem->hwlock, HWSPINLOCK_TIMEOUT, &flags); - if (ret) - return ret; size = readl_relaxed(&header->available) + readl_relaxed(&header->free_offset); - hwspin_unlock_irqrestore(smem->hwlock, &flags); version = qcom_smem_get_sbl_version(smem); - /* - * smem header mapping is required only in heap version scheme, so unmap - * it here. It will be remapped in qcom_smem_map_global() when whole - * partition is mapped again. - */ - devm_iounmap(smem->dev, smem->regions[0].virt_base); switch (version >> 16) { case SMEM_GLOBAL_PART_VERSION: ret = qcom_smem_set_global_partition(smem); if (ret < 0) @@ -1215,63 +1061,19 @@ static int qcom_smem_probe(struct platform_device *pdev) qcom_smem_map_global(smem, size); smem->item_count = SMEM_ITEM_COUNT; break; default: - dev_err(&pdev->dev, "Unsupported SMEM version 0x%x\n", version); + log_err("Unsupported SMEM version 0x%x\n", version); return -EINVAL; } BUILD_BUG_ON(SMEM_HOST_APPS >= SMEM_HOST_COUNT); ret = qcom_smem_enumerate_partitions(smem, SMEM_HOST_APPS); - if (ret < 0 && ret != -ENOENT) + if (ret < 0 && ret != -ENOENT) { + log_err("Failed to enumerate partitions\n"); return ret; + } __smem = smem; - smem->socinfo = platform_device_register_data(&pdev->dev, "qcom-socinfo", - PLATFORM_DEVID_NONE, NULL, - 0); - if (IS_ERR(smem->socinfo)) - dev_dbg(&pdev->dev, "failed to register socinfo device\n"); - return 0; } - -static void qcom_smem_remove(struct platform_device *pdev) -{ - platform_device_unregister(__smem->socinfo); - - hwspin_lock_free(__smem->hwlock); - __smem = NULL; -} - -static const struct of_device_id qcom_smem_of_match[] = { - { .compatible = "qcom,smem" }, - {} -}; -MODULE_DEVICE_TABLE(of, qcom_smem_of_match); - -static struct platform_driver qcom_smem_driver = { - .probe = qcom_smem_probe, - .remove_new = qcom_smem_remove, - .driver = { - .name = "qcom-smem", - .of_match_table = qcom_smem_of_match, - .suppress_bind_attrs = true, - }, -}; - -static int __init qcom_smem_init(void) -{ - return platform_driver_register(&qcom_smem_driver); -} -arch_initcall(qcom_smem_init); - -static void __exit qcom_smem_exit(void) -{ - platform_driver_unregister(&qcom_smem_driver); -} -module_exit(qcom_smem_exit) - -MODULE_AUTHOR("Bjorn Andersson "); -MODULE_DESCRIPTION("Qualcomm Shared Memory Manager"); -MODULE_LICENSE("GPL v2"); diff --git a/include/soc/qcom/smem.h b/include/soc/qcom/smem.h index f946e3beca21..a955db08c0f0 100644 --- a/include/soc/qcom/smem.h +++ b/include/soc/qcom/smem.h @@ -3,18 +3,13 @@ #define __QCOM_SMEM_H__ #define QCOM_SMEM_HOST_ANY -1 +int qcom_smem_init(void); + bool qcom_smem_is_available(void); int qcom_smem_alloc(unsigned host, unsigned item, size_t size); void *qcom_smem_get(unsigned host, unsigned item, size_t *size); int qcom_smem_get_free_space(unsigned host); -phys_addr_t qcom_smem_virt_to_phys(void *p); - -int qcom_smem_get_soc_id(u32 *id); -int qcom_smem_get_feature_code(u32 *code); - -int qcom_smem_bust_hwspin_lock_by_host(unsigned int host); - #endif From patchwork Sun Nov 24 19:17:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845204 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841606wru; Sun, 24 Nov 2024 11:19:04 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUHBbSoAeydfVcWw9t1KH0LkJBs8j2s7N45MR0fJm3CEWV5xOiZ64s9PqqCk6/6hIAWqMBzwA==@linaro.org X-Google-Smtp-Source: AGHT+IFPJx6t1PtmQ/uR4NflqLSC0bgY38GIDLyJ8qxtpAZT4OrNB8seG46KD1Ggv9Mi6cbgC0DU X-Received: by 2002:a05:6402:1e89:b0:5cf:dcd4:1277 with SMTP id 4fb4d7f45d1cf-5d0205a7f3bmr10517179a12.7.1732475944696; Sun, 24 Nov 2024 11:19:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475944; cv=none; d=google.com; s=arc-20240605; b=CrvkiWHs9zmXx1X1OnGLSGbA66h8EOn/5rP6xOJ25BNmp1Jm2UmVROh5j3VMsCvrJA uM+dJogTIbUaCfWgoMpfJylety8w9YO/uLJIUKvStsFkUIy3SQcqgZGbh0WHhFDlrvc8 84KAKtE/Qbrv9QvDdMadGnc3AFN/t1ErZxwl/BCzcWYpdc3K6a8uOETxihmMyYwiRwDk ayWKIWkfG/Ag7IWfNgOobWUrz+s6+qUrUjcZhGqF/RbVPnMiY1hnExeAazdHym6AaBEZ DTPyWc7J4mPKYCnXGS7vKTvwOQVFsou8LGFupEIkyrkga7IETKZ1b2EGKCsAOy9QbcOM eESw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=XBM2x2KNEvKiAkDcaHJnKhElyqHsy4crCo5njXmLu/M=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=MQG0EOYBkP2fJ9gl0ADaWGcVj7TOOn3b4IFXvQ8jkUc2Szyu5Pxpg03cdi7q2Zu0PP sxCg2XT0TiimvSVutivHc4BpUQNiMmNfF3UjfLwBJyVljYILZaS8j+Pv79rya7RLpMcm ceY3YuzBmeZ1yD48EGjFYQDkC3Ng/tEXf8X/pyqj/aW1sKw9Y2UB46rWw/7JJGQlSXPt TL+88Y/iylipnc4wFcw7c7CRWMrlHMa3nMJXh1kK7WcgdBIe1f3TJajjEfZqRHp33LUp LMbGIM2qnHbqtBMhtuEMWHKra3kboHnpDy/IMpmPXVFBaGYrGagnmm1u+yJdzNpU7xJm WLBg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cKHkkSIl; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id 4fb4d7f45d1cf-5d01d3adcdcsi3801984a12.15.2024.11.24.11.19.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:19:04 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cKHkkSIl; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7A90F89922; Sun, 24 Nov 2024 20:18:02 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="cKHkkSIl"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5BF0D89812; Sun, 24 Nov 2024 20:18:00 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E76178956D for ; Sun, 24 Nov 2024 20:17:55 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-5cfaa02c716so5053662a12.3 for ; Sun, 24 Nov 2024 11:17:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475875; x=1733080675; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XBM2x2KNEvKiAkDcaHJnKhElyqHsy4crCo5njXmLu/M=; b=cKHkkSIlbEcCcO5ylzRZ/DNUWKOlwhprhkosi1wfXDhAD8jdphI528I9sz2gXMFUuF y0dk5A+bY8+XZJJZ4zlSbTDmIyi/YcRfwcq7yxrb8B45iP3nsIl/8CE2xZJrhXTOqqoe V4N3VcugmiebRJ8kkBRldi0Yv4INfngegpi/h/SVSEoMqxFW8F+7Ad2yLZdvMXSO8cc3 /JZi7TstTsqn/BSx4mPm5C6ZxJdI5A3E6FlCRQp4jtAVU3uy4cITTN2PYV37Q+51Hv7Z ztoIvw45awm4LPJHeI7RZ4q4B+Bw5V0XTIqq5ph3kGrpc4HIbYKQc7DA/J4jwuJ6qpwp iyjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475875; x=1733080675; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XBM2x2KNEvKiAkDcaHJnKhElyqHsy4crCo5njXmLu/M=; b=c25GPPBLQluOqyaJ2ki8q2RNN3VUdHMb8l6uM4Ote7WwOZaDicPocoFSrndCsktyEW rqOLfWq8ypapxQGrely60FAZvmGajwhtlwEEVCWW7HKDkryCmRX1ZcoQDOT5D9ebfWXr wi3V9wccCUWA4hbWpy/X+17bx+uQGs7u84xobKWMhEz7SNmyEC/9LF8xaNnKjctwUpZM 4RQYBHUTscw57As0oHOvnhGCbM/hkigUNrvOHeKRGDg+/6r3od3tXHEmYycxZ4JOuyEt sbEKmZw6iqgwR5idQ6Y4px+3ECd0U0tKquvX8u5nIiLNYLqKnXwl5mJ5JbOPntkuJgmz eiFQ== X-Gm-Message-State: AOJu0YwPLdKhtY/16oLRA32TfDrs1Wjl/gZutTkH3mNELUFfXePWMqny +4rgcoAcfPjck0MNxGgewEUoCfxHzO7xo44o3s+6DuitHsEzc0jyoujbQo66fBM= X-Gm-Gg: ASbGncsTIkjt6F+vF1CkbgG8z8YG+LQeg5QrKL41SC1d57+upc9WWcGIIT40sgnsotk gQxnmkCYzHee8NvLfEiYURQk8BUT0TTY3GKlUhfHZbb/1TlnBMWdZaNvnwfNNhbZhVgP+JBKuDT ah2XDNQCgsp7jSZuU9N9nBl6cqJkxvqPbrBlqegOFMoW1+5y7XsoCwHDyBofTDIEmCGpP7L3+dE CyLSeKX3/Ver0PdQEKOnVvXaHVdfEpvClgK2PoDecguiq4kRhs1bFPgTO5wWYT1OO2/ X-Received: by 2002:a17:907:ab5:b0:a9e:b2da:b4a3 with SMTP id a640c23a62f3a-aa509bc13ffmr768672666b.42.1732475875492; Sun, 24 Nov 2024 11:17:55 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:54 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:50 +0100 Subject: [PATCH 08/15] soc: qcom: smem: get serial number from socinfo MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-8-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1975; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=WUGycCEx0AhKcEQDcuUT58urz11+dO8c/zjsD9E5QQw=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6pt7mDgCNy40SeySYe4TMTr241JwefpMTk5Nlw3xJ 9dsbQ3sKGVhEORgkBVTZBE/scyyae1le43tCy7AzGFlAhnCwMUpABPpV2b4w8ugW6gUukenuZJr zhqtqIcLLt2f7ZBxqlnoOWN28zMtJUaGZfFti+7mfniyr3bm9k+5LWkstbd+uPBODPLkOfFqX9h CWQA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Implement socinfo support to fetch the serial number if available. Signed-off-by: Caleb Connolly --- drivers/soc/qcom/smem.c | 25 +++++++++++++++++++++++++ include/soc/qcom/smem.h | 1 + 2 files changed, 26 insertions(+) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 5166f289dfb6..5570c5c907ad 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -13,8 +13,10 @@ #include #include #include #include +#include +#include /* * The Qualcomm shared memory system is a allocate only heap structure that * consists of one of more memory areas that can be accessed by the processors @@ -982,8 +984,31 @@ static int qcom_smem_map_global(struct qcom_smem *smem, u32 size) return 0; } +int qcom_socinfo_init(void) +{ + struct socinfo *info; + size_t item_size; + char buf[32] = { 0 }; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, + &item_size); + if (IS_ERR(info)) { + log_err("Couldn't find socinfo: %ld\n", PTR_ERR(info)); + return PTR_ERR(info); + } + + if (offsetof(struct socinfo, serial_num) <= item_size) { + snprintf(buf, sizeof(buf), "%u", le32_to_cpu(info->serial_num)); + env_set("serial#", buf); + } else { + return -ENOENT; + } + + return 0; +} + int qcom_smem_init(void) { struct smem_header *header; struct qcom_smem *smem; diff --git a/include/soc/qcom/smem.h b/include/soc/qcom/smem.h index a955db08c0f0..755003807dba 100644 --- a/include/soc/qcom/smem.h +++ b/include/soc/qcom/smem.h @@ -4,8 +4,9 @@ #define QCOM_SMEM_HOST_ANY -1 int qcom_smem_init(void); +int qcom_socinfo_init(void); bool qcom_smem_is_available(void); int qcom_smem_alloc(unsigned host, unsigned item, size_t size); void *qcom_smem_get(unsigned host, unsigned item, size_t *size); From patchwork Sun Nov 24 19:17:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845206 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841688wru; Sun, 24 Nov 2024 11:19:23 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUztWCuKGWfzjc7hG1fB/J5vgwGukQdrqkDf9lDdNw7ytnmSl7AEWB7fv4CNsT8L/wLQy9Bjg==@linaro.org X-Google-Smtp-Source: AGHT+IHsA2U0hYjYRVG5dO9qT2ig/X9SDbnTiyIKk3pJUrXtAaCnVzlCZDF1NJBPwqaYWJCaywQH X-Received: by 2002:a17:906:3101:b0:a8d:439d:5c3c with SMTP id a640c23a62f3a-aa50990b09emr663317766b.8.1732475963612; Sun, 24 Nov 2024 11:19:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475963; cv=none; d=google.com; s=arc-20240605; b=dZIL0E5P9YWFlv7IINEcda5WDJmjQx0I/bj3+Jn6/djvzSaZ357c3KIZq/OynI3BFE 0ZqNvjfTnh8UI5cshKULPgk8GCpcUM3K1FgrejE61Mo2JpvHKhLnJEV5fPDlaLqv4MKM hnwlv6Pe6YX3iKQU7ukHsSiIFewebh5xAYKUNe5+icf7NSgqxujAuEM51sXVPSskVXS/ Zr64oRv2BVg3XSYVs3ApHvbdMVRlasq92HWuK0A5gy1N9F+44YPF5j9BhFXEmUrW2Ryj Fe8lLPuQpbPXI4VGwnKc9EV7SuEqDbHOfgaWaVIqEMl9zHZbgo1N5e09mp9BL23AVJon Qv0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=fbZv7I51Fvc8FujdGK3KkOlLr4aE65D95KWDsJk/+u4=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=bRaguviSsCoBs2Kub61xx8ZgEMXtgqFMWeF+sD+N5GaSa+oSNrdgO1WWrsVBoYW89x twbBXaxuL64QY+V9yMedPX3W/jVAILXfVFp+09gqHNoZJ6s20LiA+eZiAoqPpap4nhyN 7EWSIpWnDeNQ/VEs2llqG0s7pPRrbFK3zqOrynGRfApeX/dFUZ4Rb3xkPYq+9ZB1U9/w 8ZVfcXvOL+aVSwVW/shm62y3r6fK2MrRMweEC5BGF9P1ygdpok1MiqamvlFKsYzmLvVQ yYmpm35XdIkioflFnpwO/qAu5RJqX/aXOJEEqGvyExvIctdFcJrXXLTOA2CSPEP77K9s QRQA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Et873+BR; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id a640c23a62f3a-aa50b55a502si383206766b.585.2024.11.24.11.19.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:19:23 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Et873+BR; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C3154899BE; Sun, 24 Nov 2024 20:18:03 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Et873+BR"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7084E899AC; Sun, 24 Nov 2024 20:18:01 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9DDC289986 for ; Sun, 24 Nov 2024 20:17:57 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-aa549f2fa32so80085566b.0 for ; Sun, 24 Nov 2024 11:17:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475877; x=1733080677; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fbZv7I51Fvc8FujdGK3KkOlLr4aE65D95KWDsJk/+u4=; b=Et873+BRKrbyghp5Sn1l8z40o5B3SacSbV3RWmsPfshyK2P5/r5jIj5pIzsFuTjGOx ety1JVyhPqUP2pab31Hjs2XtETxL2pTAwnJy9eZl32VmGpIDRAupfI/HWROd/aAb48tn dnfhAg/y0yDGnKZT1suBtF5d4ly3B973nDQVVdi3wHEZEVMTBaAR9GoxrAz31ZGIxdU2 NBRd+Oy8NqB+rwRXtZJC5Vhm36U1SXo20u4Yuv/bVgObLoKvsulvCWSgc6fCtzUYYe4x a8NVT9DwDUjs5ZHbL0NGX3vFKkRC4t5EGzjwZw2+cVs/+n381jLxKes6hMT3KQa2ikdp pTuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475877; x=1733080677; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fbZv7I51Fvc8FujdGK3KkOlLr4aE65D95KWDsJk/+u4=; b=h5Qs5Xytq+M6wc6KsVqc1kgZ6a7VKSyNsbq2r1JLNnHIMcXrne0mk5tkJI7kubZpQu e2tK2P9YpQFNcFuujQHpu7dTodQTdj88mYqDVHmr02SW0DocDSn27h4Hj/s8YzKr0dHY jHI+Zz5GEWwkdKXPig39ObB/OxaBzFS8ot1DpjiuMnkF36UItaQEc/AKO18c63QYCLmo 8GSi0smbmyZaV21i3EQCr8xmhwE+ZG7ctvb9X8wTRj768SwLOwioeIkbViXeUZy6attD 60jXovgCiAFMouILYtfw1YGk8n/hb+1deh6xNs7uCY7kPKaumx5sYqxmR33TMFjf6zvt zw+Q== X-Gm-Message-State: AOJu0YzepB3pbU7Aw9iBP2SUCXyqxgi6dJ1SY5mW6AWaOGC2l0koiLu7 yNoRpcB/43JF/l8ScUoLHMZBzGFG/aXfUZMGt2M4mGJj59nuT4mmM0rhiRArid8= X-Gm-Gg: ASbGncsuUbNu3MAaVoogFTV0/EZkJ2bA2asJUixP3f7FnGlwmhz9F/2Jv99k4wcD/mm 6GSwsJempIZrv9mMEPZpAAl1hThZAT3Wz6Ju7OFB6mqQwfAMqCgU7Ylr2xWYx5jhQvBE/Wu7aVC Aj/guDyHudR0W9QPC5vHInFltoL1t8bmkKC2yrFTnI5jL5V8Wsh1tgPaedeUy5s90/OhWIyRKnI CyNviteDcdzI5Vcr33a/Qyd5DKzH1UiXwPuTsfiZkOTVeleBnVCWjAgMIRj/FyD6rVx X-Received: by 2002:a17:906:9c2:b0:aa5:297a:429f with SMTP id a640c23a62f3a-aa5297a431cmr640441866b.51.1732475877104; Sun, 24 Nov 2024 11:17:57 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:55 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:51 +0100 Subject: [PATCH 09/15] soc: qcom: smem: stub functions MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-9-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1326; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=0Q7QWrKEhKPoIqHJdNt08/uJsx0eh4DAgJs/Cmym8Yc=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6psnKzhEp80KPNjBdqWQ+67q+oS312dwLJyRd0j1e u+5qdusOkpZGAQ5GGTFFFnETyyzbFp72V5j+4ILMHNYmUCGMHBxCsBEtGwZ/icx90b/enFIYXXN vX3C7dJumxsWe3p5qn88suf+vqiVwicY/kdzsGZxbW75M//v6tmP5h83U/Lp2SD9ZJZGwey5GxZ I+O4AAA== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Allow smem to be optional for Qualcomm platforms by providing stub functions. Signed-off-by: Caleb Connolly --- include/soc/qcom/smem.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/soc/qcom/smem.h b/include/soc/qcom/smem.h index 755003807dba..586432412eb8 100644 --- a/include/soc/qcom/smem.h +++ b/include/soc/qcom/smem.h @@ -1,16 +1,36 @@ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __QCOM_SMEM_H__ #define __QCOM_SMEM_H__ +#include +#include + #define QCOM_SMEM_HOST_ANY -1 +#if defined(CONFIG_QCOM_SMEM) int qcom_smem_init(void); int qcom_socinfo_init(void); bool qcom_smem_is_available(void); int qcom_smem_alloc(unsigned host, unsigned item, size_t size); void *qcom_smem_get(unsigned host, unsigned item, size_t *size); int qcom_smem_get_free_space(unsigned host); +#else +static int qcom_smem_init(void) { return -ENOSYS; } + +static bool qcom_smem_is_available(void) { return false; } +int qcom_smem_alloc(unsigned host, unsigned item, size_t size) +{ + return -ENOSYS; +} + +void *qcom_smem_get(unsigned host, unsigned item, size_t *size) +{ + return ERR_PTR(-ENOSYS); +} + +int qcom_smem_get_free_space(unsigned host); +#endif #endif From patchwork Sun Nov 24 19:17:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845205 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841648wru; Sun, 24 Nov 2024 11:19:14 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVyJ1zv7cgQ9tucmmimaVSWfZCJ8kEut3wQUZTx5iev8FgPCUs3LRLF3NGcXkZL5B6XR38axw==@linaro.org X-Google-Smtp-Source: AGHT+IEvbIruiVSba67dj9x3E+TEJOmis8ul6RV68saNTKfRcr/9a10T+91XcPhcYO48zMUUvhBx X-Received: by 2002:a17:906:292a:b0:aa5:1ccb:79b1 with SMTP id a640c23a62f3a-aa51ccb7a26mr804088366b.38.1732475954031; Sun, 24 Nov 2024 11:19:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475954; cv=none; d=google.com; s=arc-20240605; b=DUrgzeExEE3xMqVRxqOQMqLjO2DR3FFs5a/9Lgywb/6U2k2g99Ex2mEd9z+5+Jl+2e cA7/RwTNsgRbQutK5FQRNumxEqzjBMvOp3FUG3EksQLi3xmAbtWyDzjsJzdV46OKhOR9 pbBI/OVkSxfvZB+1qsDh7JDBEbs6WNz+R5DjVoNw0zB55TyWxSf7S5JxdbbMrArA0P8/ 71R4vlv4q+pnUEHH5XBJ86MPusEl7agT9YO9yOq21dyLgClsPLsFUw5LLCspsHEpX3JW 6ZyEm5cB53FaYav9KvPorr2K5Dy1nvIzCFCrAgBCHWIg1qk/9Vc41XibrA6PxE84HNVe HjVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=bz0DcyHRx0hkL1S8HbghMdXXb2wIen88j5kPHngewYA=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=Gb/HfMc30CCmkoUvSt30AC3hUvRyb1rT4/alt3aQFfCg81VVWSkuAAgAbYqy8yMNhL 1bDQgGqOPEydM+DnpPFE6iciyxuG/E9k3hGS9X7ATxI1ppez5wiVYEbIe5FDKeDIqB7g tXq1mogyw4NxBcG0RQ4C2o5QR5+FuwpZmg9L2AnjSq0zNVEMis/xgkfYdm4i3B+JL0l9 sG56daYalVcKa/MiGdJKVjdqc/YC1UlXKmeT5MwrSrnx5VyZLPI9wB/wZ7ay6Iu3SxDm SeCKTHtC1/sQQ96okU9W/PBASdZnvx4eh7PQSwGdbMO1mjgZ1+q08eYayHki4kjr1TJ9 18ew==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h01RwCfP; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id a640c23a62f3a-aa511f62302si382925666b.392.2024.11.24.11.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:19:14 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h01RwCfP; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CDCB6899AC; Sun, 24 Nov 2024 20:18:02 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="h01RwCfP"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8FECA895B2; Sun, 24 Nov 2024 20:18:00 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8DDEC8976D for ; Sun, 24 Nov 2024 20:17:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-a9ed49ec0f1so601870166b.1 for ; Sun, 24 Nov 2024 11:17:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475878; x=1733080678; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bz0DcyHRx0hkL1S8HbghMdXXb2wIen88j5kPHngewYA=; b=h01RwCfPFDHTWV22o9UFcWxWSCHimU2TpqMUEZmAe6wRWC7CIwBxQT02JSeiV2MsYC UIsMwP4nL5hbwuJ8aecrJbftVU7x2cT9Swwc6jVsZHeGo/1yq3NgUM3KWNAebPJJM1O2 Q8OYnlvlQuXtRk7eZkb29r9yDiU/bZLpyPxk5Ie26iS6+G1gp0n2ZshA8N83khcEnH00 L8JMO5rMk92FQtQBCciKy35pLEkcDIDCDOmzVa+sDpNGEirTLdYiK6eKsg3e7vtzkuYD OPdyjuQ3MJ+iiKsG+iAlpMDRahCabSMfq7WmiJgPFT1dncTRhtMxEKjTpCdqefcQdPCo XuoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475878; x=1733080678; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bz0DcyHRx0hkL1S8HbghMdXXb2wIen88j5kPHngewYA=; b=ezxb8DquBajkoHS8ZAYxjLUsxc7mj0cLENzQevwiAV3lrh9sd0zrAh4UqI/tHzbcsL yIsDY9ZohTj7WMu1/n1sjLr/iESn3vcTvU1FEzshlL2dmEK130f35fxSWnAB5r/tAMam 5rc4DeRxmZWVpou9cmZvWE3lzgvQ84KAPFqtTKVYuu7N9uhjOigdjjbyPIECkdkfgeed h8HmcLcM+iWiVSZO8NGqRTaA6usbLud39Rfqwch5yUXOZsctOVfHrd79Xayv/Xumd1VR NYS9sm+4ppFvK2tWWap+7J2pk//GgOc8FxF0eQ/cHXY8A0vZZx+NJ/ppIPzpSFZ1UPZT aOZQ== X-Gm-Message-State: AOJu0YxTmxzLtfm7jKWSJ1qiuAQQe/BUTko1rigfAaHN1iCCPoEMnEWk Yl5/kwTv6SQM0l3fz4J+GX4Cf+4NqhzNTE4nD9njgyn+ZQZ8Xhedj50NEIGEL58= X-Gm-Gg: ASbGncvalgzdKYGhum+Ks55zeOs01cm8QWMjI1q1g1y06/TuseKeRGH9Qzghp+U/zY4 R2vPloiTNKd6vhZrHle2LwRQ1ZsuN/jsm0Xlw/lv9WoYyBCun+sqhq9uKiPwL1UeZtSKo4Cd+Br r+PgfirhNMHooVgH4kIgBD/AmILsuFHFqGH6UGWF47PupIxM2le1MVWCjl0nFQ/1fSuezCwRm7X ljzDulpGECVorr80IyHyPmmDbLD1QHHmIMnhyfP1LZt6m2GgdYdNUHpJtqGaNjwbwmQ X-Received: by 2002:a17:907:7807:b0:aa5:38c5:c1c8 with SMTP id a640c23a62f3a-aa538c5c29amr372977166b.19.1732475877967; Sun, 24 Nov 2024 11:17:57 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:57 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:52 +0100 Subject: [PATCH 10/15] soc: qcom: smem: add build infra MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-10-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1419; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=rqzJL5uV+UGped6diF7bdsE/hCg6rNpz2vZE9yG+F80=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6puSen/ufbj/a/GCB9nhPyyT18Y3L9NKkWduzu7Wa 0r4YHi5o4SFQZCDQVZMkUX8xDLLprWX7TW2L7gAM4eVCWQIAxenAExk33mGH6/utnpKcqYyXVKa c3n5yelzb3G0J07On81il3X035vQDQz/c7L1FG9+kz53/HfzEm2TQ+or9om9eWwwp+H/2ZzO/Ip HEgA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Build the new SMEM driver port, and select it when ARCH_SNAPDRAGON is selected, since it will be a hard dependency for Qualcomm platforms. Signed-off-by: Caleb Connolly --- drivers/soc/qcom/Kconfig | 8 ++++++++ drivers/soc/qcom/Makefile | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 4aa7833930c7..ee3d299eebe6 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -23,5 +23,13 @@ config QCOM_RPMH help Say y here to support the Qualcomm RPMh (resource peripheral manager) if you need to control regulators on Qualcomm platforms, say y here. +config QCOM_SMEM + bool "Qualcomm SMEM support" + help + Say y here to support the Qualcomm SMEM (shared memory) client driver. + SMEM is a shared memory region that is used to pass information about + the hardware (e.g. DRAM layout, PMIC configuration, etc) between bootloader + staged and the OS. If in doubt, say y. + endif # SOC_QCOM diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 78fae8bbfa16..f4102f9155a8 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o obj-$(CONFIG_QCOM_RPMH) += rpmh-rsc.o rpmh.o +obj-$(CONFIG_QCOM_SMEM) += smem.o From patchwork Sun Nov 24 19:17:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845207 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841729wru; Sun, 24 Nov 2024 11:19:33 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXF49jRguuXUG2K1hfPRmqR119ftuvEU2yxuIXTUSESVeocFMW90gaxhPXlkaKkPiFnyCQ0sA==@linaro.org X-Google-Smtp-Source: AGHT+IEydL+5/wx/scfmyHvdTQVV3ZjIyzCLdT5w/AFrE/HTlAuW6OY5WKMm/oCF26GU1wcBZCC1 X-Received: by 2002:a05:6402:1e8a:b0:5cf:95c4:ff1 with SMTP id 4fb4d7f45d1cf-5d020693eb8mr9288398a12.24.1732475972960; Sun, 24 Nov 2024 11:19:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475972; cv=none; d=google.com; s=arc-20240605; b=CvlUk2HB7w9oTUjbWkkaSL6U71wbJzN+7h0bSj1fjOqRa+Ig6rVrTQTBFV/gWoQwJa fYJzxb8e9buzGF03PSANm0pylCyOLH2CeE2F6gATqAaQ6v0T0JQL3/s7mVsLylKXa4NJ XwbXJ4eMxIu+d6iuF5aBzoEI87PtaKxN5thcpbw+WXRKyjVdFsk+YvsrkJCMcUqNcfIC ly5FmQv9ML4gV6jORBqPoQxAtzz7yv0ztO/hRR2nv05U/c7VUqrr2W/Q+dmyltnpDamB wNv2cGN0OVm7q/GguB8XE+ZyZ/yArfPYuB2UqoBWniCq2vggmF74IwufFkgf8x6FnT3r odOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=MClsSL1e2wvBAGUc3z1v56Mq9hCHj5kkjYLV+fa+pnY=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=BM6uCgUWJknHQK2uGWbq8qPX7hwnomlRWA4wECwrmAjIH6J7xWNTdCzHqG9/HxPxoL 2qFIjZdQvUFl/yRbjDKhp6t5LSueb2M1D9HOSAypEl0DvLKzxhSnRSftgXlBdqHNahel uP+yp0A+oa+GnMOep/DUzwoIrmfTcWstE6Jns5PNYhnG1/K9Y2pcyUoGS9SYNFRUgG5U eXAT9vZDatsPq02H0Tj20VHbL5+Cm2ixMuggejgLB+Puuf0EMikjKSS7HIO8FcPkklCS KyyQ0FZ1kdjz2/zl4U1gKAW7Bv+zvgV5NgOMR1otPB3kHShoMjKAeKC/x1OzPPMUIdUv 2sRg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FKHRcp8b; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id a640c23a62f3a-aa54fc668d1si54004366b.564.2024.11.24.11.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:19:32 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FKHRcp8b; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2878E899AD; Sun, 24 Nov 2024 20:18:04 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="FKHRcp8b"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 750C989922; Sun, 24 Nov 2024 20:18:01 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 67A0789578 for ; Sun, 24 Nov 2024 20:17:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-aa549d9dffdso88846966b.2 for ; Sun, 24 Nov 2024 11:17:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475879; x=1733080679; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=MClsSL1e2wvBAGUc3z1v56Mq9hCHj5kkjYLV+fa+pnY=; b=FKHRcp8bTdvksPYjeti/dUHnWyWmux757vvmARvszFKpf650kd+LQ4oE7wQURB/C+u bmhMRe7JgRBUvI40s09l9yTBbHmUmhq7pmqpDC0Dnx8RflAuoz0j6DFFKIV228ddFN4o RQ+0jtWROSP5tqk8gMPFkuGUWLmVl2i9tn0OqyO+SMuoOFuB0Cu+GZ2W7M1oj8PILZLM Ga/qmMh8T8tpZF35JwTmxC6cUaREwK5S9UlO0NFW+U5tsFfOJW2qprqjuLFYV3QByvfR Mqeddfcyisnop1GQRY8yV/yVis/SwDl1hYCAHpV6EQkQjbf/uCDBygZ+8cguFIEUb5qk oKWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475879; x=1733080679; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MClsSL1e2wvBAGUc3z1v56Mq9hCHj5kkjYLV+fa+pnY=; b=jbc9Dka4gAS7mDuMQy8wQV/bKzjh6EhEJPOkapiyzMAs88JMgcjzIvagEvI9ce+RMY 5iZqcFGjG3cW8+w6B9AR/p1ZSWZu8oMGXYC0qtwbUsdSB7CXlkx4YmA0BEPTPlZ3H8ZT VeJweJBorpktnMxBuoRPKFc9o8pSQxFO7dLOftpLDk8NlGF/gC7Ykk/pPxVHSp/VX/dY t7kCZKF1ysruTFFcd4ugV1iuvMaFS3DQ8hfgqUCdpQKnRubBfMJ5MIH6sINMJkjRBfU1 lQ26teZ1A47aZ3h4Hmf56zWw7DTpCaAH/pDyqgTduRAxkCJwFoettn5x4VKLBE07xNi0 lmUg== X-Gm-Message-State: AOJu0Ywex0UMDmx5E79TDg9svIUKj6OCAQi3RPuUPMWrKNII5H9Pf4ws pVKEEq7cJzP0t918Gf54pg04OfjiqaBNjVdLN6/hcPXRyao8+GyTNCpnLwJEFbg= X-Gm-Gg: ASbGncumCAqVzb1IEe/v2jWZgNQBlBFIrC67Bw/JRpl/9zPpavJx6vWf+S+Hyzass2w LPu4M/BUO+KjjEO0I5UkHwfiq20sWHfRkL+SJGnUqgBs9JrJwoPoIeeRlPQkXukBXvUFQOUPgx/ 3+kPxde7zV0gv2VpLRAG9T0XQ8esASOqq3iKhXWYn39GNgY7sVZsoqrzRUO4ytS4Z1XByZwQF5m eLrRG9V89byvM7Qrdy6NYrtEYEP41XFN5LRTieeafzUnZMsBIRmn8ePkAhG6SuS8e2O X-Received: by 2002:a17:906:18b2:b0:aa5:152a:d0a5 with SMTP id a640c23a62f3a-aa5152ae2a9mr960416366b.18.1732475878912; Sun, 24 Nov 2024 11:17:58 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:58 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:53 +0100 Subject: [PATCH 11/15] mach-snapdragon: increase pre-relocation malloc size for smem MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-11-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=687; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=P/QiqoWmYOMMkdpsxY7kqwwQ68XMYt+OSTz5Ofylu2o=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6pu/Sm5wuTiaTV/m6nUlMsP014QYhuxHqw7ujD3/w 9sp+kRyRykLgyAHg6yYIov4iWWWTWsv22tsX3ABZg4rE8gQBi5OAZjIXx5GhuWZx7mEuBqv/7oe 7js7/LzDBP8bS95YFP5jYe5caO2sW8jwvyqymqnxQHSu3qK199br/unXyTe4/YNfvJ4vN4VZPWR mEwA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Ensure we have enough space to init smem prior to relocation, since we might parse the DDR bank layout from there. Signed-off-by: Caleb Connolly --- arch/arm/mach-snapdragon/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 976c0e35fcef..5f3a1b11d8e2 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -14,9 +14,9 @@ config SYS_VENDOR config SYS_MALLOC_LEN default 0x10000000 config SYS_MALLOC_F_LEN - default 0x2000 + default 0x20000 config SPL_SYS_MALLOC_F default y From patchwork Sun Nov 24 19:17:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845208 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841774wru; Sun, 24 Nov 2024 11:19:42 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXBJXR2duNO5rHwmXhXifFDHZQ/0OiR5us+ekcMDbAz07qdbxZbAOCEGOfRrmlrXhZkT66sOw==@linaro.org X-Google-Smtp-Source: AGHT+IGW+I/jjWWVjRMnvi3iET0IIOGkWtE4VdFwo8dYHILfr5uNUyqCbyu/kCGnEHWSKooy4M+Z X-Received: by 2002:a17:907:7786:b0:aa5:249f:8431 with SMTP id a640c23a62f3a-aa5249f849bmr709963166b.18.1732475982364; Sun, 24 Nov 2024 11:19:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475982; cv=none; d=google.com; s=arc-20240605; b=A61qyRTYnnShv/o93GfCg2/ix2rYqFuZcWYqVdkTfxTrSpfDmsrT9+b6GZQP50FrB3 7qCjvW3rQ2V1XD5QoPnGLmw1jVIY9+MeVHIyvvEFewDsHAXT5SanIsKcBrKd27axy6wU FOh6hNVsTbl0Zh2kniCjFhXoC1ErQcODsmLU13OX7Qj310p1ucTi8sEvNxvJ+Ew7wpKQ agE0LBNPTOvMc8/pLbiTaNhTdyFtnEJ642yjzbMCwA8xRc0aPdAl8b4G+zKMXCfp6hxo SbyqlBtmrRG5+AA/swc7n7SSVSYkuZVjwBEYn0LL7q6O+8gptet4sD7vBDkiz4yk+Eoa 6+Kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=43kMLVc8y31AVo6TYGPBMHQM94BUyokDNhg0TrxJyHM=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=XTWU1QGXlX5KMSycV0Za9UorngxFH474IduXUlhJYzq7q2MSyPvreSf64RvqfMZ63d +z3PdqshuLtLQdoKqPZxE+y1D7kLa+/E20Me8qTa88IBQcWaqhSh9kayI+deABl9s7cx kbykeUjCt+uA+wS3nzIRLiDRvM7P1sPG0B++na+si4Z0XhuHJ6E+ddma93cEgVAZ3Ma+ D4SPMlKmkrqpkXkA2Pwr1aeRdylAj9qPOt1fdnxQIWP4CaRdzH2fg45gMZDg/ZG55kEj LVZLYx+zTztqI6xhz97ZQCsJBciVuOmFcRWdMMxwjHw/i7UQdpud1XrmgUM+a0tKxPrM Rt9w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PY8T1Y+S; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id a640c23a62f3a-aa50b55725esi373297866b.543.2024.11.24.11.19.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:19:42 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PY8T1Y+S; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9551A896BB; Sun, 24 Nov 2024 20:18:07 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="PY8T1Y+S"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B091589987; Sun, 24 Nov 2024 20:18:02 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 63E108953A for ; Sun, 24 Nov 2024 20:18:00 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-a9ec267b879so578306166b.2 for ; Sun, 24 Nov 2024 11:18:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475880; x=1733080680; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=43kMLVc8y31AVo6TYGPBMHQM94BUyokDNhg0TrxJyHM=; b=PY8T1Y+SmArsNBBJUXLe8yaclG8K7hGns1Up9hxzB9cyuWrpfxc0bo570q9hEOo8qG EYQnkijx2a47Vp/o7yz84FUyHyYq2RxL21ebY428Pu+Ze9/H7yqQ1Y46BYYv8MB7yMOz KYpDMDceHkcN8advpdPjNKc0fLOKaZ4b7/dx8wfWkCeR5BSjeWYq+txevsJxDuAqzdkE iLw8QiesyQqt5BmwylaiH1P6zImg5e4UQL4cVK2s9cwKOuiPuLRY3idIRZeFcI2nGO+4 zEpTSdOMqWlnpxKx0OH7v8ZVv/jTwv5KcBHG42F8CWzLK3Y2GkApU7hUKqP85Q6kqwcq 5y9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475880; x=1733080680; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=43kMLVc8y31AVo6TYGPBMHQM94BUyokDNhg0TrxJyHM=; b=Nzp01ejL64VqQJQkz1dKsOlCpV3atR8sn+xL5Zri3n3WpScnzku40iK9XfbeztJ0xV HfB3XRxxh4GYZkNrYtHuPM4ameZYIU4gTzdQYcrehWTZC7pulDAJieukq1AwEJsFQvFF tif80yquXYEplIzaN/BYaZjNOprnI2SFuh8bIAguWKjw7hyS2NWiESu5ZSbAf2BbFVl0 TWV26gBJyjO7Dw/0ABRNrG4NEcdgr+oyI7n6vAZWYQZ6DBuHgP1HQOJpwub4/InPEjbL 7q/idzfzYdpN0ZZ02I6XSfkxcIPSD4noZ7jzZYMe26TY39PijOxweLjIX7kkIJA2zu3X FDVQ== X-Gm-Message-State: AOJu0YweTE+8FjciUcZtKLtbYqsyTo/RQl9WTpeHdWhXBrRTX7dNOxFa 3JRznjqSvs8z75GgqxUa+yCqlrGmgL3UjKJvH2a+utcVs+ntGcH9iHh5DJZVNwI= X-Gm-Gg: ASbGncuCFF+w/0zV2dOf21DfV5SZ0+4jH83Rb1uG9IZPKkHIWaJk06qZIXxQZizcVS0 UwO1FPkYHQGYivISjJfw1W0KSA1T1dCOgNFsm7rhOLTpmgVzsqYYLHFOLvqxuVmkI7y6g5onNlj u6Sazy3byV/qVbHY1dO50ZCBdeLaeyLkGCYORNBQmC8CCPja1TxV7a/kg08vvGmvLUk9iuGyhft MbaWkWE2QDINsa9dSMPDTt6CUs9tvP94UHpC3c84DLhy+Jwl5eWOOiV5AexuLflyYhf X-Received: by 2002:a17:906:d511:b0:a9a:1437:3175 with SMTP id a640c23a62f3a-aa509d6c7cfmr787953866b.51.1732475879791; Sun, 24 Nov 2024 11:17:59 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:17:59 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:54 +0100 Subject: [PATCH 12/15] mach-snapdragon: move memory parsing to its own file MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-12-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=7755; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=xqCHJt/ssNiAHJDI8IlKzjUA34nKWu98djFxudHRclU=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6ptHj/1p8ud948bYVBtlKRvF+F9j6+8FcZ8Duif6f JOxfr6uo5SFQZCDQVZMkUX8xDLLprWX7TW2L7gAM4eVCWQIAxenAEzkkBLD/zrZJSe2L9h4rFzI 0mHth4Djd2N2FO/Qf3drVeBMpvNBHx4x/PfVuVXHsWuJ3KUl57lipptoR6Q87ooI04+JMRDmO83 8zwgA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This code is getting a bit complicated, split it out to try and keep things a bit better organised as we're going to be supporting populating the memory layout from various other sources. Signed-off-by: Caleb Connolly --- arch/arm/mach-snapdragon/Makefile | 2 +- arch/arm/mach-snapdragon/board.c | 94 ---------------------------- arch/arm/mach-snapdragon/dram.c | 116 +++++++++++++++++++++++++++++++++++ arch/arm/mach-snapdragon/qcom-priv.h | 2 + 4 files changed, 119 insertions(+), 95 deletions(-) diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 343e825c6fdd..e481e4f26e5c 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2015 Mateusz Kulikowski -obj-y += board.o +obj-y += board.o dram.o obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += capsule_update.o obj-$(CONFIG_OF_LIVE) += of_fixup.o diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 75a880f093ca..8d171957b852 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -40,102 +40,8 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } }; struct mm_region *mem_map = rbx_mem_map; -static struct { - phys_addr_t start; - phys_size_t size; -} prevbl_ddr_banks[CONFIG_NR_DRAM_BANKS] __section(".data") = { 0 }; - -int dram_init(void) -{ - /* - * gd->ram_base / ram_size have been setup already - * in qcom_parse_memory(). - */ - return 0; -} - -static int ddr_bank_cmp(const void *v1, const void *v2) -{ - const struct { - phys_addr_t start; - phys_size_t size; - } *res1 = v1, *res2 = v2; - - if (!res1->size) - return 1; - if (!res2->size) - return -1; - - return (res1->start >> 24) - (res2->start >> 24); -} - -/* This has to be done post-relocation since gd->bd isn't preserved */ -static void qcom_configure_bi_dram(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start; - gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size; - } -} - -int dram_init_banksize(void) -{ - qcom_configure_bi_dram(); - - return 0; -} - -static void qcom_parse_memory(void) -{ - ofnode node; - const fdt64_t *memory; - int memsize; - phys_addr_t ram_end = 0; - int i, j, banks; - - node = ofnode_path("/memory"); - if (!ofnode_valid(node)) { - log_err("No memory node found in device tree!\n"); - return; - } - memory = ofnode_read_prop(node, "reg", &memsize); - if (!memory) { - log_err("No memory configuration was provided by the previous bootloader!\n"); - return; - } - - banks = min(memsize / (2 * sizeof(u64)), (ulong)CONFIG_NR_DRAM_BANKS); - - if (memsize / sizeof(u64) > CONFIG_NR_DRAM_BANKS * 2) - log_err("Provided more than the max of %d memory banks\n", CONFIG_NR_DRAM_BANKS); - - if (banks > CONFIG_NR_DRAM_BANKS) - log_err("Provided more memory banks than we can handle\n"); - - for (i = 0, j = 0; i < banks * 2; i += 2, j++) { - prevbl_ddr_banks[j].start = get_unaligned_be64(&memory[i]); - prevbl_ddr_banks[j].size = get_unaligned_be64(&memory[i + 1]); - /* SM8650 boards sometimes have empty regions! */ - if (!prevbl_ddr_banks[j].size) { - j--; - continue; - } - ram_end = max(ram_end, prevbl_ddr_banks[j].start + prevbl_ddr_banks[j].size); - } - - /* Sort our RAM banks -_- */ - qsort(prevbl_ddr_banks, banks, sizeof(prevbl_ddr_banks[0]), ddr_bank_cmp); - - gd->ram_base = prevbl_ddr_banks[0].start; - gd->ram_size = ram_end - gd->ram_base; - debug("ram_base = %#011lx, ram_size = %#011llx, ram_end = %#011llx\n", - gd->ram_base, gd->ram_size, ram_end); -} - static void show_psci_version(void) { struct arm_smccc_res res; diff --git a/arch/arm/mach-snapdragon/dram.c b/arch/arm/mach-snapdragon/dram.c new file mode 100644 index 000000000000..c4c60039cb4c --- /dev/null +++ b/arch/arm/mach-snapdragon/dram.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Memory layout parsing for Qualcomm. + */ + +#define LOG_CATEGORY LOGC_BOARD +#define pr_fmt(fmt) "QCOM-DRAM: " fmt + +#include +#include +#include +#include + +static struct { + phys_addr_t start; + phys_size_t size; +} prevbl_ddr_banks[CONFIG_NR_DRAM_BANKS] __section(".data") = { 0 }; + +int dram_init(void) +{ + /* + * gd->ram_base / ram_size have been setup already + * in qcom_parse_memory(). + */ + return 0; +} + +static int ddr_bank_cmp(const void *v1, const void *v2) +{ + const struct { + phys_addr_t start; + phys_size_t size; + } *res1 = v1, *res2 = v2; + + if (!res1->size) + return 1; + if (!res2->size) + return -1; + + return (res1->start >> 24) - (res2->start >> 24); +} + +/* This has to be done post-relocation since gd->bd isn't preserved */ +static void qcom_configure_bi_dram(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start; + gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size; + } +} + +int dram_init_banksize(void) +{ + qcom_configure_bi_dram(); + + return 0; +} + +static void qcom_parse_memory_dt(const fdt64_t *memory, int banks, phys_addr_t *ram_end) +{ + int i, j; + + if (banks > CONFIG_NR_DRAM_BANKS) + log_err("Provided more memory banks than we can handle\n"); + + for (i = 0, j = 0; i < banks * 2; i += 2, j++) { + prevbl_ddr_banks[j].start = get_unaligned_be64(&memory[i]); + prevbl_ddr_banks[j].size = get_unaligned_be64(&memory[i + 1]); + /* SM8650 boards sometimes have empty regions! */ + if (!prevbl_ddr_banks[j].size) { + j--; + continue; + } + *ram_end = max(*ram_end, prevbl_ddr_banks[j].start + prevbl_ddr_banks[j].size); + } +} + +/* Parse the memory layout from the FDT. */ +void qcom_parse_memory(void) +{ + ofnode node; + const fdt64_t *memory; + int memsize; + phys_addr_t ram_end = 0; + int banks; + + node = ofnode_path("/memory"); + if (!ofnode_valid(node)) { + log_err("No memory node found in device tree!\n"); + return; + } + memory = ofnode_read_prop(node, "reg", &memsize); + if (!memory) { + log_err("No memory configuration was provided by the previous bootloader!\n"); + return; + } + + banks = min(memsize / (2 * sizeof(u64)), (ulong)CONFIG_NR_DRAM_BANKS); + + if (memsize / sizeof(u64) > CONFIG_NR_DRAM_BANKS * 2) + log_err("Provided more than the max of %d memory banks\n", CONFIG_NR_DRAM_BANKS); + + qcom_parse_memory_dt(memory, banks, &ram_end); + + debug("%d banks, ram_base = %#011lx, ram_size = %#011llx, ram_end = %#011llx\n", + banks, gd->ram_base, gd->ram_size, ram_end); + /* Sort our RAM banks -_- */ + qsort(prevbl_ddr_banks, banks, sizeof(prevbl_ddr_banks[0]), ddr_bank_cmp); + + gd->ram_base = prevbl_ddr_banks[0].start; + gd->ram_size = ram_end - gd->ram_base; + debug("%d banks, ram_base = %#011lx, ram_size = %#011llx, ram_end = %#011llx\n", + banks, gd->ram_base, gd->ram_size, ram_end); +} diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h index 74d39197b89f..b7f3bf798d3c 100644 --- a/arch/arm/mach-snapdragon/qcom-priv.h +++ b/arch/arm/mach-snapdragon/qcom-priv.h @@ -22,5 +22,7 @@ static inline void qcom_of_fixup_nodes(void) log_debug("Unable to dynamically fixup USB nodes, please enable CONFIG_OF_LIVE\n"); } #endif /* OF_LIVE */ +void qcom_parse_memory(void); + #endif /* __QCOM_PRIV_H__ */ From patchwork Sun Nov 24 19:17:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845209 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841810wru; Sun, 24 Nov 2024 11:19:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWfwYgIm7kZEFZBO0kQ38bEy1sV6BAvZK93KxcnRJHNcDF54DoKA+RZzrCPPHp8Fz4oNAv37A==@linaro.org X-Google-Smtp-Source: AGHT+IHrcQ71dxdB0VoWSvWfD3hedvRp0lYes50wlucNc9KL3QPE1W88rGcjkQ8uKPXmNypU8D6h X-Received: by 2002:a17:906:308b:b0:aa5:2d9a:1526 with SMTP id a640c23a62f3a-aa52d9a15c1mr500573366b.61.1732475991008; Sun, 24 Nov 2024 11:19:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475990; cv=none; d=google.com; s=arc-20240605; b=aQx1N4i1TCL6m+SYwmXHku+OJOeoH/lKnkoQeCWmsyMP3ElEwV4aezfJAmwqVmDqRR 9WUgkpa7IF5QOVxln8b9z4QPnw+CE95rLHN3KMHGkufMsRQX7kYvNnvt/1tjsy76jd6S fXcluvk9ApbzMWBWiSPOwcve20duhRu7gQrunl2w7+L6YSLRISVPgFxz7c7B44DJYuof yFUs1d5JV6acVK+a+/Xc6zczg/RhT9VybCyzPpu4h6mK0/hX/nWh5UmEDIJhRJsdaNqH QHcjNMNNnGVvAAL9L6gCAhK4L9ZV5UgDBc/E3MflmoYv7SZ6TdWYJA3juYEZMETpKH8x Q1hQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=hmFseKUkt7mwAk/sUu4EJEETAWTt5Zgjg+i431V9GSQ=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=eIQuJutMC4NLXROvpN1iGzjfPN3ajdGMbAOYvp4oG19Q1QLttYdklHrxLinrdu625l wsYRE4+XNJSkp9CkgUgOGwb+pHvDwlA0/dTKeq/NrEDgPpnEGPyM4A1I5C9BXZQJb8VA aUHMzSMN7e4DfeS9BpN7otOwNXQwZkbiYKZSUqPjnjlUchHKJzfKYnLjiEOh+4W9XulB B1YLNzG3ULJ99+V/Gd8UntJnJNmxHMCwj72oBFaP4TLUmcpP8+ZDGr5P+aPW6fejSvF/ RLnohEgbl8Yb9eNp4jUpSQ2veiF6mOo509/JdnHdZuIO7bs1DoCknIs5KTvb+6Gu/NRO qXXA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oeMmkizN; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id a640c23a62f3a-aa50b242b81si396834166b.124.2024.11.24.11.19.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:19:50 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oeMmkizN; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E3E2689939; Sun, 24 Nov 2024 20:18:07 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="oeMmkizN"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 988D889812; Sun, 24 Nov 2024 20:18:03 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 51D5E899A0 for ; Sun, 24 Nov 2024 20:18:01 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-aa52bb7beceso208172866b.3 for ; Sun, 24 Nov 2024 11:18:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475881; x=1733080681; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hmFseKUkt7mwAk/sUu4EJEETAWTt5Zgjg+i431V9GSQ=; b=oeMmkizNuv5MxNfgQA7xm5sgvXOnZy8SL5Cq2A5eiph6KYQRphU4vzsl47teEHy3iv dzqtl09AnTuP/90OXtS7IDojFa6OhpKYFES1hrelrAZusqn9iGXO3rexdrlNQBLgWb4y bmk6YJ9ojrJFo+dRYfDSqfvLDD1wVVbnHTBLueDKUBguPrdGCMADytyEseYXSNwqFqv+ C1B4XGoEwdZ9O23ytR+OLbASel2rtrdNjD3WF3EIWgtgksR1GrpqWQjqV1dGkLf/cmMi YpB8AQS+ooVMlgr/Valsx2M3KnriMCEDkDxQsU47Gi+BhOQbvTJT7GvnGcHas5daOzsT 5zpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475881; x=1733080681; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hmFseKUkt7mwAk/sUu4EJEETAWTt5Zgjg+i431V9GSQ=; b=vYZe2X+n2BUVaa5UGH8mZ8tNyFZTJIlqBHM+k1nflSyhxagEiwz6J8wbX82/rP63WX DNAkRk7OIkAKYLqZHWpVDH98WIe+loFP32+Razo2eMjKovufDXsqk2F5KpT8qj0FTz4h O6fTVe7Z5PYrLfCude5yYnKzvvimxG/sgoEP+zDsmjuQj1mgGr/QS0efn0+Xo0DAaOXZ WfPOQCbZwGS/QcY99TowK/i8w2JrpCZYg4JFoIpmZ57BoYUGTbmn53RZi39v3rVdc7J/ PGAIeFE4YpXFRjSnMj1QcZqeTOriz/SxEnc9/K+xIVu7IjhSOSbFlSO6SSKD3b8cO8ur LMJA== X-Gm-Message-State: AOJu0Yz8Sfoc0lbkxNjyk0aFITdmBsqysRzLslLKHQvqAsov9vFCWPh+ FwZOcEnsv1qET3EuWvR/mKoda9NX91ljVl31V2a9b6hKux/cCGYdIxt+rffgj1k= X-Gm-Gg: ASbGncvZTxh6cTHk8sVkUuVMk/V1TDfM2Xp3YiTG9QDwuUfMiCnYgmAH/thb24OKl+Q ZQpmNifa+VszoXZyiEz/GXQlmg+tQC4PXxaHQ5M85xwtRB3lzqsGmDFmTvSN1rQeBv8FLzL/tnQ vXITjyjr/ZRsR6KEZYH9IhcvruEGEMp+c+pGs6vhxVCQK6um9PWACMiODwHtqnprsPOPS526UF5 MdRuUwAwIr6qffeMaOSi/aeXe6C+Mdyej5Hh6cVd/2M/5bFmRYA+7O0FACEoJ4Sw1z6 X-Received: by 2002:a17:906:9d2:b0:aa5:b2b:f236 with SMTP id a640c23a62f3a-aa50b2bf7ffmr774292266b.28.1732475880741; Sun, 24 Nov 2024 11:18:00 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:18:00 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:55 +0100 Subject: [PATCH 13/15] mach-snapdragon: support parsing memory map from SMEM MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-13-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6934; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=nzCEFARaIj7wTx36KBeY5Je7ny5WpUDpLbORIGhEk70=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6pt/rR/b1iqqd83dwC7/TVFdOtQhcVnXwniDR3nbi 3gkZ77sKGVhEORgkBVTZBE/scyyae1le43tCy7AzGFlAhnCwMUpABO5JMXwV1yo6ueWq23swW1V cf4XjvZsW9Xr5TY1KWr2icfduf93mTL8j3JfoLD4vXddsdPnDTNEJzrq/m49++NNunlj6DmRYhm 1bAA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean It is possible to derive the memory map for a Qualcomm platform from the SMEM shared memory region. The memory map is populated by the preloader. Introduce support for parsing this data and using it to populate U-Boot's memory map. Since we aren't yet sure if this will work for every platform, it is not yet used in all cases, if U-Boot is booted with an internal FDT which has the memory map defined, this will be used instead. If the FDT comes from ABL, or we're using an internal FDT with no memory map defined, then U-Boot will try to use SMEM. This should remove the need to define the memory map statically in a U-Boot overlay DT for most boards. Signed-off-by: Caleb Connolly --- arch/arm/mach-snapdragon/board.c | 2 +- arch/arm/mach-snapdragon/dram.c | 106 +++++++++++++++++++++++++++++++++-- arch/arm/mach-snapdragon/qcom-priv.h | 4 +- 3 files changed, 106 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 8d171957b852..269d39e4f6e1 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -85,9 +85,9 @@ void *board_fdt_blob_setup(int *err) /* * Parse the /memory node while we're here, * this makes it easy to do other things early. */ - qcom_parse_memory(); + qcom_parse_memory(internal_valid); return (void *)gd->fdt_blob; } diff --git a/arch/arm/mach-snapdragon/dram.c b/arch/arm/mach-snapdragon/dram.c index c4c60039cb4c..ef226e000858 100644 --- a/arch/arm/mach-snapdragon/dram.c +++ b/arch/arm/mach-snapdragon/dram.c @@ -9,14 +9,47 @@ #include #include #include #include +#include + +#define SMEM_USABLE_RAM_PARTITION_TABLE 402 +#define RAM_PART_NAME_LENGTH 16 +#define RAM_NUM_PART_ENTRIES 32 +#define CATEGORY_SDRAM 0x0E +#define TYPE_SYSMEM 0x01 static struct { phys_addr_t start; phys_size_t size; } prevbl_ddr_banks[CONFIG_NR_DRAM_BANKS] __section(".data") = { 0 }; +struct smem_ram_ptable_hdr { + u32 magic[2]; + u32 version; + u32 reserved; + u32 len; +} __packed; + +struct smem_ram_ptn { + char name[RAM_PART_NAME_LENGTH]; + u64 start; + u64 size; + u32 attr; + u32 category; + u32 domain; + u32 type; + u32 num_partitions; + u32 reserved[3]; + u32 reserved2[2]; /* The struct grew by 8 bytes at some point */ +} __packed; + +struct smem_ram_ptable { + struct smem_ram_ptable_hdr hdr; + u32 reserved; /* Added for 8 bytes alignment of header */ + struct smem_ram_ptn parts[RAM_NUM_PART_ENTRIES]; +} __packed; + int dram_init(void) { /* * gd->ram_base / ram_size have been setup already @@ -47,8 +80,12 @@ static void qcom_configure_bi_dram(void) for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start; gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size; + debug("Bank[%d]: start = %#011llx, size = %#011llx\n", + i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); + if (!prevbl_ddr_banks[i].size) + break; } } int dram_init_banksize(void) @@ -57,8 +94,48 @@ int dram_init_banksize(void) return 0; } +/* Parse memory map from SMEM, return the number of entries */ +static int qcom_parse_memory_smem(phys_addr_t *ram_end) +{ + size_t size; + int i, j = 0, ret; + struct smem_ram_ptable *ram_ptable; + struct smem_ram_ptn *p; + + ret = qcom_smem_init(); + if (ret) { + debug("Failed to initialize SMEM: %d.\n", ret); + return ret; + } + + ram_ptable = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_USABLE_RAM_PARTITION_TABLE, &size); + if (!ram_ptable) { + debug("Failed to find SMEM partition.\n"); + return -ENODEV; + } + + /* Check validy of RAM */ + for (i = 0; i < RAM_NUM_PART_ENTRIES && j < CONFIG_NR_DRAM_BANKS; i++) { + p = &ram_ptable->parts[i]; + if (p->category != CATEGORY_SDRAM || p->type != TYPE_SYSMEM) + continue; + if (!p->size && !p->start) + break; + + prevbl_ddr_banks[j].start = p->start; + prevbl_ddr_banks[j].size = p->size; + *ram_end = max(*ram_end, prevbl_ddr_banks[j].start + prevbl_ddr_banks[j].size); + j++; + } + + if (j == CONFIG_NR_DRAM_BANKS) + log_err("SMEM: More than CONFIG_NR_DRAM_BANKS (%u) entries!", CONFIG_NR_DRAM_BANKS); + + return j; +} + static void qcom_parse_memory_dt(const fdt64_t *memory, int banks, phys_addr_t *ram_end) { int i, j; @@ -76,10 +153,23 @@ static void qcom_parse_memory_dt(const fdt64_t *memory, int banks, phys_addr_t * *ram_end = max(*ram_end, prevbl_ddr_banks[j].start + prevbl_ddr_banks[j].size); } } -/* Parse the memory layout from the FDT. */ -void qcom_parse_memory(void) +/* + * Parse the memory layout from FDT or SMEM: + * + * If using an internal FDT (where the memory map must have + * been written by hand) then we prefer using the layout from + * there. This allows overriding SMEM. + * + * If using an external FDT (coming from ABL), we prefer SMEM + * since it is likely to be more accurate / simple, especially + * on newer platforms. + * + * If SMEM parsing fails, we always try to fall back to FDT. + * + */ +void qcom_parse_memory(bool fdt_is_internal) { ofnode node; const fdt64_t *memory; int memsize; @@ -103,10 +193,18 @@ void qcom_parse_memory(void) log_err("Provided more than the max of %d memory banks\n", CONFIG_NR_DRAM_BANKS); qcom_parse_memory_dt(memory, banks, &ram_end); - debug("%d banks, ram_base = %#011lx, ram_size = %#011llx, ram_end = %#011llx\n", - banks, gd->ram_base, gd->ram_size, ram_end); + /* + * If using an internal FDT but the memory node is empty + * then fall back to SMEM. + */ + if (!prevbl_ddr_banks[0].size && fdt_is_internal) { + banks = qcom_parse_memory_smem(&ram_end); + if (banks < 0) + panic("Couldn't find a valid memory map!\n"); + } + /* Sort our RAM banks -_- */ qsort(prevbl_ddr_banks, banks, sizeof(prevbl_ddr_banks[0]), ddr_bank_cmp); gd->ram_base = prevbl_ddr_banks[0].start; diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h index b7f3bf798d3c..690557463642 100644 --- a/arch/arm/mach-snapdragon/qcom-priv.h +++ b/arch/arm/mach-snapdragon/qcom-priv.h @@ -2,8 +2,10 @@ #ifndef __QCOM_PRIV_H__ #define __QCOM_PRIV_H__ +#include + #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) void qcom_configure_capsule_updates(void); #else void qcom_configure_capsule_updates(void) {} @@ -22,7 +24,7 @@ static inline void qcom_of_fixup_nodes(void) log_debug("Unable to dynamically fixup USB nodes, please enable CONFIG_OF_LIVE\n"); } #endif /* OF_LIVE */ -void qcom_parse_memory(void); +void qcom_parse_memory(bool fdt_is_internal); #endif /* __QCOM_PRIV_H__ */ From patchwork Sun Nov 24 19:17:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845210 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841859wru; Sun, 24 Nov 2024 11:20:00 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXD433gqxkOZyA9SF+j2tc+5jZ43RlKNVn2mMHWgnupFRG5MHlmqgRJb4yLBoBUZu+PiA+fkA==@linaro.org X-Google-Smtp-Source: AGHT+IG84PnharCndsWqGHbUWOYw1ELIHo/eccJPH+UHeHphfLkUtdqorZu+dLFoFB96mVSgfrvH X-Received: by 2002:a17:907:7639:b0:a9a:3cec:b322 with SMTP id a640c23a62f3a-aa509d3fd2amr912170766b.45.1732475999843; Sun, 24 Nov 2024 11:19:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732475999; cv=none; d=google.com; s=arc-20240605; b=EO4QTR/k3yESVO106xkXVRq9I9lyLD+auZscXT21apwZKmZ3QbA8ashJqSDUXXgmSM kFm9+MZhmogfs2yHJ2xZI42k4gr+2qiWn3LpFQXKuZIUJJLLwo+5PwGW/xIlNczdyyPB hZj0O/8+PIYR/TS+0qwellvo32llq7JATSg8NYIXXlwFNs1Fh9N/RHdU3EyCcemf0keF T1uS7iqtaexdeaU9yMlgJOQKl/hQFYYID5kUz458xAY01VoRImrqFPKhrm0Vi8++rdqC DZz+0Cks8oocaV+BrXrTSzW1Mft4lV4K1zRNxrYXTkk2c5hZjcHInUw16pOAtqVj7HV+ /Jzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=tUPs0yp6kU8qCe+jxwHLZfTPx5odl1foc42JUWMVeHU=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=EON5Ws+TkwgZlz48JQv7nlvQykuYGTWREFLIdsms2jxj22U6aicZV37KZRo5WaQno3 FzFfwXSMO14rkYBAi8a924qI30hV2igKAHVAaDzr2jibha6RYEVedy1H3Yk8KEgyBY0i h5qEv3fVCd0tFXjQqBOZ59SQxhZLal6P15IFW+auoQiZSikQibwzwHHf2GBuq2VGHNc7 8YwKKlqAs5gxhsHNUBk6oFjQakNmZMlNXxN/oTrQVqHj5Zi31N0NdjjSRGUAPx/j37Gb IrWgObpbZVJK69ovzU/JoBdzBs5Yt3ko37LYd6+jzQQGJdq82XaPNAaDx/NTZsjdiASX 6jLg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JZEeMc+w; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id a640c23a62f3a-aa5123618d8si385678766b.553.2024.11.24.11.19.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:19:59 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JZEeMc+w; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6685B899C2; Sun, 24 Nov 2024 20:18:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="JZEeMc+w"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6804D89920; Sun, 24 Nov 2024 20:18:04 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 183FB89578 for ; Sun, 24 Nov 2024 20:18:02 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-a9ed49ec0f1so601873666b.1 for ; Sun, 24 Nov 2024 11:18:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475881; x=1733080681; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tUPs0yp6kU8qCe+jxwHLZfTPx5odl1foc42JUWMVeHU=; b=JZEeMc+wUJfudqw7d3MUqFz2JOc5I4sxo8rJYi0yed0JfR5y1rehv+GhG+ISjVRyMk 1k1Df2Mv6Ouk6DXK9VmMGSpPx4HvxFBYcTvaqaCu2kXUyCfJ9SDjInfh7AxL+xqgAaW+ BV3/z+H/RM5eTY95Q3UvJfuz1Ht5kBtHliR5IDKCqFN2Gb26gDgImRjlsjU4j2YSurh1 Pbe5G7E8RZ0HHtdhMFXatfgxUXkIbEY4xBxQeu7YSPNKXwnheAkdsqHXsjAV9qtr05yq lWXzgnxb6JuA508NJ3MsA44kZ6boFf9mI00VTKXIPkBrg6nyAf3Giq0bHidArunzFySU swVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475881; x=1733080681; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tUPs0yp6kU8qCe+jxwHLZfTPx5odl1foc42JUWMVeHU=; b=LBFwj9v8z9OPBfWGR4uR6hmjl/NsjSTLXQslq7hA1H2E/YYd9UrPWqnpyvcQqPY+QF ccWRmpZS4g8bPWj+/X4R0WYTOi+epNV1JY7XxNMD6Ogmac+SGfq1kAoGFoCYk0znlIan oLkff8OD0q/v85FzX3nZSxTwOZyac9lS2+bqqFWZnpovS6dvlXw0Tq6G6zAnAYMFMNig oSSQelHrh62BOTYkqQGnegy/75rgn1fZSkcwtd8VyOmUxZvae2yac5B1svZQqyKWueQW o9drpFbPpd47mJ0riOwoM7NaYZ5VUOpgSgxiZw52TWSgNpwCn75oAOkaLz/PhJVEzoNh G5jQ== X-Gm-Message-State: AOJu0YweTHeUnbLpOQfhrZTJoaez52POF/i8L827zXlZ0vAVtxxBT9t6 kth1xHhM3evd8HRhI8fkWoN+8ijHcALJq96psMRpxJ0bylT6PJ9bGnPmSLVINNKBYJW4WstR+qu mSSg= X-Gm-Gg: ASbGnctwRrN6t5UfLDzU2xYMDGOkK0/fIH9REmtodL21exg5OX2K3j0EHnU5MM9VxTk NCLKRcjYpjwmDoyVW9Jy+UMdk/XN0v4zsK8p+Liwd1GlnP6YojP5DINTmZpSxVe1IWsMEf7wBCu 1jF4VkA6DBGUn7PUFYdG59maTgEtRHymFLsmAvSBuJz7wHIs4m6Fy2xXtJGivp+paizMofx8FcD +ltDshE7RA5eyA3RQ4cERF5bmC1vVHKLP9QG2XDMBqFu6tchefFRtlkIvYg+/XWoelI X-Received: by 2002:a17:907:ca09:b0:aa2:c73:3720 with SMTP id a640c23a62f3a-aa50a0a7d77mr820548466b.58.1732475881638; Sun, 24 Nov 2024 11:18:01 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:18:01 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:56 +0100 Subject: [PATCH 14/15] mach-snapdragon: fetch serial# from SMEM MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-14-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1342; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=vXtKUBdkMOD+rs8Qv8lyRTm3q8cJlHAlpVPQp8PMFtk=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6pv9d8um73rrHyrTrHLbyzhgjZzVy4Bbdy7dY9/Io Lgg4GdYRykLgyAHg6yYIov4iWWWTWsv22tsX3ABZg4rE8gQBi5OAZjICQGGv2LZ58Uu/JlsFbeB r3lV5xLhoE1/cifEvl4u71h5w5bR1Yrhn6W4x/XLoR+TPxhKlb1MNijXuNWyRfDM5i1SGbP326g f1gcA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean If available, otherwise fall back to cmdline. Signed-off-by: Caleb Connolly --- arch/arm/mach-snapdragon/board.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 269d39e4f6e1..dbac8aa2709a 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -30,8 +30,9 @@ #include #include #include #include +#include #include #include "qcom-priv.h" @@ -198,11 +199,16 @@ static const char *get_cmdline(void) } void qcom_set_serialno(void) { - const char *cmdline = get_cmdline(); + const char *cmdline; char serial[32]; + if (!qcom_socinfo_init()) + return; + + cmdline = get_cmdline(); + if (!cmdline) { log_debug("Failed to get bootargs\n"); return; } @@ -353,8 +359,11 @@ int board_late_init(void) /* By default copy U-Boots FDT, it will be used as a fallback */ memcpy((void *)addr, (void *)gd->fdt_blob, fdt32_to_cpu(fdt_blob->totalsize)); + /* Initialise SMEM if it wasn't done already */ + qcom_smem_init(); + configure_env(); qcom_late_init(); /* Configure the dfu_string for capsule updates */ From patchwork Sun Nov 24 19:17:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 845211 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp841917wru; Sun, 24 Nov 2024 11:20:14 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUTufZrAvWz+10WuR/P/ZwSetrr47izyYygFqpM4/TwlP9CFvj47cdAq/xpuwsF3UbMW2wpVA==@linaro.org X-Google-Smtp-Source: AGHT+IE8XawTiVglWgv82xZpgXeIx53mjJM9HVgiB51qqpU8413NuN9I4GQCKZfmSHC+HyhDa0Ym X-Received: by 2002:a17:906:318a:b0:aa5:324f:5318 with SMTP id a640c23a62f3a-aa5324f5393mr571087066b.20.1732476014307; Sun, 24 Nov 2024 11:20:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732476014; cv=none; d=google.com; s=arc-20240605; b=fJs4CYWx6VBDf28b3odhA7/XlrmQ+vwIJTwuYfX6JeRBhtMsYrCd5jEsCHKXUrFFA9 d37jki0NG+Uk6o/goG2W/I/cJooKuhJw4bpafe9dO4cSG3Mz8bbojdOWVHy9xd07I4ga A3qwqZLurKq7U6uw0nv/kCbIn7KODe2X1tEqO8UCeBqHbD5m7JbidbWOJmzBQ4n9O5Fb aPFJHCwf1GYvPH7ebSkkkufPH4TZMqoF3E3013MhxBHr4x5V6VOJXX4zbZYtHWsDTPxB FlGd//DvSDtSSTrwNvh5OrsHPCjB9rg8+5OLHTCkKR/8G+WXWBtC4NZ6BT4nG3+VRNmO XJpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=RjeBhaqIirQRAw5XkNFw7+PXaJs9j/MkAcv8cgNDNtY=; fh=g6j3SUyAhGUS8ikRCXsn3qFv1vKph7cSMPqtKbzTuc8=; b=UOs/1YYmSsjTqG0OjDr4iI61AyGy4cQDNJGLiv9Tua4W6z+uz3ZwxtZJ76NWgMpQ2z 1G8Cwd3F/wbE5EF1m/XXOxt0nbnhj569tNpMXww68S0M45ERZpKNUP7KLJo9DrEoqppf L5TUoPKxp+Fzb9ZJHRnij1KxO+mvppo2uzcKARYjvYNGw/lpTSpJw1JVuwKzOsbEBFL2 TfMRgUF8QqfBdlUFkn8sOQ6aCtH17uNVTp9q4o9LX7M0m+K27CtPMtyT4mVEc0YbEewu hYJyrQ8Nm8ZDIEoqjnVLHMkzPhWfexA7QodzK9fa+Esdfl0pxPisAU6eUPzH800nHWLY 09yQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L7fq+orU; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id a640c23a62f3a-aa50b246991si379799866b.69.2024.11.24.11.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:20:14 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L7fq+orU; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B602E899C9; Sun, 24 Nov 2024 20:18:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="L7fq+orU"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E5EFB89920; Sun, 24 Nov 2024 20:18:05 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5056F899B5 for ; Sun, 24 Nov 2024 20:18:03 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=caleb.connolly@linaro.org Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-aa5325af6a0so189247666b.2 for ; Sun, 24 Nov 2024 11:18:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732475882; x=1733080682; darn=lists.denx.de; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RjeBhaqIirQRAw5XkNFw7+PXaJs9j/MkAcv8cgNDNtY=; b=L7fq+orUGOEFkdVzKGy6ILfS7Afo9BSxvyXMUY8JhOwnT+bfhIQC3nDCS2Rl7Tn66j mVAnB/X3Jhn92ecfqRGG9ynZ/42/2DWVdfxUEC7osHbCOvYrWQ0wQc4ume6DN53JOnkH 171M0XUl5Ca14nVfuysUxJAJzqbfuBvaZu1YCLU6ktY3oU8UIUVvSDaYnQjrbkuaRlHk qD3Z9SQBJoTbRapGHflhhrhkN/bSvc+oUckRzLxbVWI6M2ZjV8Ise2aQEXrneTjRuHVA ySAi39sAIcEwbx+rFkXJcba8D3x+gOiVar0xjJs19oX0UyH35KZsrcZcGtkK8ZKqBv+R 1AkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732475882; x=1733080682; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RjeBhaqIirQRAw5XkNFw7+PXaJs9j/MkAcv8cgNDNtY=; b=T+YvzwJmzN2epJZeAvpFXQjCWdGHClKcmnwyhtxA3tXm4MPPvWn4ahBue0ocmJk6S7 fryT79OXjV4bzHu6TFunQhQNZfj/jvrGDGrKwwMknU4AfOmjCTMqnAV+UXtMo1c6M7Hv b/HHYVZZUNIg9ugoHHihx70ly8ZqeODRMKlz96C4HY/o9ovQ3KzbppweboZ5czBzb0g3 y2SdqxH3VKVE5BQf0h1ZScjPhvAG0nWCiblQwkxGZ6fWkFZWibRK6M9EguuwjLm11TIo iZL9EUcwog3U5vpbRg9V4tRDym/F1f5i72PwqMt8yH8bZFvHGiP8eSmcC38J9CHdwEkW PJKg== X-Gm-Message-State: AOJu0YzTahmQcC3R6TlNMPAZLCzch7ypvCm5pext1yJOVB4TsQrN84g5 7wUOi2Nfphfl4ZGMK2+yJWkzmBqE4V7JWg00mR9FtgL8MN59ObxNDgFYSdv6eKQ= X-Gm-Gg: ASbGncvIioM/f5nUeXaG5IyVjH7qwFL/2pxPbrj7iKKmSTW49hEKqDdMcQbxModb+A+ qEu+x8jHS02pE9jl8Mziwq6OO8taOt3GwpIX8bpEZw3GVIfEkkYHnTYy6r9FCclW+GFbPdRWtT5 hjM4aQZ4oLlF6KX+ccVLMIeuMZzB4VzPiq+IFkAgBz1bL5JeT8qjX78tpHuVNR247qXyse5g646 xXeCCfI5hXxtP9aEHqOW4ghMjJ+hUINnXB82HCEc3Fq+zuI+mERgOW4t7Ul2DsDp6wB X-Received: by 2002:a17:906:599c:b0:a9a:eeb:b263 with SMTP id a640c23a62f3a-aa509c0d7femr831025866b.58.1732475882512; Sun, 24 Nov 2024 11:18:02 -0800 (PST) Received: from lion.localdomain ([2a02:8109:888d:ff00:ca7f:54ff:fe52:4519]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28f848sm371874566b.36.2024.11.24.11.18.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 11:18:02 -0800 (PST) From: Caleb Connolly Date: Sun, 24 Nov 2024 20:17:57 +0100 Subject: [PATCH 15/15] qcom_defconfig: enable QCOM_SMEM MIME-Version: 1.0 Message-Id: <20241124-b4-modernise-smem-v1-15-b7852c11b67c@linaro.org> References: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> In-Reply-To: <20241124-b4-modernise-smem-v1-0-b7852c11b67c@linaro.org> To: Rayagonda Kokatanur , Tom Rini , Simon Glass , Caleb Connolly , Neil Armstrong , Sumit Garg , Mario Six Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=596; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=rjav2a8/SG5oSCZLcwsNWj1/xZr8bVLlTaBGS/39Uj4=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhnTn6ptbfwtmbD9r4pzxbVbO1FSN+ysSm/p9Z62JuPaq9 uj/nDXbO0pZGAQ5GGTFFFnETyyzbFp72V5j+4ILMHNYmUCGMHBxCsBEJnUy/LNo4X+9/+3K7vmL iyOD+e09rydNvMVctG3vIn737C9c8Y8ZGeZnWj85n6EfyPJgk2j6XFU5mz8TxErrXhVbP24sV5g dJgYA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Used to parse memory layout in some situations. Signed-off-by: Caleb Connolly --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 30f7b1c773fa..b49d897123c1 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -109,8 +109,9 @@ CONFIG_MSM_SERIAL=y CONFIG_MSM_GENI_SERIAL=y CONFIG_SOC_QCOM=y CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_RPMH=y +CONFIG_QCOM_SMEM=y CONFIG_SPMI_MSM=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y