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Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 1/8] hw/pci/pci_bus: Introduce PCIBusFlags::PCI_BUS_IO_ADDR0_ALLOWED Date: Mon, 25 Nov 2024 15:05:28 +0100 Message-ID: <20241125140535.4526-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Some machines need PCI buses to allow access at BAR0. Introduce the PCI_BUS_IO_ADDR0_ALLOWED flag and the pci_bus_allows_io_addr0_access() helper, so machines can set this flag during creation, similarly to how they do with the PCI_BUS_EXTENDED_CONFIG_SPACE flag. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci_bus.h | 6 ++++++ hw/pci/pci.c | 1 + 2 files changed, 7 insertions(+) diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index 2261312546..5c8b0d2887 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -26,6 +26,7 @@ enum PCIBusFlags { PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002, /* This is a CXL Type BUS */ PCI_BUS_CXL = 0x0004, + PCI_BUS_IO_ADDR0_ALLOWED = 0x0008, }; #define PCI_NO_PASID UINT32_MAX @@ -72,4 +73,9 @@ static inline bool pci_bus_allows_extended_config_space(PCIBus *bus) return !!(bus->flags & PCI_BUS_EXTENDED_CONFIG_SPACE); } +static inline bool pci_bus_allows_io_addr0_access(PCIBus *bus) +{ + return !!(bus->flags & PCI_BUS_IO_ADDR0_ALLOWED); +} + #endif /* QEMU_PCI_BUS_H */ diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 1416ae202c..de3f93646f 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -1475,6 +1475,7 @@ pcibus_t pci_bar_address(PCIDevice *d, MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); bool allow_0_address = mc->pci_allow_0_address; + allow_0_address |= pci_bus_allows_io_addr0_access(pci_get_bus(d)); if (type & PCI_BASE_ADDRESS_SPACE_IO) { if (!(cmd & PCI_COMMAND_IO)) { return PCI_BAR_UNMAPPED; From patchwork Mon Nov 25 14:05:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 845319 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp1198013wru; Mon, 25 Nov 2024 06:08:25 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXILdYikNI+HpJJaxG5bCbblUsMAhUXMrZfy2M3x1SAzFbfPxiXtHyTZOHeAYWKyXmHpOI7Nw==@linaro.org X-Google-Smtp-Source: AGHT+IHLZBBUF/g02bRG+LV7qWFXb9l/26pL6Il7oNgRdAThWhcwQtPuknu+T65GnDRl7dIA9MI5 X-Received: by 2002:a05:6512:3195:b0:53d:ddcc:5139 with SMTP id 2adb3069b0e04-53dddcc5273mr2568873e87.19.1732543705248; Mon, 25 Nov 2024 06:08:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732543705; cv=none; d=google.com; s=arc-20240605; b=U+ZrtFKMfKUfPrPTNCmty5Gd+Bh8bg20z882QyRLvraJfkESIk2P8sGFPTsgh8XzfC DboXxOLBoJy2YBLbz2K4zSemgIXU/hr3lnNCgV3xJpWMYqlLws+iwioujgHpWfCR/d22 MCBIRtOlRKdXxsznqMJ+YnlSLZitj/wYCzlEW5CxTpfjAHUNMbJRxlD3lQSHrbsE4pCr rRwxBWFVDM8GKWr/MSIzb/0aQ+52qTl6SboP7Gj+wHJws2Ei43VLirIwycg2EPN8khuV 3vFApmM79t2HwHUrtz1ujeGzpN8Zdnecm7ls+TzC2hqLOcMNib/0XF3G+Ft5b7Rem+cv OgZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cc3WE7woH120Qpt/FsE+B5ZgZ3+8Guj7ZUtw6nH9Jhk=; fh=01MTBs686u0z/v+1HBxc617dy4wgnTfT5lmRb9hvZO0=; b=eRLCtOUR+v79sYhJkYsIiFE+HuEeUhQtgqU/F5cOHmKdmGi2LlZkg59Q7KZ4f8yroC 2zn/bOOo3vKIqzdZtOrE2vZBDAQAMXOEOFrSvF0lyTtQZE/7RMTyXbwlSAg4NzgXVxFF vjF6d+w69VEMcNVtkbipbWx8nqORUZPioe5TOcK/SZyTeJ63Lq3M8Ups+RcIzw34qGoE 6wNd+tvyHeBJdZZQz2dto87skz4kCDhnoZkQ0Dx522e/bMbnrZzj5TrRKPn1G8spGN8J bvN+UYO8HfgB2G5bjt/EcYgw//JpwYCLpAvpLIKgFy5pk0XbmQInsc9B6Q8VpEzLXvf7 QYuA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A3hutD5V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 2/8] hw/ppc/spapr_pci: Set PCI_BUS_IO_ADDR0_ALLOWED flag in host bridge Date: Mon, 25 Nov 2024 15:05:29 +0100 Message-ID: <20241125140535.4526-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=philmd@linaro.org; helo=mail-lf1-x12b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org See commit e402463073 ("pci: allow 0 address for PCI IO/MEM regions"), all sPAPR machines set this flag. Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/spapr.c | 1 - hw/ppc/spapr_pci.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 5c02037c56..8af56bd68a 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4600,7 +4600,6 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) mc->default_display = "std"; mc->kvm_type = spapr_kvm_type; machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); - mc->pci_allow_0_address = true; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler = spapr_get_hotplug_handler; hc->pre_plug = spapr_machine_device_pre_plug; diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7e24084673..16f3a18d2e 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1888,6 +1888,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp) PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); + bus->flags |= PCI_BUS_IO_ADDR0_ALLOWED; /* * Despite resembling a vanilla PCI bus in most ways, the PAPR * para-virtualized PCI bus *does* permit PCI-E extended config From patchwork Mon Nov 25 14:05:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 845322 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp1198388wru; Mon, 25 Nov 2024 06:08:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVf1BB+AqELLMn2Oq3qTxoAm99f5if1pa80ZQREDwosDuCfOJWUAb/7GEmBPAMR2z7U/HKmPA==@linaro.org X-Google-Smtp-Source: AGHT+IH41gEFj9L+qAcGal+Z7eRdVW+o09iHySLszHE/TEjxrJZHFBRoWx9gUrCZTYS5RgyfJePU X-Received: by 2002:a5d:6487:0:b0:382:4b69:9ca4 with SMTP id ffacd0b85a97d-3826060d08cmr9526681f8f.26.1732543731363; Mon, 25 Nov 2024 06:08:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732543731; cv=none; d=google.com; s=arc-20240605; b=D0YeqU7mCwiNaYkeOon92G0L5z5mU2U0z4KeNMutEYJ7qDMdjkSKxCBZ+rV7SKLDN8 dWLENXi+Lz1HRdOoEdulJ4yvvOSEpmrkpvGWdefg8fYsHNYWIlfO/J2QNFEwd0I6gKeh gb98K0VmsDXF4t8ifUmuSjnUjttIigem3VGnaaK8QtJtwbOSQG9EV30sNQgpBr5jG9ht vRKM/fGKOy6uk+UfEW+C9N+Ned/s7f5La7X1q5uQ0Wndhs2iEVLV6pOwhmHvsqpFcb9i Rwu/bfLRT6k1Th+W4/QL8E/hRYzxhofzxzo3DbhLczd3wxpzVw4woJ8O/ptlgVEqbxQI JYVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nwOFcDol4u8ZIeIm4VbuTBCsXEbth7QSSqvQY7JvfPk=; fh=01MTBs686u0z/v+1HBxc617dy4wgnTfT5lmRb9hvZO0=; b=NOvzFQFGc81tfsxxlHbkQNSUn2ZWFVSoDHJyUmW8IeMOYWwZ75ahgnGR1AM10kTuee EpDTMfdCCupEzkBUoygVMsTQEsRFX9fnQz7XK1NOclVGV1Kxd8QQLChtamMYquTVpXdD l5KZ+pb55WzErfGeoqhib7Ia2SsjMbFlxxqfjE4qwT36rVOWn7ZXeO+syq8R3CUy0VIq V3Xqyc5Htruqbl8fHwIeP9+NssesOmtyBy6acDJSoovapMxPxq0lYCRSz8CjpiubVBgO fvUMM6dPmPDdG/YqBT2YJPkjJxAuehCFAa+lyQedmuLF83grIEvCKxpVjV0S9Og+0XTm GHIA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r8cgP8li; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 3/8] hw/pci-host/gpex: Allow machines to set PCI_BUS_IO_ADDR0_ALLOWED flag Date: Mon, 25 Nov 2024 15:05:30 +0100 Message-ID: <20241125140535.4526-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Expose the "allow-io-addr0-accesses" property so machines using a GPEX host bridge can set this flag on the bus. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci-host/gpex.h | 1 + hw/pci-host/gpex.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index dce883573b..8c990bff5f 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -64,6 +64,7 @@ struct GPEXHost { int irq_num[GPEX_NUM_IRQS]; bool allow_unmapped_accesses; + bool allow_io_addr0_accesses; struct GPEXConfig gpex_cfg; }; diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index e9cf455bf5..635467016f 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -32,6 +32,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/irq.h" +#include "hw/pci/pci_bus.h" #include "hw/pci-host/gpex.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -136,6 +137,9 @@ static void gpex_host_realize(DeviceState *dev, Error **errp) pci->bus = pci_register_root_bus(dev, "pcie.0", gpex_set_irq, pci_swizzle_map_irq_fn, s, &s->io_mmio, &s->io_ioport, 0, 4, TYPE_PCIE_BUS); + if (s->allow_io_addr0_accesses) { + pci->bus->flags |= PCI_BUS_IO_ADDR0_ALLOWED; + } pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq); qdev_realize(DEVICE(&s->gpex_root), BUS(pci->bus), &error_fatal); @@ -154,6 +158,8 @@ static Property gpex_host_properties[] = { */ DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost, allow_unmapped_accesses, true), + DEFINE_PROP_BOOL("allow-io-addr0-accesses", GPEXHost, + allow_io_addr0_accesses, false), DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0), DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0), DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0), From patchwork Mon Nov 25 14:05:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 845318 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp1197942wru; Mon, 25 Nov 2024 06:08:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWEkZZjY6P2OSvi4yoapJASIsQxgBWPhfLwjpEUfvRpQp9TGofjpEv+GTevHqnowBKEbmevjg==@linaro.org X-Google-Smtp-Source: AGHT+IEFAMY0Pmil3hgrJ/s2K7vheT1HuE+6UejABdQ3lDtZmw5CT//zI+bGsbuXqMBxjINzIUML X-Received: by 2002:a05:6000:2102:b0:382:3419:46e6 with SMTP id ffacd0b85a97d-38260be1efcmr8864164f8f.52.1732543699288; Mon, 25 Nov 2024 06:08:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732543699; cv=none; d=google.com; s=arc-20240605; b=fGfVXr3AOBeCQrl9vEQhdXSn9SS1B18N3ff4PMopsXFt01CERxk4cwbWMejVMXlu4u rXdCYXxUkBJJS9B2SdsbhVSOl3GlV530xaTDrXOk9GUA/nVBWfjHzJPUbfxD6vGFj+WN oDBmxqL+yXpAfmcLbi/QQnVJXF9M/4nw6IcswhzUazbTTbew8GQsyG5aX9p2CBdnsi2k 2XvZaxxHfeIBd9RYGTPjL7WafJHQog0cpB/B7XKf6gWB5lKSgrC2kfDpVt2F27HCzHQ5 6Hh4W42oaWK5tVE0J8AfS/XdKBtNro5JlRSKHN5/OUVQIHUhADqqqDG9dSHwoUbxiLAW L8gA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IiajgqU0R6qJd99dKLrlrhZ7TYSpLeZ4tGBPN+dLT/4=; fh=01MTBs686u0z/v+1HBxc617dy4wgnTfT5lmRb9hvZO0=; b=DkQ5i5xvgQNjribpHI16DbvBczku0uAaPyVev6iM6p0bTNXN4jW2RN56Yjb8wObIqE AsWTISFUEyEP4mCzihF/AlXL8GrWOGopdeDlo5L2OvAiB5+Sik2tN8qCMdoHHd7wIo2a 1i494Wxb6TeiixnirTIdwIOsmT9f0vDc1IIyv5g+ospW6vSdGpMPh2OLSKVc1ogVEJiQ NxMjgU+fSNpqEyv8VpOXMwnROPUNFDRHOchbRmt8kjQfcv+DaDydvCZyeNB0fLHByR49 poSof+B9aMFGWbNfswSuS7wxop7I+9wERnFOWT3fI/AqCeYTx0UyKtcoPSEcKnqkPAfZ YctQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hymtg7DN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 4/8] hw/arm/virt: Set PCI_BUS_IO_ADDR0_ALLOWED flag on GPEX host bridge Date: Mon, 25 Nov 2024 15:05:31 +0100 Message-ID: <20241125140535.4526-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org See commit 74de8c3568 ("hw/arm/virt: Allow zero address for PCI IO space"), all ARM Virt machines set this flag. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 1a381e9a2b..773df5f04b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1510,6 +1510,8 @@ static void create_pcie(VirtMachineState *vms) MachineClass *mc = MACHINE_GET_CLASS(ms); dev = qdev_new(TYPE_GPEX_HOST); + object_property_set_bool(OBJECT(dev), "allow-io-addr0-accesses", + true, &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); @@ -3124,7 +3126,6 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) #endif mc->block_default_type = IF_VIRTIO; mc->no_cdrom = 1; - mc->pci_allow_0_address = true; /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ mc->minimum_page_bits = 12; mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; From patchwork Mon Nov 25 14:05:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 845320 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp1198155wru; Mon, 25 Nov 2024 06:08:36 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXOOLVBlL1EcuxKHyiJXbHIBPTfiYJw9uZsFr5PIqjfFQmYPvp3hwMANxBNF1cV4tbh7RzPJQ==@linaro.org X-Google-Smtp-Source: AGHT+IEPPZfYR+hb30qZ4r0dd8rb0n6LV44PtgSx+/b5jr0CLabjrdTFI6L6XjzWztddW+HdsP4J X-Received: by 2002:a05:6000:400b:b0:382:4f70:10cf with SMTP id ffacd0b85a97d-38260b6213cmr11392609f8f.20.1732543713946; Mon, 25 Nov 2024 06:08:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732543713; cv=none; d=google.com; s=arc-20240605; b=FYgykI4Yc/5cdpgcI3w1BsZ+hxAMZDuWeTNCKX5iILY2AiAW7tIToUestFPLOpXsWp WUQaR3++Lp60JmrzVgbQLufzcEYDfOzTEOjeERP0bi/0nwGrOATDo1wUIOT2wvYtlHyz BrsksqsNO1WjnSwdkx+kO0w20REv76KasUGLtSgPQZbjFBCf37+/SeXB7MoEdNU0kWdq nGdk+u4aiPYoWca2JwQBcdBYDuQ1Tedc9WVAB4Oq/UkJLLUP24VH0+WU8VSzFQ4JKlDP W+s0WhlZ7zyxAJI8jQjuU3D3FNRUHQUt4UewjIqk0Yn+xoej+WpTiTmYROt6eOduiXrS Lk5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KEkIR2vBaISG4rMjnIPuSSQYyM7zelGC+1W4S9oVQCo=; fh=01MTBs686u0z/v+1HBxc617dy4wgnTfT5lmRb9hvZO0=; b=j9Z/Zfaf2WyC74Wd0GPK5Mqb6RaicKepyJqid7vo7ax+Kisxof9kfWrToogBl5qENE Ve6IjDSwlJAfpUTo7Qu/mDDmVnas5OK3SLEutDZISfDP0E2FSl16U+dzkQfW7F6dBm6S U97+CyvyGPVR+OsAzqqNYUsslV0fH+CuCGqv5ZyTgVYzrddAIyF0x1YIvoIXe2mf53a2 ei4D61YThVEH36c7MQiEQP/Dq04EnDO8VWtzaF+qJ5FVuSLNNDzgXcXoD2g0jTozx29d Jd2HiqFF9oWjpHaNAec2VACFTKijr7HkSUw0zATKTWm16sauw0jUxA10lWV4NctjgU+6 XcnA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rrKyp7u7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 5/8] hw/arm/sbsa-ref: Set PCI_BUS_IO_ADDR0_ALLOWED flag on GPEX host bridge Date: Mon, 25 Nov 2024 15:05:32 +0100 Message-ID: <20241125140535.4526-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=philmd@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All SBSA-Ref machines set this flag in MachineClass. Directly set it to the GPEX bridge. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/sbsa-ref.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index e3195d5449..988a0a236e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -647,6 +647,8 @@ static void create_pcie(SBSAMachineState *sms) int i; dev = qdev_new(TYPE_GPEX_HOST); + object_property_set_bool(OBJECT(dev), "allow-io-addr0-accesses", + true, &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); /* Map ECAM space */ @@ -896,7 +898,6 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n2"); mc->valid_cpu_types = valid_cpu_types; mc->max_cpus = 512; - mc->pci_allow_0_address = true; mc->minimum_page_bits = 12; mc->block_default_type = IF_IDE; mc->no_cdrom = 1; From patchwork Mon Nov 25 14:05:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 845324 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp1198936wru; Mon, 25 Nov 2024 06:09:41 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXVe6l+BWXqiBcFf8tLAFB7gZliijE9GwRiymni5jxx92YpbT46eQcgkuTa/pTmGKlI7vHHUQ==@linaro.org X-Google-Smtp-Source: AGHT+IGgWeUCf7B1wGOoiFNpKwqIVHi12vvM1kgQyYdv8to3+NAltx6JKwpK7uSGl+o7eWVoO0kg X-Received: by 2002:a05:600c:4447:b0:431:55bf:fe4 with SMTP id 5b1f17b1804b1-433ce491837mr113182635e9.24.1732543780972; Mon, 25 Nov 2024 06:09:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732543780; cv=none; d=google.com; s=arc-20240605; b=GZL0kLqyBxwva+ekdzStEDIG9J60kq7keO0c/8cI6cF+8/j1VCISeH3GFWw0iGVbnU 7BYUhjDzB+HZi4ax+HSVhVmQKcbBM0s+DMan0LRpXRrX/H3O3AeO9YndHj4yK6dFIYAd CRQFI/1uxwDaZ+BKpA+ewKlLWbvmSYOi9xsd1OuEdvA5cwXdgzLLjux0vQlOG9+Dgzd2 NllzJ9b6wHeXVfeibQlGOM+6gdY8IzfuAG6XS0LQ+ZF0du5tTJ7Umo3X2HGZpXhgTC5m wItwt4n4IQDoAVuD03P1ho5yyxzGwzv5A/wgVInrzDOdDuk6DcqPO60Pv5Zvl5wwQkNz j4LQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=CidC1DzNGex4xdl38okZ6dg7MoluQ+zRZMKK1keD2+U=; fh=01MTBs686u0z/v+1HBxc617dy4wgnTfT5lmRb9hvZO0=; b=HmlP77BaHj9h2P3oAz8gjPLPUuuSfB3+D2qPgrfNplDva6Cy9i/h73wTbrKtrmdXDL AFdH0xpH4s5jSxu9lf15R9hyhj4EFjcej+BppIsFVmTkkhxWiS6SoMPzDhCcPlixgEiD HKTR3mY4sptJbyi+k91yz1CLo/ymRo5ohQ74I58HaGC6Sp05UaIC8NQoRsCZQSL3pWiz LwC7YVztxY7gJ4xQKs2pPkgjQTGEbC9/tMD0w7bPp62Hp68f3u6TH3XJnBlqR1mQ5GE/ J2NQFqqBaInFzjFYciQZFSC1xqTo1VoP/hfRg+6mGcDBW69RDkIB8+MmKya2Kh8GI9ZT o/Ng==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LSk6hKme; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 6/8] hw/riscv/virt: Remove pointless GPEX_HOST() cast Date: Mon, 25 Nov 2024 15:05:33 +0100 Message-ID: <20241125140535.4526-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=philmd@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org No need to QOM-cast twice, since the intermediate value is not used. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- hw/riscv/virt.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 45a8c4f819..2feb851f15 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1140,23 +1140,21 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, dev = qdev_new(TYPE_GPEX_HOST); /* Set GPEX object properties for the virt machine */ - object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE, ecam_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE, ecam_size, NULL); - object_property_set_uint(OBJECT(GPEX_HOST(dev)), - PCI_HOST_BELOW_4G_MMIO_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE, mmio_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE, mmio_size, NULL); - object_property_set_uint(OBJECT(GPEX_HOST(dev)), - PCI_HOST_ABOVE_4G_MMIO_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE, high_mmio_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE, high_mmio_size, NULL); - object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE, pio_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, pio_size, NULL); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -1189,7 +1187,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); } - GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; + GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus; return dev; } From patchwork Mon Nov 25 14:05:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 845323 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp1198653wru; Mon, 25 Nov 2024 06:09:15 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV96CFuRby5rF0MokSVXjL/2Rey1z9TRl4NRyaz2lk9CS6/38y+vUncHt7jlWBdFmnGNW4SOg==@linaro.org X-Google-Smtp-Source: AGHT+IFWXLatquT5P8+fU9QeovtPkHiZj4p0plsmgreZIrZtSuiFtLlIq08iUzP3fgt6yluJN+Fv X-Received: by 2002:a5d:47c6:0:b0:382:5016:fd0b with SMTP id ffacd0b85a97d-38260be5406mr7351959f8f.50.1732543754676; Mon, 25 Nov 2024 06:09:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732543754; cv=none; d=google.com; s=arc-20240605; b=Et0NTIP8Bj9mwFedmkAbyqK6QsHzphY9Z5VXLdD2rgGzXObKsimIYuJuMU9sMNacjY /1hiLAv8qt0ufwQQ0YHzcqHgPGM1H13yMKTVE4paaj32XxseaBqYXu8MyC6O+z1taSFt yuSv24oFV23xVR8V4kE1Kg7sP4bSy9mfNRlX8IDqyzJAy5X2aDwj9DFZcfJcvQC3TDxD E/0/mV13JbgXYl1FSxB3FHZBqferyrn7cf0sEWTHAhSt6A4OfnzMHA64F7JvR1PT+a7W Y63S7DGaQ7RVQXExIOGYdiUXHOJYJisiWCh964OmU0L4t0c+9G8J6gvEe78x6JQFdRjk CnyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mBLNIub1rHgG9lgkZtJGEcAkQWIxnGXQvYMrFBUCUkM=; fh=01MTBs686u0z/v+1HBxc617dy4wgnTfT5lmRb9hvZO0=; b=aR45URSynXSGsKNq61XdczXESsbGgb0izXYGyEDmZQGUy+UG56wSvnbB2u3xzqI8EB vV5GSkcu0UiE6v7GdrikK9D/1bQ3d2Fy9pPyvlB2eYO26JgtgV6abqY78yNqXlEoJzKg +U0snSahgHH9ynXO6hc8sQHX7/FewGCY7NvPfAet0ybPA2sLXfAwPWWVjdcOM+Q7X/22 Zxcqu3Y5fdbIfU5s5SDLSYJ7SJ7mz+BYJsxzCBAidt/EMpRi1wXW2qNlEVOdmIw9b2h5 x+TG0BgcL2fW9Ch36uZRUuTy5vEzWf6KQGzbZsgD79pqlJJlF0i3wkstWuGubI5a+Eqt on7w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r49EAaOR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 7/8] hw/riscv/virt: Set PCI_BUS_IO_ADDR0_ALLOWED flag on GPEX host bridge Date: Mon, 25 Nov 2024 15:05:34 +0100 Message-ID: <20241125140535.4526-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=philmd@linaro.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org See commit acead54c78 ("riscv: virt: Allow PCI address 0") all RISCV Virt machines set this flag. Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2feb851f15..4e1ce3a423 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1156,6 +1156,8 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, pio_base, NULL); object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, pio_size, NULL); + object_property_set_bool(OBJECT(dev), "allow-io-addr0-accesses", + true, &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -1803,7 +1805,6 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = TYPE_RISCV_CPU_BASE; mc->block_default_type = IF_VIRTIO; mc->no_cdrom = 1; - mc->pci_allow_0_address = true; mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; From patchwork Mon Nov 25 14:05:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 845321 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp1198378wru; Mon, 25 Nov 2024 06:08:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXoDmMUzEDfi/5niWYNU+UPFSe1rDE/tUIgHg96RPPYdRYr7EUg9wGTlsmn7obo3EsDIMbGCw==@linaro.org X-Google-Smtp-Source: AGHT+IG+b5BnoaJ3C4PBmTmGbUht7SkmMgjzaucnyEAxil4zXsPZgOvLRw8M2wCXaAkB2a0mM5dG X-Received: by 2002:a05:600c:4690:b0:431:2b66:44f7 with SMTP id 5b1f17b1804b1-433ce4d4c6emr127758535e9.31.1732543731414; Mon, 25 Nov 2024 06:08:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732543731; cv=none; d=google.com; s=arc-20240605; b=TthBxJtcM80Pycg4tPCGOQPtgPkcln2xqs6Wtr2qHSu9RQTTA6DO+6iDogtGglD0ca pcQAbJ7g1hAif7t9NyvO9TMaNUKNTXlD1LdPvRMc79c/mWWgAw4LUUZjs37rpNMAE/kr fepj7rNLiSgGpfyheUHcOSYWYx6MH5gMLsIjNWwac2YEBjlHmmANsicYAQPDGUKSHkdE jDAJPnPLvax1KVvv+w6Z3aCBLpjIf5hInMumQNkZ/s8nPQABgio/KXZKJwVV5jZ0LSCy 9uSsMK0wUHG+LfIMOcSrCDh6ygb+jKjE24FpX8hG4FTuHEVBLyj6K9pRsV64G4DjJnui UEeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hhPIY1VBzTRWV9NVUC530URyYQIaOfJGukKvr94mbQc=; fh=01MTBs686u0z/v+1HBxc617dy4wgnTfT5lmRb9hvZO0=; b=SRjExQnhD0qOHSliCzCnmCrUfQuwsB/xlkbd8lkn4mIARgThk7JUs/JTWIROujNUH2 DIBObkMxuymhvtQ+ha/HWLT+QlDUPWwrevAhO2j3ru4Q6+uqOWXkd6R28j1O08WpohN+ SO2+DUX5eK0kSehii8nbeP4BRrfKEg+30s7QE11Vf5EZNDzMOTs3xOAqp9TW3FJr/VEn 5L/RFKc0MLBRXAZKp4lfCDGl0l1o/hT8vMgDJtxmVC9iLx36T6RpnQk3jVpxbS5RHtVu vi0s+wSANA5WclUrqJmMFg2K/nEyvB3C3kr1QePWY7wC/eaeuP8h+E+JocptwErJWIsj 6xZg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KTVO1eLk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 8/8] hw/pci/pci: Remove legacy MachineClass::pci_allow_0_address flag Date: Mon, 25 Nov 2024 15:05:35 +0100 Message-ID: <20241125140535.4526-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=philmd@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All users of this flag now set the PCI_BUS_IO_ADDR0_ALLOWED PCIBusFlags. Since there are no more users, remove the field in MachineClass. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/boards.h | 1 - hw/pci/pci.c | 5 +---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 36fbb9b59d..66fb2eddd3 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -284,7 +284,6 @@ struct MachineClass { no_floppy:1, no_cdrom:1, no_sdcard:1, - pci_allow_0_address:1, legacy_fw_cfg_order:1; bool is_default; const char *default_machine_opts; diff --git a/hw/pci/pci.c b/hw/pci/pci.c index de3f93646f..d27166dd75 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -45,7 +45,6 @@ #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "hw/hotplug.h" -#include "hw/boards.h" #include "qapi/error.h" #include "qemu/cutils.h" #include "pci-internal.h" @@ -1472,10 +1471,8 @@ pcibus_t pci_bar_address(PCIDevice *d, { pcibus_t new_addr, last_addr; uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); - MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); - bool allow_0_address = mc->pci_allow_0_address; + bool allow_0_address = pci_bus_allows_io_addr0_access(pci_get_bus(d)); - allow_0_address |= pci_bus_allows_io_addr0_access(pci_get_bus(d)); if (type & PCI_BASE_ADDRESS_SPACE_IO) { if (!(cmd & PCI_COMMAND_IO)) { return PCI_BAR_UNMAPPED;