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Fri, 29 Nov 2024 07:43:15 -0800 (PST) Received: from m1x-phil.lan ([176.176.147.124]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa5996df797sm188427366b.68.2024.11.29.07.43.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 29 Nov 2024 07:43:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , Bin Meng , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Palmer Dabbelt , Paolo Bonzini , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.0 1/3] MAINTAINERS: Cover RISC-V HTIF interface Date: Fri, 29 Nov 2024 16:43:02 +0100 Message-ID: <20241129154304.34946-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129154304.34946-1-philmd@linaro.org> References: <20241129154304.34946-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The HTIF interface is RISC-V specific, add it within the MAINTAINERS section covering hw/riscv/. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- IMHO 'RISC-V TCG CPUs' should cover target/riscv/ which are the accelerator-facing implementations, and each machine or device in hw/riscv/ should have its own section. Not going to clean that in this patch. --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2b1c4abed65..046e05dd28d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -324,8 +324,10 @@ S: Supported F: configs/targets/riscv* F: docs/system/target-riscv.rst F: target/riscv/ +F: hw/char/riscv_htif.c F: hw/riscv/ F: hw/intc/riscv* +F: include/hw/char/riscv_htif.h F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ From patchwork Fri Nov 29 15:43:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 846145 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp961699wrp; Fri, 29 Nov 2024 07:43:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVQdJ2hlrMpWixf1xNeQsUla4SyUq+Rh32lg+XGotMx2y4x0iBUQNa/3orRJD0IkWFEYk7E5g==@linaro.org X-Google-Smtp-Source: AGHT+IHWTtPbyxNnRbK9+gZkE7DM1/grFF5rZL1iYAnMrMTLbGHHpTH7wQLvp7WJvaEWEeN5qp6s X-Received: by 2002:a05:620a:6881:b0:7b6:6c6f:fb5c with SMTP id af79cd13be357-7b67c266c49mr1780737185a.15.1732895031691; Fri, 29 Nov 2024 07:43:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732895031; cv=none; d=google.com; s=arc-20240605; b=bX8zGSUGSuIqOrmCwUrsdku3CLE/ULoSnGb76GXpaDdzuGeodYpEunARZQzdLbl5g+ YOmvv5+aWtxfF9DoZBACGxGzVRs/OYEZk11oCombZqY7n++jQ8TPBe2YhxHz/GTSI8xf 5v2w5DsS8sL1sr7ER1zN6bg1aqaqu8/taWVjr52plwIw6uUyvjlAeOVQJV5wUcHA6T3z G4gAPk2C+zasHNplX2CtcHMQ7fIbRIZJtt8LlDt5vprzWun+OmCYmak1g+HWOTEUHF17 15+Bv8HEGkhM0Z6ciDRvC/P3/zEYAHy1vCPObInlmZxARYUWRBCj5iAplrhS9eJOkYXo TqCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=S4770bBXPnBP2gTFUY4zpq0rPST/rXd6Oo6sAl27oUs=; fh=8phz+9c/BelGAOF2Y4hh3pUo2o0wWrN0eFl1GvxvTtU=; b=Kh/2Ys0oRahiNBiCXo2bxt3Jj0b6LLJhEGB76ZL0ZRlJ2T/eJBXqs03toAk9/TPTTj WE5SVitnqB4cG7JqA/GQb+cjICpcLOq/Wk0HmIn+WBYiwsnr+JcOHH2N3PS7ie7CsF1g CP3znPDcOu39SE45y4WJFFZ4LSUtdVAp2bOjRuhEbVFlddUHW+/onmL4IBvi82guoMjb mhUIQGW8Uh6xXnfvTS2lWl3WqrVQcC7isvBofEp7HB62NbnYveKk62eZZOX0of81oPV1 HlRLRHjVr4UKH765DOzIeXas8UJdJo/rC/F6D8PQ2NOKG3YjgLZk2jfdO1irZagIXk5a Fa5g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eehNeRAY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 29 Nov 2024 07:43:21 -0800 (PST) Received: from m1x-phil.lan ([176.176.147.124]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa599973565sm183685666b.202.2024.11.29.07.43.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 29 Nov 2024 07:43:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , Bin Meng , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Palmer Dabbelt , Paolo Bonzini , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.0 2/3] hw/char/riscv_htif: Explicit little-endian implementation Date: Fri, 29 Nov 2024 16:43:03 +0100 Message-ID: <20241129154304.34946-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129154304.34946-1-philmd@linaro.org> References: <20241129154304.34946-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since our RISC-V system emulation is only built for little endian, the HTIF device aims to interface with little endian memory accesses, thus we can explicit htif_mm_ops:endianness being DEVICE_LITTLE_ENDIAN. In that case tswap64() is equivalent to le64_to_cpu(), as in "convert this 64-bit little-endian value into host cpu order". Replace to simplify. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- hw/char/riscv_htif.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 0345088e8b3..3f84d8d6738 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -29,7 +29,7 @@ #include "qemu/timer.h" #include "qemu/error-report.h" #include "exec/address-spaces.h" -#include "exec/tswap.h" +#include "qemu/bswap.h" #include "sysemu/dma.h" #include "sysemu/runstate.h" @@ -212,11 +212,11 @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) } else { uint64_t syscall[8]; cpu_physical_memory_read(payload, syscall, sizeof(syscall)); - if (tswap64(syscall[0]) == PK_SYS_WRITE && - tswap64(syscall[1]) == HTIF_DEV_CONSOLE && - tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) { + if (le64_to_cpu(syscall[0]) == PK_SYS_WRITE && + le64_to_cpu(syscall[1]) == HTIF_DEV_CONSOLE && + le64_to_cpu(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) { uint8_t ch; - cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1); + cpu_physical_memory_read(le64_to_cpu(syscall[2]), &ch, 1); /* * XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks @@ -324,6 +324,7 @@ static void htif_mm_write(void *opaque, hwaddr addr, static const MemoryRegionOps htif_mm_ops = { .read = htif_mm_read, .write = htif_mm_write, + .endianness = DEVICE_LITTLE_ENDIAN, }; HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, From patchwork Fri Nov 29 15:43:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 846144 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp961695wrp; Fri, 29 Nov 2024 07:43:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUNzs74OtFYQOXz9n2ro25zjWl8VWGZi/W6o0DPoDbpI00tyK4ZeWzku6fcoH04A+jWvmbSJA==@linaro.org X-Google-Smtp-Source: AGHT+IHEPK3+g2fRtGGi3ZJPSeuFq78uo/S6mwzmZ0JwzBtlevnu5JJjI/l4YF5lUGlWHYV9qXW3 X-Received: by 2002:ad4:5fc6:0:b0:6d4:215d:91c3 with SMTP id 6a1803df08f44-6d864d95c5amr199332196d6.28.1732895030868; Fri, 29 Nov 2024 07:43:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732895030; cv=none; d=google.com; s=arc-20240605; b=I+DHvxDdi0gNFsfcRmFJGk/AuY28auGM+cZeFbydf6tau6A2vyMyUVsaAI3TO9wfaA AgTNyA9yESM8VJt+Vg//ECLH/PF5qtQibK0ITNlH4Rg+yE1Zn3R70esKwg7227ILttgD s57QW4pQx2+3tV5qCgDlCHOjC78HjM4LHrodZ3zkDKCHLm5s7W27NdqmKyO59W/47efU HzKTs7VZM6tH1OAUlG9hAsS0eGzfs+L42LsO7DcLMMjM7EmXQYDUGuup5zB+h3eahVig deSTZZ3cVxEfqrAJCww9+MuoO3xGMnIINBgfRTINTooSFSKl7JxmUlRQ+GcgckmS9nBE L1kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Sg+SWcDqWlUzlCEJmd/1EXEzYbTMn5ymk45kdZhKOZs=; fh=8phz+9c/BelGAOF2Y4hh3pUo2o0wWrN0eFl1GvxvTtU=; b=HVXpI6lVtSTcDSIhkPejht9APPo2ku0sKweX3waVfuTi1POPa0rMYqUlDuWTEQnpaH puRkogZVdgXFC1xUCD2Q+vC6C/HmSwA71MeOd67ckp3HqbnvXbjmqDZ7aMmHUI4clTt4 oyJIoHXb9DeNNxefTJtxMbPTjVYdDmARTXv1OWo9cpDsJa1JbM9ItlwRVXF8Br6gHXDQ n6br6lbDarPYFW3kE4aFFzbwwhbu6PXBz3rzdlJF0DqPH6f2e8iqAOn2IwgwoqbOfBHL tu7kDFqHCXMTZ1iPk5rtfzu64How3qVL+XjLWhp3yt2yNJhjT23pUM1i1VWubhW81PoZ DWpg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zm2IcYYF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 29 Nov 2024 07:43:27 -0800 (PST) Received: from m1x-phil.lan ([176.176.147.124]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d097e8dcefsm2003596a12.55.2024.11.29.07.43.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 29 Nov 2024 07:43:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , Bin Meng , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Palmer Dabbelt , Paolo Bonzini , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.0 3/3] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses Date: Fri, 29 Nov 2024 16:43:04 +0100 Message-ID: <20241129154304.34946-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129154304.34946-1-philmd@linaro.org> References: <20241129154304.34946-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Looking at htif_mm_ops[] read/write handlers, we notice they expect 32-bit values to accumulate into to the 'fromhost' and 'tohost' 64-bit variables. Explicit by setting the .impl min/max fields. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- Notes 1/ these variables belong to HTIFState but are declared statically! static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr; 2/ I believe a 64-bit implementation would simplify the logic. 3/ This is a non-QOM device model! Signed-off-by: Philippe Mathieu-Daudé --- hw/char/riscv_htif.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 3f84d8d6738..db69b5e3ca7 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -325,6 +325,10 @@ static const MemoryRegionOps htif_mm_ops = { .read = htif_mm_read, .write = htif_mm_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,