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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 01/54] fpu: handle raising Invalid for infzero in pick_nan_muladd Date: Mon, 2 Dec 2024 13:12:54 +0000 Message-Id: <20241202131347.498124-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For IEEE fused multiply-add, the (0 * inf) + NaN case should raise Invalid for the multiplication of 0 by infinity. Currently we handle this in the per-architecture ifdef ladder in pickNaNMulAdd(). However, since this isn't really architecture specific we can hoist it up to the generic code. For the cases where the infzero test in pickNaNMulAdd was returning 2, we can delete the check entirely and allow the code to fall into the normal pick-a-NaN handling, because this will return 2 anyway (input 'c' being the only NaN in this case). For the cases where infzero was returning 3 to indicate "return the default NaN", we must retain that "return 3". For Arm, this looks like it might be a behaviour change because we used to set float_flag_invalid | float_flag_invalid_imz only if C is a quiet NaN. However, it is not, because Arm target code never looks at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we already raised float_flag_invalid via the "abc_mask & float_cmask_snan" check in pick_nan_muladd. For any target architecture using the "default implementation" at the bottom of the ifdef, this is a behaviour change but will be fixing a bug (where we failed to raise the Invalid exception for (0 * inf + QNaN). The architectures using the default case are: * hppa * i386 * sh4 * tricore The x86, Tricore and SH4 CPU architecture manuals are clear that this should have raised Invalid; HPPA is a bit vaguer but still seems clear enough. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-parts.c.inc | 13 +++++++------ fpu/softfloat-specialize.c.inc | 29 +---------------------------- 2 files changed, 8 insertions(+), 34 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index cc6e06b9761..d63cd957a19 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -66,19 +66,20 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, int ab_mask, int abc_mask) { int which; + bool infzero = (ab_mask == float_cmask_infzero); if (unlikely(abc_mask & float_cmask_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } - which = pickNaNMulAdd(a->cls, b->cls, c->cls, - ab_mask == float_cmask_infzero, s); + if (infzero) { + /* This is (0 * inf) + NaN or (inf * 0) + NaN */ + float_raise(float_flag_invalid | float_flag_invalid_imz, s); + } + + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); if (s->default_nan_mode || which == 3) { - /* - * Note that this check is after pickNaNMulAdd so that function - * has an opportunity to set the Invalid flag for infzero. - */ parts_default_nan(a, s); return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9bca03c4aed..c557c41b2af 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -480,7 +480,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * the default NaN */ if (infzero && is_qnan(c_cls)) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -507,7 +506,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * case sets InvalidOp and returns the default NaN */ if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } /* Prefer sNaN over qNaN, in the a, b, c order. */ @@ -529,10 +527,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -553,10 +547,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } + /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -576,10 +567,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * to return an input NaN if we have one (ie c) rather than generating * a default NaN */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB @@ -592,14 +579,9 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_RISCV) - /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - } return 3; /* default NaN */ #elif defined(TARGET_S390X) if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -617,11 +599,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 2; } #elif defined(TARGET_SPARC) - /* For (inf,0,nan) return c. */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* Prefer SNaN over QNaN, order C, B, A. */ if (is_snan(c_cls)) { return 2; @@ -641,10 +618,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns * an input NaN if we have one (ie c). */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } if (status->use_first_nan) { if (is_nan(a_cls)) { return 0; From patchwork Mon Dec 2 13:12:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846599 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1197045wrt; Mon, 2 Dec 2024 05:16:50 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWUo168vpAguaCHCiOHwmhG8QU0MC7+/IZfFZJmm95GE0ST7CcQzIRWtFi7g5ncE9lfngFQkw==@linaro.org X-Google-Smtp-Source: AGHT+IGxMiBLY3na2l0rCkVB0VdLd8NO0LiH1TiLJJkjoh26s+wMpck+ZqAXw0Dv24BY03/kV5s4 X-Received: by 2002:a05:6808:2206:b0:3e6:5f6:c2b5 with SMTP id 5614622812f47-3ea6dd48f48mr20239148b6e.26.1733145410381; Mon, 02 Dec 2024 05:16:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145410; cv=none; d=google.com; s=arc-20240605; b=HQAkZW/ndZ9eMrChkgajzaJdIfW3ZlMfHElJVnf85e7mW+tap94ROWelfvWgz9rnGL cNiEQLCZVhqPnHasBawRlftkKFWI/U/FBlSCYhPwTGyqjOAHY617PpRiYqkzv9sil34u 3i9GrJ4YnaUlFJ6drxHWoR5IALl4W5+yKlSqeH7kz1Onks9cJeB+5iFQKQpgXSh+JkOC xUwfBPDjPeqq4USxRjm6aKMyofFyZZt5YoWYq3iKcnyFKPdDicaiYXm2PA5prbZBjP8a ULsnmcavHm7nB13setG9YaERdfWtz/2Edm96MN0bfdJVKH4csreP+dKholBgZUKCjvEh 1nPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uI1GHeNAVBACaAOyrekRei9EE5yyDUO5Im1pzl3+9DM=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=KDPzYRye6ERTXg4nMZvsUEfZuWhLas00CsIXzxKefuHHobnAOZYH3DFCeQic2Mw09K pC9tGFho+9FRrQzGgr7KmMhO0jKSnTYJAuKTCooPGuz1LYHlYB+PFEBPjgKrzrKoIUEq zFqWwt7R5z/Q1OLf31p+92fSkaU+N2B4bfKtOZIfT058FLQUHrceZeZYWnkcmsyObk49 BK184Iq4Mi7DnBVlwJQuG3HhH5mIq5HX0Ibm6Q3BTn4ePwK+GSh2tB1nxloJSbtnMwZC yyb7wiO1lAIFtfW6GRqDEj+bRYpprzNvI+WkDvMmdUa4cQKzBbT+29+tOWW9QAgtkAAC +wrg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D5ei9pNm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 02/54] fpu: Check for default_nan_mode before calling pickNaNMulAdd Date: Mon, 2 Dec 2024 13:12:55 +0000 Message-Id: <20241202131347.498124-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If the target sets default_nan_mode then we're always going to return the default NaN, and pickNaNMulAdd() no longer has any side effects. For consistency with pickNaN(), check for default_nan_mode before calling pickNaNMulAdd(). When we convert pickNaNMulAdd() to allow runtime selection of the NaN propagation rule, this means we won't have to make the targets which use default_nan_mode also set a propagation rule. Since RiscV always uses default_nan_mode, this allows us to remove its ifdef case from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-parts.c.inc | 8 ++++++-- fpu/softfloat-specialize.c.inc | 9 +++++++-- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index d63cd957a19..aac1f9cd28c 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -77,9 +77,13 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, float_raise(float_flag_invalid | float_flag_invalid_imz, s); } - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + if (s->default_nan_mode) { + which = 3; + } else { + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + } - if (s->default_nan_mode || which == 3) { + if (which == 3) { parts_default_nan(a, s); return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c557c41b2af..81a67eb67b5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,13 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { + /* + * We guarantee not to require the target to tell us how to + * pick a NaN if we're always returning the default NaN. + * But if we're not in default-NaN mode then the target must + * specify. + */ + assert(!status->default_nan_mode); #if defined(TARGET_ARM) /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN @@ -578,8 +585,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 1; } -#elif defined(TARGET_RISCV) - return 3; /* default NaN */ #elif defined(TARGET_S390X) if (infzero) { return 3; From patchwork Mon Dec 2 13:12:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846597 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1195815wrt; Mon, 2 Dec 2024 05:15:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVsBt3KYvXoBJTJRf5NOFt8oaU3bvdZMnGoIagm4ss8zhGislG69mO/pUaXolSnkVR0YsI/Eg==@linaro.org X-Google-Smtp-Source: AGHT+IH1m93qs+4Ei8S0mWGZkFRoXU2ubYZVLdFoe8JhBPT2rqBJl/riHBIe2UMawKIMUqJBk7cp X-Received: by 2002:a05:6808:2f0a:b0:3e7:b9be:52cc with SMTP id 5614622812f47-3ea6db61ff7mr20003540b6e.6.1733145315937; Mon, 02 Dec 2024 05:15:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145315; cv=none; d=google.com; s=arc-20240605; b=eXRDWgypWEXOsU94zw//ZgKOwi+4gq4JCAtB+vHX4tRcZYrXBA5S9tFizhviljjuLi SJkrHPTWEg9rt2qi5+0FRUKVMT8cJmM9wk3bzz0UVhtkFFPoVYCZqW7HveGlTLMi7FKM vRs+BEF8ooJ2Pp7a1BRaaEfrPpg3ftfa3pb6TXsDbkvzVOY0N/kDZFIn4Y3iMRhJ1iAW V9rFegWs0HyK+ikp1WShc8/t2Ohg50yQ8PiUUU4m4Mrqw1ciE/n4DDeq5RxhHbPUUOIn l4Qa6Cs3nzu0hgJ3PS2MyeCUH3E9Sh9tnK62TBNfGyWiMVtay1VBiqWfvVPyMupWLpvi lMDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=v4zzS01bYybKsGEAJxbtpX4MUEAVNVSp3HeO2uhMqBQ=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=FZ2ZULNdIrNJ1scPoHxPdnPllIRS6CNXlZ+jsXhZAEoaGH1Oz4wU7iNyxkdf+zNQEt oAHAv9m3NdRjBgyzKVIcDenGCRMhxuF7K89i6xBqCK+Yq/XIZSGxf/kXCkZBsvrj9WyF Ujg2tEHNeICjCLCbhYjuk47LPQV3QsJP0xqE88PxW+ReQEDufahvXdApu4qmLfH175sk eDMS3q6Hh++soC7MfML8qyp3MEMh/hCDKQOGofpRWZgzFsP7kn5aGaWO5IGAj2E6X85j NsKxCXkTYBqdL/CL53qx3HizvecIETZ6pyq7LQvWADAM3auZTMhuwB0+Iaxom1CRWlvh ytIw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QqxYOHpG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 03/54] softfloat: Allow runtime choice of inf * 0 + NaN result Date: Mon, 2 Dec 2024 13:12:56 +0000 Message-Id: <20241202131347.498124-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org IEEE 758 does not define a fixed rule for what NaN to return in the case of a fused multiply-add of inf * 0 + NaN. Different architectures thus do different things: * some return the default NaN * some return the input NaN * Arm returns the default NaN if the input NaN is quiet, and the input NaN if it is signalling We want to make this logic be runtime selected rather than hardcoded into the binary, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime In this commit we add an enum for the propagation rule, the field in float_status, and the corresponding getters and setters. We change pickNaNMulAdd to honour this, but because all targets still leave this field at its default 0 value, the fallback logic will pick the rule type with the old ifdef ladder. Note that four architectures both use the muladd softfloat functions and did not have a branch of the ifdef ladder to specify their behaviour (and so were ending up with the "default" case, probably wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set default_nan_mode, and so will never get into pickNaNMulAdd(). For HPPA and i386 we retain the same behaviour as the old default-case, which is to not ever return the default NaN. This might not be correct but it is not a behaviour change. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: float_infzeronan_dnan_never shouldn't be the same value as float_infzeronan_none --- include/fpu/softfloat-helpers.h | 11 ++++ include/fpu/softfloat-types.h | 23 +++++++++ fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++----------- 3 files changed, 95 insertions(+), 30 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 453188de70b..0bf44dc6087 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -81,6 +81,12 @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, status->float_2nan_prop_rule = rule; } +static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, + float_status *status) +{ + status->float_infzeronan_rule = rule; +} + static inline void set_flush_to_zero(bool val, float_status *status) { status->flush_to_zero = val; @@ -137,6 +143,11 @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) return status->float_2nan_prop_rule; } +static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) +{ + return status->float_infzeronan_rule; +} + static inline bool get_flush_to_zero(float_status *status) { return status->flush_to_zero; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8f39691dfd0..47bb22c4e25 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -207,6 +207,28 @@ typedef enum __attribute__((__packed__)) { float_2nan_prop_x87, } Float2NaNPropRule; +/* + * Rule for result of fused multiply-add 0 * Inf + NaN. + * This must be a NaN, but implementations differ on whether this + * is the input NaN or the default NaN. + * + * You don't need to set this if default_nan_mode is enabled. + * When not in default-NaN mode, it is an error for the target + * not to set the rule in float_status if it uses muladd, and we + * will assert if we need to handle an input NaN and no rule was + * selected. + */ +typedef enum __attribute__((__packed__)) { + /* No propagation rule specified */ + float_infzeronan_none = 0, + /* Result is never the default NaN (so always the input NaN) */ + float_infzeronan_dnan_never, + /* Result is always the default NaN */ + float_infzeronan_dnan_always, + /* Result is the default NaN if the input NaN is quiet */ + float_infzeronan_dnan_if_qnan, +} FloatInfZeroNaNRule; + /* * Floating Point Status. Individual architectures may maintain * several versions of float_status for different functions. The @@ -219,6 +241,7 @@ typedef struct float_status { FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; Float2NaNPropRule float_2nan_prop_rule; + FloatInfZeroNaNRule float_infzeronan_rule; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ bool flush_to_zero; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 81a67eb67b5..f5b422e07b5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { + FloatInfZeroNaNRule rule = status->float_infzeronan_rule; + /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -482,14 +484,68 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * specify. */ assert(!status->default_nan_mode); + + if (rule == float_infzeronan_none) { + /* + * Temporarily fall back to ifdef ladder + */ #if defined(TARGET_ARM) - /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns - * the default NaN - */ - if (infzero && is_qnan(c_cls)) { - return 3; + /* + * For ARM, the (inf,zero,qnan) case returns the default NaN, + * but (inf,zero,snan) returns the input NaN. + */ + rule = float_infzeronan_dnan_if_qnan; +#elif defined(TARGET_MIPS) + if (snan_bit_is_one(status)) { + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN + */ + rule = float_infzeronan_dnan_always; + } else { + /* + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + rule = float_infzeronan_dnan_never; + } +#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ + defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ + defined(TARGET_I386) || defined(TARGET_LOONGARCH) + /* + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + /* + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer + * to return an input NaN if we have one (ie c) rather than generating + * a default NaN + */ + rule = float_infzeronan_dnan_never; +#elif defined(TARGET_S390X) + rule = float_infzeronan_dnan_always; +#endif } + if (infzero) { + /* + * Inf * 0 + NaN -- some implementations return the default NaN here, + * and some return the input NaN. + */ + switch (rule) { + case float_infzeronan_dnan_never: + return 2; + case float_infzeronan_dnan_always: + return 3; + case float_infzeronan_dnan_if_qnan: + return is_qnan(c_cls) ? 3 : 2; + default: + g_assert_not_reached(); + } + } + +#if defined(TARGET_ARM) + /* This looks different from the ARM ARM pseudocode, because the ARM ARM * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. */ @@ -508,13 +564,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } #elif defined(TARGET_MIPS) if (snan_bit_is_one(status)) { - /* - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) - * case sets InvalidOp and returns the default NaN - */ - if (infzero) { - return 3; - } /* Prefer sNaN over qNaN, in the a, b, c order. */ if (is_snan(a_cls)) { return 0; @@ -530,10 +579,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 2; } } else { - /* - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -550,11 +595,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } #elif defined(TARGET_LOONGARCH64) - /* - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ - /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -570,11 +610,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_PPC) - /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer - * to return an input NaN if we have one (ie c) rather than generating - * a default NaN - */ - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB */ @@ -586,10 +621,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_S390X) - if (infzero) { - return 3; - } - if (is_snan(a_cls)) { return 0; } else if (is_snan(b_cls)) { From patchwork Mon Dec 2 13:12:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846598 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1196321wrt; Mon, 2 Dec 2024 05:15:54 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCULwpksEttRxPCvCa7dVnrUmd2kMFktoR6+t00UBCeGz46KQnOOhxLwt3NtTUsIS98PqtVAsA==@linaro.org X-Google-Smtp-Source: AGHT+IGahI2Q0SXNc6veCgT3YGanBac0wpW+THmUtKout6iAlZvg6yWE1kbpYLNaF1C3WuEbkQi/ X-Received: by 2002:a05:6358:703:b0:1ca:9094:4f52 with SMTP id e5c5f4694b2df-1cab15d1275mr794411255d.10.1733145353939; Mon, 02 Dec 2024 05:15:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145353; cv=none; d=google.com; s=arc-20240605; b=PTliy8eWDSbmW0/eHpNCI6n1TBtcF8Xo5y8jMjCTy4XZOPFXq9IBiXUEZzja/aM+ZU ucdfG18cCgy78043JU2zHX0ISyKaVHUinaoPHEAabKfuLzYonGzob/VDzMun44pWJO/K 1tRSLrRmBQyh1veYOUA9WZGBkUHSx+ltJYY2i2nuYOrEtGf+MH/kI4ysuZB4Wnx9dyDu Rr0QSFszW55CaxqH1eion+oPpxky/6GSeksCC1KNCawS8l0WnUr/mQodCLvUFnFMePB/ vsgNt8JepADLpv77g8AVhjbZmrxwKPSvOGTo8c+i0RlCYUeEqTm/v5mQgNmbGBJMVaUj vt+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OkwmxObRxprUaJij2XbynAGv6Fy1VFYe1VACXWXiwGA=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=WX46X741jDBQSL2cXeI7FDahyhRwEdYORLC9YqfFVhO1mY5kcZdo8AV8nIk9kxqKpI r02+iFP5n1TRgxqEJ6O1gOXNvur+/OiF0ZGtd+fgnaPFyQ+L1t0wWgJrcom2hRuKVWpC 7trultKa4oiOUf9Q8q9XAF7gc729pJhQxJ4DUZbUxZPMhWvOyftdFRweKma0N+nBt/TB FWvTrm9BM+hlP37A0B9tbfa6xmbXiJev8XltD0FU55irfMpT2PKSrrbNINIPNSXYycSW xmplo8yN+ltxvNwRwlLXniXjzVJtywIMVeh2yQ3fwnVplb1/EwORPCmX4FY2ZQeNWASO 1EXw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cc8YgfeM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 04/54] tests/fp: Explicitly set inf-zero-nan rule Date: Mon, 2 Dec 2024 13:12:57 +0000 Message-Id: <20241202131347.498124-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Explicitly set a rule in the softfloat tests for the inf-zero-nan muladd special case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_infzeronan_dnan_if_qnan. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- tests/fp/fp-bench.c | 5 +++++ tests/fp/fp-test.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 75c07d5d1f1..fde64836194 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -488,7 +488,12 @@ static void run_bench(void) { bench_func_t f; + /* + * These implementation-defined choices for various things IEEE + * doesn't specify match those used by the Arm architecture. + */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); f = bench_funcs[operation][precision]; g_assert(f); diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 5f6f25c8821..251c278ede9 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -935,7 +935,12 @@ void run_test(void) { unsigned int i; + /* + * These implementation-defined choices for various things IEEE + * doesn't specify match those used by the Arm architecture. + */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); verCases_maxErrorCount = n_max_errors; From patchwork Mon Dec 2 13:12:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846602 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1197716wrt; Mon, 2 Dec 2024 05:17:33 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUCTg832Ic8PtZCIeWHTSwCB4YjuDqMYfwM+hHRVwIHetj2VMmpvCIJVcUNpUdB2qeyJ7z5aQ==@linaro.org X-Google-Smtp-Source: AGHT+IH5zspqCQtThgKoNqJzVeJplMzsR729wB6Q9JqDYiV6dpJFIp7/aAxXa4E0tnwviaRoTjDl X-Received: by 2002:a05:620a:454c:b0:7b6:6701:7a4c with SMTP id af79cd13be357-7b67c4aa7fcmr3136681785a.62.1733145453725; Mon, 02 Dec 2024 05:17:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145453; cv=none; d=google.com; s=arc-20240605; b=eCfWggXl4RqJoHfhLwMc7zcW+6yys9OABpPtfROBt247IXR6SlHTPRMwo9HOi0uqLY X5XPF9H5NBMMt/WRAcMCUgU9QPJyL65mxCrBMgyr8PyIibLS3MkCV2mxAJJbGXuCiznm H7bAxAjnNK49PcDawMxpMscBb28Xda18fMHHfIKL85LKY5iGcz+1NqODQ3jYqgPD4fSn 152wxbWLHo02brQsk9xu1agZ/CdrRmXqe7LJiugQeP7DbJ8cFNdfXjiJtD2ayNs1OywO aWFYusWKYpcrhfWu6EiSlsuRIIYW7+xyBOdGfNBEvFcLUnpjttR28wiiV4bkMWFRQ94t /aiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=X86TKVmBDvN75raroOS5cqB5k378L/9aSAueAeunYPY=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=KXqAtLTokypEKhNblOBIUlJpOzmyCi51LSajBoaG0aC8ygHPaNGpxhOicEOu0IUOzl HfiUqwK+HRzR8qags07K25YyP0kkYOOPQhthJhRI82EbqO/ErweY6POE+5Q+pf7d0s7n +7UUr85eMazNUtNRy3qieawOcQIvRozNwjLZORvGtKMEhkwy1AZTw91ws3chyNrbXtXB 8TGupy8TpcdgmD/9Xq+qZ9ZZ51Vl9LSgkTtNf6U79u6pBpxHRRsAi18TZ8RJY8Rgr2zN tPobmT9uI7nVbZzqXzmdtrO0mKi2z0GhdQHnoZdaB1wJYdC1KY1tshkJKZOOqule0X7z WDaQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xSTlkBXm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 05/54] target/arm: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:12:58 +0000 Message-Id: <20241202131347.498124-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the Arm target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +------- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6938161b954..ead39793985 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,11 +173,14 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, + * and the input NaN if it is signalling */ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f5b422e07b5..b3ffa54f368 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,13 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_ARM) - /* - * For ARM, the (inf,zero,qnan) case returns the default NaN, - * but (inf,zero,snan) returns the input NaN. - */ - rule = float_infzeronan_dnan_if_qnan; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { /* * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) From patchwork Mon Dec 2 13:12:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846608 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1202506wrt; Mon, 2 Dec 2024 05:24:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWwNdIUKKi3zxl7EmN94WZCa2owOdXUliA78gk3w51OGvKOT5xwNghmQj2bMN8ZgaDJfWRWnQ==@linaro.org X-Google-Smtp-Source: AGHT+IHyEitEf7QxtNp6X1qtt8gVU3CM9FzSf/ixwljLq3c4/FNXSJgw+03qkliEGa17nzMj65Mn X-Received: by 2002:a05:622a:20b:b0:463:8e7d:d4d6 with SMTP id d75a77b69052e-466b36457fdmr397208141cf.37.1733145859045; Mon, 02 Dec 2024 05:24:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145859; cv=none; d=google.com; s=arc-20240605; b=GU5QEG5Ep+W7zQtI6sVNp3PEtHwvtEYMmKyRS3iQ6WfI7ol5XcNsnKDEE+/BOgx3SM K0zQawidqEUIkEHxb6ydxuCvCepgLqXWMOPSnVn6ImY/OEiTCEzJWZDcfIhZBhVMJHxm MWmLEuaoMQRQSCX/aUsRF0nrKWx+1kQwalDA97zNd9Ajq/5U+Pu+D2t7JetK9y64COaF y3vS4l2MnG2XIB3H2N3rtqBL/WPagJbYXtHVLnaN13YPfLnKgxRamiL86aBrEORDc9Fx UxObwZKx1ibtikQr7a8UZAiUQCUZ1axAgqh1QrO4VHpqRxQkqEX5w0kVHLBsv9xb5QI3 /4Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=04rCvvMWBdPOtJMZYEuwTadqTTp/Q9o9M7TcBLMjcm0=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=B0ecxMrKP6kKTIzhy5BoS7Fc+CGsQn+eU1LNAQWbsbhV2kz1RhhqAne+dDSrVRt3qx bm9+qBokOZnBCABmOevNYX5uYrP08mk0p5PBgQYbUSEEN30dtPHgtQ+hHS+PIzg2h9+C hFaEj+SKwnJrtPl291jbXNPkPSEIDLTusq8T+5KU1R9lYp8XvOlDFX/8IZLxUe/LAVcf qjj92Om2LYWV5/0YQhNJouiyHH+Vx3yzfg4M8MD7v8K6kBWi/OLKJ/S01y+iRES1QSqy LMfLabItQtxv5nnxS/BX8hLu3lMriAxRFvXmipHag5RMbae2qOZqYZX4KHTACrhRL9Qm 3D/g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jG5Vec1C; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 06/54] target/s390: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:12:59 +0000 Message-Id: <20241202131347.498124-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for s390, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/s390x/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 514c70f3010..d5941b5b9df 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -206,6 +206,8 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_detect_tininess(float_tininess_before_rounding, &env->fpu_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); + set_float_infzeronan_rule(float_infzeronan_dnan_always, + &env->fpu_status); /* fall through */ case RESET_TYPE_S390_CPU_NORMAL: env->psw.mask &= ~PSW_MASK_RI; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b3ffa54f368..db914ddbb1c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -516,8 +516,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * a default NaN */ rule = float_infzeronan_dnan_never; -#elif defined(TARGET_S390X) - rule = float_infzeronan_dnan_always; #endif } From patchwork Mon Dec 2 13:13:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846600 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1197195wrt; Mon, 2 Dec 2024 05:16:58 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWC2S+UPBb0TaZGBOJJJJ9tctvNelJn76Tsa3FWuzvYg264woOqMwho5UHVbXtaBLytTZ4gdA==@linaro.org X-Google-Smtp-Source: AGHT+IFeQRqq0HG34JyDKcuFObPIHf427SiBYlfL+v1gd2Y1yXkxWgZWL1eJK1PYAliGH1t0jV3m X-Received: by 2002:a05:6102:b04:b0:4af:1614:858f with SMTP id ada2fe7eead31-4af5574dd8amr21220547137.12.1733145418538; Mon, 02 Dec 2024 05:16:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145418; cv=none; d=google.com; s=arc-20240605; b=aIiRlgbbU442r2lt96m/8U5Hza6F2DkvUkoLzTnN1IeYJJbO5ceDZSqW+TWFCwFGtm 52qDjZ6UkfX+iwVkEY4zdy+ORcS7LBKSRmxd17mk+/vNqyUjNqS/G5slz8Jr+gZSRzNi OFuV8+z67geHZAwCfvkqc15K3+wCmt+VtDKaEjtx+af4Se4YmyXXgz0MXmK0EST+27vb bWROMhz5yY+Ute+d4V9mWBi3pUjmPzJjqpgMnryULKTsDG9HfudC5SUzrUJllMldV7w/ mNPHq7ft+GOWcfEBCDgXs82e6f6/64nFtiX9selFlPW8+6pdHzOVgbGyPF6sIjyBhWnC ZkxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HfpQEPdfErqnjNX6r5VLZdc7V0ZgOPNgi8c10TCw4Tg=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=hQyJ+0XSQGxRt3U7CkLomzzqHzFBcbLrJq7VSvaQTPRJU+RbzU1fg//S/h0EOkkiGR hdKL9VIuYPMqnb0kwZ9X6PRrX4ITmBKW6ilhtEuPoZtTDcerr3kd5Mr4phGabDPOT8fD z6ukQWMnZx8ep7P8wyN/ywb4baenaA/gwC55pzjFSLVaMPmDVuNHrkguSq7/YkPqY3VA 4P2clWegX2FgztJpG55XXwIS6NA+PglvQw6ko/gpczreRIvMUC6OWnCrG+rcLvDnOWY4 UK5sDNY/tK7tkk9tBeyU+Y3gfAoYjH/kzEtJfHlL2HrK1NrXrYHBDX6wjBtJ8NDguxju GqwA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X7A1roEw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 07/54] target/ppc: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:00 +0000 Message-Id: <20241202131347.498124-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the PPC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 7 +------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index efcb80d1c25..f18908a643a 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7270,6 +7270,13 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); + /* + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer + * to return an input NaN if we have one (ie c) rather than generating + * a default NaN + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr = &env->spr_cb[i]; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index db914ddbb1c..2023b2bd632 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -503,18 +503,13 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, */ rule = float_infzeronan_dnan_never; } -#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ +#elif defined(TARGET_SPARC) || \ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - /* - * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer - * to return an input NaN if we have one (ie c) rather than generating - * a default NaN - */ rule = float_infzeronan_dnan_never; #endif } From patchwork Mon Dec 2 13:13:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846643 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1213953wrt; Mon, 2 Dec 2024 05:41:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVKUMUx3FkNx0CNxzwO3fOHBIaIovwNS7aQCs641oMOVQccBWoAB/KPz0g5jRwqlfAyaCMGOg==@linaro.org X-Google-Smtp-Source: AGHT+IGcbyRQcjeQuF/H4mkDZgB7v9cw9MdnLzq1u35uaq+zHZ3uuIpA1J4t/cepTBsKKs2qji1h X-Received: by 2002:a05:620a:1a8e:b0:7b6:6e7e:5b1f with SMTP id af79cd13be357-7b67c278e42mr2999626785a.18.1733146907031; Mon, 02 Dec 2024 05:41:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146907; cv=none; d=google.com; s=arc-20240605; b=PxpH4Kgm8KnV1fd1CBdnColsqeq/1glNdmtWf1Xb4nfrEUzhLle4J0ZvJ1WoJWm1w0 GThZ2KSkvIgTrds7V1hB0BL55dX05z+8PvaG9EW7p2YsM1mplWsL1CweQCallDwGS+wF udAnlH2qelQIN6AGGtxmYNhQCsJyFuM63hkYwKB6czxDsVGAUkrYJ6UcHpNheenVggZj Q25yofFoGIj0nx4hHZry7iw0YGcHZzcWoTUkekwDx+kj1dnQkTYK7b3WPNnMYrkYpSxp JOHYdB4fB+8HJw8SgAKtSWO7JTxrqWuwos1NJM9KHMTUTQkHrVN0xoEnFmABAXevB0Tp LPLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=q4kNtCiwJHe+Pk4Qi2sHCtONsH6gpm3d9+pTiscaZow=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=ZF8SK/mZZb0Jj37kjvRcvGcGudOOZig2bN4t/DCsqoOurJ+u1FLvkMEr989shS39MY ySga5nwiu3Zq9Wc/ngis8AFHyealco6+IMw1RPqu0uxhbGgghjOFFN5GPq4dtqtRyEYJ r92pDpNEY2qr6oSXEA4vt//4n+des7akBq7A88gyni5WNW0jZoeQ+Qik5ReW5VUOxP4d 4WRyiH5oV2R3I1FJL7jgDnhXgzyH30AXq/X4FYw74OwNjDXuA46bLNtfwyHGxyK6syxO IS5KHIeYSTNuiV9GTBSX3k5p3hvo4h3dL9Gvo5kL4Uon7pcIlTE0KRWq9q2vMaSWmXr2 r4mQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CJKipe4c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 08/54] target/mips: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:01 +0000 Message-Id: <20241202131347.498124-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the MIPS target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/mips/fpu_helper.h | 9 +++++++++ target/mips/msa.c | 4 ++++ fpu/softfloat-specialize.c.inc | 16 +--------------- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index 7c3c7897b45..be66f2f813a 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -28,6 +28,7 @@ static inline void restore_flush_mode(CPUMIPSState *env) static inline void restore_snan_bit_mode(CPUMIPSState *env) { bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); + FloatInfZeroNaNRule izn_rule; /* * With nan2008, SNaNs are silenced in the usual way. @@ -35,6 +36,14 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) */ set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN. + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c'. + */ + izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; + set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); } static inline void restore_fp_status(CPUMIPSState *env) diff --git a/target/mips/msa.c b/target/mips/msa.c index 9dffc428f5c..cc152db27f9 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -74,4 +74,8 @@ void msa_reset(CPUMIPSState *env) /* set proper signanling bit meaning ("1" means "quiet") */ set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); + + /* Inf * 0 + NaN returns the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, + &env->active_tc.msa_fp_status); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 2023b2bd632..db9a466e05b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,21 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - /* - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) - * case sets InvalidOp and returns the default NaN - */ - rule = float_infzeronan_dnan_always; - } else { - /* - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ - rule = float_infzeronan_dnan_never; - } -#elif defined(TARGET_SPARC) || \ +#if defined(TARGET_SPARC) || \ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* From patchwork Mon Dec 2 13:13:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846649 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1216481wrt; Mon, 2 Dec 2024 05:46:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXIm3I8uMWTl5Eao5xYrKYGS6N58N2UlhyXUX2LD8Uu1jRu2Mgujh/ZvC+COeWyWM6/aaY15Q==@linaro.org X-Google-Smtp-Source: AGHT+IF1N6ubeIoV/1Wz9bCosQG3Q6087GwtJY3t4r2Oe3M+tCjfbOvmePafY1mn6xbSyXGtQ75R X-Received: by 2002:a05:620a:8013:b0:7b6:72bc:df67 with SMTP id af79cd13be357-7b67c250380mr3632028785a.1.1733147160973; Mon, 02 Dec 2024 05:46:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733147160; cv=none; d=google.com; s=arc-20240605; b=g1xbOtDjXx22yFIGWEFVAB6Z83ZGK8KkRzPKFI3LAK/c4y+fUcSGEIzTRj1tM8n74X NrUTON60ZG8VQgAQz6rhmZktRL0eSJD2IgWuJSHSSLOH7btvhX5ufeEdm1VZyNFP2t/i +UMBOx+bX5SNU/nl2LLlasKJVYUqjxi0s5L5J3UWUA2+HWzofYGVDIgsnaaRYOSgXU3w 2v2NiaM3JLCsi6TMFJYr1otCXZaYssGS5ReiTauKpQMlo425J3Ov2+XJNDC48EXKmD3b XOL77/YCW/dbp1EjaMenrPQMBh/g8rLGm8XtXFG3/QE3863YB3o44HNTf0a7/SWSJtTZ qrtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kkb6PbnkCxHke0j4zsNXKqcSWFA8ovR1gPxWc3WytsM=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=VB1bh1vnowwzD5u2/3XN6UNQUcNamKh5KgoP2s/3rYIG284Ul+Mq/qr1RB5iTnViEg ZRLO3mvCH2zgzaAUBsZxl/ksvLj99v0NeZCMSMlTZUkPjv9O59HMG3/wS7IEeyUdhfaJ 11u56HPjDHLnl99PeeVk8GJyQjByAjLFIVp8MYGiA/WmKITUBVmOKgFy3/mOlvcdqssk qNQqVwwBAMrhNHhV7WYLTbJt1NNkg4dKJ9S3P2bdck+8def1ADBts/OdTT9zvYZjxx72 zB7BwJNbPGmu7Mwx/KWNsd5nsg6wHA6lMWhIaokvPN1eboqf4tUvvruL8QD31a/ATHF6 +Acw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YJfNazbb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 09/54] target/sparc: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:02 +0000 Message-Id: <20241202131347.498124-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the SPARC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index dd7af86de73..61f2d3fbf23 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) * the CPU state struct so it won't get zeroed on reset. */ set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index db9a466e05b..7e57e85348b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,8 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_SPARC) || \ - defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) From patchwork Mon Dec 2 13:13:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846648 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1216452wrt; Mon, 2 Dec 2024 05:45:58 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWiHtdmxD8zUfLNMTevmrX0qSXqw5x9cQRxEV5jka0RgrY4uGZFOZEUpw/Ou4Tlguc2OZ9LYQ==@linaro.org X-Google-Smtp-Source: AGHT+IEf/I4Su3On0eFUe0yykKXLZeXDeNe2sVeyoDGLO5DkaUOUuAGhGNF74LgGm4inLpDGhBKw X-Received: by 2002:a05:6214:194f:b0:6d4:586:6292 with SMTP id 6a1803df08f44-6d864d795f1mr325583526d6.26.1733147158264; Mon, 02 Dec 2024 05:45:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733147158; cv=none; d=google.com; s=arc-20240605; b=jYfX/p/K2hffuZQoxV/AY15c4HSEKzTzIB4M77h3346CwZg2bHK5BlCpn2T9HM9S4j Tm9fuT5aIuIdrnCOvtMPJ7rxUUALjBe3iSWXZwvknb8pi+cLcBamcFJ+ioxj1xHNp2To p1tQx1+HjeSk0qls5g83HRFT7YIbT3L8cmyu9OEg0UM1I9pMLwCEX+ECAua+C6xjgVyH JTyXKGTFQhSqauZmMbtPpmLden1KxjdOXjuJwMZfTMf90idc3+4w+4VKjE6Mxm7L/RVV vTFBA0/+4L0PN1Q83nnFX1ZiaIex+nQ6+towDa8DTzOUvloaNmCn02NpQQWi6PyPvsTP 59TQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uAvUlUwIT6mon/4ZVWSLpgO6VDhWersS5LUlGU6M2Ag=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=DqaC0EZi2LC1L+VixoPjsUUBMVs52SLgH6+Nw36dJrQr/Jv4BMLPM7tfwkfLdHHnZz jvzoZM8JLMS2H+kOMgjxvsWOmRmz6ZFBkl+YxQ1Nq/vJKGLfxPChzrPUBQuSX2MkS9/L oxj0d1wzSkz1awvkqjMDjub1YkPHYhw8IOpweVe9qaGukK5MiwXDVp8rLf+jQVr4qv6n 6rVC9gAAC/py33Op+Gg9fKsOyUONqBZtaqlSn6gAa8KnuqbAF2KdE9Y5QjQM90Cx7vDS uUiIjfBQklIHRLqQIc24RET2MPtMVRrJ8e0ZFCRTOo/M/Mt+ifdg0PdfYOt64ixDvxni b3CA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hRopcZuP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 10/54] target/xtensa: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:03 +0000 Message-Id: <20241202131347.498124-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the xtensa target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/xtensa/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6f9039abaee..3163b758235 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -133,6 +133,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) reset_mmu(env); cs->halted = env->runstall; #endif + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_no_signaling_nans(!dfpu, &env->fp_status); xtensa_use_first_nan(env, !dfpu); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 7e57e85348b..3062d19402d 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,7 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) From patchwork Mon Dec 2 13:13:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846612 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1204993wrt; Mon, 2 Dec 2024 05:28:08 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUe/4wlUrpm4/aFz50Y5uhy7Gvb66aQRxHeqUY6WmcAXu4KE+WghrLmTEAK1RioGK2V1yz7VQ==@linaro.org X-Google-Smtp-Source: AGHT+IFhCyuoi8YXQHZKjvJ6N90jXtlVpzDzHJ4FZX8N2kQ59mehViDwZhr26U38H3myAJoAHn+Q X-Received: by 2002:a05:6214:c47:b0:6d8:7e03:c427 with SMTP id 6a1803df08f44-6d8b2ff4d13mr4918876d6.20.1733146088228; Mon, 02 Dec 2024 05:28:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146088; cv=none; d=google.com; s=arc-20240605; b=YBZjRw0ni6dwzL6wo3UFJsKgDH7C64kg9Tnnkd/DWahRS6d+GbJk1iQ0YmMgJV7vjW xEZDOLs4x2hBuxu6chm2j7xlvTKd3DyRxQv0Bh6QH1JWi4z/3J0RdsqbSiXaQ93NyONv hDWpfjsBYdF0XCBTsuqZR/l0/b6OLoQB3tWaPAD/7DtIUF4qPnwlTwVJTFfMycgNJVgh aBYLZGaJhdxy3Z5iWTUMm1nxC69cSrNnRBVuFpVfQdQ2tJD59D4HmTZxo8L2vqo/EMv5 yncTZo6yY4yOCnoJ2XtSc3YR4NRUZMaRZDPyvuUCi9T39FaJxENiBW7QVKz781LtOIBY eF3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iLWBUHvjOah3un3/57/rPBpB/Wh0uSx2UDmLN935xs0=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=RsYwxjdS5J5j1G+O1PHh/O0ve8u9mD6FZuOYNiYD8Tutrfufa5vH51GAEjBBJF9/SU F4A/vAMpbkJSqkYOZ7BINA1ypb+qSqSkSaMQoV8LhzF+px35JaBj8RODdgDTnom64hF0 /FFiREnWO7qYYnhPnLDNjpV0JSEL2sEdbRpq6iWikhXRvXUbOfSh3nsHbaMghAV3xR7n 3BH3LByq8xJVjYCxwN/oeT5QeLHyOOVRQeNi/9dCz5h9PuLsjnem/RRoKElJNy7UrG32 7dWod80LSDuyyvFipkDmXSZ6UbQSa0TY258acOTH75sRBHbxDaoRuWv6wTr0+MHUChm/ kBVA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z+s9kM6o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 11/54] target/x86: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:04 +0000 Message-Id: <20241202131347.498124-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the x86 target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: Update the comment to give the info from the x86 spec rather than a TODO comment saying we need to check it... --- target/i386/tcg/fpu_helper.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 53b49bb2977..a98b4f67ff0 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -173,6 +173,13 @@ void cpu_init_fp_statuses(CPUX86State *env) */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); + /* + * Only SSE has multiply-add instructions. In the SDM Section 14.5.2 + * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is + * specified -- for 0 * inf + NaN the input NaN is selected, and if + * there are multiple input NaNs athey are selected in the order a, b, c. + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3062d19402d..ad4f7096d09 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -490,7 +490,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * Temporarily fall back to ifdef ladder */ #if defined(TARGET_HPPA) || \ - defined(TARGET_I386) || defined(TARGET_LOONGARCH) + defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' From patchwork Mon Dec 2 13:13:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846614 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1205195wrt; Mon, 2 Dec 2024 05:28:30 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW2BmuMrFY+ltZWr2amG/qes0iX0QwriHNBxCAllgfDcbJXMDDPa/NApWVYWzC45eJ+l9MiwA==@linaro.org X-Google-Smtp-Source: AGHT+IE90yb4B1wJapTlqUhlhdDLg2atJsnn9qEVMu2/f5Yi/lzUZ0il6UuMza+QTrM/DTU6RhGN X-Received: by 2002:ac8:7e86:0:b0:463:59f2:1835 with SMTP id d75a77b69052e-466b366855bmr268760081cf.54.1733146110303; Mon, 02 Dec 2024 05:28:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146110; cv=none; d=google.com; s=arc-20240605; b=QVFcmrJShDytz76LINB2cHPyCkFcuz+5P03vPOX0TEJcvBffbty1P2aiQlmKM8k1+2 ZoDC/XJV5WJweARIieIg1ASJgWGko635vpRNZa36aqHcPKu7SeLvVZNt0ETPwyuLm4fc u/aUJFajuCk68JHZKA/NbkOEwcN0kgvK0Ft6urf/Bv2Z67pe+xCHPeWdXERdIzPHTFDK 9aZ/OJs8bR65mWXA86Mn8ghgF4s1Pua+qif6VXX/dq82XTnuCovFkF0EF+YahB/IncKw AUemoY0QG058NzoCVRkE4qETvzDlLSGdf6B9YjzLZs4AZdg50ztAmX6tvYFXMoMm/lSH boig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hfWcIGFElRwNWX99Qr3KLu7RlocWXtaK9gnVDhRhWYA=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=PGl3QuEen76Y+k/Lik/uXnZ881IYzrH5lKlqXC+YaHHSmzD1kroTs4UiOrwRUuv4/V RVg9fur9ZuPCqw+v01BOCi3HX848TatvxOGo2wNYkbwecj0hD7FWu/ruVig5g8M/Y2Vg P+x2S3z8FqGDfawoGyAzgxDJhT5oylmXDq6i8HNI+1yhtI2oPbm1sLHNau0CjyTMgEYY qIUSEF3KN6O3PqXQ6s+jBDp6s1NAL+jzrgHS9VqCyHQ9XRcMN9KHy9tgba8Et02a3q63 JsODMdLxty+JUQM2LawAuXvnGZ2YaEvB4x0SWvzIVnyqztkUT07H5h3FOucgw1TuWvPx E4SA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rYQ36UQv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 12/54] target/loongarch: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:05 +0000 Message-Id: <20241202131347.498124-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the loongarch target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/loongarch/tcg/fpu_helper.c | 5 +++++ fpu/softfloat-specialize.c.inc | 7 +------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 21bc3b04a96..6a2c4b5b1db 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -32,6 +32,11 @@ void restore_fp_status(CPULoongArchState *env) &env->fp_status); set_flush_to_zero(0, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ad4f7096d09..05dec2fcb4c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,12 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_HPPA) || \ - defined(TARGET_LOONGARCH) - /* - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ +#if defined(TARGET_HPPA) rule = float_infzeronan_dnan_never; #endif } From patchwork Mon Dec 2 13:13:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846601 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1197361wrt; Mon, 2 Dec 2024 05:17:09 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUPltcz72vlv2O+KD7VjvPVeTBM+yu/19RAjTUvxyd0280R6U/HIo7BJEQ+FOVhcFckOVgV7Q==@linaro.org X-Google-Smtp-Source: AGHT+IHUKOE2Bz/D8ozEimswwgQf2PAbDMq5lxENvCDDoYcXYV3usBs1N0GFQn7wxSL8Zy51hVOq X-Received: by 2002:a05:6830:911:b0:717:fdbb:146d with SMTP id 46e09a7af769-71d65c7f843mr15097017a34.2.1733145429150; Mon, 02 Dec 2024 05:17:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145429; cv=none; d=google.com; s=arc-20240605; b=JbxfDWypnl+qXQKN5Jmd2HRmwkKaJM0iqx9t43+MvdE0t3B8/WJK0gYpQ3hMrsBva8 w8dRIPdJ4PKXmCMPIxt19YhxsQ6Ge8U5MyuhhnznbG4tUw85FhoKrEeCYu0IrAMonF7l NbTYWSeSswCmhLyrObNZI3rr5B2qm0ScDqp2fUmvJfkUB/bQRidXLaglOrYNCeHkS7aG Vm4weKWxOTywTs/1PCaraQ8hnGm13vf5nXp7CWbACOCmO307UozWGvpaSGvwrfD6wH0c EmqZM0jYDwgyduZEeHTjNIJA/lURydi2bXfc1pc2lp/9mG69zEoMKqp+/tPERWXlf2U0 Dcyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=r8XgmjddIhM612jj3JENDu5XxtMOP1j+6PXpvtg3rDM=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=BGvJ0QMBuXB/UGyCIx3uqZjNHtZXkh1VhIo+ZgKn5r+tOoum5RPqVFv7Ic8JitY7Bs CJ0dganuyKDsPCX6odUTWNkSl9ouH3KGTuGPmjEVbgy9Mbdck7Js5qav5LG5gWtb2xBB luxzxaveKagZWik7CkOJjyTRZrgoLLydva1cmpKqrwOmwBtfHYJO5lVW/PhbpYUxEMXM XFnLKNHH/LXoIXrKGIglvtg0V5fJFEYZjx/uyvcxOkBunFDjF15JwFywn9slbnkns086 cjO/b9APd+Es3ZVJAt5NtTjh5xzg91WEnTRUrC6UnwV0ju9gwOWQtMjtAhzVNzru77sU 1hOQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uoX88bBc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 13/54] target/hppa: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:06 +0000 Message-Id: <20241202131347.498124-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the HPPA target, so we can remove the ifdef from pickNaNMulAdd(). As this is the last target to be converted to explicitly setting the rule, we can remove the fallback code in pickNaNMulAdd() entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hppa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 13 +------------ 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 0e44074ba82..393cae33bf9 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -55,6 +55,8 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) * HPPA does note implement a CPU reset method at all... */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 05dec2fcb4c..3e4ec938b25 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,8 +475,6 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { - FloatInfZeroNaNRule rule = status->float_infzeronan_rule; - /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -485,21 +483,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, */ assert(!status->default_nan_mode); - if (rule == float_infzeronan_none) { - /* - * Temporarily fall back to ifdef ladder - */ -#if defined(TARGET_HPPA) - rule = float_infzeronan_dnan_never; -#endif - } - if (infzero) { /* * Inf * 0 + NaN -- some implementations return the default NaN here, * and some return the input NaN. */ - switch (rule) { + switch (status->float_infzeronan_rule) { case float_infzeronan_dnan_never: return 2; case float_infzeronan_dnan_always: From patchwork Mon Dec 2 13:13:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846606 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1201696wrt; Mon, 2 Dec 2024 05:23:04 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXpdkmWpS8I4ytna2pZ+/6qfaEMkzWO9XRfHj4WfG1FE8Mo8+E4l6IN5zWlmkyc4c7DnGENwg==@linaro.org X-Google-Smtp-Source: AGHT+IGVdegNFJH7Rwvck4tJ+LLRbPBzZW6osE0azzBLJwPjh+OHNNxfNr9Hp4KB1cxFD+f7EOpQ X-Received: by 2002:ac8:5889:0:b0:466:b1b2:6f0d with SMTP id d75a77b69052e-466b3645d0dmr354297181cf.36.1733145784606; Mon, 02 Dec 2024 05:23:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145784; cv=none; d=google.com; s=arc-20240605; b=WqXv5Sqscs+SmmSoUaf4SVwa+cvgPSQpdBIPn3Lgs/qlHgZ7fhkY/82+SF+Arj90H9 CpBO3qddi5aj/BB4w0myOCigHUZ5X9oDDwp+i1Am8NPGXsSrufzc+ZXfcQGf+ij3l6SA H2gQnLHSBF58XGX0IX/hZ3y5pq4If7HrlATwp22NaLFSNZ/nn9jX5wZcvqq9UG6d1fq8 sfQv1VFb94X3RsDcy1bwg+gtZNS+b9+DSBwLBGLrSEJBYGTaHtOXDXi0dcKg5A02UrO2 IbOdsz+MNNHyYrdon4JQEVmUeecRT1Gv2dq/iEQYGxBOSWWuwu2G7DFr4Gsd2D7dWbNY X6AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ILG1Z/M6B7uFxp4kFKW2IzoAsh4FqMmE+eh75zkfLko=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=La1Ksf5vZYur4Xxu+wEP3P2ZExcSoxaPcQ5qqqEHjzEEuPzYazeI6wbBYdCruj/Tg7 0MU0heKUMLd4bOnne3ojo2Bjx1T9LuzlTLY+Mk/2Y/6VXRRUTZWkb/piva1S/zeKbJDd HRYAKvWNdH+R3PCbdKxZcQS+TA3qwpalvgEtPY4HYnjd8nijd0YK7wreMlz6Ppw455va vcRGj4QmF6T8kS18IqbVcpl1yWt+yySmRcZVwGYwopnCjP+QZJM3nzzcsoLqCYA8h6Vw bD4UfG3ezctOUhregScMr5YOzRT1lcyA+8zoEwEuF+HMFtAvQF7L7D4/ZLXLkpFD0YTy btwg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FiXc4x5z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 14/54] softfloat: Pass have_snan to pickNaNMulAdd Date: Mon, 2 Dec 2024 13:13:07 +0000 Message-Id: <20241202131347.498124-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The new implementation of pickNaNMulAdd() will find it convenient to know whether at least one of the three arguments to the muladd was a signaling NaN. We already calculate that in the caller, so pass it in as a new bool have_snan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-parts.c.inc | 5 +++-- fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index aac1f9cd28c..655b7d9da51 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -67,8 +67,9 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, { int which; bool infzero = (ab_mask == float_cmask_infzero); + bool have_snan = (abc_mask & float_cmask_snan); - if (unlikely(abc_mask & float_cmask_snan)) { + if (unlikely(have_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } @@ -80,7 +81,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, if (s->default_nan_mode) { which = 3; } else { - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); } if (which == 3) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3e4ec938b25..a769c71f545 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -473,7 +473,7 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN *----------------------------------------------------------------------------*/ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, - bool infzero, float_status *status) + bool infzero, bool have_snan, float_status *status) { /* * We guarantee not to require the target to tell us how to From patchwork Mon Dec 2 13:13:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846640 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1213515wrt; Mon, 2 Dec 2024 05:40:59 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV4h4QZU8Odk+KSUFMSX/UfmwaIqc0gWcZH0EFasRtcw4dS8QWz4LMZk1vdBHzAczpMZt3QHg==@linaro.org X-Google-Smtp-Source: AGHT+IHGyCwp+JtuhV+3qze/czcGa/a1ciIK8fJTLkC9iqKhfPEoCHxebQhhpyy/4urBq/TWD8zq X-Received: by 2002:a05:6214:28b:b0:6d8:86c8:c29a with SMTP id 6a1803df08f44-6d886c8c8a3mr189715446d6.10.1733146859337; Mon, 02 Dec 2024 05:40:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146859; cv=none; d=google.com; s=arc-20240605; b=TLU7JhVVqWZuqdhBpRUok5Fnk/UGEnZpo0oQj0XGsGdlCb503E10ZOlAYVH7jxwu5f FKRXKBZMOTVFrOQgjIVV6fRdjiy/2H+8eRaXw2bmqVBcusP0cBFBEeut/i2z1vXQrXnq 0bFhejFMr227f4/a4lt5fm4+hLdHOKl1JIlwIRU4kq/JJ65PVMUjBLSJloSHKQx5zUYi utFWsM7Nmj8EmzFfuz376bPrGlhL1cCTFvY+TxXKQcF7gKwFIzyW5nr/TrgW/HNRCYz+ pUnle+BYy+T+izKFI8nieeScki1fklZEBA+J2qJhn1XVLtX5SPpMG1rhDTnVxHRpvHKW LpCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Z7XmwuWfuj/+3cn8NxGnH6Ft8d9tN3X6vv1sP/vbV6k=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=Uh1Y4tFgHi9Fx/c4KKL7JJXjrw6ZKZGvAm+sk4AHhh0Dd8AYhsgHQhoDpgcc/4ZzUd pea76Bx4W3EUW61+y67UycHFcbANfDIun+veDmXncv2ZybAUcNqFNBtp+snJWLSWfTtH vJ+6tcrFZ8PF/vEyYApCTmF9HHbSnmELhi2NtgrOavyqtfQFcMT1x9oturZ6pY9fhc8b c8LQQVmIILN0+lZpodObkOQck9Qa10cL4K/ZVzQQqhTiRfk1/4mupb0pwuR9pTbBUQs9 wekcZhlm/apdHAcJVfw5doEydhQcRvArKkFHIMuT7dtmEDiz45dQMYvvLHf5Axb9dFQJ 0T6w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gc7cwTmx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 15/54] softfloat: Allow runtime choice of NaN propagation for muladd Date: Mon, 2 Dec 2024 13:13:08 +0000 Message-Id: <20241202131347.498124-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org IEEE 758 does not define a fixed rule for which NaN to pick as the result if both operands of a 3-operand fused multiply-add operation are NaNs. As a result different architectures have ended up with different rules for propagating NaNs. QEMU currently hardcodes the NaN propagation logic into the binary because pickNaNMulAdd() has an ifdef ladder for different targets. We want to make the propagation rule instead be selectable at runtime, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime In this commit we add an enum for the propagation rule, the field in float_status, and the corresponding getters and setters. We change pickNaNMulAdd to honour this, but because all targets still leave this field at its default 0 value, the fallback logic will pick the rule type with the old ifdef ladder. It's valid not to set a propagation rule if default_nan_mode is enabled, because in that case there's no need to pick a NaN; all the callers of pickNaNMulAdd() catch this case and skip calling it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/fpu/softfloat-helpers.h | 11 +++ include/fpu/softfloat-types.h | 55 +++++++++++ fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------ 3 files changed, 107 insertions(+), 126 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 0bf44dc6087..cf06b4e16bf 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -81,6 +81,12 @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, status->float_2nan_prop_rule = rule; } +static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule, + float_status *status) +{ + status->float_3nan_prop_rule = rule; +} + static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, float_status *status) { @@ -143,6 +149,11 @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) return status->float_2nan_prop_rule; } +static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status) +{ + return status->float_3nan_prop_rule; +} + static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) { return status->float_infzeronan_rule; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 47bb22c4e25..d9f0797edaf 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -80,6 +80,8 @@ this code that are retained. #ifndef SOFTFLOAT_TYPES_H #define SOFTFLOAT_TYPES_H +#include "hw/registerfields.h" + /* * Software IEC/IEEE floating-point types. */ @@ -207,6 +209,58 @@ typedef enum __attribute__((__packed__)) { float_2nan_prop_x87, } Float2NaNPropRule; +/* + * 3-input NaN propagation rule, for fused multiply-add. Individual + * architectures have different rules for which input NaN is + * propagated to the output when there is more than one NaN on the + * input. + * + * If default_nan_mode is enabled then it is valid not to set a NaN + * propagation rule, because the softfloat code guarantees not to try + * to pick a NaN to propagate in default NaN mode. When not in + * default-NaN mode, it is an error for the target not to set the rule + * in float_status if it uses a muladd, and we will assert if we need + * to handle an input NaN and no rule was selected. + * + * The naming scheme for Float3NaNPropRule values is: + * float_3nan_prop_s_abc: + * = "Prefer SNaN over QNaN, then operand A over B over C" + * float_3nan_prop_abc: + * = "Prefer A over B over C regardless of SNaN vs QNAN" + * + * For QEMU, the multiply-add operation is A * B + C. + */ + +/* + * We set the Float3NaNPropRule enum values up so we can select the + * right value in pickNaNMulAdd in a data driven way. + */ +FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */ +FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */ +FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */ +FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */ + +#define PROPRULE(X, Y, Z) \ + ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT)) + +typedef enum __attribute__((__packed__)) { + float_3nan_prop_none = 0, /* No propagation rule specified */ + float_3nan_prop_abc = PROPRULE(0, 1, 2), + float_3nan_prop_acb = PROPRULE(0, 2, 1), + float_3nan_prop_bac = PROPRULE(1, 0, 2), + float_3nan_prop_bca = PROPRULE(1, 2, 0), + float_3nan_prop_cab = PROPRULE(2, 0, 1), + float_3nan_prop_cba = PROPRULE(2, 1, 0), + float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK, + float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK, + float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK, + float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK, + float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK, + float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK, +} Float3NaNPropRule; + +#undef PROPRULE + /* * Rule for result of fused multiply-add 0 * Inf + NaN. * This must be a NaN, but implementations differ on whether this @@ -241,6 +295,7 @@ typedef struct float_status { FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; Float2NaNPropRule float_2nan_prop_rule; + Float3NaNPropRule float_3nan_prop_rule; FloatInfZeroNaNRule float_infzeronan_rule; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index a769c71f545..b4f3f0efa82 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,10 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, bool have_snan, float_status *status) { + FloatClass cls[3] = { a_cls, b_cls, c_cls }; + Float3NaNPropRule rule = status->float_3nan_prop_rule; + int which; + /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -500,145 +504,56 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } + if (rule == float_3nan_prop_none) { #if defined(TARGET_ARM) - - /* This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. - */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } + /* + * This looks different from the ARM ARM pseudocode, because the ARM ARM + * puts the operands to a fused mac operation (a*b)+c in the order c,a,b + */ + rule = float_3nan_prop_s_cab; #elif defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; + if (snan_bit_is_one(status)) { + rule = float_3nan_prop_s_abc; } else { - return 2; + rule = float_3nan_prop_s_cab; } - } else { - /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } - } #elif defined(TARGET_LOONGARCH64) - /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } + rule = float_3nan_prop_s_cab; #elif defined(TARGET_PPC) - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB - */ - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(c_cls)) { - return 2; - } else { - return 1; - } + /* + * If fRA is a NaN return it; otherwise if fRB is a NaN return it; + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB + */ + rule = float_3nan_prop_acb; #elif defined(TARGET_S390X) - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 2; - } + rule = float_3nan_prop_s_abc; #elif defined(TARGET_SPARC) - /* Prefer SNaN over QNaN, order C, B, A. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 0; - } + rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) - /* - * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns - * an input NaN if we have one (ie c). - */ - if (status->use_first_nan) { - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(b_cls)) { - return 1; + if (status->use_first_nan) { + rule = float_3nan_prop_abc; } else { - return 2; + rule = float_3nan_prop_cba; } - } else { - if (is_nan(c_cls)) { - return 2; - } else if (is_nan(b_cls)) { - return 1; - } else { - return 0; - } - } #else - /* A default implementation: prefer a to b to c. - * This is unlikely to actually match any real implementation. - */ - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(b_cls)) { - return 1; - } else { - return 2; - } + rule = float_3nan_prop_abc; #endif + } + + assert(rule != float_3nan_prop_none); + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { + /* We have at least one SNaN input and should prefer it */ + do { + which = rule & R_3NAN_1ST_MASK; + rule >>= R_3NAN_1ST_LENGTH; + } while (!is_snan(cls[which])); + } else { + do { + which = rule & R_3NAN_1ST_MASK; + rule >>= R_3NAN_1ST_LENGTH; + } while (!is_nan(cls[which])); + } + return which; } /*---------------------------------------------------------------------------- From patchwork Mon Dec 2 13:13:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846633 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1211482wrt; Mon, 2 Dec 2024 05:37:35 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXprnOoLOQfW/gDr4VsP0QTsCdQS2+IkUaaU5ioFqD8OxOwMFRelErbb7f28u6v0aTurATWpA==@linaro.org X-Google-Smtp-Source: AGHT+IEl/Ls2ITXKBAo8XJSyniKeeL/yQVgQ3bn/7SwY/jNk+0TZZpfCkF8gWsRF+qXjLub5fYYX X-Received: by 2002:a05:622a:588d:b0:466:949a:de51 with SMTP id d75a77b69052e-466b34f2c07mr411029561cf.19.1733146655546; Mon, 02 Dec 2024 05:37:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146655; cv=none; d=google.com; s=arc-20240605; b=g4veor37YYKtSG2cMX+CyC+6vLTHABp/9pZ1CHbPgIb3hEAg6hwxiBzuZClKG0jhiy MTSlqJb8XEa+ly7/xXj5rPAI+0N5CVzykqvyC4noyDAy9ecqR+PxjpfDVWmRqswtudqW FdkR8LIXD+R8p3d5kiNqfC1usf1HVpY1NBx94gD4k72BNwIge/zf+Ht+6fcRMSg6Ajr1 fgYjiFQ6B/890n+ZONdH9xUygrHTFsU5t29+iJ27ymU/5wQVfBHCDxKsiwv5diPo1Uce 1KYRNW3RfhNtNZGZ67Rrf9TJQhOBEMZ/fC1BXu8mIEzKg7fSkvHjC24wV1TFFzsRUF0i qvEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=I1o8XZNdx+7TX2Hd+GlCvP6YeG8j6TyLd31LJRVrH9U=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=IbhPvgZMiZKT6+INnq6eKGAwN/HWrCZj6LNQ6sEiNhsDWSHe5qkysrj21G0IRReqLq tcLpxUSqpzbqblbYypIe6mMiS7JYSpbgpNad4qS+JQyAk/MlN/ytaI3h6+Y5jRQAcII8 Naoo6W5OTtmBARB5YOQTa+VibCcCS8tHgUjEwEYLnchw26WpGzPDWK1QImIFiTupMLU2 Jqcktvp2YYMZ7w8JRDAlBjbW0rEdPwlopf9ymb5SVHRAWKULHnvJyZ3ghUanO1Mladh4 7c1Ej3bG5My5NX9pEAumSL48OS7YkhCIkpnZx6aKvtY6sB4jw5OX31P5n0yQtbGIRe7l T/Sw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XWxwHwcf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 16/54] tests/fp: Explicitly set 3-NaN propagation rule Date: Mon, 2 Dec 2024 13:13:09 +0000 Message-Id: <20241202131347.498124-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Explicitly set a rule in the softfloat tests for propagating NaNs in the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_3nan_prop_s_cab. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- tests/fp/fp-bench.c | 1 + tests/fp/fp-test.c | 1 + 2 files changed, 2 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index fde64836194..39d80c9038f 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -493,6 +493,7 @@ static void run_bench(void) * doesn't specify match those used by the Arm architecture. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); f = bench_funcs[operation][precision]; diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 251c278ede9..f290d523ab1 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -940,6 +940,7 @@ void run_test(void) * doesn't specify match those used by the Arm architecture. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); From patchwork Mon Dec 2 13:13:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846615 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1205583wrt; Mon, 2 Dec 2024 05:29:09 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWMH5ng8H3imb+VN6Obz4fDoLeOKn0xcdOx1rW4AVnzZfzswpY5fiTqLiZKOtGeBdS7IpdWaQ==@linaro.org X-Google-Smtp-Source: AGHT+IEThfNSbIQ9V0Ja3pXhetOmWrXVy1kxVEpIn51mCDREVyKKGiw2byZ1fUknBuu7WeZ6BFq9 X-Received: by 2002:ac8:5955:0:b0:466:a260:a6bc with SMTP id d75a77b69052e-466b361885amr384094891cf.34.1733146148831; Mon, 02 Dec 2024 05:29:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146148; cv=none; d=google.com; s=arc-20240605; b=D85cqk71c1lHwWqY6ScHccU3I4WA0ANnmzSQHuaCTT9Sx+HZoZ5nkzlWFcmelr9fh9 AaR/iQiE83atVcV4qWx0OH6gWnM2EE43WGDvTI41uXHvjioj82RH0TpV5yzG3G/urkKk +lrpL6fKLLMcsnXSDvNqbTShNmxBNHpj/Bm/c9ILWT+wpmSi+r82Nez1Sk6BC3OCnUO3 7bPaIu2L28SYZv9PN5xD9fvgiMyv4Sz2wH6ZMHQNhNr/LEZZ5uYxWxJUHVAhF4K2dJOb llCBdGQ8n0uj51+XqjZQfHzG/woXLomxrueX6/b9mYPw8Ucp0C5Fbmf99/b8y7j1tBev PHbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2Xzjo6YdgDduUN5CW5xi57KmQUyStE6Nvif1Jh7XAts=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=Uc2cocozuCBoQxk6zKGZpypWrGX/ygNmtjQJurvDhUE7fuMb4xAfmwtgIHyTvapJ12 SJpo2MW2jpvZTlvYdEb69MLay13+mRc8GY2vbU+QwAkFAwZr/ENtku4/HhOfx04wfHTP 8FVLAeoHtDaTDpsZZjmK/kkzm59LBCA079EoQ12SxqLfHT8rQCjMHaMKhyVKg+th1CMo OvJGQ1TGD5bSP4y7DrADEFoBa8dex2k1GXlzERFyEAal5Ef7QzLheqUtpB65VzI78bzn GOPUjYIFE9WyS3Lm7T61EHjEqV+TGFS1Fdi7uIBStTWCZrm+J22MpId2cEbWuI3XeXn3 uDYA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ahiOZbe0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 17/54] target/arm: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:10 +0000 Message-Id: <20241202131347.498124-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 5 +++++ fpu/softfloat-specialize.c.inc | 8 +------- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ead39793985..c81f6df3fca 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,6 +173,10 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 3-input NaN propagation prefers SNaN over QNaN, and then + * operand C over A over B (see FPProcessNaNs3() pseudocode, + * but note that for QEMU muladd is a * b + c, whereas for + * the pseudocode function the arguments are in the order c, a, b. * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, * and the input NaN if it is signalling */ @@ -180,6 +184,7 @@ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b4f3f0efa82..3a2d0444475 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,13 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_ARM) - /* - * This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b - */ - rule = float_3nan_prop_s_cab; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { rule = float_3nan_prop_s_abc; } else { From patchwork Mon Dec 2 13:13:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846603 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1198130wrt; Mon, 2 Dec 2024 05:18:08 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU/waVec/US55qj65vwwSfgIuljMC3hij2qKCikJ8y+yusMG93txlMSA/ywJD8vznzcFzmtEQ==@linaro.org X-Google-Smtp-Source: AGHT+IEVLgy+qA5HGWTDFKVyuihkIKKrCDGzYEZ4e4jMhuVDp9jVzGsmuDYb9k+DolqWjFdEfYgO X-Received: by 2002:a05:6102:4190:b0:4ad:dda5:858e with SMTP id ada2fe7eead31-4af448f4727mr28095792137.3.1733145487681; Mon, 02 Dec 2024 05:18:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145487; cv=none; d=google.com; s=arc-20240605; b=NmO6Vo2SX0Wxd/cUnbHkQgeoKgzW/UTOde9iiiYXe35pEzyEiMNZc1948pILreSr8L 5mB7ltnZe99oQ5QYNqAMrbyeVNsReSsGTfN1Zd+t4mugaujstX2TUpAXEO+/PWD1Nqv4 joc+POAnRuc+Jl0MoCzLWA0OdcCb9A8d5sZeoyuGp24JvpnogsgYj/r7rgYQMZTA8sRa pAOoqDlV4hwgprxVSOq9jnm+ojj4Gud4cQ4G4SaSpWzqlTNnnUnKYVxWVZxdNNc+MYZh V504W5BhOtqN/CrBEWDuL3/AV2Kpilvq6JHbtvHxVS0wfTm0TkybCiw5C4awZSnGpaOn u5zQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qV7tBbcBhiVlOigWvkNnjFqiUrRYKt540d7v7M5Z7xA=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=Z3nrhW2+aPmETDw7tAROoyHs+Gmka40K1h9mahVY1juSlj+3/q+CI0SEk1K1kbTLRB TAT9Bh9JfmeXdtFjwrVjvOL2BZr2bBSRqPeySPobvZtqQoov4urmspTsK4fhNwZyaCmg yVzstEe4+PXKE9nGpnpKpLdY4zhGWualy3vvVN6WBId4Qy7gkGJJ/MxNIvpe8bstrwV9 RJXyBXHXbwKRgmMTN3TgMknR4qI/7qFKdfoJRXClEyeaRNoDysKDo7LYn+y2pOtUTB2G OddXRKAJcSW86yf8mauUF1LN+muA1CF9vJy5kPY7hqLXE9KIaTGNqADdM3jlH9HB7VhW Vgcg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m9DVwWRQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 18/54] target/loongarch: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:11 +0000 Message-Id: <20241202131347.498124-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for loongarch, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/loongarch/tcg/fpu_helper.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 6a2c4b5b1db..37a48599366 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -37,6 +37,7 @@ void restore_fp_status(CPULoongArchState *env) * case sets InvalidOp and returns the input value 'c' */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3a2d0444475..d610f460026 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_LOONGARCH64) - rule = float_3nan_prop_s_cab; #elif defined(TARGET_PPC) /* * If fRA is a NaN return it; otherwise if fRB is a NaN return it; From patchwork Mon Dec 2 13:13:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846634 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1211823wrt; Mon, 2 Dec 2024 05:38:08 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXQwIKWloDRreolid7qqdbPHImBcOjLnvudBKtvES1HYbBRKTw5LMCgFHHes2ZcLoDP6aWkVQ==@linaro.org X-Google-Smtp-Source: AGHT+IFhPcGLqPA9mGkdFp7zxRmThaKNSafkPYRZWK/sS9MMRgizxCeDzvt3lup7snLMMU1YSoCI X-Received: by 2002:a05:620a:2a11:b0:7b6:704e:3520 with SMTP id af79cd13be357-7b67c2ceaa3mr2810557385a.29.1733146688512; Mon, 02 Dec 2024 05:38:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146688; cv=none; d=google.com; s=arc-20240605; b=Av+3hWriqjy3rQbua76NCo3zIvU/slbE3hWJPHyHeQ3hzLVN/oz1e5w4mCCVBMJc/d U2YRA1RoZ9u033DZBMq1tiW/pW/lKFhB2GVcU7qLUTvHLnwB2zlAOML2xfhhTAUErDn9 xGU02hvDzseYA5iXYa28JPPGj1aeADsl11jTcd+h05L44WP1K/VZ36/RDdhdlIly1LsR BgKZSDoz+PXH33/QkJRkUrbkNGpKhM99+gnmu12mA5lulGeVMbsodEu9EFUIGmjapSNz odMhJE//k86A7RQyeARE9oKtuiC0knpb2yKmlZHtXlDCMJcEMFEfUsnqGsRw7f1uNWdW AAaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=D7hgTTAcAvvo63kNZS2ll5arN5VoViH9sR+6kv3WAC0=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=LS3cE8W1HC9JShMM7cGmzJ+yZpMQrmWH20EiDo0czuLnN1KSpdE1TKESykImiRcYIl P4eKdtoN6+1TR7hF3rWNZpYMDhLdKk4izDEVB4OvBM02paMIFY+6I00NjbBzWdxJHokv cceotGGE91rbcWtWNtzmG6lUKJHp2uO0Lp+jFlsTwJj58omcuYeUTQVUyOP6Wz1xCQT8 dUw/pxlraVd0bAjkP8tfYiTXdAiLHQXhCdUR+5sQsORGxes10L3ezaj18P+glwIJBzR/ l+OpgtyFtxCI2M9VAqIBYeCLUE+ulDY18KSLFltI9k30JGDyWpmQSZ+lwkZAI+NU1SXF ZuDQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iydRV8ew; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 19/54] target/ppc: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:12 +0000 Message-Id: <20241202131347.498124-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for PPC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 8 ++++++++ fpu/softfloat-specialize.c.inc | 6 ------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index f18908a643a..eb9d7b13701 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7270,6 +7270,14 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); + /* + * NaN propagation for fused multiply-add: + * if fRA is a NaN return it; otherwise if fRB is a NaN return it; + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB + * whereas QEMU labels the operands as (a * b) + c. + */ + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); /* * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer * to return an input NaN if we have one (ie c) rather than generating diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d610f460026..173b9eadb57 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,12 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_PPC) - /* - * If fRA is a NaN return it; otherwise if fRB is a NaN return it; - * otherwise return fRC. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 20/54] target/s390x: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:13 +0000 Message-Id: <20241202131347.498124-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for s390x, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/s390x/cpu.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d5941b5b9df..e74055bad79 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -206,6 +206,7 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_detect_tininess(float_tininess_before_rounding, &env->fpu_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); + set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); set_float_infzeronan_rule(float_infzeronan_dnan_always, &env->fpu_status); /* fall through */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 173b9eadb57..8a36280df1a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_S390X) - rule = float_3nan_prop_s_abc; #elif defined(TARGET_SPARC) rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) From patchwork Mon Dec 2 13:13:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846619 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1206771wrt; Mon, 2 Dec 2024 05:30:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUpwBQYg4qG7sCEtzMujVDlB2G1M61Q+MoVoGGx/zPmmawixfnFP+mUeVuhdt3tX6yXzgoIPA==@linaro.org X-Google-Smtp-Source: AGHT+IGFrwSkqguptcUpbAzccEMeQqE5yOiyPOyKPlkcCB9CSBZlvAHxxFq1j1b5J2fQMJoAHgNB X-Received: by 2002:a05:651c:154b:b0:2ff:c3f6:a2fd with SMTP id 38308e7fff4ca-2ffd6040dd8mr115045451fa.1.1733146253173; Mon, 02 Dec 2024 05:30:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146253; cv=none; d=google.com; s=arc-20240605; b=l2SfRD7WE9czaPnTx1LPExVCCV6FVlU1oJHaweR0MC/2ZpmwoiLUy2FniisVIK2jOq 5IIoQBx8QP2+abItJYrmgZ4IgFhlTVzrtJY/2b3fGRIOV/34rzSxg/MKQjJMNTidVv9E 0S9syfkAtzNeOmtSv4CU7Ha6r2b3xT2nSRhhA3BM7UEqyRty+6DK+BFUQYKYrbn1onCf 3Uzzo9uLreuyn5qfVMpHel2y/eANVjyvAAPTmVlRIU0J45D/qBagXB3QRnjFcWLsMziy K+9lFmFjPLG71kA6RvZtMsv+cQV9Z+Mwo7bHYfvedKe5oKAvaa6IYBIdtDrxEgHtCE/q Q5/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=buw3vsQorwZwaR50k4S9PXYAF2rd+6sbEuYUjFK5KVQ=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=Atcl7L6vgBzR9ISzZO5AzAnyExUickETZW1FcFg18Vcvwf+EiYJNIv90HgkwMbHYqD 8ne20DIzmHRZcU44W6XmcIPC4Lpllkd9Z6b2HF6pxFvamqdGy8pmM9HwbugWIm7hRRm0 Q/2QLz5fdsvzmBSSRdx6OqTlBIw/lyAMbzk+WuEyY1kLSjmcyRAvtxFIOboNB+hVxTa8 ulRj/vDENSfIwcVcW0nr3Ew4KPlu7lT0IoKurZjFBGJk2Q11NpL3l6vC9NU/cxUb0yZR F3wk2qSx3UKmskFBeBExefs3jKQrXaT1dYgAvgJq2hyV7w67/pn4wgJ2akMFSlyShczo M7Kw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q344wjlf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 21/54] target/sparc: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:14 +0000 Message-Id: <20241202131347.498124-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for SPARC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 61f2d3fbf23..0f2997a85e6 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) * the CPU state struct so it won't get zeroed on reset. */ set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ + set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 8a36280df1a..c4d8d085a98 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_SPARC) - rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) if (status->use_first_nan) { rule = float_3nan_prop_abc; From patchwork Mon Dec 2 13:13:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846616 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1205765wrt; Mon, 2 Dec 2024 05:29:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXN+kjtH3iND3Dhd/J+97BNgmug+wUzezGTH7g/8O6gqzJGU/p+Ureyb8odYde+WHDC4p/ZCQ==@linaro.org X-Google-Smtp-Source: AGHT+IGNjJiffk9J2HhogybnkNsEDoZ0mUrhSJZ5/+JxQSlIcNi+xCt7zw6XxPWFzh1ylclvVg2R X-Received: by 2002:a05:6102:38d1:b0:4ad:b85c:e6c with SMTP id ada2fe7eead31-4af446f8fa5mr29360226137.0.1733146172105; Mon, 02 Dec 2024 05:29:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146172; cv=none; d=google.com; s=arc-20240605; b=RSF00UcOrlyZHEkBHwCeNazahhCESICVnS85RZ1hvthJCh3Fj1qVy0coVCWcs8ht9w DYfuB2j+32LZdGWMQayzjZdJQrS6456/5ANqyiDjKVIcDFeq1GtUPOnLgVbYFNjltxYx s3geRmwWIKuvREz8NedLJ9ogwsyrKGdv3Fjjub0DOnT+q0n9sQhQu5b7xAcCXr+QStHC yVLn56ByEmdFGPpRpc55dZrNcUfLZXapOi9/LkDm6JY9Xx7sTvukoJYRjGNy1swFmYmZ ZeojLewjUHFoTs3Pq9wP8x8+jXqEANrTExHcyrAwO34th9GiFMctnMJRhlkUes3eVzGK Vk2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=74ZFmjtVXHtNex2HC0gYU65u2vZGTycqwogjuvw6ju4=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=EaCtU5sYSutPK1Gnt5pPeZcddMFmIPruEQ+cVvN8jr6daT+OsX5bp8djXZ+avYCv0Y rEF5v8J08X2S4DeSkbm3q1EZOIfuZXtkooMF2C6CnCIlbYhZBQvI1NS8oCep7dwvLKhu 0TknZATrkfDEUzTc94UasGgE8pOwpbyhDrcPTvyYMHUSxgcqlau2qI7CPptzVK375BEK gCxP2Jt2RvBamkr9J8mFcrgBvzughaU85wrZxMlwgEC2cYC4OYAn4OSD+839KcdR37HU AWfoSqRLmp7b5xFE1kRytwosPQu7xwlGqZFDsXwH22FU31bqcYXIWCaSO7tjhQpQfPKe 64yQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Gc9PmP/Y"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 22/54] target/mips: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:15 +0000 Message-Id: <20241202131347.498124-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/mips/fpu_helper.h | 4 ++++ target/mips/msa.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +------- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index be66f2f813a..8ca0ca7ea39 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -29,6 +29,7 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) { bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); FloatInfZeroNaNRule izn_rule; + Float3NaNPropRule nan3_rule; /* * With nan2008, SNaNs are silenced in the usual way. @@ -44,6 +45,9 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) */ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); + nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; + set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); + } static inline void restore_fp_status(CPUMIPSState *env) diff --git a/target/mips/msa.c b/target/mips/msa.c index cc152db27f9..93a9a87d76d 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -66,6 +66,9 @@ void msa_reset(CPUMIPSState *env) set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->active_tc.msa_fp_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, + &env->active_tc.msa_fp_status); + /* clear float_status exception flags */ set_float_exception_flags(0, &env->active_tc.msa_fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c4d8d085a98..28db409d22c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,13 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - rule = float_3nan_prop_s_abc; - } else { - rule = float_3nan_prop_s_cab; - } -#elif defined(TARGET_XTENSA) +#if defined(TARGET_XTENSA) if (status->use_first_nan) { rule = float_3nan_prop_abc; } else { From patchwork Mon Dec 2 13:13:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846621 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1206884wrt; Mon, 2 Dec 2024 05:31:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUrqyUmkyfvy6POrz66BlPHSecmnQIZ7JuNFlc8IwLL4QerDkNaj8wH6JZsC1wrUY5KWqvkdw==@linaro.org X-Google-Smtp-Source: AGHT+IHsoaNhVtyT4AK1tHjZw7zsOOkZ9poXF+BXqaSBUnOvtEsAOD/4xO6a1K6DASxFgPsMs3VR X-Received: by 2002:a19:ee09:0:b0:53e:f38:60eb with SMTP id 2adb3069b0e04-53e0f3860fdmr105350e87.10.1733146261261; Mon, 02 Dec 2024 05:31:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146261; cv=none; d=google.com; s=arc-20240605; b=gSsOkvwf2/3dvfPWgI0O+okbKpQJQl6KxrtaJkWn2K4eMG+UHLfv7iK/5FNYS+BQ2f AaIJW4Yieq5AxJOXrxbTgoDDmQ3mq6ie0kFBCH3HLwFICpPINu0I++Pw1gzanTdiybBl mVa2+Q5WAxA/f37C+hXr23SkYBKjxjLlwS3SCdkLdNgMXGzOosCA05RvpDOZyTTbcMLn j3jHEadU2nhMEq1cc8Ezq+0Lg5Xog1Z9RVEsqGxw0xrySBC3nVrXb2CGFMNwIxDtyLHP Tj/KZTfLuI1GiBHS4bMhQ2sa+J/bvGoUvQa14Ye4gfyP9JZsJC5Hz1XsFZbmZFEk0u/W sjxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oNFUiJahMuoZ73+h4VdLlQSeFpgNJO8VlBUcPmwjIjg=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=jj38Wis5uvS5HGfOuUc8UCgpEfCLG7yRiCwsQQZ+Lg/6APvRuuibBGPvxOM/Ee7Ypr RPdnj17gQlB7kyLCQ9Ec0dy1KGmPWy2B9ZcyBZLD6gqfMZUgiTV4A0/wlrs9mKQY/eK8 xH50gcrQMykxe42WbJK21YmY81cmOd3GKBRXABec0sUUhRPquE0FSmJ3WMIgu/7WSmeg gCkurSQc3YIVt/rE/oQxHyrq3uMTTNKb07T4O70RsXSTOB25aL0SImnOIFW3fEUo3sn3 YWXVFoDPv96JiCR5zw7xjhHHFJKQvyfLkv74rq41TZfd8nf1xiTdUih/V+1CInP8p+oi 4xEA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D6PkyBbD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 23/54] target/xtensa: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:16 +0000 Message-Id: <20241202131347.498124-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for xtensa, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/xtensa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 8 -------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index f2d212d05df..4b1b021d824 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -62,6 +62,8 @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) set_use_first_nan(use_first, &env->fp_status); set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, &env->fp_status); + set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, + &env->fp_status); } void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 28db409d22c..67428dab98a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,15 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_XTENSA) - if (status->use_first_nan) { - rule = float_3nan_prop_abc; - } else { - rule = float_3nan_prop_cba; - } -#else rule = float_3nan_prop_abc; -#endif } assert(rule != float_3nan_prop_none); From patchwork Mon Dec 2 13:13:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846605 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1201236wrt; Mon, 2 Dec 2024 05:22:26 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVwndwXAZW3EuYD7oaB0uMj+rkjTUkZFGDA73LxMJotvokcKiIKf8ju+1zhKHnK/x4h17xkHg==@linaro.org X-Google-Smtp-Source: AGHT+IHr1Wu1QGUhAd8XwRyq/W2FJ6rvx2d+WwYKZaoYiJ8LfFxOWs4fc1Px4W1q0hJvsWh5CT5C X-Received: by 2002:ac8:5f93:0:b0:466:a1b5:be4f with SMTP id d75a77b69052e-466b3516854mr296073701cf.15.1733145745857; Mon, 02 Dec 2024 05:22:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145745; cv=none; d=google.com; s=arc-20240605; b=QTM4otIZOjts5BDkrDMudMKN3SfezlKDL1cDU+zXlnk8knBy/nmAdir2ZmnN01DHDh di1Gz6ULcwZkfmBANX0wsAtZQ1z7YpAu+rTj62gWyMyYHVaFYpnQB6VlwPTFj6vrmipg moPrSjJhgyQtLCpg72vciPyjxTwM7VttTiCirHXIGFNv/lohw2084KcqHuu9ebehaYih Q14y6baC5CwA63Of/vjWiVmBulHby5FzC6IMC9W9+0I5ynmXCLVSDjZ710sUSrMYA8NO 5VzvcTB7om/HEDlI5C54y64boKVM/afvs7HQQREdcPbPhth7lGR9x6X3T81OPCAoxTyj XaHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=73eMz7OCXkqR25Bej28Tzkpl+eCdRMSro7tB3M4lS/Q=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=ZuEp+LPmn80Fuhm2ueAcb5QDvuvftBSfvxhb8M2RPZJCb2m3ZxdvVpO8OwWIYUKw1b /7RbxkuUhhasIyhvySCdK+wSShUOp8GisnR6chcmMwteGjQLCNLyGTR1iVI0uqQVI4+e qIypbMrAzlHyEXvcCdqCv1ePyZrbk9Z2l1WJI07LB2EOya/iYkjfXg6TtdHjnJk79vqD pp5Lq4PnaSmmee9QTyhUWaf/C8H5OpVSenvM0sBEiyAlVAygbhNWUziXpuhHaIYsMefx DozrE2HJaj6qQgtlhEN+4LbWZcS6O357s+qjUIu7usoDqkrpTI6Oi0I2XXndUXVNi61k E7jw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s+gdHeQo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 24/54] target/i386: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:17 +0000 Message-Id: <20241202131347.498124-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for i386. We had no i386-specific behaviour in the old ifdef ladder, so we were using the default "prefer a then b then c" fallback; this is actually the correct per-the-spec handling for i386. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: drop comment saying NaN rule is wrong. --- target/i386/tcg/fpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index a98b4f67ff0..c8bc5b7cfb3 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -180,6 +180,7 @@ void cpu_init_fp_statuses(CPUX86State *env) * there are multiple input NaNs athey are selected in the order a, b, c. */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) From patchwork Mon Dec 2 13:13:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846604 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1200968wrt; Mon, 2 Dec 2024 05:22:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVAOzx/F6zL2EKw9NaeAvMuH8oWo2fj/dbYJohpAomGEL3CDO6BmgteL7puVig2BQpc9oDFPg==@linaro.org X-Google-Smtp-Source: AGHT+IHwQ98ohnmiBOwCybXtqZmxJlegom32+fecw0i5c4EXEHNH3pX1gG2Pkg9UZRucwVftFP1n X-Received: by 2002:ac8:7f0f:0:b0:466:a0cf:a655 with SMTP id d75a77b69052e-466b32ff27cmr323047541cf.0.1733145721240; Mon, 02 Dec 2024 05:22:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145721; cv=none; d=google.com; s=arc-20240605; b=XTsdpTvxG7qHpG3N+AQh1UIvTyoVmixgx3Czf6rnTFWcNRdH0QOCV0zavpd6+n2O4k susjq/unFoFux+htLvo/THa+QZZPDOKJnTZRTaSzBPCKskhrOwrrUvdgz7EKCaxn/Rpg +6oDfn6mQjkNF0vzTu3poYAKu/o/bVTMRUvSLdH0sZoZ0C5vu2tab4CKO1HWQsp0k7IC 43AuC/ThKrCJn5mBs1pDqUPacJuIh3rcaRhLBJA+tjGCqEvstm2TPHztIjpb0sloIddU DmroW0haveygKQNHuxc9hp/p2Zf3nZtr86pU637wfEwouR/Bbr2GvKycKJSl2mgEuHrb m71g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=e3mx5QSLs3F08ZGNoyI8psAl3Pzx9Z5IpdlAACesozc=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=ZL1IS8qm0UBN+dBRJJkWBVV+dZ8eCWa0qmWSkf822hju4Kuty2TqrG/lec7rDSiT8l wGtW9fndvsIAH1/blaGr04HZCWgXYGeKk05nnPQ+TVHLRs0YZm9nNhjWTsGLHa9qCctN J7fZJF9w58vihJEhiz2jKqNyNDc6FtvDsgXVNoVQ2wsEDuGsEO6hlo/TLU26+4KZa8QT ZHm/xePob1cNuyc8iTCE3ZpJ/6TsqjBf1bD8K1EswMy7L7UwI7dXmuBRMLyhC9tmLwyY 8AOqqyqZuYnJILMZjsraQfilVQq3ZptTuretnW9jA9aUc1mNirvIDeCnwRS1r+2BI1q3 J4bg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i2lfPV4x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 25/54] target/hppa: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:18 +0000 Message-Id: <20241202131347.498124-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for HPPA, and remove the ifdef from pickNaNMulAdd(). HPPA is the only target that was using the default branch of the ifdef ladder (other targets either do not use muladd or set default_nan_mode), so we can remove the ifdef fallback entirely now (allowing the "rule not set" case to fall into the default of the switch statement and assert). We add a TODO note that the HPPA rule is probably wrong; this is not a behavioural change for this refactoring. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hppa/fpu_helper.c | 8 ++++++++ fpu/softfloat-specialize.c.inc | 4 ---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 393cae33bf9..69c4ce37835 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -55,6 +55,14 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) * HPPA does note implement a CPU reset method at all... */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* + * TODO: The HPPA architecture reference only documents its NaN + * propagation rule for 2-operand operations. Testing on real hardware + * might be necessary to confirm whether this order for muladd is correct. + * Not preferring the SNaN is almost certainly incorrect as it diverges + * from the documented rules for 2-operand operations. + */ + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 67428dab98a..5fbc953e71e 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -504,10 +504,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } - if (rule == float_3nan_prop_none) { - rule = float_3nan_prop_abc; - } - assert(rule != float_3nan_prop_none); if (have_snan && (rule & R_3NAN_SNAN_MASK)) { /* We have at least one SNaN input and should prefer it */ From patchwork Mon Dec 2 13:13:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846609 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1202791wrt; Mon, 2 Dec 2024 05:24:43 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWNESCLyhgCLUOeQi5BkKzhrL83dvqYpOdSEbrnptB2KM+r5kasP5NtlS77/+tT1HrHNzawEg==@linaro.org X-Google-Smtp-Source: AGHT+IEQGt4ROIIWjiKUe9iKIxBKtdAyKMbBixRXOdOeiJ1IivMg01ZqznOBLePApSA1xRGCPW5t X-Received: by 2002:a05:6902:2ec4:b0:e30:d479:fc55 with SMTP id 3f1490d57ef6-e395b8a6087mr14280823276.18.1733145882870; Mon, 02 Dec 2024 05:24:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145882; cv=none; d=google.com; s=arc-20240605; b=BiuLgymHc9sAZX6w6OsEQ4dw0hvuYqsLA/WnqswzmkqF17Vy0y1ZPhrCkHnlRfsZYY 9EGk6dm+FiNxQdnrtn2HiFmYn39P90XLP6K/YwWA6Xzj9OaCa6ET63xaH68JQM2RJbIH 8nJ4Q8e0hD00h5GafnY8cqrsTvhW9U/kzZcADCJ36GPoTl3jK4VTS2QqBlY04k1vki2O F2EY+1NRM36HOd6FqezZmFaCYNSkm/R3jYrLpO6uS1r+IGJv6Y+gbixjHxrKr6wrR9qB nrkla7ouoiVaF5cJTMEa/IEkq01uk5lIz1+oBhhdmjmW41q/9fBOU2adkP/8f/uA2q3d X9Cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jZmEjYqAtBnicHjPyhH8ft0gcTQribvPLCBufh/En/c=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=SetRrBmDK8jKqKHLjFXOHnNoW+ZSyJsnnDF1lKnhPa5QOy07xKe+7a173KBbVqAqXl T4llIrsksT5NuxezS86qBgqgcM/+CPLpxNlFpmEzbkGoS6CPvmguLR1gcXqFvA8tz4kY fCIMklU3gOs7Zc2T7QOWOVUTYwMSzwGoBSnTqRHA3vkko1I9zRRVua/v1zymg8yPP8pP wfzcxJtzvdF2Pnh5IbDYqKwYZxaE2u4a8Ji5d5NWbWICiZ9zmA8AVHBsZ42uNzsbCVPM MbH/DShTx4SXIs/XP2L2cIbC1BkVYDAC51+Isqbf+Cw6CoKxrjKH9d3jK5I2iAk3v2vR R2sA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GU37X9Lj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 26/54] fpu: Remove use_first_nan field from float_status Date: Mon, 2 Dec 2024 13:13:19 +0000 Message-Id: <20241202131347.498124-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The use_first_nan field in float_status was an xtensa-specific way to select at runtime from two different NaN propagation rules. Now that xtensa is using the target-agnostic NaN propagation rule selection that we've just added, we can remove use_first_nan, because there is no longer any code that reads it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/fpu/softfloat-helpers.h | 5 ----- include/fpu/softfloat-types.h | 1 - target/xtensa/fpu_helper.c | 1 - 3 files changed, 7 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index cf06b4e16bf..10a6763532c 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -113,11 +113,6 @@ static inline void set_snan_bit_is_one(bool val, float_status *status) status->snan_bit_is_one = val; } -static inline void set_use_first_nan(bool val, float_status *status) -{ - status->use_first_nan = val; -} - static inline void set_no_signaling_nans(bool val, float_status *status) { status->no_signaling_nans = val; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index d9f0797edaf..84ba4ed20e6 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -309,7 +309,6 @@ typedef struct float_status { * softfloat-specialize.inc.c) */ bool snan_bit_is_one; - bool use_first_nan; bool no_signaling_nans; /* should overflowed results subtract re_bias to its exponent? */ bool rebias_overflow; diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 4b1b021d824..53fc7cfd2af 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -59,7 +59,6 @@ static const struct { void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) { - set_use_first_nan(use_first, &env->fp_status); set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, &env->fp_status); set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, From patchwork Mon Dec 2 13:13:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846610 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1203198wrt; Mon, 2 Dec 2024 05:25:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVXZB+Tj7aSBp+kcKh7bYbfBSdXdE1TJx3pEs2ovs/mpbntX7hE3Y+zQtqCOeWmus0aB7yNRg==@linaro.org X-Google-Smtp-Source: AGHT+IEVK0K72FQh/wuQJBgz9hikT14nrEvNzIojyhSWGWnJI/ek0W8vwRMst4ThfI8lLvWPr74G X-Received: by 2002:a05:620a:2447:b0:7ae:4b83:daf2 with SMTP id af79cd13be357-7b67c4a7696mr3467592785a.61.1733145919059; Mon, 02 Dec 2024 05:25:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145919; cv=none; d=google.com; s=arc-20240605; b=R20JvTrRSnDN+dK6jcSicOSFYsPDeTLyc7kDQ3RWiWunUsOEdZgwxMJHAYsGt0uXYc QtE8sa6D5HBZdosGNCt9kzSJ6jfBohF+JpsVuygDbiLQBg7RUkBpiz7XOL9d3TDllQsF kcajKzOv1CyaKtnr+uA2nLFFo9FRdJPhI1pI3g4EuNppE3K6BeeF0qetG8q9WmX6b858 +xyyEDj56KrCnRfuA994hKcyqLkVSpkvrimNnnrEqNjc8tKuYyO5mj6YC00jnqws86lC ShONEly9IDa2ePHRl/02nNHGsGj7tMugntAmpaQyASoKH5tCrpeb4xz8QY5rnwOQvTrp eLsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MX9sc7FmhfylUuxW0cA+BWl3jSlP2Yj9aquR2jby44k=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=GM9Bs7uuw6K0N56jEUa6USwJMI943O4ZbOQyEo580OLH9KMBp7XfMAqlS71hSv59FH 68KE0TOXSnCEIckPrPYCvlmdwQ2newpA1qBShGOuM/Q/82iz6s57tmv2RY6N2pyzN7mW Fuu4tQ9ulUuV86za3BFXlBFqMEKnjNooW3NlzN252DmUyQHIRg7s/Y+5hLcm7Et3bzC4 S+YHzACtKa1G+HPGLxjLPOX65NnRTIhxx7b3IHe2UxoLBltDz3xOnMmu3L3qmc3Ojy/X gx3vszjK3vaLqgBCq3BLkCoomHduEo7s4/Wg/4XdZGcexxuGvSaDHJQEvBQ0ZfN+P6RH exrg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PHi2UVs8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 27/54] target/m68k: Don't pass NULL float_status to floatx80_default_nan() Date: Mon, 2 Dec 2024 13:13:20 +0000 Message-Id: <20241202131347.498124-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL) to get the NaN bit pattern to reset the FPU registers. This works because it happens that our implementation of floatx80_default_nan() doesn't actually look at the float_status pointer except for TARGET_MIPS. However, this isn't guaranteed, and to be able to remove the ifdef in floatx80_default_nan() we're going to need a real float_status here. Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status earlier, and thus can pass it to floatx80_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/m68k/cpu.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5fe335558aa..13b76e22488 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -76,7 +76,7 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) CPUState *cs = CPU(obj); M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); CPUM68KState *env = cpu_env(cs); - floatx80 nan = floatx80_default_nan(NULL); + floatx80 nan; int i; if (mcc->parent_phases.hold) { @@ -89,10 +89,6 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) #else cpu_m68k_set_sr(env, SR_S | SR_I); #endif - for (i = 0; i < 8; i++) { - env->fregs[i].d = nan; - } - cpu_m68k_set_fpcr(env, 0); /* * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL * 3.4 FLOATING-POINT INSTRUCTION DETAILS @@ -109,6 +105,12 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) * preceding paragraph for nonsignaling NaNs. */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); + + nan = floatx80_default_nan(&env->fp_status); + for (i = 0; i < 8; i++) { + env->fregs[i].d = nan; + } + cpu_m68k_set_fpcr(env, 0); env->fpsr = 0; /* TODO: We should set PC from the interrupt vector. */ From patchwork Mon Dec 2 13:13:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846646 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1215885wrt; Mon, 2 Dec 2024 05:45:06 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXLr+gMJUSozwDaXUddrTZMoh9ugU9fU1d7lZSXHubwwLvOp2ouJfBZN5FSQbfZoVlgE2lFxw==@linaro.org X-Google-Smtp-Source: AGHT+IFn4ZXhiD1LZ1r9rWpWRhRAc44kh37gOKYTxpUx5Dynawc9sk+J1ooJ11P+Ij/RzUbji/QO X-Received: by 2002:a05:620a:1713:b0:7b6:7b35:7b4c with SMTP id af79cd13be357-7b67c283e6cmr2947728885a.23.1733147106647; Mon, 02 Dec 2024 05:45:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733147106; cv=none; d=google.com; s=arc-20240605; b=cBrwz7Y84tuMUL4z00pSowMuT8IgGMyQpvtFi/gjR5YRpkVrDPFMhyDfF/np0+7D+Y fl6l/DgIf2XSHsL6KDc4kWftg8udANeUUfQxE3KtVFDeJ3Ol/YW26PJErHMq7AmrpQ6/ Pac38+3Ska7DO/VvAsnYOsU2jcZ0UFB53Ot4MjQwGk7J+RqVR4QPnmUVjIIPX7M5KM7W SazdsWv2eGBrbyAxELDAiTIKi/DjkZ97QwCC1Tj8yXnyBZkx4EJ1vrAeWymqrHYqKrSD 0l88gYnyxVjPEf1EQpKUO+GvTspQhwJcvVOolRxFWwFa9zHJN20BwJ+RurAy5AKo+THH W6kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wdqAdxMo/Zjt+7gjYfOwzXdT/5QjRbRXYw8xftE2ZL0=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=LKxspu7hA0Tbdn0PRXeJ8lm+gxbXcxVfMd8iVut7eqZvlBDB1enViBeY3L6L+d6MGf dk44yxU8HNyBhUUknanMAHuLvPzN4byoLF8KFmRcMJ8r90pwqD7DnIqR+swxwo3Ru+Tu acN1hoRKKqIrI0hZ6qLxhbGppehQBbJ+1gywMhsjEfoPmjm/VN0m5ANwHiVk/6epXicw Rnkv7wgnczmtllZF5oEyD966t5bLQlrWvqBuyVAs6yh4SK1sAOxMUEhkquSxRXetwScX dJs/fVKXmqVWvj7Bsoy1OHHt6ah7efRNWc1yUnrocMBOTqTnwU4pGH2qYV3yyxFk89ek qUCw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sgmIvl9u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 28/54] softfloat: Create floatx80 default NaN from parts64_default_nan Date: Mon, 2 Dec 2024 13:13:21 +0000 Message-Id: <20241202131347.498124-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We create our 128-bit default NaN by calling parts64_default_nan() and then adjusting the result. We can do the same trick for creating the floatx80 default NaN, which lets us drop a target ifdef. floatx80 is used only by: i386 m68k arm nwfpe old floating-point emulation emulation support (which is essentially dead, especially the parts involving floatx80) PPC (only in the xsrqpxp instruction, which just rounds an input value by converting to floatx80 and back, so will never generate the default NaN) The floatx80 default NaN as currently implemented is: m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1 i386: sign = 1, exp = 1...1, int = 1, frac = 10...0 These are the same as the parts64_default_nan for these architectures. This is technically a possible behaviour change for arm linux-user nwfpe emulation emulation, because the default NaN will now have the sign bit clear. But we were already generating a different floatx80 default NaN from the real kernel emulation we are supposedly following, which appears to use an all-bits-1 value: https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267 This won't affect the only "real" use of the nwfpe emulation, which is ancient binaries that used it as part of the old floating point calling convention; that only uses loads and stores of 32 and 64 bit floats, not any of the floatx80 behaviour the original hardware had. We also get the nwfpe float64 default NaN value wrong: https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166 so if we ever cared about this obscure corner the right fix would be to correct that so nwfpe used its own default-NaN setting rather than the Arm VFP one. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 5fbc953e71e..9f913ce20ab 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -227,17 +227,17 @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status) floatx80 floatx80_default_nan(float_status *status) { floatx80 r; + /* + * Extrapolate from the choices made by parts64_default_nan to fill + * in the floatx80 format. We assume that floatx80's explicit + * integer bit is always set (this is true for i386 and m68k, + * which are the only real users of this format). + */ + FloatParts64 p64; + parts64_default_nan(&p64, status); - /* None of the targets that have snan_bit_is_one use floatx80. */ - assert(!snan_bit_is_one(status)); -#if defined(TARGET_M68K) - r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); - r.high = 0x7FFF; -#else - /* X86 */ - r.low = UINT64_C(0xC000000000000000); - r.high = 0xFFFF; -#endif + r.high = 0x7FFF | (p64.sign << 15); + r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac; return r; } From patchwork Mon Dec 2 13:13:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846635 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1211858wrt; Mon, 2 Dec 2024 05:38:12 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXscVCu0qYTW9NB/uiuTdDZT1QqlhLVP2hXOUnyFwq1vZralMvFWZWJ6opQxjzTB2TlAtcyrQ==@linaro.org X-Google-Smtp-Source: AGHT+IFgVh5xbeAlw4ZL1e02PGb+py2GnnB/xbrNLEC0TXoWpmJQM++0v3WS7Sx0auk92AUv1xAe X-Received: by 2002:a05:622a:188c:b0:466:9630:c721 with SMTP id d75a77b69052e-466b35845d9mr348840581cf.33.1733146691642; Mon, 02 Dec 2024 05:38:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146691; cv=none; d=google.com; s=arc-20240605; b=ixvF4IzfZ8uB9hxfCGenHHX1lkFm3rD1OaChymQeeIsHW9HwfFdXnMn81wvMAGjEae owdcWqRnD4XjBZ3oUUBr2iOnCuDj8/NKcv5y1mEnNE3FaZYIOPCOj7SFv6t5GC3KxJ5C /TqGXN9vOGZv4O2+q1Ow9mdMs9xeGaFpZNJyPrZy79Rh4WXD4XcbcrxoDePciIyWpzc+ 9lA1dSWlHem5Rg5KcEzHRd/napnTfvtZwFHcKS1KH4r9pK5ErA6p5zcDUk+Wb6zUzpw+ jHE7XFqZEdG8wxMJ7k6GhItnEFEi9rxNLgtu4dX3zibhbhv5QELHImq25tpVZcJz1lji S9Cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=y0Xx5AyANaS6WVZhR0dQwQ3Dsfoy1K8k2mwf7TXf+0Q=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=YuELfHz6+Fp34vUG9Mav823vgQTJfGXf9CjP7jXG3aLKb7MGDYx9hzq4uoSWi3hNZV rd26vCrZDoZn56uIb7GOgZDeycX5k0eSsxb6sN+6H5JKNPgSP0ymcG4WeO1BzGSl/bfH /n9VY68vKiBOd2dHGopPUPBzzDOaKtd0Nt0EaEwwK4ltOSRVZbBXg0xfpgp79HoY7LMg 7DzTPmihBlgL9z4ft7idReHCoySR4k7Krw3WkMWC+drXx9vBbeX3SwY7nmDwxlu9eNCF 4+Sh5zu+BADU1K9t4aHGx4AAaKBj76+pgViEXjNTh63IcLpVWBwugaQCXOSQQdbSSMA+ ha0Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pn7j5F7M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 29/54] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers Date: Mon, 2 Dec 2024 13:13:22 +0000 Message-Id: <20241202131347.498124-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass a zero-initialized float_status struct to float32_is_quiet_nan() and float64_is_quiet_nan(), with the cryptic comment "for snan_bit_is_one". This pattern appears to have been copied from target/riscv, where it is used because the functions there do not have ready access to the CPU state struct. The comment presumably refers to the fact that the main reason the is_quiet_nan() functions want the float_state is because they want to know about the snan_bit_is_one config. In the loongarch helpers, though, we have the CPU state struct to hand. Use the usual env->fp_status here. This avoids our needing to track that we need to update the initializer of the local float_status structs when the core softfloat code adds new options for targets to configure their behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- It would be nice to get the riscv fclass_s etc also not to use a stunt float_status, but plumbing the env through would require fiddling with the macro magic, and in practice for the is_quiet_nan functions it works out OK. --- target/loongarch/tcg/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 37a48599366..aea5e0fe5e6 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -359,8 +359,7 @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj) } else if (float32_is_zero_or_denormal(f)) { return sign ? 1 << 4 : 1 << 8; } else if (float32_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; + return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; } else { return sign ? 1 << 3 : 1 << 7; } @@ -378,8 +377,7 @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj) } else if (float64_is_zero_or_denormal(f)) { return sign ? 1 << 4 : 1 << 8; } else if (float64_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; + return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; } else { return sign ? 1 << 3 : 1 << 7; } From patchwork Mon Dec 2 13:13:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846632 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1211383wrt; Mon, 2 Dec 2024 05:37:24 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW+mckfNwuXFmIvCvyiT95RILFzBY/ZAIjB7VHKe9qb4Qz8MykX6/zRWJ0CrMduivsjhwiRsg==@linaro.org X-Google-Smtp-Source: AGHT+IH0Fo/jkVirj+P6oXnssVJoxF8lCEgCwfkgbPQb0XBDR9HQRZODa76hB+NIHN8XpMioW6z3 X-Received: by 2002:a05:6214:301b:b0:6d4:1ea3:981d with SMTP id 6a1803df08f44-6d864de4b4emr294452476d6.43.1733146644356; Mon, 02 Dec 2024 05:37:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146644; cv=none; d=google.com; s=arc-20240605; b=BY+0FJI08JkLnhDpRI5KA1oAz2qGOq5t+meIWFZC5ukQuzIwDHH7QAOiHvRPjrWobn vwZC1xuV9NTabf3GrfyCeiIxylQ9hatxNDK+yHnkudW+dZSezuBIjMlO+7BIkizR7Ig4 eK6HngGTqsKdXuBrvuD8rj/bVWbSTlONhFdW5RTXGeyAlFAmh+zVrjtMdB71gTQWXz8i XfPKfSxaB3kibg1C+hJd5RsZb44Tmqwkb1dGxrLySI3kq4tvFe5Fs8XjAy2AwztYzxTs JdWtfwT1bZD+iVHN7LcruOe6AczCMmTxbKz+lQhkQaaeHdy5WtG612ILLxq9bqCC/Du6 RKSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qFtiFfBBznBZexAeUlFNfBbsHlolyVwbUxMya82sU1M=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=Rd+hnqAzVAPaMcnBlCSlu+yIL8I6cewm/s2Ox3Z7IPJodIlleAKqdO8DZus3rrDV7j maRbv6N82cfMRPxf5frz9jtMwNU3iMpoDn3Wl4CfMSP7eGazYQMB59LBJLS7PeD3fP2e o2WmO6IOQYZoA+bG/4mHGWrLbqd3guhjBockVVWhz7fhh2T4OugiD/ICcbY9yS5j3Biu MTXLZLs/28Tn46asLBdeFTfo1Ej6IeeDVv9k2l4PQUBQAvMAzF9akvnOnQWOEY51L7yz 6c90SxCI8ZYToF32956p+2K+x40AoDrxMDg40ZnXL+RltIZy8D8qDh1rgj1YAox7evCY gaVg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=atwcCUNs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 30/54] target/m68k: In frem helper, initialize local float_status from env->fp_status Date: Mon, 2 Dec 2024 13:13:23 +0000 Message-Id: <20241202131347.498124-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the frem helper, we have a local float_status because we want to execute the floatx80_div() with a custom rounding mode. Instead of zero-initializing the local float_status and then having to set it up with the m68k standard behaviour (including the NaN propagation rule and copying the rounding precision from env->fp_status), initialize it as a complete copy of env->fp_status. This will avoid our having to add new code in this function for every new config knob we add to fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/m68k/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index a605162b71f..e3f4a188501 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -615,15 +615,13 @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status); if (!floatx80_is_any_nan(fp_rem)) { - float_status fp_status = { }; + /* Use local temporary fp_status to set different rounding mode */ + float_status fp_status = env->fp_status; uint32_t quotient; int sign; /* Calculate quotient directly using round to nearest mode */ - set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status); set_float_rounding_mode(float_round_nearest_even, &fp_status); - set_floatx80_rounding_precision( - get_floatx80_rounding_precision(&env->fp_status), &fp_status); fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status); sign = extractFloatx80Sign(fp_quot.d); From patchwork Mon Dec 2 13:13:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846639 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1213405wrt; Mon, 2 Dec 2024 05:40:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV+RkPGEM5rvwj3gfvRbyH+s5g9gm0ueR/i03EbfVovcGhuVuYB6PtikIVmS8Rg/nCEGZjymg==@linaro.org X-Google-Smtp-Source: AGHT+IEapGbpdae7wnJznYOBtwT4nI5ogsuPf+tcZ73q5m6nvtHEhNEZTQg+jg0+3/xtqgD0jKZD X-Received: by 2002:a05:622a:48f:b0:460:946c:9e47 with SMTP id d75a77b69052e-466b34d2eb7mr388390361cf.10.1733146846985; Mon, 02 Dec 2024 05:40:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146846; cv=none; d=google.com; s=arc-20240605; b=ATGScI9HY3czQQrMnhymRaSeFTz5NJZcpE+1lZI9WKqejHf/KAb6CNWzKqTAIEt9gG m6omHUqaF4ObhrGAlsFYlw+0hWk/+Gish0YoeqyTNaHkMLOhOyYh8AvoK+S0zVAwlHnH 4mmRU59sdmlZZKQZPedTO9QMnx1Q6QPjBDb1sMiO2broTe5NCbS1guVQryAxy8WVVkYV JLedQBTv2Zye7GrwrOkVMYDvkHIRpWksNTFiq3w6CTfZBOJP5xUds/M0ErtrUPXncwy4 1UwC3VETvqseRO+P7kWqaXSCCvmmkkHx+lnrrYCx7QzEspWv+PB7kVmdJiZx+Xu/6BPp Xt6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=F9P3Zyg8EWDd8Ipp5Pjnvse0G07D293rwdAJ1WyzXl4=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=MqD2hdSQ+ta2GPQ+BZc4rHUGydt2COPXXmzmGMVpT5Sl+J15d8amY7uxPfScFCE+2x tqnc7uK39veRqoFzUI/VO+izmtk8cMr7GkXT47JpoAUoh9BFQWw+kZKZLy4uaXGATH6k /rzQdCWvkPypgR8vA7JmAjvgL1BY4Ir9HNMIl3KfU2lR7P8qJAutVnECh+yIxD2Wlacn f8UyALnxGespV/tC5g/AJL3O/NtEW/KELz3Cql98oZva6XoFxoQ1faK0tgb7pNoRwcIm C2JJfAIek460EG+EelW0mpvJtJTXK+E1Fh7hLCrgT4u3wP7qqyW38kDp1v0h7sqUHl/I W7Rg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K3Uar6D9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 31/54] target/m68k: Init local float_status from env fp_status in gdb get/set reg Date: Mon, 2 Dec 2024 13:13:24 +0000 Message-Id: <20241202131347.498124-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion from float64 to floatx80 using a scratch float_status, because we don't want the conversion to affect the CPU's floating point exception status. Currently we use a zero-initialized float_status. This will get steadily more awkward as we add config knobs to float_status that the target must initialize. Avoid having to add any of that configuration here by instead initializing our local float_status from the env->fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/m68k/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9bfc6ae97c0..beefeb7069c 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -36,7 +36,8 @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) CPUM68KState *env = &cpu->env; if (n < 8) { - float_status s = {}; + /* Use scratch float_status so any exceptions don't change CPU state */ + float_status s = env->fp_status; return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s)); } switch (n) { @@ -56,7 +57,8 @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) CPUM68KState *env = &cpu->env; if (n < 8) { - float_status s = {}; + /* Use scratch float_status so any exceptions don't change CPU state */ + float_status s = env->fp_status; env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s); return 8; } From patchwork Mon Dec 2 13:13:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846647 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1215935wrt; Mon, 2 Dec 2024 05:45:11 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWizUt8hP4Z5mHvnPC8/8j2qIas/uGkrpSqtqmx/a+81woR8Esa4ktacI41kSNxhOLiPi/tKg==@linaro.org X-Google-Smtp-Source: AGHT+IFcO6tm7QUCACH0jePhtdvhLYT1XO3vKAQwrYsh9kTIrPPZJ9BQNCNTReQNn8SmJTO4JePg X-Received: by 2002:a05:622a:1646:b0:463:4be4:b03f with SMTP id d75a77b69052e-466c1b2361amr368678581cf.11.1733147111315; Mon, 02 Dec 2024 05:45:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733147111; cv=none; d=google.com; s=arc-20240605; b=XCfMNdsk696EEkz2YuNHVl1+aW/wVtVsSIPJM7+7r2ivvlINKyMmKY8H/sbzpf+ROE zyySxHKfaSlTcp3bDCeHfF9pcWSju6lFsOGplEzC74QXx3hUjlHcpCVVyZAx/abaC5mU kQ2DW+Uz3QsVgHy/4oBt+081TxWvbAhKtGmIGkHbpQGhrS4JGfQfKGt/OKp9WZad89Jz 54rdeu+1tmW/BTDMyInGiOYMO0UC1VVQ8ohvBMIq6Fv0VJM6Z0tvWgwx6J5BnlSJel3f Y8XkoqnPZxDkCT0YYadcqvDBEfASB1KcVDenuuZz/GosP/kcd8hT1ct35EN7PJUvdbTI c/gA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bcSQWPJxoEZ5kc/cEyAZreOowNhccL15M84TKXenqM8=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=PDx6tlAS113C2n5dYOD2MJ0YAxFXN6+YlGplshrb20ZCQqK3BgJAv1KQQn6x6Aop8G iQlboDChiRsW+RmBPzE3WiiDX9UkrG3HtMseh6wH/8CJ8BrEGWMBFd8PCphwrdOLcVVZ JAjVCkzxTVMcmYNRXPfEnQIJk5PglxyFhL7qTqSdJjuR1433SQpmSkXhTjIAwRaglZzG dn6hKg01w3ttrh7FQZe3P7wJ0fulUVKB+zYjIJjLkfFPpVrDMoH70Q7BHOX4TmvWj/mc K1L5aFk/X3LDxr2izlfl2aP7UmdtcfXzEhC4I4crbzc7bQqX4280Yfh8yprRJMwvuCYP LpLA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ufE9gu07; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 32/54] target/sparc: Initialize local scratch float_status from env->fp_status Date: Mon, 2 Dec 2024 13:13:25 +0000 Message-Id: <20241202131347.498124-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the helper functions flcmps and flcmpd we use a scratch float_status so that we don't change the CPU state if the comparison raises any floating point exception flags. Instead of zero-initializing this scratch float_status, initialize it as a copy of env->fp_status. This avoids the need to explicitly initialize settings like the NaN propagation rule or others we might add to softfloat in future. To do this we need to pass the CPU env pointer in to the helper. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 134e519a377..1ae3f0c467d 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -51,8 +51,8 @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) -DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32) -DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64) +DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64) DEF_HELPER_2(raise_exception, noreturn, env, int) DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 6f9ccc008a0..236d27b19c1 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -490,13 +490,13 @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2) return finish_fcmp(env, r, GETPC()); } -uint32_t helper_flcmps(float32 src1, float32 src2) +uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2) { /* * FLCMP never raises an exception nor modifies any FSR fields. * Perform the comparison with a dummy fp environment. */ - float_status discard = { }; + float_status discard = env->fp_status; FloatRelation r; set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); @@ -518,9 +518,9 @@ uint32_t helper_flcmps(float32 src1, float32 src2) g_assert_not_reached(); } -uint32_t helper_flcmpd(float64 src1, float64 src2) +uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2) { - float_status discard = { }; + float_status discard = env->fp_status; FloatRelation r; set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cdd0a95c03d..322319a1288 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5584,7 +5584,7 @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a) src1 = gen_load_fpr_F(dc, a->rs1); src2 = gen_load_fpr_F(dc, a->rs2); - gen_helper_flcmps(cpu_fcc[a->cc], src1, src2); + gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2); return advance_pc(dc); } @@ -5601,7 +5601,7 @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a) src1 = gen_load_fpr_D(dc, a->rs1); src2 = gen_load_fpr_D(dc, a->rs2); - gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2); + gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2); return advance_pc(dc); } From patchwork Mon Dec 2 13:13:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846625 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1208573wrt; Mon, 2 Dec 2024 05:33:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWPnBXpJNme8sfgmQmDUA4mbY9FbwGqrvxvpiu3YkmuR/9GZdrqv3mkcNmi4J6AFwczAoU7/A==@linaro.org X-Google-Smtp-Source: AGHT+IFjlj9roHAfRM/2dFR+nIMRYlDMEKbz+D34OTSx8I+x9xTy4iClKbYzwCHVZrzVFwpxryPO X-Received: by 2002:a05:600c:1d8d:b0:42c:b905:2bf9 with SMTP id 5b1f17b1804b1-434a9dc7875mr226122455e9.16.1733146395818; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 33/54] target/ppc: Use env->fp_status in helper_compute_fprf functions Date: Mon, 2 Dec 2024 13:13:26 +0000 Message-Id: <20241202131347.498124-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the helper_compute_fprf functions, we pass a dummy float_status in to the is_signaling_nan() function. This is unnecessary, because we have convenient access to the CPU env pointer here and that is already set up with the correct values for the snan_bit_is_one and no_signaling_nans config settings. is_signaling_nan() doesn't ever update the fp_status with any exception flags, so there is no reason not to use env->fp_status here. Use env->fp_status instead of the dummy fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 230466a87f3..d93cfed17b4 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -155,8 +155,7 @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ } else if (tp##_is_infinity(arg)) { \ fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \ } else { \ - float_status dummy = { }; /* snan_bit_is_one = 0 */ \ - if (tp##_is_signaling_nan(arg, &dummy)) { \ + if (tp##_is_signaling_nan(arg, &env->fp_status)) { \ fprf = 0x00 << FPSCR_FPRF; \ } else { \ fprf = 0x11 << FPSCR_FPRF; \ From patchwork Mon Dec 2 13:13:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846627 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1209232wrt; Mon, 2 Dec 2024 05:34:15 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW0nC7+ZcRhPNpmirYqKtXMLv33oB0tulBvAYmwangZTF77lEtcM7t+V5vDGZdym647dt+U1w==@linaro.org X-Google-Smtp-Source: AGHT+IHbWs1zWQKHdoGAzEwM7vB/6LweZRLzgOT6nAP5tK6Yh2CYZFZzYna1adb/z1DBomziER1q X-Received: by 2002:ac8:578a:0:b0:465:3a62:a8f9 with SMTP id d75a77b69052e-466b36b9962mr424874311cf.50.1733146455277; Mon, 02 Dec 2024 05:34:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146455; cv=none; d=google.com; s=arc-20240605; b=LqmyAdq1P7Ln5zICUo+R+Y+d5EEB4yZ4afvI8CQw4hsZ8Hz82ikZgHroEVhunEYiXP GK5kCzCZNi5maSined/vMv3/x2PpoWh2743BDG/gkGZxhdmLtC1cwB/Zljeou/Zd0AED E7BwiWdbVX0UaTmM0BQ+ThkpM5gI1/iE0BhOcwCkyVujTrDrr9P8gPGCt4a/Wtyfyy6g U9p+fCl10Ju/gMN9kvC0lQZE6wWw3pRWZEyU+l5Pd4WywoQnDm39VefyotYHZn/hPrwk W2lmxBDCY4YQT4UyyZ2n8AgS8eySbtGsQNOKQ5gFE7ga/AhAg6No9geoN4ktUpwjx59y lb1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yKV708lbVufub1eS0i2nRrYGl0qdKJsRNu5HvpEXaMM=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=lkAuhhTzs2epME96Gunc22WdTD1fuPo/KCHc6j++uxN5LCykHb9TFAVoBCHAe+XG1O P/UAuDmx5Z8vSQIgJuCy0diwzB9f6CuwXmIDVSNQX9CMbKOWMgAL5qZJF5kizZjTxkls qQz4d5BrfJXqYMr843VyNF4rA4+GaMPgqk/qWMuBxZvihaE16xv5kYGiIJrNZ/CwnMQZ xFyE2DDjEP/8hjaGQf5cgO0Cyrkm2S/TfjcVzvJ5fsg5EJbhCDnywOwx+4d8m9uJM0pU oPqmMMNAls2Zm5Yemgtyydl4RqfNjQ9hu9cenL9N1yxu8YoKGiKg4J1zp616bGgPreeT c2rQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=limuPtMs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 34/54] fpu: Allow runtime choice of default NaN value Date: Mon, 2 Dec 2024 13:13:27 +0000 Message-Id: <20241202131347.498124-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently we hardcode the default NaN value in parts64_default_nan() using a compile-time ifdef ladder. This is awkward for two cases: * for single-QEMU-binary we can't hard-code target-specifics like this * for Arm FEAT_AFP the default NaN value depends on FPCR.AH (specifically the sign bit is different) Add a field to float_status to specify the default NaN value; fall back to the old ifdef behaviour if these are not set. The default NaN value is specified by setting a uint8_t to a pattern corresponding to the sign and upper fraction parts of the NaN; the lower bits of the fraction are set from bit 0 of the pattern. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/fpu/softfloat-helpers.h | 11 +++++++ include/fpu/softfloat-types.h | 10 ++++++ fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++------------- 3 files changed, 54 insertions(+), 22 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 10a6763532c..dceee23c823 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -93,6 +93,12 @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, status->float_infzeronan_rule = rule; } +static inline void set_float_default_nan_pattern(uint8_t dnan_pattern, + float_status *status) +{ + status->default_nan_pattern = dnan_pattern; +} + static inline void set_flush_to_zero(bool val, float_status *status) { status->flush_to_zero = val; @@ -154,6 +160,11 @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status return status->float_infzeronan_rule; } +static inline uint8_t get_float_default_nan_pattern(float_status *status) +{ + return status->default_nan_pattern; +} + static inline bool get_flush_to_zero(float_status *status) { return status->flush_to_zero; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 84ba4ed20e6..79ca44dcc30 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -303,6 +303,16 @@ typedef struct float_status { /* should denormalised inputs go to zero and set the input_denormal flag? */ bool flush_inputs_to_zero; bool default_nan_mode; + /* + * The pattern to use for the default NaN. Here the high bit specifies + * the default NaN's sign bit, and bits 6..0 specify the high bits of the + * fractional part. The low bits of the fractional part are copies of bit 0. + * The exponent of the default NaN is (as for any NaN) always all 1s. + * Note that a value of 0 here is not a valid NaN. The target must set + * this to the correct non-zero value, or we will assert when trying to + * create a default NaN. + */ + uint8_t default_nan_pattern; /* * The flags below are not used on all specializations and may * constant fold away (see snan_bit_is_one()/no_signalling_nans() in diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9f913ce20ab..b1ec534983c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -133,35 +133,46 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) { bool sign = 0; uint64_t frac; + uint8_t dnan_pattern = status->default_nan_pattern; + if (dnan_pattern == 0) { #if defined(TARGET_SPARC) || defined(TARGET_M68K) - /* !snan_bit_is_one, set all bits */ - frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ + /* Sign bit clear, all frac bits set */ + dnan_pattern = 0b01111111; +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ || defined(TARGET_MICROBLAZE) - /* !snan_bit_is_one, set sign and msb */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - sign = 1; + /* Sign bit set, most significant frac bit set */ + dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) - /* snan_bit_is_one, set msb-1. */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); + /* Sign bit clear, msb-1 frac bit set */ + dnan_pattern = 0b00100000; #elif defined(TARGET_HEXAGON) - sign = 1; - frac = ~0ULL; + /* Sign bit set, all frac bits set. */ + dnan_pattern = 0b11111111; #else - /* - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, - * S390, SH4, TriCore, and Xtensa. Our other supported targets - * do not have floating-point. - */ - if (snan_bit_is_one(status)) { - /* set all bits other than msb */ - frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; - } else { - /* set msb */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - } + /* + * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, + * S390, SH4, TriCore, and Xtensa. Our other supported targets + * do not have floating-point. + */ + if (snan_bit_is_one(status)) { + /* sign bit clear, set all frac bits other than msb */ + dnan_pattern = 0b00111111; + } else { + /* sign bit clear, set frac msb */ + dnan_pattern = 0b01000000; + } #endif + } + assert(dnan_pattern != 0); + + sign = dnan_pattern >> 7; + /* + * Place default_nan_pattern [6:0] into bits [62:56], + * and replecate bit [0] down into [55:0] + */ + frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern); + frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1)); *p = (FloatParts64) { .cls = float_class_qnan, From patchwork Mon Dec 2 13:13:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846624 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1208091wrt; Mon, 2 Dec 2024 05:32:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX/16xXxXyHmdqmSpCPSpZeMZICa9GLG2gmnedddnjiN98vdh4w8gUk2qlF73WAiaG92+4zTQ==@linaro.org X-Google-Smtp-Source: AGHT+IG1qykVtkEE5J0S/d3yfXaJyIE5T5UwqBdyTDRKCyrPV2DWtZU+Lo3J6/1AnSQRzz7osbFL X-Received: by 2002:a05:6102:954:b0:4af:4a56:1c00 with SMTP id ada2fe7eead31-4af4a5624d2mr24176752137.15.1733146352506; Mon, 02 Dec 2024 05:32:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146352; cv=none; d=google.com; s=arc-20240605; b=Y98mR9vBRkF442UqkRWm+kPXR4uOBlNafgkzAEolHFqEjKHsK/D02dQNJGC+NGqO4n j9mXBgLVP488B6MfBneyMZBynAWTdFwQNPNl7Y4JUXaf384pjjyrd3U7tvfaJYh6Kkk1 CJijrAMjkJgKkqh5lKhCEZRWJOPFvYZU+fGkjDglAw9nrLfM9MUm1WXXIOGQagkb2XV5 Rgxjmbk+xReK0ZPsh9E7hMxyjWlrdS5VnSzltz/roNdY0wKJh371TcTIOFqrI18Xy8qs MmDC7uzHm9GLyyIbZBEbTTnB5hMqepPiqXHokpvmvsH2WLLjc21tPZu2xsy0PlVljDEr X81g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=q4IQwxgZ7TI3dnLUr9pZJR/1M5zZVOxtymkRhBauZGw=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=jFn8xNmLtOvfGNNOI7ySgwh+wuT1srYz7ZBP7YTKXvaDeW7fs/NZW/qxHaj572le91 zdtKqt4ZO+hmkj2UqbuxWv3PP1gnsUMWjGzTH/W/BQqdRfPrjry4FbvY+Y1wEhXuWGS9 uoAtODkyGlOEMUNqtW19QEBVYjPBx7gQ8d/OJiw9juARZPtuEXhIErTsHS/jYGvlcbAl gvrHhRmYgdNYnR5IO/mUw9AEtQMar20fvS1DPFhrFOcNyKT/E2Ktzj4nYalBGK48PsKj gVOz0NJLE/mmHL+YVdNqjOhvqKMUaCk5C9CbmH9IQ53ys9lAS2DwEdZHj0a6FZiuCf3y 3Xhw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CSpOnLhu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 35/54] tests/fp: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:28 +0000 Message-Id: <20241202131347.498124-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for the tests/fp code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- tests/fp/fp-bench.c | 1 + tests/fp/fp-test-log2.c | 1 + tests/fp/fp-test.c | 1 + 3 files changed, 3 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 39d80c9038f..eacb39b99cb 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -495,6 +495,7 @@ static void run_bench(void) set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); + set_float_default_nan_pattern(0b01000000, &soft_status); f = bench_funcs[operation][precision]; g_assert(f); diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c index de702c4c80d..79f619cdea9 100644 --- a/tests/fp/fp-test-log2.c +++ b/tests/fp/fp-test-log2.c @@ -71,6 +71,7 @@ int main(int ac, char **av) int i; set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_default_nan_pattern(0b01000000, &qsf); set_float_rounding_mode(float_round_nearest_even, &qsf); test.d = 0.0; diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index f290d523ab1..c619e5dbf72 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -941,6 +941,7 @@ void run_test(void) */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); + set_float_default_nan_pattern(0b01000000, &qsf); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); From patchwork Mon Dec 2 13:13:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846641 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1213688wrt; Mon, 2 Dec 2024 05:41:18 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWiPG5jHNVgLtuge82yeyioELJmqLWBA/i85rERKUfigPVHLYgsp6+h4k4ROAoE8OJ52DqaUg==@linaro.org X-Google-Smtp-Source: AGHT+IH/QuKmlpkQ+uR2sl60/4DbwRiUNHH78H1fuU6gBKmeMp5lsFKZzWQnzAltWVIUJnWT9x3l X-Received: by 2002:ac8:5f94:0:b0:466:96ef:90c with SMTP id d75a77b69052e-466b3610acemr353057601cf.41.1733146877835; Mon, 02 Dec 2024 05:41:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146877; cv=none; d=google.com; s=arc-20240605; b=WAAem1XZ9vVI5IbSWlB+GndsHfHAYRQDrGZZVvq79XAAHBrSWndTLCDmjs1sgAnlDQ wJBGhLBqqnplm3DVA4mcJr2Tfi9Ia1iW53vibQaesxB66D9hUnvdJUjYFjqeIVvmunU3 h2koSdL325z3vfhxbmdVKetA7PgzrtIEBMsd1IVB79uBCI84MH8/4M90EKrtz/E7s2h1 l0nsi9cA2OoK4waoAkOQ1PD+lq6f0ZxjkSfDtPhnNKpsWRdDE64DcrguNzQljFoSM3NW E2DVohNKTGAOt5X0tM2QUd1NshDIYXn7GWX9//+GjlS6KKuHYvPkeL8M8/JVyyJiTbGR 8njg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eg5CLJnIGFMP+7pRukJjMkkCwPMh6g96Ep2h3Ltgz5o=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=cj2LkV9rioo1f4Sf4wL4GDrf+Bx8WUg0wEX5eHOoc2jdOLpGLHM2jwsKSjYKOT+Try 2R7YEwcRmyOAfNB/n91PBFDYZAqFQU9OEpAx8ZWQaciuOA/HQRsgeP8iDndQlummE4Uh tBOUlrPQ6zQsSRwDTMsmEXM6/rVXqVGJnghgTU7Fd20e0bqWLab/W3OH5abDr76MnhV+ 6ZcP29yIEG3pFAzkPUluNwx6oM5UCA/NQSNUhia8L0CXvnF2VJ2QbtwF8ELsrArViYro bb/ZyPE0Bvu4belSKeGvFjIrzbsRhKXoZw8ZC1yTt7FMQYdkzG5E9Anm+Y6eEvW0vBp3 7Kjg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SHxdBlKI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 36/54] target/microblaze: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:29 +0000 Message-Id: <20241202131347.498124-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 710eb1146c1..0e1e22d1e8e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -207,6 +207,8 @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) * this architecture. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN: sign bit set, most significant frac bit set */ + set_float_default_nan_pattern(0b11000000, &env->fp_status); #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b1ec534983c..d77404f0c47 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,8 +139,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ - || defined(TARGET_MICROBLAZE) +#elif defined(TARGET_I386) || defined(TARGET_X86_64) /* Sign bit set, most significant frac bit set */ dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) From patchwork Mon Dec 2 13:13:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846611 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1204514wrt; Mon, 2 Dec 2024 05:27:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVd/qQzexKcHTCcqC+iJwLI2FMHVEvH7b1FOF8uNe/00JzfRiC6lLDZ11UfWnaHDbMQiIb+IQ==@linaro.org X-Google-Smtp-Source: AGHT+IG/vW6R3CKZ2Byzojx0stDLtSI35XJ09YWVGE6Fm7HhtB7Z/u9zgpBYd4swgEzPROdWxYsE X-Received: by 2002:a05:620a:1a93:b0:7b6:6bff:d147 with SMTP id af79cd13be357-7b67c4c00a6mr3336030585a.48.1733146039346; Mon, 02 Dec 2024 05:27:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146039; cv=none; d=google.com; s=arc-20240605; b=U/J5INRY5aa/TgHIDWsUjIr2AeuthBWW/I+29Nw3G2wjt8H9YvqUaThhyqIcpDUtjt SUYz4utRRqcFCe5s4veMbwxuV7R4A6H0C5pg88sNAWyCqquedaGgUvXadrCPnAs2U9vf H57UB5TuARBaXl7XhMI1CpnJHc6dzZBh9FrcEGmKgxkSTPfl0WyzdmaCgWK5lTEGUKtv KLiODsmdhox3PvPNkcGzqdol4PMFZqc+BeYzB0weGtNPQvPiCmlc73sgCbeppe64QVnX 5locpU+XfNxC6Ru1Y/AqHxRSMdnCi1pMH7lmRH+NUu2K1/1m/RfbLB+D+k+1vIjgNcT6 k9dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TSWsGbiJd5nUa8W+i0kSSd0cIwA3gG9T6rGPFTmCLJc=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=bnRz1fAWzznBrzX7YPuWEeZXt2znqPaFS+oBOptRB9IVNmpVe4+dC4On3xdSGlIaFA pmcGlEUCOF9sHLyNMpPGrRVz6MmczkKr1uc6F4jpNZHI1+EOBACPtrcMQgRXDCd9Er77 eVHV+ZGiNVIzwaUvos7iiRenpEvcPUA+3PuM2kPtkvRqV8KXgV+s5asuSGtZfsf3qgsh Wvw07Odqk3hDFvs6Lxp2qPE61/61a3MzDKk7uCLojNJCrOZgNY+PMfnvH3YQVdSBqq6u 4ih7aW8JWCdqBwI92kTQ7N9iamc3g5usZPYrhBRx9CYAGQamhJDrBHr9NOoKO1/8JFPH bVKA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WnjytF3N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 37/54] target/i386: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:30 +0000 Message-Id: <20241202131347.498124-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 4 ++++ fpu/softfloat-specialize.c.inc | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index c8bc5b7cfb3..e788fcd1b25 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -181,6 +181,10 @@ void cpu_init_fp_statuses(CPUX86State *env) */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); + /* Default NaN: sign bit set, most significant frac bit set */ + set_float_default_nan_pattern(0b11000000, &env->fp_status); + set_float_default_nan_pattern(0b11000000, &env->mmx_status); + set_float_default_nan_pattern(0b11000000, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d77404f0c47..452fe378cd2 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,9 +139,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) - /* Sign bit set, most significant frac bit set */ - dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) /* Sign bit clear, msb-1 frac bit set */ dnan_pattern = 0b00100000; From patchwork Mon Dec 2 13:13:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846618 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1205889wrt; Mon, 2 Dec 2024 05:29:46 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWRbfp/dj29AGy6LNc4tFOK4vsPuJBh53dHfVKyWvSUt4ivEkk2d//VIxqbYv6AzzYHHtDZdA==@linaro.org X-Google-Smtp-Source: AGHT+IEDQj2xsYSoryUEXPL4xwDadVuHm9phZYzFSJhZi6nQE3oSEbP/5fzRyCc5xTYUBNs/1mzu X-Received: by 2002:a05:6122:3710:b0:50d:4cb8:5b10 with SMTP id 71dfb90a1353d-5155690c3admr28079238e0c.4.1733146186646; Mon, 02 Dec 2024 05:29:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146186; cv=none; d=google.com; s=arc-20240605; b=i3gP08FTM7Eszmrc2zE7cMG4yTCVEBfFnPuyTcgemW9FUq0vgJW45USqILnx5+hIIC y1rDOt53nkXta+PIuekBIyFrrG8KQb4eBPiZvn108JiZzckVTDa7bxMUVO+89YIS1VhM anAsqX1Yw5j2bDau+f07GJT8ak2fOxgkXgVZSjbslzbjlzH892wjL7od05z3hoKX2fPk Osq+aNHFcRt1oeEBrb0yM+M1PHGEX4Ka5n5eW73a4yLaimawCE/OeYn9Jhs2Rr+SL75v 74uGpfQ7k9fhLp7LYKLGLto2jacGVS8kDHxynDPbSWKfquCdh81DFnKH6d2AD+/5k9rl XyLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=j3RxyO1FT5e89Qph7T+rokhc4ELopzGup08oCLW4wD4=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=OjccSaLDwkTQQbK/qzv9cOMXSxGHsNkJbH8CY5fMR08fRh2fvsCy1OTifpOOHmAKz5 JGP6aiUnYMQ03Scbyta4gECLu/K+5A8SNPeEGqvLO059KIke48amAiev8O2W1Z4/6PWM jJABEWi6ym9tXmFdOJcqytwmq5oxmVGuCAk1BSUji2F9JjUWkcY/XO0JrgEOshNIkY/2 KFBia0sUk5K3S5yVZqwy0Dzy+X6FHRwANTd9Vkxe87WXXniHUF4PvX7FuIRgRe6EZxcC 8m8Pc0ZFnkyViz86ZGF4T+WyX/ac2DjDXYxe04a6qHZ29dlgw43eOgBcm9JgDeOKM9yf +YmA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jorZy3HO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 38/54] target/hppa: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:31 +0000 Message-Id: <20241202131347.498124-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hppa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 69c4ce37835..239c027ec52 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -65,6 +65,8 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + /* Default NaN: sign bit clear, msb-1 frac bit set */ + set_float_default_nan_pattern(0b00100000, &env->fp_status); } void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 452fe378cd2..b5ec1944d15 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,9 +139,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_HPPA) - /* Sign bit clear, msb-1 frac bit set */ - dnan_pattern = 0b00100000; #elif defined(TARGET_HEXAGON) /* Sign bit set, all frac bits set. */ dnan_pattern = 0b11111111; From patchwork Mon Dec 2 13:13:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846607 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1202281wrt; Mon, 2 Dec 2024 05:24:00 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUkIHb5z9NA9s2jP4EEpohCQOn/2BPu8EgtmBfc2+uokEAohzyGOWwfWTdN6ncobI19DNCUQw==@linaro.org X-Google-Smtp-Source: AGHT+IHXueYiO1pgCwhYqngtTzj0gGzOctB/KT8TASb8u17+trTaqbZDghlIPnHw8jM9ZH2Pgj3u X-Received: by 2002:a05:620a:2b85:b0:7b6:67a0:499d with SMTP id af79cd13be357-7b67c2568e4mr3754971485a.1.1733145840112; Mon, 02 Dec 2024 05:24:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733145840; cv=none; d=google.com; s=arc-20240605; b=Pn6haugzg99pMi3tRozPT1AGNgX6RfddJF0Aal6xGV8Dmjp4f36AOSya1nCMKpLmjt Uj11Rs3b0T7SZOvlPGXhe6nx3bYUGNCzYo7UbscbUYJASuW8hUzw2HA3ncm254q5YTye F/EeLkjiQNyUT/Z+KpfWKXMlP6CirzhXnb6aLTY5OE/v6RG7Hp/Ju368cofkg96vHXSY +3sTZM8fw6JLXCDF1limbDj7Gj0+lI2LwfnDqi+TVaahpwAlWMuMlYu2aIMSCf1Oa7Gy O8o7C77DR+hO2nYjSUIA8zWsVAG5F7y4IUgUh+L9v8EG0TmCcI/EAOke8H3KHE/Fd8GP aJRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6b67TuxIIuUbvFPYapA8HgByL1UEo/kP+YGdKuHFudM=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=cenRc0OsBjqH0ojOd5GueeAhVnLL47VoeUNtc4Y4wdwI5S+7K1V50PTvlVtXqMAKd7 mbMXG0yGlSgC9v8EuKz5Ayc4VpxyHkxOj1nwX3k+hDzDquH55qvwNdRMkTrwR+Jl1pnw 7ZCsHwgyCGhOYV3H5rEY1XUj8UQRN3iDgUD3s16Ndm16rZTbibDPRixefHcRShGGeC9F RK42qAk5vypV82ob3h2jTwINnfG40CCEXEBXlokOz21TZV3pW+APWx8ylQTAq3IKsr+Q bd3VJk52gNnYRPR1JwBwNbEOriWKKF2jvMuAnisXkRQxxsMv316ECyaHXj5Zkjo9dpNM PrxA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E9BQ0oLv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 39/54] target/alpha: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:32 +0000 Message-Id: <20241202131347.498124-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for the alpha target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/alpha/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 5d75c941f7a..70f67e6fd4e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -199,6 +199,8 @@ static void alpha_cpu_initfn(Object *obj) * operand in Fa. That is float_2nan_prop_ba. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN: sign bit clear, msb frac bit set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); #if defined(CONFIG_USER_ONLY) env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD From patchwork Mon Dec 2 13:13:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846622 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1206992wrt; Mon, 2 Dec 2024 05:31:08 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUPX3Jrcv8/IrX7gOb+iiDxG5rsXAw3IjzJ7osmlfaOWU/axRKwxlEAp/9rupHJVMcJkAd40A==@linaro.org X-Google-Smtp-Source: AGHT+IEuWKMU135LPo9U4Xi8KDb/ncQhwwYTUBBfBVWLgeeKkonVKjYU3r6wun+JT07V8bsoxnaQ X-Received: by 2002:a05:6122:8c0d:b0:515:5008:118b with SMTP id 71dfb90a1353d-515569aa362mr24423179e0c.1.1733146268104; Mon, 02 Dec 2024 05:31:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146268; cv=none; d=google.com; s=arc-20240605; b=bcxxKM0+nzpRLuwFJ5fq6K5Ee9jYy+uNwpWESidONyAGfcMJPihL2uzmKn5zePtMZP lC615TzHycUw4gtWjZE0/6VswMB8+qb7L6PD4q8sE+rsZvgoukc8gpJ9BqRwjvu62Q5U RIDKlkxDOS5qZRJBbp2chyxjuBxLuyan+eMvZ6IvLLQiJiEIVQ1rRdn54rQ2gDz/BUyc EK3HprcV+n26SSrPdLpCpP/HnO1jA6h0e2KVelfeWhuCmWv+iSOLObt7J1sfVFCsHtfa rvuyP/A6Gl7zeflw39pw02Az0h8PFyuL2KVpiSDjuDtHs4Lk+3htXj3uvgofNUCU4e6e tZyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=te7O3NG5V4E3qWDfy7w3qXeqH4l7GoDjlHVXASIpOuQ=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=RdzHMbelMZIR4W6oiu8BgqA/fHytiWWtRF66gbB+Ccp9V9kW0iR8ty4dRssUPRHPhB J+a9TSrRplGHfQ5HvZtBUEK/nzGkbQxEvDXCzJIxT78cpMZuTwJbuySqZPVLR7g+4cI+ ucCWXuWaF7u4Uf5m9XaIm/wdqf9csfMkBT9Ygsc/M2aMNVb/jMKF2dy5RMfU04EfKPoU kOHpabT+yPh07ABTFWJjJ8kZ/FeoK7uxt0r7yHdqVV6xJqvbt/DQcjJHyiLzqcfpE7K0 vbpeKC2p6LdiWgE1Z+WqSIaMuZwNcRhlK8BU5EL9LqHzqOnks/dF1a5a9AcwY17f2UDG i6/A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=poWayr43; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 40/54] target/arm: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:33 +0000 Message-Id: <20241202131347.498124-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for the arm target. This includes setting it for the old linux-user nwfpe emulation. For nwfpe, our default doesn't match the real kernel, but we avoid making a behaviour change in this commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- linux-user/arm/nwfpe/fpa11.c | 5 +++++ target/arm/cpu.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c index 8356beb52c6..0f1afbd91df 100644 --- a/linux-user/arm/nwfpe/fpa11.c +++ b/linux-user/arm/nwfpe/fpa11.c @@ -69,6 +69,11 @@ void resetFPA11(void) * this late date. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status); + /* + * Use the same default NaN value as Arm VFP. This doesn't match + * the Linux kernel's nwfpe emulation, which uses an all-1s value. + */ + set_float_default_nan_pattern(0b01000000, &fpa11->fp_status); } void SetRoundingMode(const unsigned int opcode) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c81f6df3fca..4f7e18eb8e6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -179,6 +179,7 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * the pseudocode function the arguments are in the order c, a, b. * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, * and the input NaN if it is signalling + * * Default NaN has sign bit clear, msb frac bit set */ static void arm_set_default_fp_behaviours(float_status *s) { @@ -186,6 +187,7 @@ static void arm_set_default_fp_behaviours(float_status *s) set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); + set_float_default_nan_pattern(0b01000000, s); } static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) From patchwork Mon Dec 2 13:13:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846626 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1209045wrt; Mon, 2 Dec 2024 05:33:59 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU2q4lhE9pyTvxiP+8SIb7c25Pihg7P/R+MVlXk20zcHlgUYevjZOs/mU7xan3TTsuPsNHItw==@linaro.org X-Google-Smtp-Source: AGHT+IGT07VI49giC9AnUaD41Sg3JtCoNdkj5PZQ79zaRSrHamQb5Eg/ysE1RXLks9+ADgepy7Sh X-Received: by 2002:a05:6214:dc4:b0:6d4:2748:ea19 with SMTP id 6a1803df08f44-6d8729ce609mr349406016d6.16.1733146439024; Mon, 02 Dec 2024 05:33:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146439; cv=none; d=google.com; s=arc-20240605; b=g8bN7Z0ltYBg5mvUDDTkAmfc5aufUJBoRxBlhpeZyUb5Q/uUyQQa1hkWEgo6C+tu4q dJdGU50jc2IXqhp7MCLp5850BU0Fr5eTGTJhAC/k5if9Cfd9IV98vq5PZTZzrphu/Ru5 TUUKaL17YtHAfWz14M1Xc0Lo7h98OziHEqHk7wyFWmJFx22gHqY4hExLQr4274PmUt13 l4xxqbqFmZXlte+UorsRWML/1+50TQKoiYrRog3ZQpp8tbMLtTeCXgGegfETe2Q77aGQ YeBomjXuQNLO/oPqjAbmdJGNrWBAHT1sELSYVNGHCs9UIx1vxmbx+LuNQFEm4tYwqbB4 L3rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mc9TdQ5B4JVTfGpbGlyL+6fSC7bsW93adDUcKdH34tw=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=GY7QgIjIrh+wNyXbWUUvkoaUk/i821ItQLIzUPn0UXpfVVVUYCAfzOJEJkpVcjOom3 HKrnwVIsa9JAOhf+aftDKMpHSm36jRLNMVG9ipgdNId0gjpJaIOKpJ6WieeOcKs6ZzTC JmPc5CVuh/CGWIXt5Lbghx1Gh0u0VW/DssGocRSykoW2PY/Z8z2uFhCsNvrz7RYq+RTU sXsW4GSciKXXXtESVg5Jbd8DYYeOAK8QWcqBbAnh424mbuZ0y45i7DCRnJEcuqxGfGsT ZFmAg4xVH6l0n9A5omOHbSDpSTRlcfOuB6ivvNo12atDX3EoPZVcPspAOIP5qbtC5lHj h7vQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UnO6jmJa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 41/54] target/loongarch: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:34 +0000 Message-Id: <20241202131347.498124-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for loongarch. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/loongarch/tcg/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index aea5e0fe5e6..a83acf64b08 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -38,6 +38,8 @@ void restore_fp_status(CPULoongArchState *env) */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); + /* Default NaN: sign bit clear, msb frac bit set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) From patchwork Mon Dec 2 13:13:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846613 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1205192wrt; Mon, 2 Dec 2024 05:28:30 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXJOXe4L+eMaTUnLifMwq4XRzEjtXbae0mJhiR20EVWu2PnYeZiG1gyxKIrL3+e7NVOS8pq6Q==@linaro.org X-Google-Smtp-Source: AGHT+IG1CfQcVygqsgPZauCGpGzvIT5YCw1fwg4kt8Lpw9v0rmIRNyvucJISo4cO49rYwq6tjb7o X-Received: by 2002:a05:622a:1a0e:b0:466:adbc:f1e2 with SMTP id d75a77b69052e-466b34f2f94mr392002851cf.18.1733146110252; Mon, 02 Dec 2024 05:28:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146110; cv=none; d=google.com; s=arc-20240605; b=M2d2ZZV9i/+hhprstRuxKwU4mYtwFV+jSdwU/J3jWPe+7ZsaU2O5hIYHbsSAa/Rg48 S1hRo5O7BpK7RvjT48zBoyz445llAqgFKpAEzjwm6cp8RiuzT5qo//dXYun9hvYLDkVH lbkbB6G6zWbfbINQyMe+o8NcTz2eMOos97fG6p5X90XBP16G17IqNPY4QAKjnKnb2Hn3 0RzKQ01fQBp5KI4UnCgzcgLzVaGYx8ca+hVsQ1y0we4cE3jeznXzHCeFxngd6VtvFgbi /Tv+sI3y/kQG/FudAsAuSeJ6SXBLoYO/u1D6+YuQEWKz5TzKHDoOmpnbA/iE+7Mv4Puo 2FNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7mmqERnKJTYNHU5Lv8qXJWCaRjH14PqNpgofF/931Yw=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=PBnlFD2mgUIYWtzGr6f2/F5YW43Z9aqgGGTbB1cbX3XTXgieKyr1RZ/kFoLTOB4uua LnAMJ2mgPzONrWwWnaMEuuVqLJjs+OSY0mc4h7zrXFZuV7rEmWy1sig5g8iZsSA4+UaE rlsST+SQYkigdMAhopsjI0N9pFEJSmo+KdovoccO+P5Gm6tTc1DR0wjkTYFw0I0KyDE7 5O0LWtLoVY5EAmCH5vcYU1+xwc0lzFMPtgr3KyeYWkMSZL81EAOB4wOgLytGNQQQbA0V +i1br5byNdyuaBlodKQw7PduM3HV3QavQ62BvO3F3e66ZYSr0Cy4l9CKSiZbDWcqrmqw zx0w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iuKSdGLo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 42/54] target/m68k: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:35 +0000 Message-Id: <20241202131347.498124-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for m68k. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/m68k/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 13b76e22488..9de8ce67078 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -105,6 +105,8 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) * preceding paragraph for nonsignaling NaNs. */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); + /* Default NaN: sign bit clear, all frac bits set */ + set_float_default_nan_pattern(0b01111111, &env->fp_status); nan = floatx80_default_nan(&env->fp_status); for (i = 0; i < 8; i++) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b5ec1944d15..ecb7a52ae7c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,7 +136,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_SPARC) || defined(TARGET_M68K) +#if defined(TARGET_SPARC) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; #elif defined(TARGET_HEXAGON) From patchwork Mon Dec 2 13:13:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846638 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1212955wrt; Mon, 2 Dec 2024 05:40:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWj6nhaWxHE7ogsTIga7ugNgVW/RWtSsq7i822EfvMOiPedhl6mmKnXZNlfDnGheTG0NoUIUw==@linaro.org X-Google-Smtp-Source: AGHT+IHkNODlA9mG9RoCiBHazFJaoFxfD2hI210CFr6nYdXYMLXObImV022SRImzDRyXGLRvII1D X-Received: by 2002:a05:6102:3051:b0:4af:5c79:4f8e with SMTP id ada2fe7eead31-4af5c7951cbmr21227101137.7.1733146801443; Mon, 02 Dec 2024 05:40:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146801; cv=none; d=google.com; s=arc-20240605; b=jskyeaT1vzdAlZ6/vL9+0oQ8kqjNunQ0k2QLCQW6sehwDOjmJ/6eeDFT+t+Ha0wUJD /32YgvfAKRuTIMNdZH9vS6pNAgANwZkZ2OQ8ey2If+tU2Rmtt563GdkTgtuJXjLisR2l E2F1hJf6KHo4LMgbe6KB5dcvrlOZTtnHqeIeGsn1hEq9VvhAedlZD3r+WK2nv8F5/7mj nQIMGg2n4FiLQEmG4QE+BgpeM6iNa7NMS+/SHEd79UP5pFRx1L3i88gijcR88Ny+gQtj w9TQT9Mibh/PaHUiz8Rncf29iC3crLkaJYiieRpx693sQyIc67JWG7ahQbYkGI9uUhm0 9YOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vygoGC00xfYC/uInMNcn40F6CC96Rh4moS0oHLIBbXA=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=SJLU/rS15BAxRsRRMBZ1gXgbHjkCVJd7rlbqZA1m/Sj/hyDISmU03PkOUlQ7YdD9qE HyXMgWug5OVw7tyf6QXDByU8CITj/XH2oL3+wJqAs5bdgRMJ+W1eXYJ9qcCyzmBeHNx6 G4YnNu/JY2gnEwgYDUj+TM6tj0zbpyl8Dj1Bu1IZdwUoblnUEy3XtzvXjC7gA6+mVOms e78/PFgRIaPwVjdZvEnUSG4kgWKiNqr/Pmg0K7vP9Dh2vAIoLE6T/wd7j/QUz84orIDa dxjXBhdDrwt1jzxCP07uQy8NKgiNILUtrt3eMGynzQI+s9L+DbEFu6sdJYYBRl96MfhO nlgQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ERypsltw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 43/54] target/mips: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:36 +0000 Message-Id: <20241202131347.498124-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for MIPS. Note that this is our only target which currently changes the default NaN at runtime (which it was previously doing indirectly when it changed the snan_bit_is_one setting). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/mips/fpu_helper.h | 7 +++++++ target/mips/msa.c | 3 +++ 2 files changed, 10 insertions(+) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index 8ca0ca7ea39..6ad1e466cfd 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -47,6 +47,13 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); + /* + * With nan2008, the default NaN value has the sign bit clear and the + * frac msb set; with the older mode, the sign bit is clear, and all + * frac bits except the msb are set. + */ + set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111, + &env->active_fpu.fp_status); } diff --git a/target/mips/msa.c b/target/mips/msa.c index 93a9a87d76d..fc77bfc7b9a 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -81,4 +81,7 @@ void msa_reset(CPUMIPSState *env) /* Inf * 0 + NaN returns the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->active_tc.msa_fp_status); + /* Default NaN: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, + &env->active_tc.msa_fp_status); } From patchwork Mon Dec 2 13:13:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846623 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1207551wrt; Mon, 2 Dec 2024 05:31:46 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX3A6GLLqAqX1kCBLwELusUIWubmSKeyvnzGRQMTh43OXGqJ74qgeIZ7lDontZXEgNMkI7Ikw==@linaro.org X-Google-Smtp-Source: AGHT+IFcYIXEVpCukMk8MGSwOWeQ63IuhY/3hAu+L+cvCnSz3MCAg9ztv/Aag21dZRA2Um5rLR0M X-Received: by 2002:a05:6358:9386:b0:1ca:9dcc:e6b8 with SMTP id e5c5f4694b2df-1cab15b63b7mr826942055d.10.1733146306229; Mon, 02 Dec 2024 05:31:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146306; cv=none; d=google.com; s=arc-20240605; b=PA1zAxJdTnrMSvkff+Iw7a/nbUxq5E8ODzYSIi42osymdQ1Kosh8sH7T1SMvMenr+H ttbAZLzvOJlMfXVZgKUIklKRguJbVut8oY6jKJQGo5A2kh5wYPWFs6RB/JhdZJIlqsg8 3rm0PT9o5pg5VdeJTd2visu4oWmvc1vYieexRHqCWQSZ6MLkWt1puEnOps0yFm/HDFAK yfjs24o2XmdfDG/B3Ze8Xb6g7kpl/Wa8pMOAqBb8T4nXPbXA+8+QMmG5zZ89BeGqkmfp 6Gl7TCIgIg9SEF3DeFNytLEmV+UU/9ezNA0nXaQ3k+11no3EoFgbnAWyiOwetybXH2vF lbyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1acc7zoNKrBVtOlWY+W2T5QYcrfhAL8i8cxJ7BeDz+0=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=I0zZ+o2rLsluWMm6lqvUhL2CtuyR81m+LPqGB5SA+Ixs/ogWAetCD2/NtrwYVLbdth DwRtguYgWIuib5/BqzF3bq6SCwngjIh6KaCeyxNAq/QLwWOgb8x0txB6fHsCU3RbIpNH 7U8p0Fix+L3/8KXFljAsTSnjf68z8EJOBUG5WZIzqmmXN5F7A9Wn9Ck4+/X7xiv0Ev2T NPZ3xFyUtfr0kgWhjXtqYnE0XQT+BIKdWbvX7GebHZ36pzPVMgzpOkHS5GNKT7fMRkTQ stLYcBdlM0gbIDxQQAsLoN56O8jQTsf3lijKNpDWZHBfZLskDQ2d1C0csW63DKy8pnV2 8j9g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XQlqIJTL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 44/54] target/openrisc: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:37 +0000 Message-Id: <20241202131347.498124-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for openrisc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/openrisc/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b96561d1f26..3ccf85e95f0 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -111,6 +111,8 @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); + /* Default NaN: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; From patchwork Mon Dec 2 13:13:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846645 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1214632wrt; Mon, 2 Dec 2024 05:42:56 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVlCCOo4yvR1MVQc3hzvNB1+QzlOc9cXEP2Ozm9TUuLV88jnRvxfXmrMvadngibt+2G65on8Q==@linaro.org X-Google-Smtp-Source: AGHT+IEiueSQVllBeKuS9NvlJlUVh+Cf+8yxuuNXtj0+RkMKB0QPCQHrVsQJCs1E20GRbpo8BB5p X-Received: by 2002:a05:620a:6086:b0:7b6:6701:7a48 with SMTP id af79cd13be357-7b67c4a0ea8mr3866519785a.61.1733146975901; Mon, 02 Dec 2024 05:42:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146975; cv=none; d=google.com; s=arc-20240605; b=TlWPTlB8G1t0Da7mp5FsESoi0UxRBX2WOfMSW1CADhvl7xeenfFb5A6d0+4HeF3S08 MV0q9KBF29H3kDftmnM/Fmdy3rhS0V9tFiuKNkHjGH6Agva11ltg1S0QXlazICY5LVWX gU1C683HjpDUPzJ6BJs61IwSZUi839qP4nfTs6376RZwoQBF7MwnV85IPgENBdpUuQLv +1pNyjPCPoibBNA/fSAoBLIzTK15J/VZp3KOI0oN3hO8BLu95Cv1+xF8j/9AZNxc4WlT 4LgY+sitYsJlw7s00UDEX3xpAKmH8skY4HtmEMq7FKSjEPZfDUKEb4wMhXrKUfoWx4o2 OXXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KxLOQbRoeGb10eLB+8NmOgmz26mWmDSAJp80nLJIeco=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=Zd374bAYYcVg21NzL7C/I/zrF9JgLsI+0/8l5u9u2tJvePfB5ru/3+cyq06nZpgH4D VdNQvunqv2+KxlR2XAsBkbm3kHA5lZCOV6nUGx+lOfGdqzCGwrkhSoxO1f39YFnJl5ZZ gDESM+4RZTiwNPbH6sm+gz0ch7PPt4FXKPpJVv3KWm8niDSyB+plCtiicmPbGA/ifc4X ApLci8tF7O174V0FTwh5a+zczi3yekaBmS7jasMJGBV/7EcNxgbT+AZCAa/szJH+yJ/r Ip0zbT93tRzxAI8muJbsYg6uRnpn7N9/Xz6DLd29pUwceDKDfqsnx+Qg/xe0vnGc76U0 sRsg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l6ueompu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 45/54] target/ppc: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:38 +0000 Message-Id: <20241202131347.498124-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for ppc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index eb9d7b13701..1253dbf622c 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7286,6 +7286,10 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); + /* Default NaN: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); + set_float_default_nan_pattern(0b01000000, &env->vec_status); + for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr = &env->spr_cb[i]; From patchwork Mon Dec 2 13:13:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846617 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1205817wrt; Mon, 2 Dec 2024 05:29:38 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVE2jAjPZ/P9n3tqhtd7kzc0Cp0i53ne9RRnL3kKzUbGKN3TBS/F/NlHY4c946cu3jtTj8XFQ==@linaro.org X-Google-Smtp-Source: AGHT+IHwVORSnm6O5tAGJFte3d/+R/tGT8HkpOMSprxTqBevJycgWHr2CLYEkGbjBog0u/MGDaI6 X-Received: by 2002:a05:6902:2b8e:b0:e30:c614:5c40 with SMTP id 3f1490d57ef6-e395b877bf6mr21463606276.2.1733146177814; Mon, 02 Dec 2024 05:29:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146177; cv=none; d=google.com; s=arc-20240605; b=lozflh+/gC249Jyd60AAZ6r4xViuDFyfT/0y0UmIEEjtrCVTUc40u4ui57p3UGpHMF L/USoQjDn03CtrsZIlXzm1x6YMNT6w2mqMFHvmMCPSSAQ733x9AEtBNu50Matms0U/np OPG3rO8lsth1cwDKYJM7je+WaWBAj/bgRyUINz20bmJO2xCC32hopA659dewBXNvw5Mg nVCl/m9xyWtnR3C88iyDj1n90SuMpNB5epa7OMZQ/GK/XJzXDrd4clW0boYQqwSrXDIp /HbMjutHH6paqsrtMtEXIJ1wQmgsK4WiNOP6pjwAgPuqGtL9P8kpQ64m2JjEGBa0TzVq JU5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Iti77Qpa/qys0505SaJu0EETHGjGdf7P6zBWbzXMDlw=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=OSuFWi7PIsIMQsUpHcJ0CyLnNPbN2drpWq1IUB1F0YjgXlUSIrxUusfWxtockeWDAQ teZpfvZPmaeEKi5STSQqPZ9TN2tE6bpiW7Zsk+ZTtEd7YJMNE8ex9dOv3Y9Ov7odJ7fP GI+CnHmVN/ljDQzcYeHu8PtdqG5wXYnZaj2ryOrygtdcRG43lr8g6M5Mpcc62awAnB8V 1tEpc0HeBWF0W9R0m2MfCQ0om6aNvc95nCOhfzD5450t/Adl8MLhsBbNV2GnMxK4G++J j/oYZWWtOimsBVDPy/uKKrki2rkmcWdIfH8EFx5evSOo7N4O7pC2mykG1gCz5ovqMdaU YU1w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DcxT71Ka; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 46/54] target/sh4: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:39 +0000 Message-Id: <20241202131347.498124-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for sh4. Note that sh4 is one of the only three targets (the others being HPPA and sometimes MIPS) that has snan_bit_is_one set. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sh4/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8f07261dcfd..d5008859b8e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -127,6 +127,8 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) set_flush_to_zero(1, &env->fp_status); #endif set_default_nan_mode(1, &env->fp_status); + /* sign bit clear, set all frac bits other than msb */ + set_float_default_nan_pattern(0b00111111, &env->fp_status); } static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) From patchwork Mon Dec 2 13:13:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846630 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1209968wrt; Mon, 2 Dec 2024 05:35:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWRpd/20SUJppl6ym+KxGJTz8PWhF7nVb4Gq96tOjHYO1YN556xXsyL1dlCtUTCyx6OcsENCQ==@linaro.org X-Google-Smtp-Source: AGHT+IHgPDbHsJa9/ZwE1Nf+Wip0aQYV+77o+b9lktEHnriBlXL26oVaIjLpGzheJF1vZtYT2H5v X-Received: by 2002:a05:6214:3004:b0:6d4:1813:1f20 with SMTP id 6a1803df08f44-6d864d0b0c8mr388661656d6.8.1733146519047; Mon, 02 Dec 2024 05:35:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146519; cv=none; d=google.com; s=arc-20240605; b=KsqfPN1fRHxP6J9kmum93aDnXrFew+RtKvkGRqcJpG894IdxP+n/Bw6t+WIbegtxCD R4s8f4C02mmcYHTYnO2TfpLPiwV/f7XgwBcKeDKP4sElP6gfvDIffUI5GeIKDuAbeJ4O AaMVDnzyo0pECh2tOkeJwEWmpur+NGoWPH11H355+MQXPTX5//HOWAXW34iZdvC7l+8e C/ZX0zbb8eRBNZxU3HHKfbinmAYFNSEggMrvWsHFz75Ose5JPgxa+COWpCAAp50Pzofz 8DCR2XvByrume3e0KeR/JwgooB7IiLKPjef8FWKBkM7T901n6RDnfACQ/048Rmz4yRn8 YGpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wIjZFE7UkHdsOrQTCFo+cXQ64MiE8Y6c27yOZdc2SmU=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=lnrIJUuobRvBZ+jOg3Jrw0PRP7hBFDbQxxeQToQ+CsfQ+1z1yTs38EhWrVF9EUxwUs AZXMaD6Nsk+Ks6UNkycK3aG+U+nAPhs425MmAjkOMrvpY6sag4bGtcXAbyIluPtlQGci PRwMeo+WX0r8HSZu6x5nI4tpXoz+4tsmDLOGBsbKlM7xiDAlc6uelhEAM4QQxg1LtlLr HzWKGDh/qOr0E1ZQb/BsJOgMPh69KrMd8XVX3n62iSYhUnMlemPdNBs2gnViN175k8s0 U0iZ4b8iFtxdsREODGiokjd7p0/VyVYo+sWELUZ7/t//NnLRZ7XxJNJsz2qmdWorScOY MBEA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="zJFYt/D0"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 47/54] target/rx: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:40 +0000 Message-Id: <20241202131347.498124-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for rx. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/rx/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720f..69ec0bc7b3d 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -100,6 +100,8 @@ static void rx_cpu_reset_hold(Object *obj, ResetType type) * then prefer dest over source", which is float_2nan_prop_s_ab. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN value: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) From patchwork Mon Dec 2 13:13:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846629 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1209732wrt; Mon, 2 Dec 2024 05:34:59 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWXi5Qb/YoQPAwN3hSOGj4RU7fM9cAWzO1NPpfEzZei286dMlgx8YKvbLlnf9wDJxN75LuHeA==@linaro.org X-Google-Smtp-Source: AGHT+IFmzrxniM+EHtM14aVR0B+HBnQcjiLOLshSQqbupuTl8InpGFdraU8QH1D0WuqlGLbjLjcV X-Received: by 2002:a05:622a:24c:b0:466:9938:91f3 with SMTP id d75a77b69052e-466b36b90cbmr352533401cf.49.1733146498897; Mon, 02 Dec 2024 05:34:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146498; cv=none; d=google.com; s=arc-20240605; b=Crf25nCjZXrPQRveFSUIxf6hzgSyMnfuWjreCD//hBgvpkRhLrx4slGbjEzSNuitRi iQUxcJuRTeX/BuIeg5LXna22FDCNJIjcS9MzABO5zcBN5kNTAcPqII7NsXBfEEbhHaqk K7PvrAfmpYwXcBrajQbRxlVMIV5mB5UuOZcIFA8l3IIAUYjKPWhxZWR9J3kLMoblGIJG jSZoiAdn1mjSfCAlL+ua8Oa3fr+mWs0zUFj9dAsnULH15UNtUb/d+jtWF+PZ1xDli+Qh H71klIA3USKLtIkMnNcM6ZRKOrsgD2/28YIY50kUmjM3K79JO+Wk9X85pC6RwnrdSbhw YekA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GcCmSt30lYdPKkQM5ubQPjbLlX8F5CbU10wVOuOifdc=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=WY7QBcVLxESVJqqhBcR1+iH+nfTbogzIORMG08XJzGZBbQqvPATVvISCw1deicR6qY l/a+HLIYYasNVimmWeUJIqOFKR3G/gVuytk/T+Lzd2KcOsOu+vF0CBF2i226/VFBlcKT CETb28NcyuwIZ8xY82sZ6r18dWU0Zh4C6UK24cVnH4vSSvhwZFOP/fN/kVAEKovlidPB Vx0GvMknxUkS8JAycAgJfEK1gYqTDY1TEon3jfMU+ZAN9kAgaQ5U0G9zi0hr3cM0chl/ M2LOPsoZD397h1oKhB7ymoBzJvGq5KKqL+ODdp86sgId0eGk+b1Fo88fd+IWh8k4Yr49 gLUQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cBZvp4eV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 48/54] target/s390x: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:41 +0000 Message-Id: <20241202131347.498124-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for s390x. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/s390x/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index e74055bad79..adb27504ad5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -209,6 +209,8 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); set_float_infzeronan_rule(float_infzeronan_dnan_always, &env->fpu_status); + /* Default NaN value: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fpu_status); /* fall through */ case RESET_TYPE_S390_CPU_NORMAL: env->psw.mask &= ~PSW_MASK_RI; From patchwork Mon Dec 2 13:13:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846642 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1213855wrt; Mon, 2 Dec 2024 05:41:36 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVwXDguUYWuIgJ1niFzRemHFsEoWJKIVuqND6iBsrhKYuN6PkAH9th5fGfbEXOjgph/wpRhyw==@linaro.org X-Google-Smtp-Source: AGHT+IG73+3nCTrDGQWgyV91ZWIxZ44LSjjOZyVffyng4HdugSmqMTHCHYEB1Ygi38p6ZM9vEY7g X-Received: by 2002:a05:6122:2190:b0:515:3bb5:537c with SMTP id 71dfb90a1353d-515569e2815mr24044502e0c.10.1733146896274; Mon, 02 Dec 2024 05:41:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146896; cv=none; d=google.com; s=arc-20240605; b=ZJeUQRRWylm94Gm9EUl0HcOtmQoQ2wQE885Ijv8O8LyRUZ0w8zbLnDMGEuCOcvAI3P AcwCtWRbMCmOLSymGI2YlWiHUu+xcG4iPrQNsFnZ43nXde99F0Wap4N/+uJidHzZXcij bIdQsgnuXZ9KK/WAD7pYw1VgH8QYLh5xmDulX1HUC3KfH11JmpuhUJWTQ+AqLeAaUlWh pBwhdIUMaLnoYNclb7P/ZX8q9pBEZ7qPGHxiaJxuGoPyW7nbiq8y6MsDOkPc0xgrnPzb LXTrte8yW8/AV1o2F7gMRcLO45FUpinRohELVU+fz9i/dVjbI2GcU46391buTwgRo3dF VQtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2ViFvWD2hAYTuBKEMhbDqPcZsE6RzFHNeiujTaxjrOk=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=JYR8tWxfQ6WH8bp2LtsDvafO+mkLmprsvG671Mm8Aq7nywUQkANa7Qd8eDapKb2+ua MC1JU/Voi+SD2aNoSWiC8+q0vAX7N54LZ8Hh4Z0E+4iI9/kbhol71LiWGXXpAsZYPN70 gLCLadEGs1fv7sPgkznj5OfNTKZ7ya70uiLH/5eDSlP1sU0I7wnSBhTqpUy9KJpQULV8 +pED5W/9CXJBTCmS9mKPs5ZBVorzHFwdcLZDZtunJMevQElwMmQ7CbNZgSRUcHwYfGF8 RTPFfIHqKWLI418LTy8nnHtI+J8Uolxrh3EZK9sxcga3sYoqduGPu3+6Kj4CKFOEwJS5 esyA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x6KNhgX8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 49/54] target/sparc: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:42 +0000 Message-Id: <20241202131347.498124-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for SPARC, and remove the ifdef from parts64_default_nan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 5 +---- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 0f2997a85e6..6b66ecb3f59 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -818,6 +818,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + /* Default NaN value: sign bit clear, all frac bits set */ + set_float_default_nan_pattern(0b01111111, &env->fp_status); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ecb7a52ae7c..06185237d0f 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,10 +136,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_SPARC) - /* Sign bit clear, all frac bits set */ - dnan_pattern = 0b01111111; -#elif defined(TARGET_HEXAGON) +#if defined(TARGET_HEXAGON) /* Sign bit set, all frac bits set. */ dnan_pattern = 0b11111111; #else From patchwork Mon Dec 2 13:13:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846636 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1212738wrt; Mon, 2 Dec 2024 05:39:37 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW1gRF5PyoodUaxFmBahkLprPtj/y/FU/tIG6PDwURriU+ZsBH5EyOj2X5V/6oelTL8brSgGg==@linaro.org X-Google-Smtp-Source: AGHT+IEEvwMM+DjQk1TJ1BmLiFgb36F8JgmTvswMAzEDoDND2ohxhMtUjvzIEbWPzxr0f+nnPyVz X-Received: by 2002:a05:690c:6384:b0:6ef:801f:437d with SMTP id 00721157ae682-6ef801f483amr54767947b3.26.1733146777602; Mon, 02 Dec 2024 05:39:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146777; cv=none; d=google.com; s=arc-20240605; b=B0qonKxrijcgSt7ZRv6VRO+CWSGIemDXWuEdsVUoR8Wl3OwIm9qupkGwt5MfP3IMJL 4N/HuUBT7MV1AVdWak6PfM91x/BTv6vnsKVPQUvVmde198HLwTT+19TW2WGN9wZKLI0V UioSEJwi/b8TwWO1hyxXxZispZ03DEC7zfi8OWlGjY5eGHcb6IG6Pn7uyXrewCVezRZ9 GiLq/I8dGbfhLbBFYpU5yLjoUsv7Ap8wycUGi0Ehv3XFSYgACvuL7JuR0fXHZpu0si2k R00HRJ8MSfYfSjg85ytpj45LtzzVWIbkDo/+t0xCCAJGjlUqSa6hmMiVOVjGF/qYW1E8 eJzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xP+uJ24vDri92uzeME3QktEyDQnUmbcE3e8V9D9jklU=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=TUL/OpW4laG5YEW1uZkm1lzxpm446CPAAgIFeqWcJxzC4bOH/Ksm5Hq2hSTvle4xHR WjdUQtikJXTLXwyWo6aO24DLHod5NDngAxVP1dpU6sbXxRlBGdTpDDzwCWmNjbaWNKDv neR539n4A/PS1rHEh16XHN3HNpgrG4GzAQkmoFWI+dshpmAW7HnZ7yF0mClGmi+hvSz9 6mhQ16oUVznAVqE+PTydRznGGy6SdyBIfrl3HoSH98cFmyaDN7DRbMOn7nEbSRzgSn0v ZVW854/X6irq94Hhw8xuOWJ0CJUU7BDZLZtdzO8fQwsNtugJ2+gZakbHLnL0hFLVv3vv geTQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uoJr4Pxs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 50/54] target/xtensa: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:43 +0000 Message-Id: <20241202131347.498124-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for xtensa. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/xtensa/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 3163b758235..0d4d79b58b4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -136,6 +136,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_no_signaling_nans(!dfpu, &env->fp_status); + /* Default NaN value: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); xtensa_use_first_nan(env, !dfpu); } From patchwork Mon Dec 2 13:13:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846628 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1209240wrt; Mon, 2 Dec 2024 05:34:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVOWdk/Lxn/1NqiF/qdEgFJqyTPqG1qYrQbTQIIKrq27aSMm8njaOcW3qg3X9qhDlAyDvDtxw==@linaro.org X-Google-Smtp-Source: AGHT+IEmZZejdH5vAvrHPHGNyXAuPw/R/UP2i5BIrVXwJXfI8ojW4PnKc3jf2L/i7x6m2hBWCf/0 X-Received: by 2002:a05:6214:dcb:b0:6d8:9f61:de81 with SMTP id 6a1803df08f44-6d89f61e7cdmr109830096d6.24.1733146455829; Mon, 02 Dec 2024 05:34:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146455; cv=none; d=google.com; s=arc-20240605; b=DwqvR6sIPBTSRstUzqgt9EmQzJ+RMjB4fQgRYbBhijr4XSC05zo+CgcWas417bFS5D j6NH472a2hyOrRVHOfvRoAfXu4Y//nbC/RFkY+1DLpm5GvC6OSNVrzWfvfNK6v0CTJzQ 1knAt4bHuKyfHgcRBY7idAI/dX84JmCT1YOvBt+2hVEtLVJYK5W6gj0BNh264vPrYxMd BM/7QYlWBWZPJ8onrNKdpkrU27bDVXFfd62R4pXZQiAmHOR7m4FXF+XsIYEsWcfzhxmc /mSQmyaS07wgQRFKqZEC7Cl7RhUDK/Zn97hhnuCTMxc5M+R3YpqqGRoKKgglilJG+V+1 OEHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SF+s3/3GUKM6ErlG9DZAUNNlPEUN5YnIqVqgW7tQx0c=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=lwau4h44OMV1T5fJ+KSC1a98msHFz/knG4XwKUvVZoa6MKeeASmfNpldbxfzMq7AGm iG56+1o8jz4KHaCcjx+Jd6BxcvnvwU2fiMjweegBXRYh4odbf41DXVHYj5WgSnLuwL3M S/TJHyh30APhHy24B9jRIszo8xoeMpkmLejip06PeFJYUGZw1rheP15/+6rFhyIRcrAb CCoKJ1ohK8bvLSxZ29vnlySHR1RsBLUfnNy1gvBUxrANMk4WkhA07nyNWw5OXLOCOtky nZLzcE55tefE7PU8BJMo8Z/PAxAeSW03JjzENFc+1/JWol/jYCgUqmaAHS8W0mgYxgc3 ufjw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z+tZk3nS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 51/54] target/hexagon: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:44 +0000 Message-Id: <20241202131347.498124-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for hexagon. Remove the ifdef from parts64_default_nan(); the only remaining unconverted targets all use the default case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hexagon/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 5 ----- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 020038fc490..c9aa9408ec8 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -286,6 +286,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) set_default_nan_mode(1, &env->fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); + /* Default NaN value: sign bit set, all frac bits set */ + set_float_default_nan_pattern(0b11111111, &env->fp_status); } static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 06185237d0f..5954a6213b9 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,10 +136,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_HEXAGON) - /* Sign bit set, all frac bits set. */ - dnan_pattern = 0b11111111; -#else /* * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, * S390, SH4, TriCore, and Xtensa. Our other supported targets @@ -152,7 +148,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) /* sign bit clear, set frac msb */ dnan_pattern = 0b01000000; } -#endif } assert(dnan_pattern != 0); From patchwork Mon Dec 2 13:13:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846644 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1214180wrt; Mon, 2 Dec 2024 05:42:09 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUMqhoW8ddLMN/etYpOtB5QVB5cohV+LQORnMOk0lsp9WGgCY8abaD/diXyxY8iyk8H7AGBrQ==@linaro.org X-Google-Smtp-Source: AGHT+IG0VrNfBJ2dmIN3Q4IpsdQgMsQC5x8ioh7CeOrfzvbTatq9DEK1nDMU+6Y8eZ4YrroMwurZ X-Received: by 2002:ac8:7c43:0:b0:460:9ac7:8fcd with SMTP id d75a77b69052e-466b349a357mr329707411cf.1.1733146929154; Mon, 02 Dec 2024 05:42:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146929; cv=none; d=google.com; s=arc-20240605; b=jyGgxY3T+GxVeW1VgZrWS6cyQ5muObLLtj+2VoREK2b4JNGUPzLpzKIy9N7ZTn/8X0 V1tlnLThrz8ycehv+elLvU0GCcL9nd2IOwwjB3fLR1mJwi91nGGgVD1yb1gsTIsrOL2K K92xPAuUyzyh2Vo1HA6/1aZklTvHaJTZQyX1m5C5MxaYn5UKogF9NFQc3ZVp3zNsrPTM gbSbFxzNZZ/oObsS7tJrdMdBIyEQr6gH2M6IZXCeebcADtDmyAYx2Q/QIC1lUo2xnRD8 155kAe+p6xl1PDPc1ubfjeJ9JR9LFW5c3vK1kmlC692uL8QuqbHNdjS0RFoCkhUmJ65c PU7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nt3T9iHPBG+FHbTn0HSdShbMUsPPH/sHv7Ur12KBxlg=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=TZUwJLRojTh7Pq8Eu6gbHSzD6MfJ9Q/vlW6cTTZq+0y9lHIvaMfZGt8cVqDfqPlO5d hdZvCMkACXH3w+8JeI1XpMqrIh1/56U7fsJpXn/Py7qwkVhQp90/O2w4TmzeFTLHG6CD NoH5PdOCaU5brfdpG2ZeEsXz4/lWU1UIl9ZUjYnF8ooLYWFwaJLxx6NSHQqJ4gA7EPfJ YrXbnPcubss/V/M34JDs5PotSn7PPp0EsK8VHvaIoqE2zCRz6IPfPMODFDYrp4JUSW6V 66tWy95buMOpvX4ftgW3Wsx/lExomtsvzBM02RM0lTvvt0BeTwNlRqp5eRIg/E4dB1+k JJTw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L8IwldFa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 52/54] target/riscv: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:45 +0000 Message-Id: <20241202131347.498124-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for riscv. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b52..80b09952e78 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1022,6 +1022,8 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); + /* Default NaN value: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); env->vill = true; #ifndef CONFIG_USER_ONLY From patchwork Mon Dec 2 13:13:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846631 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1210313wrt; Mon, 2 Dec 2024 05:35:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW7oB/6dl6RzgLJZbZsAph1D6UlmcXpnMB/+iPfsstraYXtiJZfA2no6IncYUeNN8d/e8QwbQ==@linaro.org X-Google-Smtp-Source: AGHT+IFo/sU6ar03t5M3oLGf4tt2VpZ6qos02MvAvM3WXptiqgfwNFxZtWGj7Oh2cckcawsHBt4u X-Received: by 2002:a05:620a:4807:b0:7b6:7863:cbc4 with SMTP id af79cd13be357-7b67c27878dmr3223918385a.18.1733146551407; Mon, 02 Dec 2024 05:35:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146551; cv=none; d=google.com; s=arc-20240605; b=H6+34NtsvWrDtqKD0WzfnNNPJFFp7bjBidHNJcBE5jb8rbAK+INoSamio6fYKKUcbH /e/7gonB6zLyTyHJ06nxesroEoVaN43RlEx1bJEi9mABkFsAfsD8xe5mXd+P4m3y3tgz Zx6rXySwZ0oqT5AZ19YTcVoAHgoCRSV+aspT/6o9LY0HAIxTI7xGJjZrqQwJmrDpK06S hSX/WeWJ3vRkOSGAPKmLjKsMQwaxlYKj0nmEbHKxr8NzzrR9CGVsQllv3rnJK2uGNAcu r8mgEmXjYH6DVRh8J88YLiLrqFHrA5EcgyN+N/7ICo7jQv6eoi341VLYOtEr0SYSaOig D26A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Lx4u5nyS6FnIACOhuZuILUeF3tfNByeD1RldfY5AhvM=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=JTsYGATSMiWuueRY3Q7MZV46BzOCuCYrEn/hHVKNv1mczNWcalLzdMS2mS4zTZ1WD/ Rzo19qHbD9LTRvXh/NfN4qWf3oK13B9sRjLwV25gIS6L3fmUnTL2kmmJmjsOy38JLand aXZzZKQCpmYy6R+zcEMz68l+AgBzmep7pFEYyTP6zw/TrHHUML2cxb2wSO9aW+3fWhYF iLNy1gxmpM5YYPHK9xdZeWtRPICNrl7o7xzDxkgMuff6JyFxPkCEBvrALNjoGY20BBtj cG7QIUyXivgJ/fcojApML3VIQSauVRuAQZlWKRFf822AgvSP+cClTAYEkUMBmV+9KDs7 NBvQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VtK8m5iu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 53/54] target/tricore: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:46 +0000 Message-Id: <20241202131347.498124-54-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for tricore. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/tricore/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7014255f77c..e8b0ec51611 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -117,6 +117,8 @@ void fpu_set_state(CPUTriCoreState *env) set_flush_to_zero(1, &env->fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); set_default_nan_mode(1, &env->fp_status); + /* Default NaN pattern: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } uint32_t psw_read(CPUTriCoreState *env) From patchwork Mon Dec 2 13:13:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 846637 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cd0:0:b0:385:e875:8a9e with SMTP id c16csp1212946wrt; Mon, 2 Dec 2024 05:40:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW2TLujZNCh0ScaTe3tBk1qSoulrRk5/T9w9oYbiApVF4RDx8Twz6DJsncNIrOKZMEyOP0Qqg==@linaro.org X-Google-Smtp-Source: AGHT+IHUrcoRZbZJOTRaSSZ8aLm57pPPz95C+LgYZu5RZacL3SLz9POYKPH4vYEhFYIBb9U3uw/y X-Received: by 2002:a05:622a:1442:b0:466:9388:84d2 with SMTP id d75a77b69052e-466b3516849mr385834791cf.17.1733146801042; Mon, 02 Dec 2024 05:40:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733146801; cv=none; d=google.com; s=arc-20240605; b=XqrJpo/RTcZiD3Fk2aq80b07/cxg6tdT9vJP0z5ZLHRdAPaqdrTnmfiDWpcCBCYMHG NvwtDPtlkQDfKs7AQv8GkJODwS3L/jDQf7sOeJydrdwiZMQYKGjmVcx8IcbeiWS9XFI2 G9Db0teL28+k03t+89bp/5djLvVUpWtWSL5PH9li2BoaH3myZaE81KjCCBB8sBq+aKRS 4xkFKgh1CxzjySZTdVbEaB7fxxBj50Cw7uo2ouoYYG/LiWrBjiVfUElTl0BDvVMAbnP1 PNPB3opE6bKrHIcqkycsdVqF1X0mu9LXyMlwM6S/fHAaqBMm7FkIkdlJKQn735iRZpK6 rS6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3+p59mil36Jx5sXbuX/nuYCVFK4hOA1MfgGjeXhWnZ8=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=iF3tuAFp7761r+OMVgEtafLpZPy60DcMaACKvY9qXk9Bmf6+E3CWOWhytKgtAztzbv BVGNT+UXp7ccLdcmIdhVk+LJWRl/F2+VySW5OsidNhxOpRwlMEqurvMukNYpg+Z3Pbk6 emYlN6iFDqY2E1d/M8+Wxg2NUxiNxLyk4CuO+Rt0YtFwr0heueJhhx/Qf39nB6Cd13cP iCNDo4ZDQm8p/UWlMoGjraZJCPp7KonkAp8IQOYJ/6aEw8RYD2+yzOgdQN2uY3QcAB0c Cpvu+B7X8LSe/mW/8S5sXWJ4txkXfhmY+V/qWO3T/Zyn9TZsNzJ5x1c27Zlk6gJFuqVV 7kZA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=COGpc1P5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:15:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 54/54] fpu: Remove default handling for dnan_pattern Date: Mon, 2 Dec 2024 13:13:47 +0000 Message-Id: <20241202131347.498124-55-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that all our targets have bene converted to explicitly specify their pattern for the default NaN value we can remove the remaining fallback code in parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.c.inc | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 5954a6213b9..e075c47889a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -135,20 +135,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint64_t frac; uint8_t dnan_pattern = status->default_nan_pattern; - if (dnan_pattern == 0) { - /* - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, - * S390, SH4, TriCore, and Xtensa. Our other supported targets - * do not have floating-point. - */ - if (snan_bit_is_one(status)) { - /* sign bit clear, set all frac bits other than msb */ - dnan_pattern = 0b00111111; - } else { - /* sign bit clear, set frac msb */ - dnan_pattern = 0b01000000; - } - } assert(dnan_pattern != 0); sign = dnan_pattern >> 7;