From patchwork Mon Dec 9 10:36:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 848958 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 911CB219EBB; Mon, 9 Dec 2024 10:36:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.104.207.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733740606; cv=none; b=bd+T8Gg0NRJPbJJPNUhjkU8HvZYXPs4X87/9jMVqonIWwtSVkdRsBwbPArUFFlbQoKMMEYSiUosq6S2fYEtwOrfuYcdX1FU11qeKY9d0rEm3izC1uG4ytlvTBXTSn0V91CYqn333BiZCvsbVf9am9ce+AHvEhh379yRJgsvR7tY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733740606; c=relaxed/simple; bh=JI7OPn8ArbubGWsozuWATmltmnJfJ2iGfS0abpLqhxM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Fr38q4wGe9M9MT0UrO5o5KIg2Xbb3Jp6rW0mjsnPKVhj3p0jOXA3Cj9FFkJciNnQg8XdPd9NOSXbWSaJloFw6VWCKWDrQTf7MpWaaghabS8ciYwPMrlvdls7KxI60VpFz8AawysyBcbG9CjqkuWuVzP45lJMYe09ZuleCLOdKtM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com; spf=pass smtp.mailfrom=ew.tq-group.com; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b=guzyPdZu; dkim=fail (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b=KmmjtJfW reason="key not found in DNS"; arc=none smtp.client-ip=93.104.207.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b="guzyPdZu"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="KmmjtJfW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1733740603; x=1765276603; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Wdqp1mO90TjbNxCy1UZnwPCKmuE7HC7tkaeefblMHEE=; b=guzyPdZuwln3bo8ifRStUrdoHHLn1GNxDp5JOaSysbTOUj0HWBdd6NGu ywSQkdGRo45HGlB1l4PX9DVmhpyHA2ILZLPslt0GRGNvkpC6lAVF8GK/8 Vc5ecL3JxkDsUGoFw02dg0ATpXviUTPGiKlK7hyfcxgiXnL4a+pIIEGXn pSTGDKLMe0edzFkqzMdNHgcR9o3eNtxrhqjZG2btPrFtBw1FhSRTasogZ GDbtv37M0xuqI3+dauPb1m9Bbb0YHrDOvYDVYZdEf/8PD/lqsCPWV9xKv y69/f1+fqwXD+gMpLrJdFWP/Y5cfJEs5rxhcr69lo9qvljad8VXgyQVy+ w==; X-CSE-ConnectionGUID: xppyoOrPQx2m42sZBoQTAA== X-CSE-MsgGUID: vLERhh9KSfCh3Xf/QWerbQ== X-IronPort-AV: E=Sophos;i="6.12,219,1728943200"; d="scan'208";a="40483000" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 09 Dec 2024 11:36:40 +0100 X-CheckPoint: {6756C838-16-D31EDE1A-D52D6119} X-MAIL-CPID: BE2805596DDDB0EB2CE6272D89627E81_5 X-Control-Analysis: str=0001.0A682F1A.6756C838.0091, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A232F165BA9; Mon, 9 Dec 2024 11:36:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1733740595; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Wdqp1mO90TjbNxCy1UZnwPCKmuE7HC7tkaeefblMHEE=; b=KmmjtJfWdXfa/MixZYU+Ipb4Wbf6DfoY7Mwn43PqbiKGyNWiH7e5MnxuxAQ8dADn5u/oWa 6EIHgC5lfFN79S0ZwVW2TLY9YrdS5W4nb0EZ6ZfU42T6GQe64P+c3LcSDYDoiBDLP4YeAi KVKSfekmzgxMDhMSlTa435F2ezPvTfDWU7dIhIU4A+56e02+t1bWMfZmt3iP3zbYILFyQb jPU6Qd014MUz+iY6kkGhbLMQVrMrLisRgt8QasHVsIfAa4Q915OgzmVmdW7kTjeEwuXLFu hXFgskJbEUsXvQ5D0s7lqErOrEl5d15/Fa4+PkHc5kCDW0nDwiB37kB91512Og== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: linux@ew.tq-group.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH 1/4] gpio: tqmx86: add macros for interrupt configuration Date: Mon, 9 Dec 2024 11:36:08 +0100 Message-ID: X-Mailer: git-send-email 2.47.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 We now consistently use TQMX86_INT_* flags for irq_type values. The TQMX86_GPII_CONFIG macro is used to convert from TQMX86_INT_TRIG_* flags to GPII register values. Bit patterns for TQMX86_INT_* are chosen to make this conversion as simple as possible. No functional change intended. Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 43 ++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index 5e26eb3adabbf..667cb34b882f0 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -29,18 +29,21 @@ #define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */ #define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */ -#define TQMX86_GPII_NONE 0 -#define TQMX86_GPII_FALLING BIT(0) -#define TQMX86_GPII_RISING BIT(1) -/* Stored in irq_type as a trigger type, but not actually valid as a register - * value, so the name doesn't use "GPII" +/* NONE, FALLING and RISING use the same bit patterns that can be programmed to + * the GPII register (after passing them to the TQMX86_GPII_ macros to shift + * them to the right position) */ -#define TQMX86_INT_BOTH (BIT(0) | BIT(1)) -#define TQMX86_GPII_MASK (BIT(0) | BIT(1)) -#define TQMX86_GPII_BITS 2 +#define TQMX86_INT_TRIG_NONE 0 +#define TQMX86_INT_TRIG_FALLING BIT(0) +#define TQMX86_INT_TRIG_RISING BIT(1) +#define TQMX86_INT_TRIG_BOTH (BIT(0) | BIT(1)) +#define TQMX86_INT_TRIG_MASK (BIT(0) | BIT(1)) /* Stored in irq_type with GPII bits */ #define TQMX86_INT_UNMASKED BIT(2) +#define TQMX86_GPIIC_CONFIG(i, v) ((v) << (2 * (i))) +#define TQMX86_GPIIC_MASK(i) TQMX86_GPIIC_CONFIG(i, TQMX86_INT_TRIG_MASK) + struct tqmx86_gpio_data { struct gpio_chip chip; void __iomem *io_base; @@ -115,20 +118,20 @@ static int tqmx86_gpio_get_direction(struct gpio_chip *chip, static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int offset) __must_hold(&gpio->spinlock) { - u8 type = TQMX86_GPII_NONE, gpiic; + u8 type = TQMX86_INT_TRIG_NONE, gpiic; if (gpio->irq_type[offset] & TQMX86_INT_UNMASKED) { - type = gpio->irq_type[offset] & TQMX86_GPII_MASK; + type = gpio->irq_type[offset] & TQMX86_INT_TRIG_MASK; - if (type == TQMX86_INT_BOTH) + if (type == TQMX86_INT_TRIG_BOTH) type = tqmx86_gpio_get(&gpio->chip, offset + TQMX86_NGPO) - ? TQMX86_GPII_FALLING - : TQMX86_GPII_RISING; + ? TQMX86_INT_TRIG_FALLING + : TQMX86_INT_TRIG_RISING; } gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); - gpiic &= ~(TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS)); - gpiic |= type << (offset * TQMX86_GPII_BITS); + gpiic &= ~TQMX86_GPIIC_MASK(offset); + gpiic |= TQMX86_GPIIC_CONFIG(offset, type); tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); } @@ -173,20 +176,20 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) switch (edge_type) { case IRQ_TYPE_EDGE_RISING: - new_type = TQMX86_GPII_RISING; + new_type = TQMX86_INT_TRIG_RISING; break; case IRQ_TYPE_EDGE_FALLING: - new_type = TQMX86_GPII_FALLING; + new_type = TQMX86_INT_TRIG_FALLING; break; case IRQ_TYPE_EDGE_BOTH: - new_type = TQMX86_INT_BOTH; + new_type = TQMX86_INT_TRIG_BOTH; break; default: return -EINVAL; /* not supported */ } raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpio->irq_type[offset] &= ~TQMX86_GPII_MASK; + gpio->irq_type[offset] &= ~TQMX86_INT_TRIG_MASK; gpio->irq_type[offset] |= new_type; tqmx86_gpio_irq_config(gpio, offset); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); @@ -232,7 +235,7 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) * reading the input and setting the trigger, we will have a new * interrupt pending. */ - if ((gpio->irq_type[i] & TQMX86_GPII_MASK) == TQMX86_INT_BOTH) + if ((gpio->irq_type[i] & TQMX86_INT_TRIG_MASK) == TQMX86_INT_TRIG_BOTH) tqmx86_gpio_irq_config(gpio, i); } raw_spin_unlock_irqrestore(&gpio->spinlock, flags); From patchwork Mon Dec 9 10:36:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 848495 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9675A21CFF1; Mon, 9 Dec 2024 10:36:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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b=rBDb/wjXuKm7pjM+gyzZANNkeDWZlCkzbE0g5Bu5nnZ2BuI5dOyZgHLpXFMIHpgjFnT6Y3 vgCpNUgCLwKoj1bzqyrrDbCK6Ze4bZ743WIZcE5VP0JnoOmEKivy4Pc6IQvpuNZmg1ZvTz m5Bq4bDyTDY6nu7cDqFbo6HxJBZspEeYe3LPSK+nuEKudDYHudONhbTRPHwfegkaiB5XhK rjBctmPSre2YfiZ1dePU51CVfvXD5PO4aoC21wJsiUMByQi8p8jDoxR9tAljbJbEXJq2VM 3V7hdRI1xpekAaQtp3T+VSVpyA0gHbIBGG5zGt+53SY/VLHQbfgTlSn6N8lcdg== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: linux@ew.tq-group.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH 2/4] gpio: tqmx86: consistently refer to IRQs by hwirq numbers Date: Mon, 9 Dec 2024 11:36:09 +0100 Message-ID: X-Mailer: git-send-email 2.47.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 On currently supported variants of the TQMx86 GPIO controller, only GPIOs 4-7 have IRQ support; in the interrupt status and config registers, position 0 therefore corresponds to GPIO 4, position 1 to GPIO 5, etc. This was made even more confusing by sometimes using the term "offset" to refer to GPIO numbers (which are equavalent to hwirq numbers), and sometimes to bit positions in the hardware registers. With this change, the whole driver consistently uses hwirq numbers (== GPIO numbers) when referring to the IRQs, and only the two pieces of code that interact with the hardware registers (tqmx86_gpio_irq_config() and tqmx86_gpio_irq_handler()) deal with bit positions. Space for hwirq numbers 0-3 is reserved in the irq_type array, but remains unused for existing (COM Express) TQMx86 variants; support for TQMx86 variants that support IRQs on all GPIO lines will be added in the future. No functional change intended. Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 40 +++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index 667cb34b882f0..27f44d112d582 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -51,7 +51,7 @@ struct tqmx86_gpio_data { /* Lock must be held for accessing output and irq_type fields */ raw_spinlock_t spinlock; DECLARE_BITMAP(output, TQMX86_NGPIO); - u8 irq_type[TQMX86_NGPI]; + u8 irq_type[TQMX86_NGPIO]; }; static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg) @@ -115,36 +115,36 @@ static int tqmx86_gpio_get_direction(struct gpio_chip *chip, return GPIO_LINE_DIRECTION_OUT; } -static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int offset) +static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int hwirq) __must_hold(&gpio->spinlock) { u8 type = TQMX86_INT_TRIG_NONE, gpiic; + int gpiic_irq = hwirq - TQMX86_NGPO; - if (gpio->irq_type[offset] & TQMX86_INT_UNMASKED) { - type = gpio->irq_type[offset] & TQMX86_INT_TRIG_MASK; + if (gpio->irq_type[hwirq] & TQMX86_INT_UNMASKED) { + type = gpio->irq_type[hwirq] & TQMX86_INT_TRIG_MASK; if (type == TQMX86_INT_TRIG_BOTH) - type = tqmx86_gpio_get(&gpio->chip, offset + TQMX86_NGPO) + type = tqmx86_gpio_get(&gpio->chip, hwirq) ? TQMX86_INT_TRIG_FALLING : TQMX86_INT_TRIG_RISING; } gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); - gpiic &= ~TQMX86_GPIIC_MASK(offset); - gpiic |= TQMX86_GPIIC_CONFIG(offset, type); + gpiic &= ~TQMX86_GPIIC_MASK(gpiic_irq); + gpiic |= TQMX86_GPIIC_CONFIG(gpiic_irq, type); tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); } static void tqmx86_gpio_irq_mask(struct irq_data *data) { - unsigned int offset = (data->hwirq - TQMX86_NGPO); struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); unsigned long flags; raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpio->irq_type[offset] &= ~TQMX86_INT_UNMASKED; - tqmx86_gpio_irq_config(gpio, offset); + gpio->irq_type[data->hwirq] &= ~TQMX86_INT_UNMASKED; + tqmx86_gpio_irq_config(gpio, data->hwirq); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(data)); @@ -152,7 +152,6 @@ static void tqmx86_gpio_irq_mask(struct irq_data *data) static void tqmx86_gpio_irq_unmask(struct irq_data *data) { - unsigned int offset = (data->hwirq - TQMX86_NGPO); struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); unsigned long flags; @@ -160,8 +159,8 @@ static void tqmx86_gpio_irq_unmask(struct irq_data *data) gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(data)); raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpio->irq_type[offset] |= TQMX86_INT_UNMASKED; - tqmx86_gpio_irq_config(gpio, offset); + gpio->irq_type[data->hwirq] |= TQMX86_INT_UNMASKED; + tqmx86_gpio_irq_config(gpio, data->hwirq); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); } @@ -169,7 +168,6 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) { struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); - unsigned int offset = (data->hwirq - TQMX86_NGPO); unsigned int edge_type = type & IRQF_TRIGGER_MASK; unsigned long flags; u8 new_type; @@ -189,9 +187,9 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) } raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpio->irq_type[offset] &= ~TQMX86_INT_TRIG_MASK; - gpio->irq_type[offset] |= new_type; - tqmx86_gpio_irq_config(gpio, offset); + gpio->irq_type[data->hwirq] &= ~TQMX86_INT_TRIG_MASK; + gpio->irq_type[data->hwirq] |= new_type; + tqmx86_gpio_irq_config(gpio, data->hwirq); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); return 0; @@ -203,7 +201,7 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); struct irq_chip *irq_chip = irq_desc_get_chip(desc); unsigned long irq_bits, flags; - int i; + int i, hwirq; u8 irq_status; chained_irq_enter(irq_chip, desc); @@ -215,6 +213,8 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) raw_spin_lock_irqsave(&gpio->spinlock, flags); for_each_set_bit(i, &irq_bits, TQMX86_NGPI) { + hwirq = i + TQMX86_NGPO; + /* * Edge-both triggers are implemented by flipping the edge * trigger after each interrupt, as the controller only supports @@ -235,8 +235,8 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) * reading the input and setting the trigger, we will have a new * interrupt pending. */ - if ((gpio->irq_type[i] & TQMX86_INT_TRIG_MASK) == TQMX86_INT_TRIG_BOTH) - tqmx86_gpio_irq_config(gpio, i); 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No functional change intended. Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index 27f44d112d582..54e7e193bb209 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -65,6 +65,18 @@ static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val, iowrite8(val, gd->io_base + reg); } +static void tqmx86_gpio_clrsetbits(struct tqmx86_gpio_data *gpio, + u8 clr, u8 set, unsigned int reg) + __must_hold(&gpio->spinlock) +{ + u8 val = tqmx86_gpio_read(gpio, reg); + + val &= ~clr; + val |= set; + + tqmx86_gpio_write(gpio, val, reg); +} + static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); @@ -118,7 +130,7 @@ static int tqmx86_gpio_get_direction(struct gpio_chip *chip, static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int hwirq) __must_hold(&gpio->spinlock) { - u8 type = TQMX86_INT_TRIG_NONE, gpiic; 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b=RbjyXkEzn3u/KvolU+nGSZHqIWuzYPwXprZo3blF17VEWios6CGXhmCRWs9Q1RrqVfgTdv a1qrs95Hh/etrqjao0WeQkmumvsEIPvRiJFvmRqb+6YRlJPAOIeqN4s6GCfpA9fzBil7jn 5vXvvSMCQnqJ3oXxOL1p21FSuQC23cMj9m3EDVm36662jwnWLcnI1GXP+A0EeSDBhjOFKP S8+c9MPsSGME4x09Ws9yVS4rEr+HMFkINk3eEEmF94cjAWdHTfduqJtvVE1ZvsLHvHylPC iFJnI5pGfl7uW5mOpfgkbEC78IZPIJ9BmwUgK7maFE+Y+0WpAn0rzQM5trAxag== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: linux@ew.tq-group.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH 4/4] gpio: tqmx86: add support for changing GPIO directions Date: Mon, 9 Dec 2024 11:36:11 +0100 Message-ID: <0fd4b472b1ed6d67d8d1fe2f20d3bedd7eda210f.1733739697.git.matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Only GPIOs 4..7 have IRQ support on the TQMx86 variants currently handled by the driver, but apart from that, changing directions works fine. The default directions are left unchanged (0..3 output, 4..7 input) to match the COM Express specification. A tqmx86_gpio_set() variant without locking is introduced as a new helper. Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 46 ++++++++++++++++++++++++++------------ 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index 54e7e193bb209..4c7e7b5950426 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -84,6 +84,14 @@ static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset) return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & BIT(offset)); } +static void _tqmx86_gpio_set(struct tqmx86_gpio_data *gpio, unsigned int offset, + int value) + __must_hold(&gpio->spinlock) +{ + __assign_bit(offset, gpio->output, value); + tqmx86_gpio_write(gpio, bitmap_get_value8(gpio->output, 0), TQMX86_GPIOD); +} + static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { @@ -91,40 +99,50 @@ static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, unsigned long flags; raw_spin_lock_irqsave(&gpio->spinlock, flags); - __assign_bit(offset, gpio->output, value); - tqmx86_gpio_write(gpio, bitmap_get_value8(gpio->output, 0), TQMX86_GPIOD); + _tqmx86_gpio_set(gpio, offset, value); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); } static int tqmx86_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { - /* Direction cannot be changed. Validate is an input. */ - if (BIT(offset) & TQMX86_DIR_INPUT_MASK) - return 0; - else - return -EINVAL; + struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); + unsigned long flags; + + raw_spin_lock_irqsave(&gpio->spinlock, flags); + tqmx86_gpio_clrsetbits(gpio, BIT(offset), 0, TQMX86_GPIODD); + raw_spin_unlock_irqrestore(&gpio->spinlock, flags); + + return 0; } static int tqmx86_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { - /* Direction cannot be changed, validate is an output */ - if (BIT(offset) & TQMX86_DIR_INPUT_MASK) - return -EINVAL; + struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); + unsigned long flags; + + raw_spin_lock_irqsave(&gpio->spinlock, flags); + _tqmx86_gpio_set(gpio, offset, value); + tqmx86_gpio_clrsetbits(gpio, 0, BIT(offset), TQMX86_GPIODD); + raw_spin_unlock_irqrestore(&gpio->spinlock, flags); - tqmx86_gpio_set(chip, offset, value); return 0; } static int tqmx86_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { - if (TQMX86_DIR_INPUT_MASK & BIT(offset)) - return GPIO_LINE_DIRECTION_IN; + struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); + u8 val; + + val = tqmx86_gpio_read(gpio, TQMX86_GPIODD); + + if (val & BIT(offset)) + return GPIO_LINE_DIRECTION_OUT; - return GPIO_LINE_DIRECTION_OUT; + return GPIO_LINE_DIRECTION_IN; } static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int hwirq)