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Mon, 9 Dec 2024 02:13:15 -0800 From: Prathamesh Shete To: , , , , , , Subject: [PATCH] pinctrl-tegra: Add config property GPIO mode Date: Mon, 9 Dec 2024 15:43:14 +0530 Message-ID: <20241209101314.22834-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F68:EE_|SJ0PR12MB6760:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d521c24-cc34-4625-3366-08dd183a25c2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: s/gMnhaha291Mpd5r1///inNWJb9iYXGUoeveO+s1REl4Th5Jg35aSLOgJE4Av2KqkFR0Q2KmEASv3+L1kEPA/zr5MW8URNCa4613p5IHrvrJvyZmRJTfyGA0UL/xrI0JS4yQv/UUmJ1SzTNo6pSX3eL8NbBvqDb+ve+mKJg0jDpjxSEHeJWzUgP7nSPNf7UoSIDmlUcwDGVtlneSy+LLrJqRIlwaRHsVi2qxoC8h+wFTosue3aR0Nbyo9lSCiYBze3WELCnnZeeXg7M36dSsyOyLgfLObQU5WzYc+PnH/NgxY5dGdbSMlv/8hy+b/L34pAHfaTMvTShVUobfIMscLaBlDUSrdtPzQ2JOLFCYazCmMwvG8ZpN3cmxzGXFG4XVUHsYyKu9W5mRESJon2RIEZQGIBkkfqGFKKtw8ehuXdFPbd9RScLucqevMYH8UYD7P1KKl+2StZA8LHI/gqOCxIDx3FY6B3BgBgBLMA34ABFJD2Dep8TpEpICc+89agIRznZ9b/eXwppZLjjg5TCX+zWf9FzmBZ6dgD17sqI9Z5z9M9njj1GMO12Js+iw37fGnvgzJqdVBTchMKcj7zqDCbm7hhMaDzlmjArZt4q75jpjAQB99ldIrPwlukMraZ/Su0PD2fJVKQKrwHN/KAcTvfvLI5qOeG+Ebt9CWazOOlBUwp9rfRNfcIf59sU1pDMmlp2Ecdw73LeOUMXomiGCUlHa+p9FNtTfSHvONFmx8HGwZ2h5ijFSsWh0bLPohRv5rfkbxpmLeItoZystdDM1UYrnjOYKt2aREEVYf8vqOiTPv5+PwTxBSn9FfCPwOJWaUhcjAmJtTFv/6Z1FJ+nGG6FlTPR+ocnMKgFmbkXAYQcbL7VHHcgY8bnq0U6oMFi5t440zoXhtE9RA+FkWAiXHMLQDHaoCmvO/7VCUyuiH20cXpjlo+0P85CwRUWwe4LCG3RaWrFUAkMzlaUsA9N6fGcJkq0F/a9RqhVlDuQO5egSsc6eFx+paot2ez0OfMPzor4tGrqDNLLAeutzOVcFfXrTO/Gxj6Brypi+7JPauhv7PFRYngA/36F4Ej3s61G+ft9cDZNnUiHJ24LX/o+bQ1WpIg9ed7FBg9Qdim+TSkI98byz+6jFENfIpkzjUtvqnDhjQ4g6tcd/DSjruiLqnj9X5NHSNWJt2jZvarNQxEwDQyFLxxD9fwo7q3cSz9hAdFYFdt3xRWfHnvnEE/3DIMY6jbp/F7AKMZ5i47tc3wT1MDZJSlq3w7z3as7VBpIdpcOxatpuWa+ckTkD8bJ7qPDMocxZc2qGO86qEtGrK1me4FhzHcpEIQp/v6fO9y3VPWweCkrefWj/zmWH3al5aKV+Tc/D1VdEdoWNMNqXs0M2cBt1CG406fA8SMlqP4wTUCzkgv5DNTQXadlTwZdNBYZxkOLcJC5HUB+3z5Bc2+CA1ic17scC5rn+KLH6Pzz X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2024 10:13:37.5726 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d521c24-cc34-4625-3366-08dd183a25c2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F68.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6760 The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing system: - When set to 1, the pin operates in SFIO mode, controlled by the pin's assigned special function. - When set to 0, the pin operates as a general-purpose GPIO. This SFIO/GPIO select bit that is set for a given pin is not displayed, adding the support to retrieve this information from the pinmux set for each pin. Signed-off-by: Prathamesh Shete --- drivers/pinctrl/tegra/pinctrl-tegra.c | 11 +++++++++++ drivers/pinctrl/tegra/pinctrl-tegra.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 9523b93008d0..b3501c78b5b6 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -96,6 +96,7 @@ static const struct cfg_param { {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, + {"nvidia,gpio-mode", TEGRA_PINCONF_PARAM_GPIO_MODE}, }; static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, @@ -476,6 +477,16 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, *bit = g->drvtype_bit; *width = 2; break; + case TEGRA_PINCONF_PARAM_GPIO_MODE: + if (pmx->soc->sfsel_in_mux) { + *bank = g->mux_bank; + *reg = g->mux_reg; + *bit = g->sfsel_bit; + *width = 1; + } else { + *reg = -ENODEV; + } + break; default: dev_err(pmx->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index b97136685f7a..a47ac519f3ec 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -60,6 +60,8 @@ enum tegra_pinconf_param { TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, /* argument: Integer, range is HW-dependant */ TEGRA_PINCONF_PARAM_DRIVE_TYPE, + /* argument: Boolean */ + TEGRA_PINCONF_PARAM_GPIO_MODE, }; enum tegra_pinconf_pull {