From patchwork Thu Dec 12 10:32:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 849807 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 059E620B1F7 for ; Thu, 12 Dec 2024 10:32:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733999581; cv=none; b=OGk+7p9lmFU3cUcGw+F/+dT2TvTmnhozqwG6Z2d73/cjCenticpRCupQQKJ5yQhg+soTEe9Tk7MAtT1pbJT4UDxGqiiZQXdTRRgsO0P9OezjaW9CPGQAcusfgeQrlFySt34p7xmmLrM7QlEsPdlNAFXiaFNXznR0GI08jqIP7n0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733999581; c=relaxed/simple; bh=4fCd/oHWBBMGki+2Akb2EhfJBr7XyM33W9JbVVWkoo0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iHBWwefUV+KVkDBwNMGksY5eA/cQs67dKBOsQbKSA8SmSP/ocMNCUDWdPFphqtbHpTlPq7/3+hNEAU2Z65MMUp7k5PV4tkcvZLTtZKYH7AAEqKaFlcpcXV0Ijutk6kvI9ssVxkpjUsChMVEbJmUqXXYBKbHt0nzQgrwwBpQZ8Qw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=fg4kvoYB; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="fg4kvoYB" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BC2rRhT000445 for ; Thu, 12 Dec 2024 10:32:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= UFi/NAR+8ct3gpDsCqFqJF7Dhff9C0GYs0AHfEaJe9s=; b=fg4kvoYBzrFiYwqd 9gFbVCjB0cONc5NOOqkWYD6RVLuqatdFEcvpD9hZvc3DOjbzzzbZenePtHeS4siq FNLf981CDoTSmKCGkWuHE9EYn6qUAtoPVfRtRXXy3xvbBGYOJHpAdwYwydIHL9xJ jK6+3ri1r+h2RPR29hK3IJfNbXZ5jr+Xx1ATAteeqKsci0WCH93SV9fsd1UfR7wm q+kJ5jnqK3RRkBgxHf5/CuIzdtGoL5gnHpXtVz+Bvso6eJ108WCL+EsMBUGWwHr9 0JyfiUSgLNuxSxLg7zIzhfFE8C/ne4NUT2OiwpYtduAtvZFB7ZFWFuA9arlvPtc4 DarZXQ== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43fqes11vn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 12 Dec 2024 10:32:58 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-211c1c131c4so14910605ad.1 for ; Thu, 12 Dec 2024 02:32:58 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733999577; x=1734604377; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UFi/NAR+8ct3gpDsCqFqJF7Dhff9C0GYs0AHfEaJe9s=; b=J9y3QVjl+2EWCJxWfQSdaOjjtdUqvOy/H8FBmyPlU0XqlBz5ZSILrLTeUJ37kEoM1h Y2zOUVo/2Zna57VfgzvSRr8GXrzwlaV3ppoKG4kQWE4bNsbya2L89HiaJ0Db2/+zz2UF O4aiWmf06DqJtF5BbBghnAgbRLZbttKYsRreAD6CyBm14TqClURSHOdn23oTVbO43fVi jjBdhGylcm3W7EARKPcNpCwDSue/NovwWtgqb/OD1Mo/AfXqYHgMO7whJyTlR7Bf+hsb yiFWMkS2IwFm/xFr3gCH9+r8VrZjhp47pijfGYsEmD/02WEgNFVBcl9CWviB0IDYtNHR m1eQ== X-Gm-Message-State: AOJu0YxkHe6OSzRRQcEzDx2kVBPI0OXOS1Cc3bl5LEoG53nKJUT6pSiO H1Sln6k+kHUHVUHuDrYnQdz7r2Ge45TIknf5P6/WOSWGzyEdL1V0oeOBWzFnOqJ6lxz7ZVE0BNw EiQJ1R1ulN32w3UgnWvTNom0LyHgoyfDneVRO4mahKfoCGXyrpAvrQT2B1kN9rwRG X-Gm-Gg: ASbGnctXjngN9BOPaRO4oXCEAzL8Yf0jQ1B+NsLVJtWBt6oszz5lsEy3IwEtG5+PdFu dpq8aQv4EkJhcvwaZalJ7VDmXS0tOdgwTgUYN1c/IEPiZoYm3J8QhLRAOUfccogDBSWEjsAFqm7 hNG1zyZHHqTpeL45K95UdiNMHXwfzfdq4CX5wyGcUvWgvm4Yi+C8dB8hB5oHno5lyjvLB6c5kQX DhDVJu7dsRQvfjsMS2nZmPCYmZSvhLWX51gebg9gOGUUsbXlTpdKdY9wNBqNU6H68RorfHGxR0I WFCPVxoDiIYO3Ga2 X-Received: by 2002:a17:903:1250:b0:215:ba2b:cd55 with SMTP id d9443c01a7336-2178c81b9cdmr40064275ad.2.1733999576627; Thu, 12 Dec 2024 02:32:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IF4mWFutgU/rw+IbbYhTINt+7e7TrZ+SzlYpSE72R3VJGux3DghiIZM29EuOXmiXCYsxTsX2g== X-Received: by 2002:a17:903:1250:b0:215:ba2b:cd55 with SMTP id d9443c01a7336-2178c81b9cdmr40063785ad.2.1733999576024; Thu, 12 Dec 2024 02:32:56 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2178db5b42asm11102335ad.244.2024.12.12.02.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Dec 2024 02:32:55 -0800 (PST) From: Krishna Chaitanya Chundru Date: Thu, 12 Dec 2024 16:02:15 +0530 Subject: [PATCH v2 1/4] arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241212-preset_v2-v2-1-210430fbcd8a@oss.qualcomm.com> References: <20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com> In-Reply-To: <20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio , Krishna Chaitanya Chundru , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733999565; l=1238; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=irG7UL2NaAvTYd39uNjfeRdm3pgEDinubSnLkruP6A8=; b=CazABzxzN/P1pKOWbv7yNJVkC1w8AmIQAil/8JT+kWBq+7dUUmaVzm9WhSYaeYAFC0K/s+yIv 47ULRs3PEu7Bin9vMMCplzISGOtpdHtVUV/TG00Ps59Ul/da98wA7QP X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: LuBacANnHSYlqRn38bB3_LZIAdC4Sheb X-Proofpoint-ORIG-GUID: LuBacANnHSYlqRn38bB3_LZIAdC4Sheb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1011 malwarescore=0 mlxlogscore=813 priorityscore=1501 bulkscore=0 phishscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120074 From: Krishna chaitanya chundru Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data rates used in lane equalization procedure. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index a36076e3c56b..6a2074297030 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2993,6 +2993,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie6a_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + status = "disabled"; }; @@ -3115,6 +3119,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie5_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; }; @@ -3235,6 +3241,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie4_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; pcie4_port0: pcie@0 { From patchwork Thu Dec 12 10:32:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 849806 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B301C211475 for ; Thu, 12 Dec 2024 10:33:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733999591; cv=none; b=j1Mzj4EObwVPavLbXyWBshPJ9EXoFxdnK0qy/VG0xrQcayKdOpb81QqaGMTbZ1vRIrD2Cw2LYKZpGgBpc6i33mfZOzlzWtCjDbhCDLZ86rKZWQtlIYpTV73CrBFWXvxNGCu8I5/9vGO9pUfLU3y0w/RWE5TpKbMv95vEyiyZnDg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733999591; c=relaxed/simple; bh=rCnbx3o95poXDb2/YuVF9r73FJXlFhkxVyGpIDaXoNQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MuVCLtskH1DmJHT/ruullZZGCB3Szu36oWc7DI4XZP4Y0SVR9vS4qDlZJKwuJ9GgrqfHnYoust4RTA2ItfurYFD9uKdnTZP5MVi3OhA2lx1OfC7OPLuTmrFtCM0nkUtcYH8Xy/KepSeCogHcRVdFS4cXiRAukjKi1zYgp1ow1YQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=m4sUkCaG; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="m4sUkCaG" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BC2rRSk000446 for ; Thu, 12 Dec 2024 10:33:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zTx4AaOAcUgRsKy4qkO3gaODbvQmZWa1pu23pK5Xnvo=; b=m4sUkCaGmvQz+Hlj eVBUDssJcBOF2NADCZKwxEOrXi8Tvvks3Vp0gjZCV0IZnl/8+LjxCzhOsDmIJAfq tZKr54o1mAgtocrNI8xN6PcwayqOH+IRqx/OvSUsdKQrjiZkOuvkBV2e81p3m0df 8SUXlK6eXLfJq1BrupZXmAVYZh3IqJavejAlaiYY21SbTJ8c33dhiFr8FZuEJcFu GluFe5u/q+1yrJOiHC/vLo7toj1LCCsNoGFLdtnKv6ASFpZ3HG6ONLF080r1wUsH k7mqxtH2IBXUrJgPVe0UZCErzHZh+ZplLz0YD0ZCWtvP4BqRPekTJiS2OprSRG62 bMsOoA== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43fqes11wn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 12 Dec 2024 10:33:08 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-216266cc0acso15575215ad.0 for ; Thu, 12 Dec 2024 02:33:08 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733999587; x=1734604387; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zTx4AaOAcUgRsKy4qkO3gaODbvQmZWa1pu23pK5Xnvo=; b=TSrfOeoBw5hOwuFdCNm3Lo7E4f6mBuwPVNerArHRCKKkzw6Rbji4pIWx6WQ2tnp22E FymIrvfdb2S51f0rGrA43tTBvQIRznIr3O+e4xhNMZGC1RxdW476xS4kB2kjo8PHGIHH HcUvLmQtrB/nH3lnds1iVXJtXW/rMf0TPwf/2vPT2/c6VyidgUVan/MZcbxnH0FqYJ4A hQ1tVxOQr8VBFZGRYvsgkRgYyMBsAxc/u07DO3urvfPQ57/pvf3BFz5RLqGfZF2IH+mE h5GElyZOBHmzzzVm2IyS4/EJrWlairHgAMTJdyOLm92loHiTSZL2jdt0QWIqtMW0kEsh QbVg== X-Gm-Message-State: AOJu0YxCmicwJ9pHLJpcsb0ejxtfQaq6Bv+Gejurb+xVw9TXcGH5I/bm Zj26frp3ec1A6xKz6d4tYuTvL6YAwd8cEz4wgl9LrxD1vfagnVmGZjJ5Cl6nZCBhbEQILPVx1Dq uWlr7QXq2MmkSOhuUftQ/4lHy2rdOAs7mlQIdZZKwaxoOTgM/C/iR+RH383AO5ix2 X-Gm-Gg: ASbGnctenSxZ4KfqAiDQkXpcWHaqD69GY7KEGZwPX6UzT2LSrvd/Tv8P0efi1CqlkiW goAWUXv2vkvfdEWXSpXuoaNrOwKKW1WBaHcIBaswVIz0ki3EfzqBqRVpb4Pm7Pvl/NXQyP6xNOT yRSPmU8dB9oRW/nIA7VC0PUs4pdlQ/PKpbcQ+vNvmxwTBOJsvec3Mzuk+IE6T4ceUjYqQwpe48e UvxVqh+xapvd591L0Kkbz625P8b60r8ax+DnfkAoHmQllrEnO1HPcrpGf6wLqe3LmZrHmC/RpnO L02yT9Jn0GMKgf4+ X-Received: by 2002:a17:902:c403:b0:215:758c:52ea with SMTP id d9443c01a7336-2178c834419mr40594575ad.9.1733999587345; Thu, 12 Dec 2024 02:33:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IGSZS7M1+e2mSpSTWbXLTkDIPYkw2W31sDaXU8xPhcAptvNEzmguFjLvOVr4BVhHwV0LKzhzg== X-Received: by 2002:a17:902:c403:b0:215:758c:52ea with SMTP id d9443c01a7336-2178c834419mr40594305ad.9.1733999586971; Thu, 12 Dec 2024 02:33:06 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2178db5b42asm11102335ad.244.2024.12.12.02.33.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Dec 2024 02:33:06 -0800 (PST) From: Krishna Chaitanya Chundru Date: Thu, 12 Dec 2024 16:02:17 +0530 Subject: [PATCH v2 3/4] PCI: dwc: Improve handling of PCIe lane configuration Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241212-preset_v2-v2-3-210430fbcd8a@oss.qualcomm.com> References: <20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com> In-Reply-To: <20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio , Krishna Chaitanya Chundru , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733999565; l=3448; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=5rxRkPnumzzfAdemdZBFDf4pCGC4z3dLReWUJOLysOk=; b=PfWVknQFvds1Vncgw8MASrZsGeAdq18UFhYaeSeVV0UZEfJnZ3Lq/buK38XEW+1jRTxbIcrum O73OaU8IybTBbBquqghOBSF5AbS0n20cNl5BcvOK+u7/yZW9aFD2UMF X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: j1LiaWRYmbZ34bjD7lPbtH650QOYTTMh X-Proofpoint-ORIG-GUID: j1LiaWRYmbZ34bjD7lPbtH650QOYTTMh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1011 malwarescore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 phishscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120074 From: Krishna chaitanya chundru Currently even if the number of lanes hardware supports is equal to the number lanes provided in the devicetree, the driver is trying to configure again the maximum number of lanes which is not needed. Update number of lanes only when it is not equal to hardware capability. And also if the num-lanes property is not present in the devicetree update the num_lanes with the maximum hardware supports. Introduce dw_pcie_link_get_max_link_width() to get the maximum lane width the hardware supports. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 3e41865c7290..2cd0acbf9e18 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -504,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_iatu_detect(pci); + if (pci->num_lanes < 1) + pci->num_lanes = dw_pcie_link_get_max_link_width(pci); + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d6cbc8b5b2c..acb2a963ae1a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -736,6 +736,16 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) } +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) +{ + u32 lnkcap; + u8 cap; + + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); +} + static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) { u32 lnkcap, lwsc, plc; @@ -1069,6 +1079,7 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) void dw_pcie_setup(struct dw_pcie *pci) { + int num_lanes = dw_pcie_link_get_max_link_width(pci); u32 val; dw_pcie_link_set_max_speed(pci); @@ -1102,5 +1113,6 @@ void dw_pcie_setup(struct dw_pcie *pci) val |= PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - dw_pcie_link_set_max_link_width(pci, pci->num_lanes); + if (num_lanes != pci->num_lanes) + dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35a..500e793c9361 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -486,6 +486,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci); int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, const struct dw_pcie_ob_atu_cfg *atu); int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,