From patchwork Thu Dec 12 14:08:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 851116 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90DF42153F1; Thu, 12 Dec 2024 14:08:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.104.207.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012532; cv=none; b=j653c9FDXqgPZeHiThW3vOciJcWSp8QI/PzM3uEHYWw3y0ODDHpg8JakGNu3qHj/3yW3qBN4iQftDAkMOKW0TJPY+Vqen74okCwXMImyP9PiExoDA8fhr5ZcowlAWGlEWGPYgeMKk1IunY/YN+RiDkAxZnmlhq13fT/nXF0sgyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012532; c=relaxed/simple; bh=FRwARpDPfq25XHcmUGzLwyiViyq3Mv2R1wUlUtCJjKc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dclDya2aIVjY/V1uRl/2ntxs5iGT3R2kh4wiOWfIWJYwFMW767j8ChmAHKHVwfALiCmMmP162YO8ve+g9WS0Ylwa0ZHEMBB8m9qqnlGs4BMf483YeQJntJQzbd9Q7PqBX7p0yvzZn0E4h5KtWr4u5ZO7rAG6CP+LG5a9SfgKcDM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com; spf=pass smtp.mailfrom=ew.tq-group.com; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b=eC/91xHx; dkim=fail (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b=oHPkTm52 reason="key not found in DNS"; arc=none smtp.client-ip=93.104.207.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b="eC/91xHx"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="oHPkTm52" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1734012529; x=1765548529; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EtUKXCd5mO5REGXTGnzkXbObfBe3wwqQTa4OtrOVC34=; b=eC/91xHxtUrP5OseSeIG0QZmXyKVHXwuKJ43e887vk2aJnrQkUUhtcUD tGJWsTm8YsgDKdNSGJPDAdRvpkKOwdZxGCZnZMnovpjTWpfddQ6zrHW4R tjtViwwWm1GHvKqoaTLb2opQnQnQ3OMTaHYVtG6Qq7RRrkEZqS3Y61hSF KfGbSZv0DUOEHlZ1f+tE7LHxux4BaQlmKBEJLMMOS9XeXtRfRQkJNGmvY B7B7DXUc1zWin2VWCAAdpbDWM8UmstGcAvlH4nXgoCp5B5XnHygAg5uVl s6ljxTkzcg78q/ovwO0o3+IsXWErZTbWX0ciL+xfILZ1VESn7R33uBJF/ A==; X-CSE-ConnectionGUID: W/YMomxqTVSksrdlk0kJwQ== X-CSE-MsgGUID: l84GWP9nSpmfWYzLnN6Ifg== X-IronPort-AV: E=Sophos;i="6.12,228,1728943200"; d="scan'208";a="40566520" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 12 Dec 2024 15:08:42 +0100 X-CheckPoint: {675AEE69-3B-98002871-E6E29D66} X-MAIL-CPID: E54E7DEFC4F28C67FF61896AFDAD8815_3 X-Control-Analysis: str=0001.0A682F20.675AEE6A.0020, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 66C1E1681B2; Thu, 12 Dec 2024 15:08:37 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1734012517; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EtUKXCd5mO5REGXTGnzkXbObfBe3wwqQTa4OtrOVC34=; b=oHPkTm52DdAHMZs0e5JNDxms4PHF4b5fHfnZmalXSHnKZVP5erYnrei9yjBHONBZsh4aer OZadcClPlJE7sfyoXIZSQGs4BgDO12QP+8yyeYLcoczSkdX03mCjA9UqOTq/SdL0clbPMP o3MA/g3ZOC1/c35LpThF344Z9qUuS+7S9vHGmu2FIGQUlfAIHF+g5uWs4tjVcnFRln49Px EIk2JsiY3xg75IcEvrJd/34HZ0IpfbBOrm5rEPMOo7U8k0aNspk07LNees/lRy5bj0NDTA tY1hRkyainXtVkzfxcbhViY69xl7Y38M4Me0UHru85YnHRDPZO7sYgZXMHVEsQ== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: linux@ew.tq-group.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH v2 1/5] gpio: tqmx86: add macros for interrupt configuration Date: Thu, 12 Dec 2024 15:08:05 +0100 Message-ID: <26c01bce589aedb794c19ea7ccd85f6143532e48.1734001247.git.matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Consistently use TQMX86_INT_* flags for irq_type values. The TQMX86_GPII_CONFIG macro is used to convert from TQMX86_INT_TRIG_* flags to GPII register values. Bit patterns for TQMX86_INT_* are chosen to make this conversion as simple as possible. No functional change intended. Signed-off-by: Matthias Schiffer --- v2: - improved wording of commit description - fixed comment format drivers/gpio/gpio-tqmx86.c | 44 +++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index 5e26eb3adabbf..dda57fc02214b 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -29,18 +29,22 @@ #define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */ #define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */ -#define TQMX86_GPII_NONE 0 -#define TQMX86_GPII_FALLING BIT(0) -#define TQMX86_GPII_RISING BIT(1) -/* Stored in irq_type as a trigger type, but not actually valid as a register - * value, so the name doesn't use "GPII" +/* + * NONE, FALLING and RISING use the same bit patterns that can be programmed to + * the GPII register (after passing them to the TQMX86_GPII_ macros to shift + * them to the right position) */ -#define TQMX86_INT_BOTH (BIT(0) | BIT(1)) -#define TQMX86_GPII_MASK (BIT(0) | BIT(1)) -#define TQMX86_GPII_BITS 2 +#define TQMX86_INT_TRIG_NONE 0 +#define TQMX86_INT_TRIG_FALLING BIT(0) +#define TQMX86_INT_TRIG_RISING BIT(1) +#define TQMX86_INT_TRIG_BOTH (BIT(0) | BIT(1)) +#define TQMX86_INT_TRIG_MASK (BIT(0) | BIT(1)) /* Stored in irq_type with GPII bits */ #define TQMX86_INT_UNMASKED BIT(2) +#define TQMX86_GPIIC_CONFIG(i, v) ((v) << (2 * (i))) +#define TQMX86_GPIIC_MASK(i) TQMX86_GPIIC_CONFIG(i, TQMX86_INT_TRIG_MASK) + struct tqmx86_gpio_data { struct gpio_chip chip; void __iomem *io_base; @@ -115,20 +119,20 @@ static int tqmx86_gpio_get_direction(struct gpio_chip *chip, static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int offset) __must_hold(&gpio->spinlock) { - u8 type = TQMX86_GPII_NONE, gpiic; + u8 type = TQMX86_INT_TRIG_NONE, gpiic; if (gpio->irq_type[offset] & TQMX86_INT_UNMASKED) { - type = gpio->irq_type[offset] & TQMX86_GPII_MASK; + type = gpio->irq_type[offset] & TQMX86_INT_TRIG_MASK; - if (type == TQMX86_INT_BOTH) + if (type == TQMX86_INT_TRIG_BOTH) type = tqmx86_gpio_get(&gpio->chip, offset + TQMX86_NGPO) - ? TQMX86_GPII_FALLING - : TQMX86_GPII_RISING; + ? TQMX86_INT_TRIG_FALLING + : TQMX86_INT_TRIG_RISING; } gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); - gpiic &= ~(TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS)); - gpiic |= type << (offset * TQMX86_GPII_BITS); + gpiic &= ~TQMX86_GPIIC_MASK(offset); + gpiic |= TQMX86_GPIIC_CONFIG(offset, type); tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); } @@ -173,20 +177,20 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) switch (edge_type) { case IRQ_TYPE_EDGE_RISING: - new_type = TQMX86_GPII_RISING; + new_type = TQMX86_INT_TRIG_RISING; break; case IRQ_TYPE_EDGE_FALLING: - new_type = TQMX86_GPII_FALLING; + new_type = TQMX86_INT_TRIG_FALLING; break; case IRQ_TYPE_EDGE_BOTH: - new_type = TQMX86_INT_BOTH; + new_type = TQMX86_INT_TRIG_BOTH; break; default: return -EINVAL; /* not supported */ } raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpio->irq_type[offset] &= ~TQMX86_GPII_MASK; + gpio->irq_type[offset] &= ~TQMX86_INT_TRIG_MASK; gpio->irq_type[offset] |= new_type; tqmx86_gpio_irq_config(gpio, offset); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); @@ -232,7 +236,7 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) * reading the input and setting the trigger, we will have a new * interrupt pending. */ - if ((gpio->irq_type[i] & TQMX86_GPII_MASK) == TQMX86_INT_BOTH) + if ((gpio->irq_type[i] & TQMX86_INT_TRIG_MASK) == TQMX86_INT_TRIG_BOTH) tqmx86_gpio_irq_config(gpio, i); } raw_spin_unlock_irqrestore(&gpio->spinlock, flags); From patchwork Thu Dec 12 14:08:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 849860 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F13A2153FF; Thu, 12 Dec 2024 14:08:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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b=NOOhlPvjD1iRFndGHIZCMM8IUgai+2ju8ARVX6oe63Iqn6VyHx/hHw46o3OqMnP+rD/gWG cIDbm+zi8gxUXEHJNYEHgOplk24KPA5DRY8n+Rb7ndNz12UzatyTg3xyM9q5ZrUHOPKbTW qxi/9+2g/vITTt1EQ2p9qlMWQUd/gr9NKWYtCBQ6+mSMZRlkp0NhZ+K0FSwvo/fNZdo58r 4+kw4mf+7eBAdEXwdfwNbiPDoWlNC9kqU2y5N3dz7iPeg/8Ggn2bjxZLEkuDsAD+kLindO EdJjk/ZFJ8c3OxWWGW/qoy4jHdLlSQWfjD7c7x+nXidw74ZhfrpsJ0XLAASKsw== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: linux@ew.tq-group.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH v2 2/5] gpio: tqmx86: consistently refer to IRQs by hwirq numbers Date: Thu, 12 Dec 2024 15:08:06 +0100 Message-ID: <94b78f4a9500bb71e66c0f7d3b084fec5cfe42ca.1734001247.git.matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 On currently supported variants of the TQMx86 GPIO controller, only GPIOs 4-7 have IRQ support; in the interrupt status and config registers, position 0 therefore corresponds to GPIO 4, position 1 to GPIO 5, etc. This was made even more confusing by sometimes using the term "offset" to refer to GPIO numbers (which are equavalent to hwirq numbers), and sometimes to bit positions in the hardware registers. With this change, the whole driver consistently uses hwirq numbers (== GPIO numbers) when referring to the IRQs, and only the two pieces of code that interact with the hardware registers (tqmx86_gpio_irq_config() and tqmx86_gpio_irq_handler()) deal with bit positions. Space for hwirq numbers 0-3 is reserved in the irq_type array, but remains unused for existing (COM Express) TQMx86 variants; support for TQMx86 variants that support IRQs on all GPIO lines will be added in the future. No functional change intended. Signed-off-by: Matthias Schiffer --- v2: no changes drivers/gpio/gpio-tqmx86.c | 40 +++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index dda57fc02214b..38208a7dc1e62 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -52,7 +52,7 @@ struct tqmx86_gpio_data { /* Lock must be held for accessing output and irq_type fields */ raw_spinlock_t spinlock; DECLARE_BITMAP(output, TQMX86_NGPIO); - u8 irq_type[TQMX86_NGPI]; + u8 irq_type[TQMX86_NGPIO]; }; static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg) @@ -116,36 +116,36 @@ static int tqmx86_gpio_get_direction(struct gpio_chip *chip, return GPIO_LINE_DIRECTION_OUT; } -static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int offset) +static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int hwirq) __must_hold(&gpio->spinlock) { u8 type = TQMX86_INT_TRIG_NONE, gpiic; + int gpiic_irq = hwirq - TQMX86_NGPO; - if (gpio->irq_type[offset] & TQMX86_INT_UNMASKED) { - type = gpio->irq_type[offset] & TQMX86_INT_TRIG_MASK; + if (gpio->irq_type[hwirq] & TQMX86_INT_UNMASKED) { + type = gpio->irq_type[hwirq] & TQMX86_INT_TRIG_MASK; if (type == TQMX86_INT_TRIG_BOTH) - type = tqmx86_gpio_get(&gpio->chip, offset + TQMX86_NGPO) + type = tqmx86_gpio_get(&gpio->chip, hwirq) ? TQMX86_INT_TRIG_FALLING : TQMX86_INT_TRIG_RISING; } gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); - gpiic &= ~TQMX86_GPIIC_MASK(offset); - gpiic |= TQMX86_GPIIC_CONFIG(offset, type); + gpiic &= ~TQMX86_GPIIC_MASK(gpiic_irq); + gpiic |= TQMX86_GPIIC_CONFIG(gpiic_irq, type); tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); } static void tqmx86_gpio_irq_mask(struct irq_data *data) { - unsigned int offset = (data->hwirq - TQMX86_NGPO); struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); unsigned long flags; raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpio->irq_type[offset] &= ~TQMX86_INT_UNMASKED; - tqmx86_gpio_irq_config(gpio, offset); + gpio->irq_type[data->hwirq] &= ~TQMX86_INT_UNMASKED; + tqmx86_gpio_irq_config(gpio, data->hwirq); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(data)); @@ -153,7 +153,6 @@ static void tqmx86_gpio_irq_mask(struct irq_data *data) static void tqmx86_gpio_irq_unmask(struct irq_data *data) { - unsigned int offset = (data->hwirq - TQMX86_NGPO); struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); unsigned long flags; @@ -161,8 +160,8 @@ static void tqmx86_gpio_irq_unmask(struct irq_data *data) gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(data)); raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpio->irq_type[offset] |= TQMX86_INT_UNMASKED; - tqmx86_gpio_irq_config(gpio, offset); + gpio->irq_type[data->hwirq] |= TQMX86_INT_UNMASKED; + tqmx86_gpio_irq_config(gpio, data->hwirq); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); } @@ -170,7 +169,6 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) { struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); - unsigned int offset = (data->hwirq - TQMX86_NGPO); unsigned int edge_type = type & IRQF_TRIGGER_MASK; unsigned long flags; u8 new_type; @@ -190,9 +188,9 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) } raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpio->irq_type[offset] &= ~TQMX86_INT_TRIG_MASK; - gpio->irq_type[offset] |= new_type; - tqmx86_gpio_irq_config(gpio, offset); + gpio->irq_type[data->hwirq] &= ~TQMX86_INT_TRIG_MASK; + gpio->irq_type[data->hwirq] |= new_type; + tqmx86_gpio_irq_config(gpio, data->hwirq); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); return 0; @@ -204,7 +202,7 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); struct irq_chip *irq_chip = irq_desc_get_chip(desc); unsigned long irq_bits, flags; - int i; + int i, hwirq; u8 irq_status; chained_irq_enter(irq_chip, desc); @@ -216,6 +214,8 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) raw_spin_lock_irqsave(&gpio->spinlock, flags); for_each_set_bit(i, &irq_bits, TQMX86_NGPI) { + hwirq = i + TQMX86_NGPO; + /* * Edge-both triggers are implemented by flipping the edge * trigger after each interrupt, as the controller only supports @@ -236,8 +236,8 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) * reading the input and setting the trigger, we will have a new * interrupt pending. */ - if ((gpio->irq_type[i] & TQMX86_INT_TRIG_MASK) == TQMX86_INT_TRIG_BOTH) - tqmx86_gpio_irq_config(gpio, i); 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12 Dec 2024 15:08:51 +0100 X-CheckPoint: {675AEE73-C-4B00A2D7-FB71B4CE} X-MAIL-CPID: 1C610659653579568AE90FEC259FAF27_0 X-Control-Analysis: str=0001.0A682F24.675AEE73.0067, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A73AF16B95F; Thu, 12 Dec 2024 15:08:46 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1734012526; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=meyObhqkPdWcsr2UzETU8DO1Fi7GmAJr3YpipHAnlhA=; b=L3gfY8e4EqtQX+jgAaLXIIF4157vzuau2KVoh5IXnSUEeLgkqRc/D4Kv2LVJEsuGnfAmEV jrxObrdnXuglHlEAZ2m31Q009cJuhn79/sAy4agXaOMBYM7IOoyWds0b+HywxO/gVSS0hX xrZwidqKoUMEVPmMP3IfjWDGCnCuEVHwqDwOmVgEffDY6IKEWEDs963x1hJK4unMtyDV34 AHPTUIBToY9AxxFZbP8Q2cWonhY4oW8/C7xTTn/LBv5PyM2h0ZrprRNpd7G9zHc4FTXnfW qMlBJjXnSso3K8xD5nHX0DJMYE+jm6iWV9A9WVuaG7s+CIT7UoMbd0zJhNZArg== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: linux@ew.tq-group.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH v2 3/5] gpio: tqmx86: use cleanup guards for spinlock Date: Thu, 12 Dec 2024 15:08:07 +0100 Message-ID: X-Mailer: git-send-email 2.47.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 As we're touching this code anyways, go all the way and fully replace lock/unlock with guard and scoped_guard. No functional change intended. Signed-off-by: Matthias Schiffer --- v2: new patch drivers/gpio/gpio-tqmx86.c | 84 +++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index 38208a7dc1e62..e55ce4503e70b 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -77,12 +77,11 @@ static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); - unsigned long flags; - raw_spin_lock_irqsave(&gpio->spinlock, flags); + guard(raw_spinlock_irqsave)(&gpio->spinlock); + __assign_bit(offset, gpio->output, value); tqmx86_gpio_write(gpio, bitmap_get_value8(gpio->output, 0), TQMX86_GPIOD); - raw_spin_unlock_irqrestore(&gpio->spinlock, flags); } static int tqmx86_gpio_direction_input(struct gpio_chip *chip, @@ -141,12 +140,11 @@ static void tqmx86_gpio_irq_mask(struct irq_data *data) { struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); - unsigned long flags; - raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpio->irq_type[data->hwirq] &= ~TQMX86_INT_UNMASKED; - tqmx86_gpio_irq_config(gpio, data->hwirq); - raw_spin_unlock_irqrestore(&gpio->spinlock, flags); + scoped_guard(raw_spinlock_irqsave, &gpio->spinlock) { + gpio->irq_type[data->hwirq] &= ~TQMX86_INT_UNMASKED; + tqmx86_gpio_irq_config(gpio, data->hwirq); + } gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(data)); } @@ -155,14 +153,13 @@ static void tqmx86_gpio_irq_unmask(struct irq_data *data) { struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); - unsigned long flags; gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(data)); - raw_spin_lock_irqsave(&gpio->spinlock, flags); + guard(raw_spinlock_irqsave)(&gpio->spinlock); + gpio->irq_type[data->hwirq] |= TQMX86_INT_UNMASKED; tqmx86_gpio_irq_config(gpio, data->hwirq); - raw_spin_unlock_irqrestore(&gpio->spinlock, flags); } static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) @@ -170,7 +167,6 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); unsigned int edge_type = type & IRQF_TRIGGER_MASK; - unsigned long flags; u8 new_type; switch (edge_type) { @@ -187,11 +183,11 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) return -EINVAL; /* not supported */ } - raw_spin_lock_irqsave(&gpio->spinlock, flags); + guard(raw_spinlock_irqsave)(&gpio->spinlock); + gpio->irq_type[data->hwirq] &= ~TQMX86_INT_TRIG_MASK; gpio->irq_type[data->hwirq] |= new_type; tqmx86_gpio_irq_config(gpio, data->hwirq); - raw_spin_unlock_irqrestore(&gpio->spinlock, flags); return 0; } @@ -201,7 +197,7 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); struct irq_chip *irq_chip = irq_desc_get_chip(desc); - unsigned long irq_bits, flags; + unsigned long irq_bits; int i, hwirq; u8 irq_status; @@ -212,34 +208,38 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) irq_bits = irq_status; - raw_spin_lock_irqsave(&gpio->spinlock, flags); - for_each_set_bit(i, &irq_bits, TQMX86_NGPI) { - hwirq = i + TQMX86_NGPO; - - /* - * Edge-both triggers are implemented by flipping the edge - * trigger after each interrupt, as the controller only supports - * either rising or falling edge triggers, but not both. - * - * Internally, the TQMx86 GPIO controller has separate status - * registers for rising and falling edge interrupts. GPIIC - * configures which bits from which register are visible in the - * interrupt status register GPIIS and defines what triggers the - * parent IRQ line. Writing to GPIIS always clears both rising - * and falling interrupt flags internally, regardless of the - * currently configured trigger. - * - * In consequence, we can cleanly implement the edge-both - * trigger in software by first clearing the interrupt and then - * setting the new trigger based on the current GPIO input in - * tqmx86_gpio_irq_config() - even if an edge arrives between - * reading the input and setting the trigger, we will have a new - * interrupt pending. - */ - if ((gpio->irq_type[hwirq] & TQMX86_INT_TRIG_MASK) == TQMX86_INT_TRIG_BOTH) - tqmx86_gpio_irq_config(gpio, hwirq); + scoped_guard(raw_spinlock_irqsave, &gpio->spinlock) { + for_each_set_bit(i, &irq_bits, TQMX86_NGPI) { + hwirq = i + TQMX86_NGPO; + + /* + * Edge-both triggers are implemented by flipping the + * edge trigger after each interrupt, as the controller + * only supports either rising or falling edge triggers, + * but not both. + * + * Internally, the TQMx86 GPIO controller has separate + * status registers for rising and falling edge + * interrupts. GPIIC configures which bits from which + * register are visible in the interrupt status register + * GPIIS and defines what triggers the parent IRQ line. + * Writing to GPIIS always clears both rising and + * falling interrupt flags internally, regardless of the + * currently configured trigger. + * + * In consequence, we can cleanly implement the + * edge-both trigger in software by first clearing the + * interrupt and then setting the new trigger based on + * the current GPIO input in tqmx86_gpio_irq_config() - + * even if an edge arrives between reading the input and + * setting the trigger, we will have a new interrupt + * pending. + */ + if ((gpio->irq_type[hwirq] & TQMX86_INT_TRIG_MASK) == + TQMX86_INT_TRIG_BOTH) + tqmx86_gpio_irq_config(gpio, hwirq); + } } - raw_spin_unlock_irqrestore(&gpio->spinlock, flags); for_each_set_bit(i, &irq_bits, TQMX86_NGPI) generic_handle_domain_irq(gpio->chip.irq.domain, From patchwork Thu Dec 12 14:08:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 849859 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44FDB217F30; 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b=S7Fust9PUrTSmUqwC4knQmkwMvfSf6DVU97hwh27elm4sIUYHDtTDc8a1gBA7pdbr6gt/C qEeWr4OcjqiwN0p3W7BnFzNbw88UMwYlpxgkSATEM4yJXhUcEQn2DKdWl8918bWOQz+H7+ 98EvtQ3RPPdisseFrLOhHNfhl6WMDTdtLNYRwGw1A9F/q89CEEmFjRYQMEvabW/C5tM9to nqHYsy5JrsFvZCk5mDfNDNF6hSFUKST18P5UZNYpg3pU8W32U0/hHZAzGO1mOsccrq+bwQ 29D1lLYEThLuAn8/lSam2tO62l57eAidmEKbFaX7hVym+NAe+UpjVSyv/xLO9A== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: linux@ew.tq-group.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH v2 4/5] gpio: tqmx86: introduce tqmx86_gpio_clrsetbits() helper Date: Thu, 12 Dec 2024 15:08:08 +0100 Message-ID: X-Mailer: git-send-email 2.47.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Add a helper for the common read-modify-write pattern (only used in tqmx86_gpio_irq_config() initially). No functional change intended. Signed-off-by: Matthias Schiffer --- v2: no changes drivers/gpio/gpio-tqmx86.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index e55ce4503e70b..4bef13cad1807 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -66,6 +66,18 @@ static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val, iowrite8(val, gd->io_base + reg); } +static void tqmx86_gpio_clrsetbits(struct tqmx86_gpio_data *gpio, + u8 clr, u8 set, unsigned int reg) + __must_hold(&gpio->spinlock) +{ + u8 val = tqmx86_gpio_read(gpio, reg); + + val &= ~clr; + val |= set; + + tqmx86_gpio_write(gpio, val, reg); +} + static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); @@ -118,7 +130,7 @@ static int tqmx86_gpio_get_direction(struct gpio_chip *chip, static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int hwirq) __must_hold(&gpio->spinlock) { - u8 type = TQMX86_INT_TRIG_NONE, gpiic; + u8 type = TQMX86_INT_TRIG_NONE; int gpiic_irq = hwirq - TQMX86_NGPO; if (gpio->irq_type[hwirq] & TQMX86_INT_UNMASKED) { @@ -130,10 +142,10 @@ static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int hwirq) : TQMX86_INT_TRIG_RISING; } - gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); - gpiic &= ~TQMX86_GPIIC_MASK(gpiic_irq); - gpiic |= TQMX86_GPIIC_CONFIG(gpiic_irq, type); - tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); + tqmx86_gpio_clrsetbits(gpio, + TQMX86_GPIIC_MASK(gpiic_irq), + TQMX86_GPIIC_CONFIG(gpiic_irq, type), + TQMX86_GPIIC); } static void tqmx86_gpio_irq_mask(struct irq_data *data) From patchwork Thu Dec 12 14:08:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 851114 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D585B2153EF; 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b=pJpGcjdJzs7J0lSqAVImwusNWhbVaufxWfLtGzS46BL4Y10aGgtKAtbbiby39DAKWjvsGZ I6hocPT9V/r7TzZBe1dLguxrgwX7fKU7jdv6pWh+3yUfEPd23/r1cJjhJ/I6kG3ad46mkG PjAIx8S+6HSNaXrHS899wVDKA6Xq9ZTtYfgo69GFxnqXwfm126biwLKdw+RkDwatElB4h/ umnbga9Mwe6bPpG0e1ffm6QaRpLmemXzeoc3NhzJbgjWDrbVCd4Xwk7ZpuYp5Dp1WlDxy1 tuz90imrtqFG77+nRWYwqAp4xk2p9BKqhqgdZrJ4D4dbmvzIY+6dMANQOquOLA== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: linux@ew.tq-group.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH v2 5/5] gpio: tqmx86: add support for changing GPIO directions Date: Thu, 12 Dec 2024 15:08:09 +0100 Message-ID: X-Mailer: git-send-email 2.47.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Only GPIOs 4..7 have IRQ support on the TQMx86 variants currently handled by the driver, but apart from that, changing directions works fine. The default directions are left unchanged (0..3 output, 4..7 input) to match the COM Express specification. A tqmx86_gpio_set() variant without locking is introduced as a new helper. Signed-off-by: Matthias Schiffer --- v2: use lock guards drivers/gpio/gpio-tqmx86.c | 44 ++++++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index 4bef13cad1807..18f523a15b3c0 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -85,6 +85,14 @@ static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset) return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & BIT(offset)); } +static void _tqmx86_gpio_set(struct tqmx86_gpio_data *gpio, unsigned int offset, + int value) + __must_hold(&gpio->spinlock) +{ + __assign_bit(offset, gpio->output, value); + tqmx86_gpio_write(gpio, bitmap_get_value8(gpio->output, 0), TQMX86_GPIOD); +} + static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { @@ -92,39 +100,47 @@ static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, guard(raw_spinlock_irqsave)(&gpio->spinlock); - __assign_bit(offset, gpio->output, value); - tqmx86_gpio_write(gpio, bitmap_get_value8(gpio->output, 0), TQMX86_GPIOD); + _tqmx86_gpio_set(gpio, offset, value); } static int tqmx86_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { - /* Direction cannot be changed. Validate is an input. */ - if (BIT(offset) & TQMX86_DIR_INPUT_MASK) - return 0; - else - return -EINVAL; + struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); + + guard(raw_spinlock_irqsave)(&gpio->spinlock); + + tqmx86_gpio_clrsetbits(gpio, BIT(offset), 0, TQMX86_GPIODD); + + return 0; } static int tqmx86_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { - /* Direction cannot be changed, validate is an output */ - if (BIT(offset) & TQMX86_DIR_INPUT_MASK) - return -EINVAL; + struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); + + guard(raw_spinlock_irqsave)(&gpio->spinlock); + + _tqmx86_gpio_set(gpio, offset, value); + tqmx86_gpio_clrsetbits(gpio, 0, BIT(offset), TQMX86_GPIODD); - tqmx86_gpio_set(chip, offset, value); return 0; } static int tqmx86_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { - if (TQMX86_DIR_INPUT_MASK & BIT(offset)) - return GPIO_LINE_DIRECTION_IN; + struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); + u8 val; + + val = tqmx86_gpio_read(gpio, TQMX86_GPIODD); + + if (val & BIT(offset)) + return GPIO_LINE_DIRECTION_OUT; - return GPIO_LINE_DIRECTION_OUT; + return GPIO_LINE_DIRECTION_IN; } static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int hwirq)