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Update the bindings to reflect this. Signed-off-by: Akhil P Oommen --- .../devicetree/bindings/display/msm/gpu.yaml | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 6ddc72fd85b0..1276331cb262 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -217,6 +217,42 @@ allOf: required: - clocks - clock-names + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-612.0 + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + + clock-names: + items: + - const: core + description: GPU Core clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gmu + description: CX GMU clock + - const: xo + description: GPUCC clocksource clock + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_dbgc + + required: + - clocks + - clock-names + else: if: properties: From patchwork Fri Dec 13 10:35:44 2024 Content-Type: text/plain; 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Compared to GMU, it doesn't manage GPU clock, voltage scaling, bw voting or any other functionalities. All it does is detect an idle GPU and toggle the GDSC switch. So it doesn't require iommu & opp table. Signed-off-by: Akhil P Oommen --- Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index b1bd372996d5..6889dda7d4be 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -27,6 +27,7 @@ properties: - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$' - const: qcom,adreno-gmu - const: qcom,adreno-gmu-wrapper + - const: qcom,adreno-rgmu reg: minItems: 1 @@ -267,12 +268,14 @@ allOf: properties: compatible: contains: - const: qcom,adreno-gmu-wrapper + enum: + - qcom,adreno-gmu-wrapper + - qcom,adreno-rgmu then: properties: reg: items: - - description: GMU wrapper register space + - description: RGMU/GMU wrapper register space reg-names: items: - const: gmu From patchwork Fri Dec 13 10:35:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 850867 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E67AB1BE871; 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Fri, 13 Dec 2024 10:36:39 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BDAacrl003462 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 10:36:38 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Dec 2024 02:36:30 -0800 From: Akhil P Oommen Date: Fri, 13 Dec 2024 16:05:45 +0530 Subject: [PATCH v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241213-qcs615-gpu-dt-v2-3-6606c64f03b5@quicinc.com> References: <20241213-qcs615-gpu-dt-v2-0-6606c64f03b5@quicinc.com> In-Reply-To: <20241213-qcs615-gpu-dt-v2-0-6606c64f03b5@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bjorn Andersson" CC: , , , , , Akhil P Oommen , <20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0@quicinc.com>, <20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com>, <20240924143958.25-2-quic_rlaggysh@quicinc.com>, <20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf@quicinc.com>, <20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624@quicinc.com>, <20241122074922.28153-1-quic_qqzhou@quicinc.com>, Jie Zhang X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; 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Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 88 ++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 8df26efde3fd..dee5d3be4aa3 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -387,6 +387,11 @@ smem_region: smem@86000000 { no-map; hwlocks = <&tcsr_mutex 3>; }; + + pil_gpu_mem: pil-gpu@97715000 { + reg = <0x0 0x97715000 0x0 0x2000>; + no-map; + }; }; soc: soc@0 { @@ -508,6 +513,89 @@ qup_uart0_rx: qup-uart0-rx-state { }; }; + gpu: gpu@5000000 { + compatible = "qcom,adreno-612.0", "qcom,adreno"; + reg = <0x0 0x05000000 0x0 0x90000>; + reg-names = "kgsl_3d0_reg_memory"; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>; + clock-names = "core", + "mem_iface", + "alt_mem_iface", + "gmu", + "xo"; + + interrupts = ; + + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + iommus = <&adreno_smmu 0x0 0x401>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + qcom,gmu = <&rgmu>; + + #cooling-cells = <2>; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-435000000 { + opp-hz = /bits/ 64 <435000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3000000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <3975000>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5287500>; + }; + + opp-745000000 { + opp-hz = /bits/ 64 <745000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + opp-peak-kBps = <6075000>; + }; + + opp-845000000 { + opp-hz = /bits/ 64 <845000000>; + required-opps = <&rpmhpd_opp_turbo>; + opp-peak-kBps = <7050000>; + }; + }; + }; + + rgmu: rgmu@506a000 { + compatible = "qcom,adreno-rgmu"; + reg = <0x0 0x0506a000 0x0 0x34000>; + reg-names = "gmu"; + power-domains = <&gpucc CX_GDSC>, + <&gpucc GX_GDSC>; + power-domain-names = "cx", "gx"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,qcs615-gpucc"; reg = <0 0x5090000 0 0x9000>; From patchwork Fri Dec 13 10:35:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 850388 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EB651DCB09; Fri, 13 Dec 2024 10:36:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 13 Dec 2024 10:36:46 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BDAaj5f031660 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 10:36:45 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Dec 2024 02:36:38 -0800 From: Akhil P Oommen Date: Fri, 13 Dec 2024 16:05:46 +0530 Subject: [PATCH v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241213-qcs615-gpu-dt-v2-4-6606c64f03b5@quicinc.com> References: <20241213-qcs615-gpu-dt-v2-0-6606c64f03b5@quicinc.com> In-Reply-To: <20241213-qcs615-gpu-dt-v2-0-6606c64f03b5@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bjorn Andersson" CC: , , , , , Akhil P Oommen , <20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0@quicinc.com>, <20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com>, <20240924143958.25-2-quic_rlaggysh@quicinc.com>, <20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf@quicinc.com>, <20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624@quicinc.com>, <20241122074922.28153-1-quic_qqzhou@quicinc.com>, Jie Zhang X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; 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Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index ee6cab3924a6..860a0db1908c 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -202,6 +202,14 @@ &gcc { <&sleep_clk>; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs615/a612_zap.mbn"; +}; + &qupv3_id_0 { status = "okay"; };