From patchwork Tue Dec 17 17:04:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyothi Kumar Seerapu X-Patchwork-Id: 851481 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 088711F76C4; Tue, 17 Dec 2024 17:04:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734455095; cv=none; b=bmaywfi+PPDYXEymxmUamSapTwIMO1BQVADuqOiH0WnYi7SxdsEcsq+qI3UctCrHWeAyLqcJuWNtQUEoExp8pW5FeYW9bAyqwZKL91jpaf/W8hDjqd3YDNtD146A3y/M6+BaJd0+AMttxbRHshEgbtq0ugKY96vmc97QBOOtmxM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734455095; c=relaxed/simple; bh=QHrnee/Yn0RvhpR8Djm8acNMVX6D1HuW9pkboH5MC/U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FcpwiuY/1jSVRazMMR8q+QQabHAD8ZjE1pmd2HDRF9gb89DluAqe0YwRl93ewkdSQAi9sZw5IbCzjp3tZhq9Knfh/Ll9j2cr3a+ZymfvwrMoaaqRn8H7s98pdzOH6BF33wHNGZumHwijMvW0Rsq83f4yEtvdZBRcTknPdhD2nDc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=V3Er22nU; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="V3Er22nU" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BHB2eSo003042; Tue, 17 Dec 2024 17:04:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=qcppdkim1; bh=286FtCTWicDq+EXvrGEy/Og6 /VAHYV74wP8nTr06WUI=; b=V3Er22nU/gu8sMgucEXZUYjjZsfL8wV4GdwUwf9F X26an+YOGbVmGhHPTQUR7HpVxvg8BuDgn88QV5ePblaDLzVOZlM+gMg5Sk9RPF8e qOgh1K5dGFozIsaCMheHjcacO3v8NC2aj+KYUP8wId6Fxe0HgsT8zZ5WyYQK56ek RBzQ9i6+mj7OJJaOEQK3Mtnt7wd1ambyUDBQKD/29YPKdnrs1IL6rBaTueGSUgWZ iLCZuP8OYzhky/ZmafSow8eTfzOTkFMzsFDZwHjHTp6xTFulLLfro4PBLJth7I8j i1GwTrPMNCj3qhvCMgPJ+KVM7QooOEYHKuHD/qe7jIcs1Q== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43k831105f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 17:04:47 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BHH4kfT009332 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 17:04:46 GMT Received: from hu-jseerapu-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 17 Dec 2024 09:04:42 -0800 From: Jyothi Kumar Seerapu To: Vinod Koul , Andi Shyti , "Sumit Semwal" , =?utf-8?q?Christian_K=C3=B6nig?= CC: , , , , , , , , Subject: [PATCH v4 1/2] dmaengine: qcom: gpi: Add GPI Block event interrupt support Date: Tue, 17 Dec 2024 22:34:23 +0530 Message-ID: <20241217170424.14703-2-quic_jseerapu@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241217170424.14703-1-quic_jseerapu@quicinc.com> References: <20241217170424.14703-1-quic_jseerapu@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LQBYP1yAhRykVfKte8hTy5AsVoKkJmwE X-Proofpoint-ORIG-GUID: LQBYP1yAhRykVfKte8hTy5AsVoKkJmwE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 spamscore=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 impostorscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412170131 GSI hardware generates an interrupt for each transfer completion. For multiple messages within a single transfer, this results in N interrupts for N messages, leading to significant software interrupt latency. To mitigate this latency, utilize Block Event Interrupt (BEI) mechanism. Enabling BEI instructs the GSI hardware to prevent interrupt generation and BEI is disabled when an interrupt is necessary. When using BEI, consider splitting a single multi-message transfer into chunks of 8 internally. Interrupts are not expected for the first 7 message completions, only the last message triggers an interrupt,indicating the completion of 8 messages. This BEI mechanism enhances overall transfer efficiency. Signed-off-by: Jyothi Kumar Seerapu --- v3 -> v4: - API's added for Block event interrupt with multi descriptor support for I2C is moved from qcom-gpi-dma.h file to I2C geni qcom driver file. - gpi_multi_xfer_timeout_handler function is moved from GPI driver to I2C driver. v2-> v3: - Renamed gpi_multi_desc_process to gpi_multi_xfer_timeout_handler - MIN_NUM_OF_MSGS_MULTI_DESC changed from 4 to 2 - Added documentation for newly added changes in "qcom-gpi-dma.h" file - Updated commit description. v1 -> v2: - Changed dma_addr type from array of pointers to array. - To support BEI functionality with the TRE size of 64 defined in GPI driver, updated QCOM_GPI_MAX_NUM_MSGS to 16 and NUM_MSGS_PER_IRQ to 4. drivers/dma/qcom/gpi.c | 3 +++ include/linux/dma/qcom-gpi-dma.h | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index 52a7c8f2498f..74eabcd1416d 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -1693,6 +1693,9 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE); tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT); + + if (i2c->flags & QCOM_GPI_BLOCK_EVENT_IRQ) + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_BEI); } for (i = 0; i < tre_idx; i++) diff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-dma.h index 6680dd1a43c6..d818c6a955e2 100644 --- a/include/linux/dma/qcom-gpi-dma.h +++ b/include/linux/dma/qcom-gpi-dma.h @@ -15,6 +15,13 @@ enum spi_transfer_cmd { SPI_DUPLEX, }; +/** + * define QCOM_GPI_BLOCK_EVENT_IRQ - Block event interrupt support + * + * This is used to enable/disable the Block event interrupt mechanism. + */ +#define QCOM_GPI_BLOCK_EVENT_IRQ BIT(0) + /** * struct gpi_spi_config - spi config for peripheral * @@ -65,6 +72,7 @@ enum i2c_op { * @rx_len: receive length for buffer * @op: i2c cmd * @muli-msg: is part of multi i2c r-w msgs + * @flags: true for block event interrupt support */ struct gpi_i2c_config { u8 set_config; @@ -78,6 +86,7 @@ struct gpi_i2c_config { u32 rx_len; enum i2c_op op; bool multi_msg; + bool flags; }; #endif /* QCOM_GPI_DMA_H */