From patchwork Tue Dec 17 16:12:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 851500 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2078.outbound.protection.outlook.com [40.107.223.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 502F71F63F5; Tue, 17 Dec 2024 16:13:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.78 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734451993; cv=fail; b=SLYbY8Da1EpKcg9s4n0S8bTz2ADuqXHCmhFL/kO+RnW1ESEjDewR2qUzRIvAVZK2l6zhjEGX2rEMJpirWLpQbM2FD4zD9GfWH19AlbMbO9WmWZ04TmEcCoqpZjYWoMwhnp/JpTzhaflnmMLs7cKuufuVt1EMSo8f5eACKuoaWb0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734451993; c=relaxed/simple; bh=CuX1xd6/01ZLKn9toseoMF4Y2gidmKAekxJrIfmBMes=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iTa0jSxuM3ffomImq2gbET3bXKF9XeNs7HcSAiGRpgln3J/Eh+NRieK0Rc0asQadnOlrjIHLnIwiA3b36X1JdBaYPyl9vPo2au6ImDr6d597nW8kmlw6dSIX/91bKUbhdGcIYhdaQzpZOYMMUCzU6a7DhfELiwe6HyWk/m7Dq18= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Qk8Vmkb/; arc=fail smtp.client-ip=40.107.223.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Qk8Vmkb/" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=IMdzbsUsakXLlNYQlnauI1wdeYI1TyBoj47J6VlMW/xbxMJW4iBtuQJlylm2WaBi/kplcCgTJstTTPXGn2lTsRDBk+BZSebuQLWcs+8xXocj45180CFprukZTUuMUf00GDhHhAbL19GzdX6YG4/Puf8UISCKSAXCOlMiSTKU0nX5FVoZR4Uzu3t4kTkfYcju8IDv5kwZFwcFiCFGLfjEX65NXmaj123/Kfg1U25BK4YeIwWd5rOe2YoF6tjCPXOhhsLgB9dBY9kurTxc8NcV6bVRbfZEGUGPYvtA2G5l3iqF0nXSrreZIQzLnyyXWQthDuY7MPPZW3dUCEf5611O4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=X+AYiwCXPqp8tvlNfH/KfypMvI6eUDYPB1FKwjXs7Dk=; b=J2VoI1/KRqO96gpXcm7WVqZJGKN4DAQZGkdnD2tecCgfmIvSISIxvcUe0iTncTeGYFwrl057PqZyXtVu6K+33TVGRWOeV39wbExwqdKHfZr32PS686o45830rWWhqNxKBUnRchrKljsorEr3Gvrc9H7PCYV1Gpse1ZXwGjdUcZvwELxzZrBpthVHsDhfjfK8RvRAUx96iLYqm2IRpzpX0Pg/or5e75A9mWA7Al8mUq6X3zulHdn0zPdL1ZBdIY7id3f5Rd9eBW+XheZcAfhm06yQvDsvXboNqqayf3TLeWb49eBcdPOE0k7GT4bFjWa8DZuqEWKVGHZHKjlDf3y0tg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=gondor.apana.org.au smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=X+AYiwCXPqp8tvlNfH/KfypMvI6eUDYPB1FKwjXs7Dk=; b=Qk8Vmkb/seDB5xOtu3t1qctbD2pih55VdanV8OD2o3KGRLWPtDX8Mf61XSdE2wYtJHAdRhuGxex2QK8VafXILdOH/EMDcvM6IAzH7QNLQBSXr1ZdiGcPEnQvxWSMwW+3ROygrqAqyWMKUrL8QnmcsEZdxxi9CO+x2vYCcy+teJQbyemd4R8Kd2LgiwROiBhVaKvEQxFv+BZp45dM3vVQCduKS23qFVjer4s1vvquWzLhK8pdtakU5Nzcmmwd4XPUeqctQQxYVXtz5aihmdGe9XfCw6QW++w48ADmb9RGHLoaZiCw6/6ZV2nSMxsSkNXskBTiIweXEICRbb255aUMgw== Received: from BN0PR04CA0192.namprd04.prod.outlook.com (2603:10b6:408:e9::17) by CY8PR12MB8215.namprd12.prod.outlook.com (2603:10b6:930:77::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8272.13; Tue, 17 Dec 2024 16:13:06 +0000 Received: from BN1PEPF00004680.namprd03.prod.outlook.com (2603:10b6:408:e9:cafe::3a) by BN0PR04CA0192.outlook.office365.com (2603:10b6:408:e9::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8251.21 via Frontend Transport; Tue, 17 Dec 2024 16:13:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN1PEPF00004680.mail.protection.outlook.com (10.167.243.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8251.15 via Frontend Transport; Tue, 17 Dec 2024 16:13:05 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 17 Dec 2024 08:12:48 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 17 Dec 2024 08:12:48 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 17 Dec 2024 08:12:45 -0800 From: Akhil R To: , , , , , , CC: Subject: [PATCH 1/7] crypto: tegra: Use separate buffer for setkey Date: Tue, 17 Dec 2024 21:42:01 +0530 Message-ID: <20241217161207.72921-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20241217161207.72921-1-akhilrajeev@nvidia.com> References: <20241217161207.72921-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|CY8PR12MB8215:EE_ X-MS-Office365-Filtering-Correlation-Id: 047861ed-93eb-49d9-a990-08dd1eb5b05d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: uDwxg6KwON6OuZ6WHlOSPmXlm0saO6THHK1iil9PdiDEYqeWfiOopbLs/Vli18P2vWjC+M54QWEL22zeev1V/mQudMb/8AMTPcJFoPrS3TFPLJBhllsXUr6A+ZwiH0RhyiF2DHyyJhK2v0gaSOuy5uDoCXP6XB/wjSdH91GFuxTeLSmAVRYr9VYDpdqC7SX37hIedMRURBlD/IL+gjgvcsI5lxRk1k4dCY4Z6jT9dLvCLxMmGGH5xCJwObsLpoS0QaVCj+iidBdjhtGUJprOTaQKOLNVGGfsHNtt3UIouYmSNgUh+aXaNOsLMLtBtTNMwJhDTGT4aWy4GY9A0CdHmCIEbzUHNO+WE5D6h0ldxWEakO5gXMGO5fCfuou/6VroERseH2C6yf1DZcOIkCcfSQzT4+Ey0sI6gvrZMY1lPM1A9Vi5vSQlCTiUdAKxPYAuQXBbXYa8n/GFLqTxCTY41+DOkI+Sj1Yc03vZRketDbNnbFA1sNS/STV1KU568GFhqCG+Lun/mULrkKVLWEE4PUNSThgFlSoW47K0SJA+p57RCr89DH/oV66IPdsmi3yAuqPNm/19YJUG2UegzBWNoK4XNNboyVjNZ1W5lIJhry8nZnYjl9MbGmyynzY3+btWsUwdJDdh4f2hSGw7XDBEKHmaZTLPKFjlK1GeyQbrzV7nDTrDtI7mC+8NZdT40gEVn08hhX2ErafSatiD+06wnuhENkCKXZObQM5H1E8VonuaOsHzU9KBO3vIob2MV0NEeLcgsdO0X6qZuMFLGkVcuwr0nZsH0RkmLVPZFqgIAGejK8mqPtzOdDa/tBGJaLu+cqia2JyXRiOy8Lb+MA7ssK+ku5RRUcEZCwECdczVAZbnZP9SAdikGaA655uT1EfFVjcxcV7+zKAxQILbhCuEdRs1aNb4K2934LAGeSGFuFzGR/tPVjleGMhearwmXyCl4NrhHRuhEFlyOJw4zIailufAG/UejFdcHUHhJUoXTX2fwv7pI3gX1MXNDhXLO9aJICRWnrvQSaMpAVor06MjlN2dIr3JBOG7NmWt+zBPRqBdiN2JygoxFiETO0AFlT5WTIGzg22esE8bEW5Q8G9asui2Zj4TGCfRMMHTED1AHC5U6VPb5FBx/Rca3NIAjSFtFfPditJTWXvCoQjLJf6yVInm0o8AacqcSizlbjj8is8X9JjIX9DapnkoBQ7MWw9WxbR6LlpngBLeGDZUP4KsE/+SojtVGPKtCRoSxQvQMQ1ifuv/ENwJmWb3+zy3D5txTIujh6Gmx0EVW3loGFriJHZm2aXy6bUcNwH26yeFhHUCNbx6XpUJwv88v/aQYinwGKOvYzmYcM2nXRjlKIAfF6Dnnipo7yJH9pvIl3tHU+Ar4JmRf6Vf15e2XBJJ2DjUrc/TNSjETY1FclKUMfDgi9/BeeMrdorrPSnuIcu0V6Yw/eUnRdoQHi7fWShE2/1EXJkGdysOcVEjfS6O1MV5+tlBvTEC0ShaOBF0HiPn4Ew= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2024 16:13:05.1133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 047861ed-93eb-49d9-a990-08dd1eb5b05d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8215 The buffer which sends the commands to host1x was shared for all tasks in the engine. This causes a problem with the setkey() function as it gets called asynchronous to the crypto engine queue. Modifying the same cmdbuf in setkey() will corrupt the ongoing host1x task and in turn break the encryption/decryption operation. Hence use a separate cmdbuf for setkey(). Fixes: 0880bb3b00c8 ("crypto: tegra - Add Tegra Security Engine driver") Signed-off-by: Akhil R --- drivers/crypto/tegra/tegra-se-aes.c | 16 ++++++++-------- drivers/crypto/tegra/tegra-se-hash.c | 13 +++++++------ drivers/crypto/tegra/tegra-se-key.c | 10 ++++++++-- drivers/crypto/tegra/tegra-se-main.c | 16 ++++++++++++---- drivers/crypto/tegra/tegra-se.h | 3 ++- 5 files changed, 37 insertions(+), 21 deletions(-) diff --git a/drivers/crypto/tegra/tegra-se-aes.c b/drivers/crypto/tegra/tegra-se-aes.c index 9d130592cc0a..5fc7e19b8ab8 100644 --- a/drivers/crypto/tegra/tegra-se-aes.c +++ b/drivers/crypto/tegra/tegra-se-aes.c @@ -282,7 +282,7 @@ static int tegra_aes_do_one_req(struct crypto_engine *engine, void *areq) /* Prepare the command and submit for execution */ cmdlen = tegra_aes_prep_cmd(ctx, rctx); - ret = tegra_se_host1x_submit(se, cmdlen); + ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen); /* Copy the result */ tegra_aes_update_iv(req, ctx); @@ -719,7 +719,7 @@ static int tegra_gcm_do_gmac(struct tegra_aead_ctx *ctx, struct tegra_aead_reqct cmdlen = tegra_gmac_prep_cmd(ctx, rctx); - return tegra_se_host1x_submit(se, cmdlen); + return tegra_se_host1x_submit(se, se->cmdbuf, cmdlen); } static int tegra_gcm_do_crypt(struct tegra_aead_ctx *ctx, struct tegra_aead_reqctx *rctx) @@ -736,7 +736,7 @@ static int tegra_gcm_do_crypt(struct tegra_aead_ctx *ctx, struct tegra_aead_reqc /* Prepare command and submit */ cmdlen = tegra_gcm_crypt_prep_cmd(ctx, rctx); - ret = tegra_se_host1x_submit(se, cmdlen); + ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen); if (ret) return ret; @@ -759,7 +759,7 @@ static int tegra_gcm_do_final(struct tegra_aead_ctx *ctx, struct tegra_aead_reqc /* Prepare command and submit */ cmdlen = tegra_gcm_prep_final_cmd(se, cpuvaddr, rctx); - ret = tegra_se_host1x_submit(se, cmdlen); + ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen); if (ret) return ret; @@ -891,7 +891,7 @@ static int tegra_ccm_do_cbcmac(struct tegra_aead_ctx *ctx, struct tegra_aead_req /* Prepare command and submit */ cmdlen = tegra_cbcmac_prep_cmd(ctx, rctx); - return tegra_se_host1x_submit(se, cmdlen); + return tegra_se_host1x_submit(se, se->cmdbuf, cmdlen); } static int tegra_ccm_set_msg_len(u8 *block, unsigned int msglen, int csize) @@ -1098,7 +1098,7 @@ static int tegra_ccm_do_ctr(struct tegra_aead_ctx *ctx, struct tegra_aead_reqctx /* Prepare command and submit */ cmdlen = tegra_ctr_prep_cmd(ctx, rctx); - ret = tegra_se_host1x_submit(se, cmdlen); + ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen); if (ret) return ret; @@ -1519,8 +1519,8 @@ static int tegra_cmac_do_update(struct ahash_request *req) tegra_cmac_paste_result(ctx->se, rctx); cmdlen = tegra_cmac_prep_cmd(ctx, rctx); + ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen); - ret = tegra_se_host1x_submit(se, cmdlen); /* * If this is not the final update, copy the intermediate results * from the registers so that it can be used in the next 'update' @@ -1553,7 +1553,7 @@ static int tegra_cmac_do_final(struct ahash_request *req) /* Prepare command and submit */ cmdlen = tegra_cmac_prep_cmd(ctx, rctx); - ret = tegra_se_host1x_submit(se, cmdlen); + ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen); if (ret) goto out; diff --git a/drivers/crypto/tegra/tegra-se-hash.c b/drivers/crypto/tegra/tegra-se-hash.c index 4d4bd727f498..a0460e624523 100644 --- a/drivers/crypto/tegra/tegra-se-hash.c +++ b/drivers/crypto/tegra/tegra-se-hash.c @@ -300,8 +300,9 @@ static int tegra_sha_do_update(struct ahash_request *req) { struct tegra_sha_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); struct tegra_sha_reqctx *rctx = ahash_request_ctx(req); + struct tegra_se *se = ctx->se; unsigned int nblks, nresidue, size, ret; - u32 *cpuvaddr = ctx->se->cmdbuf->addr; + u32 *cpuvaddr = se->cmdbuf->addr; nresidue = (req->nbytes + rctx->residue.size) % rctx->blk_size; nblks = (req->nbytes + rctx->residue.size) / rctx->blk_size; @@ -353,11 +354,11 @@ static int tegra_sha_do_update(struct ahash_request *req) * This is to support the import/export functionality. */ if (!(rctx->task & SHA_FIRST)) - tegra_sha_paste_hash_result(ctx->se, rctx); + tegra_sha_paste_hash_result(se, rctx); - size = tegra_sha_prep_cmd(ctx->se, cpuvaddr, rctx); + size = tegra_sha_prep_cmd(se, cpuvaddr, rctx); - ret = tegra_se_host1x_submit(ctx->se, size); + ret = tegra_se_host1x_submit(se, se->cmdbuf, size); /* * If this is not the final update, copy the intermediate results @@ -365,7 +366,7 @@ static int tegra_sha_do_update(struct ahash_request *req) * call. This is to support the import/export functionality. */ if (!(rctx->task & SHA_FINAL)) - tegra_sha_copy_hash_result(ctx->se, rctx); + tegra_sha_copy_hash_result(se, rctx); return ret; } @@ -388,7 +389,7 @@ static int tegra_sha_do_final(struct ahash_request *req) size = tegra_sha_prep_cmd(se, cpuvaddr, rctx); - ret = tegra_se_host1x_submit(se, size); + ret = tegra_se_host1x_submit(se, se->cmdbuf, size); if (ret) goto out; diff --git a/drivers/crypto/tegra/tegra-se-key.c b/drivers/crypto/tegra/tegra-se-key.c index ac14678dbd30..276b261fb6df 100644 --- a/drivers/crypto/tegra/tegra-se-key.c +++ b/drivers/crypto/tegra/tegra-se-key.c @@ -115,11 +115,17 @@ static int tegra_key_insert(struct tegra_se *se, const u8 *key, u32 keylen, u16 slot, u32 alg) { const u32 *keyval = (u32 *)key; - u32 *addr = se->cmdbuf->addr, size; + u32 *addr = se->keybuf->addr, size; + int ret; + + mutex_lock(&kslt_lock); size = tegra_key_prep_ins_cmd(se, addr, keyval, keylen, slot, alg); + ret = tegra_se_host1x_submit(se, se->keybuf, size); - return tegra_se_host1x_submit(se, size); + mutex_unlock(&kslt_lock); + + return ret; } void tegra_key_invalidate(struct tegra_se *se, u32 keyid, u32 alg) diff --git a/drivers/crypto/tegra/tegra-se-main.c b/drivers/crypto/tegra/tegra-se-main.c index 918c0b10614d..1c94f1de0546 100644 --- a/drivers/crypto/tegra/tegra-se-main.c +++ b/drivers/crypto/tegra/tegra-se-main.c @@ -141,7 +141,7 @@ static struct tegra_se_cmdbuf *tegra_se_host1x_bo_alloc(struct tegra_se *se, ssi return cmdbuf; } -int tegra_se_host1x_submit(struct tegra_se *se, u32 size) +int tegra_se_host1x_submit(struct tegra_se *se, struct tegra_se_cmdbuf *cmdbuf, u32 size) { struct host1x_job *job; int ret; @@ -160,9 +160,9 @@ int tegra_se_host1x_submit(struct tegra_se *se, u32 size) job->engine_fallback_streamid = se->stream_id; job->engine_streamid_offset = SE_STREAM_ID; - se->cmdbuf->words = size; + cmdbuf->words = size; - host1x_job_add_gather(job, &se->cmdbuf->bo, size, 0); + host1x_job_add_gather(job, &cmdbuf->bo, size, 0); ret = host1x_job_pin(job, se->dev); if (ret) { @@ -220,14 +220,22 @@ static int tegra_se_client_init(struct host1x_client *client) goto syncpt_put; } + se->keybuf = tegra_se_host1x_bo_alloc(se, SZ_4K); + if (!se->keybuf) { + ret = -ENOMEM; + goto cmdbuf_put; + } + ret = se->hw->init_alg(se); if (ret) { dev_err(se->dev, "failed to register algorithms\n"); - goto cmdbuf_put; + goto keybuf_put; } return 0; +keybuf_put: + tegra_se_cmdbuf_put(&se->keybuf->bo); cmdbuf_put: tegra_se_cmdbuf_put(&se->cmdbuf->bo); syncpt_put: diff --git a/drivers/crypto/tegra/tegra-se.h b/drivers/crypto/tegra/tegra-se.h index b9dd7ceb8783..b54aefe717a1 100644 --- a/drivers/crypto/tegra/tegra-se.h +++ b/drivers/crypto/tegra/tegra-se.h @@ -420,6 +420,7 @@ struct tegra_se { struct host1x_client client; struct host1x_channel *channel; struct tegra_se_cmdbuf *cmdbuf; + struct tegra_se_cmdbuf *keybuf; struct crypto_engine *engine; struct host1x_syncpt *syncpt; struct device *dev; @@ -502,7 +503,7 @@ void tegra_deinit_hash(struct tegra_se *se); int tegra_key_submit(struct tegra_se *se, const u8 *key, u32 keylen, u32 alg, u32 *keyid); void tegra_key_invalidate(struct tegra_se *se, u32 keyid, u32 alg); -int tegra_se_host1x_submit(struct tegra_se *se, u32 size); +int tegra_se_host1x_submit(struct tegra_se *se, struct tegra_se_cmdbuf *cmdbuf, u32 size); /* HOST1x OPCODES */ static inline u32 host1x_opcode_setpayload(unsigned int payload) From patchwork Tue Dec 17 16:12:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 851499 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2057.outbound.protection.outlook.com [40.107.244.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 661A41F63F5; Tue, 17 Dec 2024 16:13:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.57 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734452033; cv=fail; b=L7/fOeyAyli1XzKlKDLFsQwJXb4n3z239nludpMJPGL0HwYhKuWqlqaQOgHnhcX7mFFtd2XDMAFkHwexT72dKzsxi7HFdfiNZCeLyjzqIbxRNB+JQtLZ9r91BpsxPulhfx0IalFEu1IC7qY4oV8BWQVzCxqFX/8GIQbiWhlfJXM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734452033; c=relaxed/simple; bh=QN7MGsI3BwxY4U6QvLTAj1vAmLvwiZhE4Xgjw33Vmt4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZCg7tV0TCFVQNcTbOgCT1U1jwMDuWC3hHWCPnZ88z5US0vPxpKb+eG5ilTerB8oNkdCfW0LHO842ZTw7vM80Jt3TWBEI26j4uNhQLLPGX8IkMdPU1NXOArs8m4bS6O18MtZAUwjAmDMStUxPK0qLCc9Ff0oloM4684VXLw9Xmhw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=KRyhRfNV; arc=fail smtp.client-ip=40.107.244.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="KRyhRfNV" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Kl+1GznUJJYzD67Ahi/GzCrTHtr6hAJ1bXV1m0UEdbI7B1DExEQ80OHAb/rDTSADZ+scn6g5+4HNERnJdbiYOiI7USCtUNYNPd9prg0Xb7uowd6CBiYZLbNOxSlAxokj4UDoR+eCxUmAio3uOnn6Apg00sson9btIXlwc8xOp2fGmZNLAHd9brcuPqpZOYPvh1Rpaxpcqp3ETpiDYHukJzr2Pux1oSFtwKTcC4OFvzl9ELwg617B59xrE4Y8OfcmsrEJPo7AlHx54Qjxq/Y2JkglPa/QmICaVZufCkpVwuJIK7rQJ9CKN/Gs7FA9s7dB8O3cJCPZuxTpQwXJCkm6Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4DM67iu85/nkYxfzaoHOQ1PXKjJZnoizsAzXN6Bw0c8=; b=g9gNKE7gpEZQvYPHxUuyPimYfkC2XRVFT8zDx6uJ5VEsJBEZVlgd4z462YGTmlZIi3WF0c2zmjiY00EGthUTlKNeSWGGr4xHtEetY/jnMRoWNDAUyVXpApvxPz6i977UkXY4L2b0hiRLuLI/9ufwckZxxU+TXgsDWQY7eHsCDEoJfdZHLGzs2YqOYrlskzrO7tGE6Zn+Wyva6Oc01TvQia1WH5p9DLSvEGl/+dIkfbsPeAQ8AGDs1UqR7hk8ZNcU2+Gj7ljB5On1/GMCPl1sBPPgl+YQWFLIR0QzWJk+Rg4qRnPPUVrmwI2j3mX8+dRNrlR6u+eR5nDvoq9PneS6ig== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=gondor.apana.org.au smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4DM67iu85/nkYxfzaoHOQ1PXKjJZnoizsAzXN6Bw0c8=; b=KRyhRfNVYA9Il08KztyEBxjUFYhwzDbU4PpVxejXgfXiFjAdX+paqYkZYs/AzJKYdv2V0xgVdzw0e2zKvTySMFwvuQ8uAHTUZ0H9n8B4EG3Ad4LKZuRgxuz5KiSRn2zAHkiB0ZHGfk7bdFCGqMetWjsmSTuOC3MsUuBgLLU2J0ws1WP2JI5U27vxnFVh7LcFqCv7tmDd8awlHjPk9ujd56bbZ9OmXZJcFeFluHeJNkQsKcOmcnz0icthRR5Xr6JaTKyImS58ghcopNlAq0FOH6WnOISQS4RZ8G2bdeY8M62+835GCHz3yN7+h5AjAxqOWfLpD6zRzkhbM3JgXIMSSw== Received: from BN9PR03CA0626.namprd03.prod.outlook.com (2603:10b6:408:106::31) by SJ0PR12MB6926.namprd12.prod.outlook.com (2603:10b6:a03:485::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8251.21; Tue, 17 Dec 2024 16:13:47 +0000 Received: from BL02EPF0001A108.namprd05.prod.outlook.com (2603:10b6:408:106:cafe::14) by BN9PR03CA0626.outlook.office365.com (2603:10b6:408:106::31) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8251.21 via Frontend Transport; Tue, 17 Dec 2024 16:13:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A108.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8251.15 via Frontend Transport; Tue, 17 Dec 2024 16:13:44 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 17 Dec 2024 08:13:21 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 17 Dec 2024 08:13:21 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 17 Dec 2024 08:13:18 -0800 From: Akhil R To: , , , , , , CC: , kernel test robot , Dan Carpenter Subject: [PATCH 3/7] crypto: tegra: check retrun value for hash do_one_req Date: Tue, 17 Dec 2024 21:42:03 +0530 Message-ID: <20241217161207.72921-4-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20241217161207.72921-1-akhilrajeev@nvidia.com> References: <20241217161207.72921-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A108:EE_|SJ0PR12MB6926:EE_ X-MS-Office365-Filtering-Correlation-Id: 1e0bea20-9e5a-4e03-9115-08dd1eb5c80a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: Xo3eg6Z2YvCAd8QGg89P3CcHJM4em4kNqxJGc3VAkDndoaBJPUsOgw6zhqMaAOYULIqWBPn0yR71SfeulW2SWCEttRPRmEQwzlX9xK5FXqRPbiNJxaCG6zLr268K/UxlS+FytoNjzTbE6MSkv8CnbFXdQOJasvkR+syY4rp1xhBTXPmpU0fe9i/RjfGkxYj00+iuJJzp5EhjpSReZkexZXAEc6DZXWw+iKMqtRvBrarNHdihS+VSEoek0rIuSJQxRQNOT9wINQrjbPU7KBKCViYBNQKsZmOKO76IuMzaUec8dF202rx2sKqTmNtWbyuG0KQk9KZB9AAgAe7TC33CFeq0VSBxiYcHStTakugZWOucMLbLmTU6v0/2BzTGISPG0SrtkPIKc2ZQiFRqGrCFJT4mexulKIv5KH5EzOXJXCR++Jr3nwZqGeQRkFrlgP49Dqhbgzn1OVCmEV404z3H0+FjnNyw3TaIoljRxMJVHYScE/ght1KE8JvwOBgIhmhZaj+RI6vpzO8lOJx9FM4ifqJa8mI5Da6XYJjhQ8R/PWpGv+z/9tylaEruV4nZ10NQgGXRgTN55o9wfhoS0mD6UT/mbGxE5Wtv9y27EX0yaGaiC2d1u+wGWzwkee2V4avh/C4m/SVx6tNourVz3QxixrWa4jjHa/zhy1n969dz3LxKxliCUmsuuI+eD/wGpuwrbxnwnGbd6MmxZzx9VJW1mJKd9IgkWVy94fXI9MQ+xDio8nM9AH2YWB83rSIHNThfPNxQXpioAxyrcAEfgYXv4RNbdHF3dt+vHmh/53m1xIZb1IOkm97DdgDJIq8+WztXf75OUQE/brRKSkNCA3UjBTWz8bKhzBaS0qnPFCKE3DTaCgiOKvDFYpSS7LCxoXGBlIwEsPYbaDaVPSK6n9ii92DqK5sxfkpzJRZSpId2WEpfmvnVMNJGs8e5E9I5x/3NlMUv+SvQ5EUJC6L/GEA6EaXsEn1cxBOR3PqWdGruX7KWzTS4wUEzvufvX/EokWf3Cvsj6sVxjP6To3UIWpbNvcZXsW1kiBK51ttBcUl0lyraI7GX4BW43EOG+xXNWr9p4AkC+gw5Zb7Krqi9hSqo81PuN8tPjeCx0pH1JGW0nMb8LM2lBiUlmi1bOPC+jX9jcdCiiRzL12Kw75WANHImg5wBI8uSqyVgi8iPhh/cYn2xIr6sFt2zjCmGJ+XpKLIKKMbsOdzcThTpnJC14H/z9vD8Ve9rD9FsJ25MuzGZJkhMnUyzBOji+M0I8CGVq9OGjzbUXY/RvsEEbh+x6mA65qeWBMQAf0dbkrugyy0GzT4IgkgNzlzlSBFs+sYueUqU/n4kldXlyAXxzPTeJwzcxCJJ/fKEWUjyTAfURPF3iFAzqDEFda7JHQsJ9TqP+N0+G78RGWHASoOGXWUwaQLWVoV2/axhLMkgS5cc+O3MCcULUBqkb4IK8c0QFxELWi3TYjmcMCgA8YkcxBU/WIatyoRp+c6jkTG7PCWNG/TGxRM= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2024 16:13:44.8340 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e0bea20-9e5a-4e03-9115-08dd1eb5c80a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A108.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6926 Initialize and check the return value in hash *do_one_req() functions and exit the function if there is an error. This fixes the 'uninitialized variable' warnings reported by testbots. Reported-by: kernel test robot Reported-by: Dan Carpenter Closes: https://lore.kernel.org/r/202412071747.flPux4oB-lkp@intel.com/ Fixes: 0880bb3b00c8 ("crypto: tegra - Add Tegra Security Engine driver") Signed-off-by: Akhil R --- drivers/crypto/tegra/tegra-se-aes.c | 10 ++++++++-- drivers/crypto/tegra/tegra-se-hash.c | 7 +++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/tegra/tegra-se-aes.c b/drivers/crypto/tegra/tegra-se-aes.c index b80786c5e4fd..6ed6da0ecc32 100644 --- a/drivers/crypto/tegra/tegra-se-aes.c +++ b/drivers/crypto/tegra/tegra-se-aes.c @@ -1596,18 +1596,24 @@ static int tegra_cmac_do_one_req(struct crypto_engine *engine, void *areq) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct tegra_cmac_ctx *ctx = crypto_ahash_ctx(tfm); struct tegra_se *se = ctx->se; - int ret; + int ret = 0; if (rctx->task & SHA_UPDATE) { ret = tegra_cmac_do_update(req); + if (ret) + goto out; + rctx->task &= ~SHA_UPDATE; } if (rctx->task & SHA_FINAL) { ret = tegra_cmac_do_final(req); + if (ret) + goto out; + rctx->task &= ~SHA_FINAL; } - +out: crypto_finalize_hash_request(se->engine, req, ret); return 0; diff --git a/drivers/crypto/tegra/tegra-se-hash.c b/drivers/crypto/tegra/tegra-se-hash.c index aed82d82b5fb..d35bce81e017 100644 --- a/drivers/crypto/tegra/tegra-se-hash.c +++ b/drivers/crypto/tegra/tegra-se-hash.c @@ -437,14 +437,21 @@ static int tegra_sha_do_one_req(struct crypto_engine *engine, void *areq) if (rctx->task & SHA_UPDATE) { ret = tegra_sha_do_update(req); + if (ret) + goto out; + rctx->task &= ~SHA_UPDATE; } if (rctx->task & SHA_FINAL) { ret = tegra_sha_do_final(req); + if (ret) + goto out; + rctx->task &= ~SHA_FINAL; } +out: crypto_finalize_hash_request(se->engine, req, ret); return 0; From patchwork Tue Dec 17 16:12:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 851498 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2056.outbound.protection.outlook.com [40.107.96.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 998D21FBE9A; Tue, 17 Dec 2024 16:14:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.96.56 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734452061; cv=fail; b=m2rcIZZerMuDLslMBTXWU3m2fx7Q+gryggBpYHiE7vJDCZzFE63wI6GPmIq0AqVwpPmYtTm2I4Yb63GAmxl/KVEwcLJFTNvFFsjQaShPvjX0TGKVZqhjDpNPG832wdPrSVil44gm6UFCfJLSYtlETbdyAvmRbK3PyRN+/0BFOec= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734452061; c=relaxed/simple; bh=jbkCphjjxqSyf6NzRWGDoMXpWoGQ2kgZN3IsLfSIlwI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=msivgURKfeBh4m7ETLEHGVhHQqPpL2EjjKiVDUAxqMgKWayXTmY31vWdRootTmEItwMHvFvFuhBBywQsBg1OoMHmbwoPA2/kdrvBa8eESvWH+wbiCFEznPhq7n7UcdiB7SseO+/q9zJOWTPcDU2WHux7IzlJRMQYaizicN1XO7U= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=JmeXsTmB; arc=fail smtp.client-ip=40.107.96.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="JmeXsTmB" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=tGzH34O1UxfrtkhFmG7G+nVOZyDcDwAw5X5edGOm34XzlNs1AvE2SDofy2c+0J/y3VkPeFBkHEEW9I44M5LK9EojuUI4pykGBgO4+urDAUmY2tIY/Dnfb+6PzcZ/q3pkClWVGJeTsPPJ2zyMJCOjecnk8QljdXwcDNbnkaWQMf3mSWq0L1q+/htuPKAjb2vJApRioSGWE7rRgqHltk/bRHEhoM6rS2d2NZJJ3wUtm9xERy/ZcycPqFeU2FWCK1nf4bpBMeslJeJn8KvIG5q0EbttnPtUnIdQDIQ7miEprHeHh1xu/vXmKTUO6YBEA7MnHlxoJKu5vMvWoJ43awX1BA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QSoitAu1S4bUFn5FCahSzUgTm++oEbkLGV1SXf4iiXQ=; b=g4RfLeV4Zb+aGr/lalXabHLx3oye74fkH/8OX3Hj1DnpJOfQZ9LjHpyncA4XRItXMOg38b9DMiB03b8KQkb02m0EJRHg+3quhyWpnfk0TSgoGBD5+Ll6ba+RUPMjQQLxf8nM2+6QepPn5/Qdt0HeZB6k/F0QCgp9K9vh6BIoWX7WdKb+SRolWrdzqa2Ys/hOfswccm3jIvCQT2fv/RjI1uShZVtsaLDbZmiUWL5bfz+q1uXiMtajTM8hRHYb8LXWsWvycBQdFoSbfO5E7UbLynxrCzgvJ7JX1hJHUItnEPLB1H6+XY+tJdMzX7Do4GpxzxfAEDNF/t5eUN+PJaO0Vw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=gondor.apana.org.au smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QSoitAu1S4bUFn5FCahSzUgTm++oEbkLGV1SXf4iiXQ=; b=JmeXsTmBaMCh0UWYwtU0m0vW3eN4gz3m1i9bb+MoIEvOSU+LlD60LoJmj/UMuOZ7QothKXPwvdMdhSKJ88GLLOImfhU2VKEfJrsgAz2iSX0o9KeJ06DArv8nUComToCtwIJg1N8REE2xPkpK1G3Ytq7ce9e2GUvSNJJZHHTpN31TTzwfOCqg9K4WeLA34EET78LvF+GW2EMLJSnV2tLjO2OfEWIF0WUs3O/znO4ycjhn/LrTS+VX04U8JMjcO+BC3518fI120tBjhP7kbzeqJqJG5ZXCUDfNLwNgjHeFg0QTHwsIzUyVbghioVEJWiU11h+wbL9EzwetT7TXB6ARiQ== Received: from PH7PR13CA0020.namprd13.prod.outlook.com (2603:10b6:510:174::27) by MW6PR12MB7088.namprd12.prod.outlook.com (2603:10b6:303:238::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8251.22; Tue, 17 Dec 2024 16:14:13 +0000 Received: from SJ5PEPF00000209.namprd05.prod.outlook.com (2603:10b6:510:174:cafe::49) by PH7PR13CA0020.outlook.office365.com (2603:10b6:510:174::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8272.11 via Frontend Transport; Tue, 17 Dec 2024 16:14:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SJ5PEPF00000209.mail.protection.outlook.com (10.167.244.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8251.15 via Frontend Transport; Tue, 17 Dec 2024 16:14:12 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 17 Dec 2024 08:13:50 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 17 Dec 2024 08:13:49 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 17 Dec 2024 08:13:47 -0800 From: Akhil R To: , , , , , , CC: Subject: [PATCH 5/7] crypto: tegra: Fix HASH intermediate result handling Date: Tue, 17 Dec 2024 21:42:05 +0530 Message-ID: <20241217161207.72921-6-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20241217161207.72921-1-akhilrajeev@nvidia.com> References: <20241217161207.72921-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000209:EE_|MW6PR12MB7088:EE_ X-MS-Office365-Filtering-Correlation-Id: 5cf5650c-461c-4db5-a70f-08dd1eb5d842 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: V0K5iyr3MuyrzRyThkPnEmscw/LAUHmlGVwqMUsX4InX77kWIPf1n6kNaX+rZR1Zibh0YsmPAqXU1vdGPQuKg8bl/TfOXJcw+xYBWrwcnVC6yu6hbFb6ap3HXIe88iTrNnuyohEASdJFG65lAOKRznsX6FIZXK8/+ZT7j7BO7PONXVrxv3N+F6jTZifRohnfFD+ZOITMdOeSK4prvo1Pi8yLoLJE+Th5z7p58g94sHZNhSxl+ZgXHuaHsSnIeV1Vo8pdJlK5eUGX7k0Ofr9fmLTojXEoXvCjY9rGpW4pjQlCWiMn2ViZpVMk5to8sZaOcDAJPkW8rYOfEYlYP8sdSTDnTHXh25+0/L88URcf+WZO+SNi1nAM2XNGKjHyP1kDCCWc0/3i100Te632lOi9NE7Twif/AnJX2qCgg19J1famGmdcdJ0Kfq9Dns/GZqGZKXLQ61bd+uT+nz0AX12eKJkuJCDSYHJ+SIidaiSMiKHWKao8EEA1pZBu1Pcr8lhPND7wY7F6Pp5Ar/YH91Xt4RrxftMmNvXuQlH+ncycnpcfEAu8K2bVgwoamdli8VPm6H+IyTX2uu5Rb3W9hpCOlk9ka05+9hMeVogxo3WTEw00lBfYeAY8+k+blcxdwZVmu4a9/trlvUGlU8iRAVc9QzRQkkXebawYfIKBgldXtSL/5Z588bjveZVgroFw+sdL1pBRFATki5FA+vwtQZZ/gonnNB7Dehb6z9HwLH+fEPGI0BnIICWZKb7Rsev5jDg4TGFCp0B1y7uZ4Ct6ZftEv5FDtQqK+R41Nkbv0OaX/NtKuteSE+EuGNTqiGTIVZUr/16FVD7debTULsDMcgT6+8BOdBzzAw/g9B5GeiyZ1WV69yyDcSfNilQ577hnGF8M4Ewhr2P2pDEhx9orPPwS4DIDVHzlndrNwZbblnUw/ErgOPI+PZEMpHyiiutY6cm0x2JyTCwHoZVzjxqkOWgP4Jl82Gsc+KdnoTO53e+39zEVsBPr7nbCT+Tfr5V9niKXxzE/8wCBVtnYuacNDT9bITWe7aJf0FceG3YjnDnzF7QyZY0ikcq+bxnSUK7oWozxEkEKZZ+fbDFCxtSDTX2a+Xi8AoQzsuRLkIsiPep/dAgXestwFCRoWpaUIi1k5vkTpIucIewtWgDJrJJHzYHbtcrhntTXL9DeFgK8vkmNqMFM1f/pxEASnIa0Kqudyi4M+oClXtrlUvuxWrrSHzjxCrHgyaMLUqCNcJ7eVJnqXc93LKFMv+LiB9Znxr5CziRzLwJ5Ca4gTkS/Us22Q+R2Xm0drXlyEAoJUz7WjGz45N+eBh9B0is9qj+JFQ09GsK+VQj8KIwyJKzwNA34euZ1Rmg54Bjlx0fm7WBe02dlwPqIEdqW/vhIyAVvyKUXmcLlGfih0ic5dLC7RqYQVy75kmr74Z6W04hwg0DUGfThRz76Ry+otrrq2Qii2iqhzmj8uIG6jKUY9EW75EgC+6OIDFVo+pTZtAsSPbWlgOgD9kg= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2024 16:14:12.2170 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5cf5650c-461c-4db5-a70f-08dd1eb5d842 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000209.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB7088 The intermediate hash values generated during an update task were handled incorrectly in the driver. The values have a defined format for each algorithm. Copying and pasting from the HASH_RESULT register balantly would not work for all the supported algorithms. This incorrect handling causes failures when there is a context switch between multiple operations. To handle the expected format correctly, add a separate buffer for storing the intermediate results for each request. Remove the previous copy/paste functions which read/wrote to the registers directly. Instead configure the hardware to get the intermediate result copied to the buffer and use host1x path to restore the intermediate hash results. Fixes: 0880bb3b00c8 ("crypto: tegra - Add Tegra Security Engine driver") Signed-off-by: Akhil R --- drivers/crypto/tegra/tegra-se-hash.c | 151 +++++++++++++++++---------- drivers/crypto/tegra/tegra-se.h | 1 + 2 files changed, 99 insertions(+), 53 deletions(-) diff --git a/drivers/crypto/tegra/tegra-se-hash.c b/drivers/crypto/tegra/tegra-se-hash.c index 07e4c7320ec8..407ed696a770 100644 --- a/drivers/crypto/tegra/tegra-se-hash.c +++ b/drivers/crypto/tegra/tegra-se-hash.c @@ -34,6 +34,7 @@ struct tegra_sha_reqctx { struct tegra_se_datbuf datbuf; struct tegra_se_datbuf residue; struct tegra_se_datbuf digest; + struct tegra_se_datbuf intr_res; unsigned int alg; unsigned int config; unsigned int total_len; @@ -211,11 +212,64 @@ static int tegra_sha_fallback_export(struct ahash_request *req, void *out) return crypto_ahash_export(&rctx->fallback_req, out); } -static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr, +static int tegra_se_insert_hash_result(struct tegra_sha_ctx *ctx, u32 *cpuvaddr, struct tegra_sha_reqctx *rctx) { + u32 *res = (u32 *)rctx->intr_res.buf; + int i = 0, j, idx; + + cpuvaddr[i++] = 0; + cpuvaddr[i++] = host1x_opcode_setpayload(HASH_RESULT_REG_COUNT); + cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_HASH_RESULT); + + for (j = 0; j < HASH_RESULT_REG_COUNT; j++) { + int idx = j; + + /* + * The initial, intermediate and final hash value of SHA-384, SHA-512 + * in SHA_HASH_RESULT registers follow the below layout of bytes. + * + * +---------------+------------+ + * | HASH_RESULT_0 | B4...B7 | + * +---------------+------------+ + * | HASH_RESULT_1 | B0...B3 | + * +---------------+------------+ + * | HASH_RESULT_2 | B12...B15 | + * +---------------+------------+ + * | HASH_RESULT_3 | B8...B11 | + * +---------------+------------+ + * | ...... | + * +---------------+------------+ + * | HASH_RESULT_14| B60...B63 | + * +---------------+------------+ + * | HASH_RESULT_15| B56...B59 | + * +---------------+------------+ + * + */ + if (ctx->alg == SE_ALG_SHA384 || ctx->alg == SE_ALG_SHA512) + idx = (j % 2)? j - 1: j + 1; + + /* For SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 the initial + * intermediate and final hash value when stored in + * SHA_HASH_RESULT registers, the byte order is NOT in + * little-endian. + */ + if (ctx->alg <= SE_ALG_SHA512) + cpuvaddr[i++] = be32_to_cpu(res[idx]); + else + cpuvaddr[i++] = res[idx]; + } + + return i; +} + + +static int tegra_sha_prep_cmd(struct tegra_sha_ctx *ctx, u32 *cpuvaddr, + struct tegra_sha_reqctx *rctx) +{ + struct tegra_se *se = ctx->se; u64 msg_len, msg_left; - int i = 0; + int i = 0, j; msg_len = rctx->total_len * 8; msg_left = rctx->datbuf.size * 8; @@ -241,7 +295,7 @@ static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr, cpuvaddr[i++] = upper_32_bits(msg_left); cpuvaddr[i++] = 0; cpuvaddr[i++] = 0; - cpuvaddr[i++] = host1x_opcode_setpayload(6); + cpuvaddr[i++] = host1x_opcode_setpayload(2); cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_CFG); cpuvaddr[i++] = rctx->config; @@ -249,15 +303,29 @@ static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr, cpuvaddr[i++] = SE_SHA_TASK_HASH_INIT; rctx->task &= ~SHA_FIRST; } else { - cpuvaddr[i++] = 0; + /* + * If it isn't the first task, program the HASH_RESULT register + * with the intermediate result from the previous task + */ + i += tegra_se_insert_hash_result(ctx, cpuvaddr + i, rctx); } + cpuvaddr[i++] = host1x_opcode_setpayload(4); + cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_IN_ADDR); cpuvaddr[i++] = rctx->datbuf.addr; cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->datbuf.addr)) | SE_ADDR_HI_SZ(rctx->datbuf.size)); - cpuvaddr[i++] = rctx->digest.addr; - cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->digest.addr)) | - SE_ADDR_HI_SZ(rctx->digest.size)); + + if (rctx->task & SHA_UPDATE) { + cpuvaddr[i++] = rctx->intr_res.addr; + cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->intr_res.addr)) | + SE_ADDR_HI_SZ(rctx->intr_res.size)); + } else { + cpuvaddr[i++] = rctx->digest.addr; + cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->digest.addr)) | + SE_ADDR_HI_SZ(rctx->digest.size)); + } + if (rctx->key_id) { cpuvaddr[i++] = host1x_opcode_setpayload(1); cpuvaddr[i++] = se_host1x_opcode_nonincr_w(SE_SHA_CRYPTO_CFG); @@ -266,36 +334,18 @@ static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr, cpuvaddr[i++] = host1x_opcode_setpayload(1); cpuvaddr[i++] = se_host1x_opcode_nonincr_w(SE_SHA_OPERATION); - cpuvaddr[i++] = SE_SHA_OP_WRSTALL | - SE_SHA_OP_START | + cpuvaddr[i++] = SE_SHA_OP_WRSTALL | SE_SHA_OP_START | SE_SHA_OP_LASTBUF; cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1); cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) | host1x_uclass_incr_syncpt_indx_f(se->syncpt_id); - dev_dbg(se->dev, "msg len %llu msg left %llu cfg %#x", - msg_len, msg_left, rctx->config); + dev_dbg(se->dev, "msg len %llu msg left %llu sz %lu cfg %#x", + msg_len, msg_left, rctx->datbuf.size, rctx->config); return i; } -static void tegra_sha_copy_hash_result(struct tegra_se *se, struct tegra_sha_reqctx *rctx) -{ - int i; - - for (i = 0; i < HASH_RESULT_REG_COUNT; i++) - rctx->result[i] = readl(se->base + se->hw->regs->result + (i * 4)); -} - -static void tegra_sha_paste_hash_result(struct tegra_se *se, struct tegra_sha_reqctx *rctx) -{ - int i; - - for (i = 0; i < HASH_RESULT_REG_COUNT; i++) - writel(rctx->result[i], - se->base + se->hw->regs->result + (i * 4)); -} - static int tegra_sha_do_init(struct ahash_request *req) { struct tegra_sha_reqctx *rctx = ahash_request_ctx(req); @@ -325,8 +375,17 @@ static int tegra_sha_do_init(struct ahash_request *req) if (!rctx->residue.buf) goto resbuf_fail; + rctx->intr_res.size = HASH_RESULT_REG_COUNT * 4; + rctx->intr_res.buf = dma_alloc_coherent(se->dev, rctx->intr_res.size, + &rctx->intr_res.addr, GFP_KERNEL); + if (!rctx->intr_res.buf) + goto intr_res_fail; + return 0; +intr_res_fail: + dma_free_coherent(se->dev, rctx->residue.size, rctx->residue.buf, + rctx->residue.addr); resbuf_fail: dma_free_coherent(se->dev, rctx->digest.size, rctx->digest.buf, rctx->digest.addr); @@ -356,7 +415,6 @@ static int tegra_sha_do_update(struct ahash_request *req) rctx->src_sg = req->src; rctx->datbuf.size = (req->nbytes + rctx->residue.size) - nresidue; - rctx->total_len += rctx->datbuf.size; /* * If nbytes are less than a block size, copy it residue and @@ -365,12 +423,12 @@ static int tegra_sha_do_update(struct ahash_request *req) if (nblks < 1) { scatterwalk_map_and_copy(rctx->residue.buf + rctx->residue.size, rctx->src_sg, 0, req->nbytes, 0); - rctx->residue.size += req->nbytes; + return 0; } - rctx->datbuf.buf = dma_alloc_coherent(ctx->se->dev, rctx->datbuf.size, + rctx->datbuf.buf = dma_alloc_coherent(se->dev, rctx->datbuf.size, &rctx->datbuf.addr, GFP_KERNEL); if (!rctx->datbuf.buf) return -ENOMEM; @@ -387,31 +445,15 @@ static int tegra_sha_do_update(struct ahash_request *req) /* Update residue value with the residue after current block */ rctx->residue.size = nresidue; + rctx->total_len += rctx->datbuf.size; rctx->config = tegra_sha_get_config(rctx->alg) | - SE_SHA_DST_HASH_REG; - - /* - * If this is not the first 'update' call, paste the previous copied - * intermediate results to the registers so that it gets picked up. - * This is to support the import/export functionality. - */ - if (!(rctx->task & SHA_FIRST)) - tegra_sha_paste_hash_result(se, rctx); - - size = tegra_sha_prep_cmd(se, cpuvaddr, rctx); + SE_SHA_DST_MEMORY; + size = tegra_sha_prep_cmd(ctx, cpuvaddr, rctx); ret = tegra_se_host1x_submit(se, se->cmdbuf, size); - /* - * If this is not the final update, copy the intermediate results - * from the registers so that it can be used in the next 'update' - * call. This is to support the import/export functionality. - */ - if (!(rctx->task & SHA_FINAL)) - tegra_sha_copy_hash_result(se, rctx); - - dma_free_coherent(ctx->se->dev, rctx->datbuf.size, + dma_free_coherent(se->dev, rctx->datbuf.size, rctx->datbuf.buf, rctx->datbuf.addr); return ret; @@ -443,8 +485,7 @@ static int tegra_sha_do_final(struct ahash_request *req) rctx->config = tegra_sha_get_config(rctx->alg) | SE_SHA_DST_MEMORY; - size = tegra_sha_prep_cmd(se, cpuvaddr, rctx); - + size = tegra_sha_prep_cmd(ctx, cpuvaddr, rctx); ret = tegra_se_host1x_submit(se, se->cmdbuf, size); if (ret) goto out; @@ -461,6 +502,10 @@ static int tegra_sha_do_final(struct ahash_request *req) rctx->residue.buf, rctx->residue.addr); dma_free_coherent(se->dev, rctx->digest.size, rctx->digest.buf, rctx->digest.addr); + + dma_free_coherent(se->dev, rctx->intr_res.size, rctx->intr_res.buf, + rctx->intr_res.addr); + return ret; } diff --git a/drivers/crypto/tegra/tegra-se.h b/drivers/crypto/tegra/tegra-se.h index e1ec37bfb80a..0f5bcf27358b 100644 --- a/drivers/crypto/tegra/tegra-se.h +++ b/drivers/crypto/tegra/tegra-se.h @@ -24,6 +24,7 @@ #define SE_STREAM_ID 0x90 #define SE_SHA_CFG 0x4004 +#define SE_SHA_IN_ADDR 0x400c #define SE_SHA_KEY_ADDR 0x4094 #define SE_SHA_KEY_DATA 0x4098 #define SE_SHA_KEYMANIFEST 0x409c From patchwork Tue Dec 17 16:12:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 851497 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2069.outbound.protection.outlook.com [40.107.243.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E05A1F75A6; Tue, 17 Dec 2024 16:15:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.69 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734452104; cv=fail; b=FWvcefKW4bELzxsz5GF0xNUErDXBwHqi2sY3bEtlkUF1GRqB3BWQDkAX2Sajvj57Kk+2dWdxjxvGfUCrpi9DHPKgJgallrjditu6swuaP0nioNtOlac1yf6wLkuF6/T5zG47vmki5AOLPmf5APHiooyJ8Tc8+Qze/PkxOOTI4Tg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734452104; c=relaxed/simple; bh=qayZfjSgSUxtt1LUEtrQbN2GT+bHE/gUM8InuUl4taM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rG7QexoiogAKCjumd95qtjZRyR5yXpPRzL1y76FI1DC6FfgYonlrkf3gO4yAXL+VpEUNjrO45tBL/xaSdbhfgreacam3nRbP3WvY3/K0x0Zt82Yg7F63UHDOMdYrtr4EKNmTszRc3RiOuxh4aF5PE0JuR3a8ywLJ1WDJSUgc18s= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Mvy8V9M5; arc=fail smtp.client-ip=40.107.243.69 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Mvy8V9M5" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=gj+F3+ecPVBfAggk1FbHheqS+unj7mcJtDGeil+hB0rlcAl1/Zx4LbdWKbFB353ScPeaqE5IITOK/rO3CcIlUJEfnufBrRpGTNElxHULQ/9urOWLJyuBDG+x+pvGZisLVdYQmcNOUAs1o/KaxnIZop74V7NWqigCdlsydqHxE1YSGrO3CZ1C0CSmRS9xcdqqkIMSe9OvSqx8hteQoqDes9K2FQiBnYUQsRSdRcvCAxf99rBxBr/UcIEr3Lb4QrXc69KoPqUU0zaEEWrfBL273FhuMTPVOdwRVWt5JbP0cun0gi/SrMsE9T7n083xKEygNddVmbQIYsepQcv5TvZfHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=u4pAzyuq35YI7++gb63pUwYIywZttwbekA5LiKoUJkY=; b=GA/7qrsYPqhmZzOlk/gu9m5MvHAzq6Hy6fknsWATIQbKFp6buUSKOFC1fgJa1EM7Rb+O5i4y23IjGXq2vUIYCizDhCo+L97BjsiQgwF21ZHdNQrriK4VHUCWzgxgDjWV67DMQpfqDC/uyv5z9hSo9IBk82Yb7puG4csIpYEMf9Y08cZe1N2kIuUdQ5zXmfO0vNXiI9V/FegZkxzZA1cQAJTZJbiDj77Ntt7n/sKDbTqW3T+o0g+3w94LJEqnGyeRlG1aTJiznNWOWMod9yXaqineLziBPR7DgFbB5htScnmoVM4rez0j6kPNDdOfbTIdJgIDgSLInIzVbU9qhVsZEg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=gondor.apana.org.au smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=u4pAzyuq35YI7++gb63pUwYIywZttwbekA5LiKoUJkY=; b=Mvy8V9M5BQ87iHc6RLXhy0Ha2o1RxxrkDrm0NF0vreWFlGXd+RXZtTck8hVTVIL+kGTA6gCswS15RSh32LrYPfNMuJRjQRE2O1m5ZjkFZDoTVxoC5aQHaDkgJi7I/5iRQ05pTX1fUIXKku1n/UmvM4jLE3P4K+3nQFvfAq8B5q3ohN3ga3kcrbyLNzarf55zwEA9/jDGthEhBfTcc2kqrBSMUQ4ObTudDSxVWyMNKl2bmMP+mb6fRY3haswG8l1IgtDyLYxGZxHHfm6xgrm9fHIKqQ0JfCMrCN2la091To/NZW8tJH/DG+SV8dw7RRfCwQeHeoD6J/C1jbY4NMj0Pw== Received: from PH7PR13CA0014.namprd13.prod.outlook.com (2603:10b6:510:174::28) by SJ0PR12MB8616.namprd12.prod.outlook.com (2603:10b6:a03:485::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8251.21; Tue, 17 Dec 2024 16:14:57 +0000 Received: from SJ5PEPF00000209.namprd05.prod.outlook.com (2603:10b6:510:174:cafe::1f) by PH7PR13CA0014.outlook.office365.com (2603:10b6:510:174::28) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8272.10 via Frontend Transport; Tue, 17 Dec 2024 16:14:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SJ5PEPF00000209.mail.protection.outlook.com (10.167.244.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8251.15 via Frontend Transport; Tue, 17 Dec 2024 16:14:56 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 17 Dec 2024 08:14:35 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 17 Dec 2024 08:14:34 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 17 Dec 2024 08:14:32 -0800 From: Akhil R To: , , , , , , CC: Subject: [PATCH 7/7] crypto: tegra: Set IV to NULL explicitly for AES ECB Date: Tue, 17 Dec 2024 21:42:07 +0530 Message-ID: <20241217161207.72921-8-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20241217161207.72921-1-akhilrajeev@nvidia.com> References: <20241217161207.72921-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000209:EE_|SJ0PR12MB8616:EE_ X-MS-Office365-Filtering-Correlation-Id: 818f5eb3-8ccc-424f-2099-08dd1eb5f2e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: YzCr3yuyluccZ3e7lwDSxRc7AqnB83kxwOh+26ZPgxkFhXzt8bwWFQdSy3PyT6Q0ApLZNzOYpbsgw5pg9X+pJUX761B7FYxSMGhUZajOs0UWK6yXKsp4zaAQOMvYpZV3HHbN77Yk+1C1YANnYGhlgJmjBxlqEyiZe+n+8Q5wCnxDSsGmUcQ6ahtHQRvfyOATWuKkTgF6C3w9l+6XXFdLCqczj5aQ2agqWQBZN672bKeMzsbLKLcKCKZ2OsK3PHSGRzcKPyB+AKoCZNf6k7TUMuHy7vmK/wjQzKmftoGWaxNVhUjSvF7h76T1IVky7CWI5GmOzIHjbLy9aKiAaqvbZPMyQ8R+/lK3RpLcr/0DAZSMrMEv/nac+GB4fmI39pXK+OdxsAwaNHEsfwyGYrW88pIlGbd3NLF4bNWKRaYbB+NvoKWyad3g0AdkGMjWt3L6SarE90keV/yp+sNoTHW/mXaGFvxhG9m8Yhzq5EJij02Tnq85hjAKbPwuNPHKN2Lu8RjqmPamDMF4fApydpUtpIYc4u30VOsWClRXNuFYHN3sG5NNtHYCsOWiQPNa3OLgrzCu12Ocu1uYRdfoSutUGLSSmXI8Xi+E0oCjoggx6/JP93/jJkVRKHfDKp4fr66tuUTd8wmAkCV8TI75hT0CVkSDj419e69rtaqA7BRMejik6kL5flBeigkhA12vNKLyg2N9cu3VHtYYMkshZeklsQS4/Baf53rN+ykCa54NNsxq4iBIbrstdxbpnmH7UqJ9ZmpJ05hmC6GakkSA/jkywTK9pre3rwf6Ud8THvNgTaLXgKc9GPwcoM+h0TjvX0XsFOYoxx7PBqknmF99JRd6Ij9tC6dH4DAx4+5xOFY1l5LStRv9zIjpP7g+5V5OI+fuDMy+yab2xL3ucBHGodNPj0qsB+FkYfExx4iQleZ6Hhxd0EIK8Te+n2oaIytMggYfF2TQFN1hjx5HpL4WDyN7VCO/mdLpora+S9DElBGeC3S45QPNOA4eQr9AAxvr+PvPRaeZWNKgo5BjDa8Un3rb1Rwoaev0VNDeDGLiLjmp7YYc/dYV+xksXauvhhRLYXTSwTWnwdv8asKUDLEO5oJI3k/AEOLqw2HfKhGpJazLBUfxO6o0gX9nh4o1mH7SpGU0JetTtBXDISmqf3qM9axbB+3efDFf8L1/waBrLfyUbE0W7ncAeMF+OCkRd1huFz2umfKk7fJi5CjK+ksIlMS9nFmCEg+a0UbhGjGIJaCKcZhqtnRzkks/bDIdp18mzJCuUoDUnClBvWDWh1h+TbVz4DpXMRjJY8gsg4b4QQwdS+fLNYvPM8PS4OyEGew6eusskmoTLDnJqNeNHhq9HyWjFC1fDvQYqX/t0ejl27xwIcW0pGV3mUvzHReBwjAgC3CdjACsAgGB/tQt1aIm/t3MhgYQJ9WL1HOpNYjiGG6X56P45cfQMYmEI2Wr0O1ut/3fnBbqI5xMRcAoyDHh3f1J9jmDFdC3/potCG/zMmjRHRA= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2024 16:14:56.8738 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 818f5eb3-8ccc-424f-2099-08dd1eb5f2e3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000209.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8616 It may happen that the variable req->iv may have stale values or zero sized buffer by default and may end up getting used during encryption/decryption. This inturn may corrupt the results or break the operation. Set the req->iv variable to NULL explicitly for algorithms like AES-ECB where IV is not used. Fixes: 0880bb3b00c8 ("crypto: tegra - Add Tegra Security Engine driver") Signed-off-by: Akhil R --- drivers/crypto/tegra/tegra-se-aes.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/crypto/tegra/tegra-se-aes.c b/drivers/crypto/tegra/tegra-se-aes.c index cdcf05e235ca..be0a0b51f5a5 100644 --- a/drivers/crypto/tegra/tegra-se-aes.c +++ b/drivers/crypto/tegra/tegra-se-aes.c @@ -443,6 +443,9 @@ static int tegra_aes_crypt(struct skcipher_request *req, bool encrypt) if (!req->cryptlen) return 0; + if (ctx->alg == SE_ALG_ECB) + req->iv = NULL; + rctx->encrypt = encrypt; rctx->config = tegra234_aes_cfg(ctx->alg, encrypt); rctx->crypto_config = tegra234_aes_crypto_cfg(ctx->alg, encrypt);