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Tue, 24 Dec 2024 02:17:11 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:00 +0200 Subject: [PATCH v3 01/21] arm64: dts: qcom: msm8916: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-1-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: f4fb6aeafaaa ("arm64: dts: qcom: msm8916: Add fixed rate on-board oscillators") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 5e558bcc9d87893486352e5e211f131d4a1f67e5..8f35c9af18782aa1da7089988692e6588c4b7c5d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -125,7 +125,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <32764>; }; }; From patchwork Tue Dec 24 10:17:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853506 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F2951B6CF8 for ; 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Tue, 24 Dec 2024 02:17:14 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:14 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:01 +0200 Subject: [PATCH v3 02/21] arm64: dts: qcom: msm8939: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-2-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 61550c6c156c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 7a6f1eeaa3fc438f7b6c1d3b2dd17fb1b6f81d9a..7cd5660de1b33def5b9dc8a0d02583c3eaffb17f 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -34,7 +34,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <32764>; }; }; From patchwork Tue Dec 24 10:17:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853296 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8B791BD014 for ; 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Tue, 24 Dec 2024 02:17:16 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:15 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:02 +0200 Subject: [PATCH v3 03/21] arm64: dts: qcom: msm8994: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-3-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: feeaf56ac78d ("arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 1acb0f159511996db07bc7543cf4f194a4ebd0fa..e6c6582ce1eab5bb6831d3458861d0d68c056316 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -34,7 +34,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <32764>; clock-output-names = "sleep_clk"; }; }; From patchwork Tue Dec 24 10:17:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853505 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5917D1C3023 for ; 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Tue, 24 Dec 2024 02:17:19 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:18 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:03 +0200 Subject: [PATCH v3 04/21] arm64: dts: qcom: qcs404: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-4-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=910; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=rR33tk4iShQizxX1vNrKanPGs6fsj3vgKiMhLvDMp+M=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnaoog3M3tf/lRnSZbZqYVXGhcJ9Mz4IIqFzU/2 yvOKOtFgUGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ2qKIAAKCRCLPIo+Aiko 1aHIB/92B7+zTKkPhCZGUgVU9bp3zlKJ6Y89KZJam7RR3HqsFXnbCN6mxbAcP8WwGFI0bU599aq tHOP55sigjWQ7Rg1AS4x4XffLpDy8rhEqaKCsWy9/iyiZWK/DZs/FGIUf6Dw0wt40fUmdgj8+1E Yga21quoiQbtMdjZLitZavhVPS2KjQYLtpEJ1//iTBUvF9mutXT9YORJX9boR+Pyw6l1aX7zO/D 13JXojC4YTynRvdbDvXWutWziFjbI4PTXNsHnuXLJqKkevF4Mf1tCew3zL+HeGaUap1Mf/mTA9G hXGkM/dY3MCHpappNoCGt0ehMmBYz8UZ1pOoHCOh93JRyKe6 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The QCS40x platforms use PMS405 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9181bb939984 ("arm64: dts: qcom: Add SDX75 platform and IDP board support") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 215ba146207afd25128692781926cf1964743655..2862474f33b0eab7c42fa2b22006f580c567ad2e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -28,7 +28,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <32764>; }; }; From patchwork Tue Dec 24 10:17:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853295 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65A1A1C5482 for ; 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Tue, 24 Dec 2024 02:17:21 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:20 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:04 +0200 Subject: [PATCH v3 05/21] arm64: dts: qcom: q[dr]u1000: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-5-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: d1f2cfe2f669 ("arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 2 +- arch/arm64/boot/dts/qcom/qru1000-idp.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts index e65305f8136c886c076bd9603b48aadedf59730a..c73eda75faf8206181764df4d1ea32f96c9cfcd0 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -31,7 +31,7 @@ xo_board: xo-board-clk { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts index 1c781d9e24cf4d4f45380860c6d89c21e8df9925..52ce51e56e2fdc51c05fb637ed4b1922801ff94b 100644 --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -31,7 +31,7 @@ xo_board: xo-board-clk { sleep_clk: sleep-clk { compatible = "fixed-clock"; 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According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 8d58a8c0d930 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index a9540e92d3e6fc314fa91d4f055325680233f6c4..d8d4cff7d5abed405d1b4cdf9ab8264aab076830 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -545,7 +545,7 @@ can@0 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &tlmm { From patchwork Tue Dec 24 10:17:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853294 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B89941D7989 for ; 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Tue, 24 Dec 2024 02:17:26 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:25 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:06 +0200 Subject: [PATCH v3 07/21] arm64: dts: qcom: sar2130p: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-7-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=916; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=YYLN/oY9BZAxpdyRliEHDR3RyIM74cdws5RTMVCcPsE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnaoohcsqRBxIiSMe0tXJAOEA5JoOuex+QjvcVR 8imu34jSl+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ2qKIQAKCRCLPIo+Aiko 1SazB/4yKbXQEhC8CGTyOkeGZW7xU+iAW9vvGrQmYDkmLcLyLLEWT4+Mrf9uR5HXvasVNN4BMv8 2zIGplebR0U4PX7DhTfpzObIOpmV9ijaExzMiy6NfPT5F22twcHJWXp/yBp5XrWwKqeXiFhu3f8 dc34dd4lKojUx+0WlBtpCWb7+1REEDxZlyfgStTb5kc1Zux7k83EBwyzWrNEQxojWrlDq7Ftl7e hY+XVi2H5GrPay+czIJHCquc8v/JSLjp3yjj7gv7pV2J4/+02TD4kTY49nmt0Qv1gVA5rNiCqZO lFKq7i/SoQ7ZjRxVQs/RGtWKEr1WafulYWUlVvgyIDwXs4xh X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SAR2130P platform uses PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: be9115bfe5bf ("arm64: dts: qcom: sar2130p: add support for SAR2130P") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index 56f40e8ecae561d49331e51c57581d517dbc9b51..dd832e6816be85817fd1ecc853f8d4c800826bc4 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -37,7 +37,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32000>; + clock-frequency = <32764>; }; }; From patchwork Tue Dec 24 10:17:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853503 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 171CC1D86DC for ; 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Tue, 24 Dec 2024 02:17:29 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:28 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:07 +0200 Subject: [PATCH v3 08/21] arm64: dts: qcom: sc7280: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-8-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=918; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=cwHGT8dW2fufdVjeg8a7nAT+ERCmV5CuNqJS2eXbLFY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnaoohcejC0Gu9WRhXVQyWuYKALbscr5UzIWu2u sC62DiLymGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ2qKIQAKCRCLPIo+Aiko 1WJ2B/97jXYhWoXtKYMLcFjuNVqxe9zbyRK9JLpmzKHwkZPUc3NF/1XtyOKP4gc+9x3zHWpA95R XHHw7Z6/ObFTVWErTGdDzWxmOCf3cixZv9IYfcAlgrGHAs9nEBb1l9Piq10n0qYw9On/PxB+1cj EdCKFabvZ9ca+poeBWzsmW1sZizK0ZqG3gXoFmybD9jBux7pTMhTrlkcrEgelrDAevJWKxyp0iF oZumsxkG0uerUXRpCqcFJE+NN+6qka8yHVSetFw9ymKLD4hqLexlVhuvIYmcFdpJucKgeHphW2w eORNYSJLh73EoSDGBlKQc5ij8LnzaFBoxad4zM8BSlmZqRph X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SC7280 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 7a1f4e7f740d ("arm64: dts: qcom: sc7280: Add basic dts/dtsi files for sc7280 soc") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 55db1c83ef5517f82504816baeee583695065225..d12e0a63fd087461a33622e8771422c8acfdbc25 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -83,7 +83,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; From patchwork Tue Dec 24 10:17:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853293 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEDA11D90BE for ; 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Tue, 24 Dec 2024 02:17:31 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:30 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:08 +0200 Subject: [PATCH v3 09/21] arm64: dts: qcom: sdx75: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-9-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=905; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=uDWgj6B6z6pMSFBL1pDRW22fgNDuN+DRFtZx84ZsB8Q=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnaoohP7h7cVtctxfPbj16fMwxaYEJ9+KmTDopH Hz5PDWg04uJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ2qKIQAKCRCLPIo+Aiko 1ZGRB/9DjghrTVvnNixgMSDWg3D+uqLGChXSkcNOrjhQ0OKlYH0TRaX8xbW35/u4NOYe3FN4+Im zrCE5ZxzvTPy2O2+NuHHss7W8X+qSG8Pr2ZcoZzlE/wW+nwl2Ecui97DxNSzCzOTOHZ1zJkOgXO uu22n2tWy8zQlrtZHQJPuFu3/gS9/SMjV+XD3wQ4L6Mkhtzbuen1caMIz+Gklm6erpaUp25YJ5a wZQeSCVPYdgeDfj3jLhBAv9R2Znui3VMkIZxKCuDo/mfhhEYld1jjSqBI5nmgIM4s7/YFr2hFXI NfdjmjMUZ9kNhHiXhXrGxZdyf/qvGXTZZiltQMJ9ovUMJkx7 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SDX75 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9181bb939984 ("arm64: dts: qcom: Add SDX75 platform and IDP board support") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 5f7e59ecf1ca6298cb252ee0654bc7eaeefbd303..68d7dbe037b6ac49c746171e8dabd416c8813a38 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -34,7 +34,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; From patchwork Tue Dec 24 10:17:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853502 Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 492C91D86E6 for ; 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Tue, 24 Dec 2024 02:17:34 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:33 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:09 +0200 Subject: [PATCH v3 10/21] arm64: dts: qcom: sm4450: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-10-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=888; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=o/j8/+TO8OD48smfSUKUdOz/ApCt6Naf9bzdvgRGXWo=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ3pWlyJ/0Y6/KU+eet3Pe3VzyomWjZKpJ9O/3PznI7ldS ZFlm6lGJ6MxCwMjF4OsmCKLT0HL1JhNyWEfdkythxnEygQyhYGLUwAmEpTM/t/3jOMPZotf7s7X DC5s2zFN73LTilCFpGRriatnCh3ntl8LE68MYDtRLBcSO40vT737wrH+kytyG+MXR3UpT215sfa C8N40YT5WtWWaYnWNTx8L3FNYqnm4caPX2Vz5h3NUHu2VdlEP9yiWT/Fr3jrx1fflJjlCnWk/W6 wm+9w5+evn5Nm8f/cVWVSc4GzbJtXwzyJQ78jKUoEzk9Z0Hcg/WKC5UVqpUV38UP3CQ2I6F+4dW d2yJuiDYfprc/0IRqPi9pWu3ZrHp8ZJhhgvC5yYtzZj1rStO/jS6l26EhxPp+qqW+WUsn2zf/ax 5GZQxtyTOvqmQr2m/d/qF0wP+5a1+k/MhZAK44j2vSLPAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM4450 platform uses PM4450 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 7a1fd03e7410 ("arm64: dts: qcom: Adds base SM4450 DTSI") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm4450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index a0de5fe16faae5674efb0070d4017983c86603c4..27453771aa68a1c4dbd2a986af6785fa05db147d 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -29,7 +29,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; From patchwork Tue Dec 24 10:17:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853292 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD8E81D95A9 for ; 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Tue, 24 Dec 2024 02:17:36 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:35 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:10 +0200 Subject: [PATCH v3 11/21] arm64: dts: qcom: sm6125: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-11-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=928; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=q3UE0E2mDZCC929aI9do16YaC9c3UMVZhi0tXk/GPcs=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnaoohaSeH0eCgk1LpCGycJR3dezjhfMQyqDnwX /Gdqsr4IBSJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ2qKIQAKCRCLPIo+Aiko 1fxICACl/LqbVvlbE5s56U6Vwtw+gkpp+S6Z1sHAaGAj1SJ5J/Vl1hgYtgk/7vgO8wPsIShgnti zgva+P8apKkkJjOnWFFHmW0kxKbUTES/GXsqw3TIX2ETlD8+jjFT5/XHLVTjTFfL3ALxhbL5kyI TG6TzD4A6qjVQctoOCspSFA2384bRPV5g6QTiutZTgy8nlVfiK5V1S0bVHkYbmHfa5x60FCmA/G ZzMGItKMP4UAbegOGNJO08Q7rURJchUwiSGZW3z2GZ2um7zJr8Zm21Go4ZT1n0oXre3CFsAo7xZ WLo+5xnJtYoZ5/k7KTcDfpwXqa0mlvSbGInRRtXtPGqhsLa1 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM6125 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 17d528d639343b9d649167d231aad3aa63474435..f3f207dcac84fa2f72fa9222c26ab3d7fe8813b2 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -28,7 +28,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32000>; + clock-frequency = <32764>; clock-output-names = "sleep_clk"; }; }; From patchwork Tue Dec 24 10:17:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853501 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44B9B1DB360 for ; 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Tue, 24 Dec 2024 02:17:39 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:38 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:11 +0200 Subject: [PATCH v3 12/21] arm64: dts: qcom: sm6375: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-12-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=912; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=pg+0ixud7QxxrDakgimvHJR2/Qzsae3oMGYCum0sTmc=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnaooiuTqTnxaWWhR1X9lZBW6mQzWv7XY2rb4P6 pyIdLC+vl+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ2qKIgAKCRCLPIo+Aiko 1ckMB/0YmaGqWVXY///07eZg/fXcotYFcjfNsru0BqNeJd2W6uGW13/pPozbvv4rrsxx/Dystxg gMT/1hBbMRiMEbAwFO9NEItjlNH3D+B7Nb6ulZSC+t3Qw7r9HKY9pkt4mfTaMtQW2/u1ISRV4MU /XUcgM9Z65PsvgC+L7Xr5FJre6eC/oIASmd8mB9yhaH28y8mSh+CmeShQrhvKqjHkEoT+7MrF9h Vtid7q1tSlZFAp7dFaMZ/nX2kbEYvFrZcIagz+CXH40vM1XhVASQWwOYfoCav13azRXUcKW6asB pqHgZQoC4PynSa5y9pjdKL5JZl54hGE+FE7QtJ7wJ7Cdohku X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM6375 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index e0b1c54e98c0e8d244b5f658eaee2af5001c3855..7c929168ed0805e832b818516083d48968d3bbce 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -29,7 +29,7 @@ xo_board_clk: xo-board-clk { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; From patchwork Tue Dec 24 10:17:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853291 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C87B31DC98B for ; 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Tue, 24 Dec 2024 02:17:42 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:40 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:12 +0200 Subject: [PATCH v3 13/21] arm64: dts: qcom: sm8250: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-13-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=920; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=t0rQXPrtoBaJrNoELAVHdj8ug8kB5TUw+I/NzNZW0co=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnaooi9ABuF6/gcvJtVneJJwiTskffxsrfuO9Cp skgPBE5yeKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ2qKIgAKCRCLPIo+Aiko 1fbFB/0eBVRT6Wzute2kVUQ5AQ61H09fKYyRVWO/htIufrooKRmjXOwG/4UvsXtdgqfU8mfZ1Ab wgb2UYdRG6WBJvNgYGfjDRlk05uxYYB2gwzEqQkBUXLV08HhgCt+jyYCWYCSdH7HGLIQ6BC8snR 10mZBEUnqWiidmPygj4yHEtaBDL5m1YPNN+iVBnMFB/maA0+aB4966pqV7CljpekrFT/iOY+GDX jeCM3HHCU+SH8y5HzGFsqYS/wEHdoBX+NydR1q4czSBNBt7w73P3TFCZbE/8MT6YPWH7Klb+wEg pbc65+7AbDnF9VpbDIF8qj03VhZRgcKZMP6qBYdCdBKpde6P X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM8250 platform uses PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9ff8b0591fcf ("arm64: dts: qcom: sm8250: use the right clock-freqency for sleep-clk") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 48318ed1ce98ab40de75129cb9bdfe32eda4c004..f39318304da8d02ded9bc4ff833bc88139ded744 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -84,7 +84,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32768>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; From patchwork Tue Dec 24 10:17:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853500 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AA701DB349 for ; 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Tue, 24 Dec 2024 02:17:44 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:43 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:13 +0200 Subject: [PATCH v3 14/21] arm64: dts: qcom: sm8350: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-14-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=914; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=zFjg3X4sj0bxnLQr9HZSDlL6zt2ff3hQG2YCOF9/IoY=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ3pWl1Io+9HNc0S73NnTpyQsSU+YeTLM5qLf6vTsKZfff ztSH/Wrk9GYhYGRi0FWTJHFp6Blasym5LAPO6bWwwxiZQKZwsDFKQATScxj/2dzsv2hTgGjicum U2Yv0hg31L2V8r03UXCLaS//hR8zyz19YryU9xU+c8tIn1QpZbOoTPvWvrMPs5gzozM3bVxSoeG yQZg7xLiON21dWNyt19H17JLphz6Ju12NLuIKemgmudzu5RvF0za7xT4/7/IxrODovdD5cYfruc 47Gtf1Dxz322eoHNXP//3o9xT7BIUtPWHTnb/8Uj+TknVnabhA3/32xgXZK6K1WDSnnp3tO0vph Yqvwdz/buuY6x6lfjrZYJV95NQqT4VGAZln1XvM+NgThJjtds/RvLz07MoL9/giZxrffuf+nYPR 0OlLg9/fYJ55SctbDe5slhLwbj4c29q52V2g44J77RxmAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM8350 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 877905dfd861edbcd083e6691a7cfa1279164ffc..15b7f15b3836dc544cb1209ab36df85263d612a1 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -42,7 +42,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; From patchwork Tue Dec 24 10:17:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853290 Received: from mail-lj1-f174.google.com (mail-lj1-f174.google.com [209.85.208.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEB351DDA3B for ; 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Tue, 24 Dec 2024 02:17:47 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:45 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:14 +0200 Subject: [PATCH v3 15/21] arm64: dts: qcom: sm8450: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-15-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=891; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=kRo+lLE1W0MzRHuVjiZ53lpqFjRc/n5gL1+u9Wg23vI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnaooixTzAm2+3LesXsUmVxBlmaXZOhTOM9xqlC ixJHX0EB0KJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ2qKIgAKCRCLPIo+Aiko 1TdmCACA2jicMrBqZ7WsS/9B25FQ4Qp7njiilpcWxdcn05jpiiBjcXYH/n58MMsowXurPW84t1f SqpY9FRGz8QHKhrZUPXvjKFMuHeoQax3RZ7VImKs+ckE3mxAdEK+RIfn5QxqC+AObPqaZ22Rlys 70BKvdxN/afdlC27Up2E8l+/46UGO7LuQOeX3W6GwlLJwssF0x1e706LzuG/pSVxIvQ0JFSZ9rC pT94F1GGAPVD2paqfWe0rDflTMu781deiBMxAaI5mPIfpjkEJI8uOESY7aPJBtY2Sg4lS95ktMX 2WH004A0i3CMI4RjtyMgYirmAJY3FJ/QhlRRHCOtrr5Q02Un X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM8450 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 53147aa6f7e4acb102dd5dee51f0aec164b971c7..7a0b901799bc327b9d31bd84e8a00fd62b451596 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -43,7 +43,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32000>; + clock-frequency = <32764>; }; }; From patchwork Tue Dec 24 10:17:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853499 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61DF71DDC29 for ; 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Tue, 24 Dec 2024 02:17:49 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:48 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:15 +0200 Subject: [PATCH v3 16/21] arm64: dts: qcom: sm8550: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-16-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3849; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=oCnFN08aVITyKXapk9h/eTP1McSoWUQ0a6cbzA6vc4M=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnaooiUvXPsKx64BIcfs0pWTe5GSkIDnkz/PWmH zzTMlifF1iJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ2qKIgAKCRCLPIo+Aiko 1cGoB/oDiW9NQW+6/Pmp0/oVFVtqlGAZSVDJUsxV4prEjK1sZDaqbuocaTfilBifQ5NvR924SPV zkprBuYLzpJEsmiOXPWr8lJ0ng0+84vUr/9nN7mZg0jPsUw+vektwIQ6T/k8b0CoYrZcUmMAEso KKRxcol1SEmo0g97wKQVlNiGErGB9L1CWRzxaJRygotSu4dGe0VHFxmYv2Ez6yR9qLXMx06XGz1 mdHoRAgLovyvsAXu7/sd+CBX0NKziyZptSCcN9mf7dBsSdTWhdItIFuStxQXlGHc8W2EbI+uSiq /42zap/fHFLA9IugRr//muVPfC65uooQ/ellKE32oc0lLufg X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM8550 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 0b12da4e28d8 ("arm64: dts: qcom: add base AIM300 dtsi") Fixes: b5e25ded2721 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board") Fixes: 71342fb91eae ("arm64: dts: qcom: Add base SM8550 MTP dts") Fixes: d228efe88469 ("arm64: dts: qcom: sm8550-qrd: add QRD8550") Fixes: ba2c082a401f ("arm64: dts: qcom: sm8550: Add support for Samsung Galaxy Z Fold5") Fixes: 39c596304e44 ("arm64: dts: qcom: Add SM8550 Xperia 1 V") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index f6960e2d466a26bec4e5c3d31ac0bf54168ca1e5..e6ac529e6b7216ac4b9e10900c5ddc9a06c9011c 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -367,7 +367,7 @@ &pm8550b_eusb2_repeater { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 01c921602605726928bcba71abd937869880ea0d..29bc1ddfc7b25f203c9f3b530610e45c44ae4fb2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1172,7 +1172,7 @@ &sdhc_2 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index ab447fc252f7dd705fbe29725805bc1c146c10f9..5648ab60ba4c4bfaf5baa289969898277ee57cef 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -825,7 +825,7 @@ &sdhc_2 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 6052dd922ec55c65089e6b08e36c355b01bf24fa..3a6cb279130489168f8d20a6e27808647debdb41 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1005,7 +1005,7 @@ &remoteproc_mpss { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index 3c5d8d26704fd925857b5ddcc6067c2b14e1403d..e8383faac576a2f401fff74231a764712c832291 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -565,7 +565,7 @@ &remoteproc_mpss { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 85d487ef80a0be5c3586d9de69327abd2b64209b..d90dc7b37c4a74cbfb03c929646fda3381413084 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -722,7 +722,7 @@ &sdhc_2 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &tlmm { From patchwork Tue Dec 24 10:17:16 2024 Content-Type: text/plain; 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Tue, 24 Dec 2024 02:17:50 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:16 +0200 Subject: [PATCH v3 17/21] arm64: dts: qcom: sm8650: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-17-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1965; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=k6VUs1ScFCdCh+SFXZEEGEWQ1wMPimPue9P3iT/F5+E=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnaooi4JbQ9qoMYHTPz6/B+ss1zW0Z0TZr54dx6 ApifhuCgNqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ2qKIgAKCRCLPIo+Aiko 1aHPB/0fHqSZUYDtdKTHNvB7niV4Y48sLLPWpgxlxEGbqe4AzyPIcNipiJPyUzxGhQ8azo/SudL u3LPKCa4hWKWte720ttZXLwnSczS2QpiGwLrtUqLtiBbaN0XKnNRegp4NGvbWSTpW0EV6K51E5Q WmUZ5+LepC14bCNF3Xe+LhSAGdPEF4sObMUbRpNZCj1v/Om7UURpGI5bXxR/V//uXCeKRD9TVjr EsmZYbVlnZT3rtk+rHegHQv6rQTvmUJITaQXMhZw10qhZ7B5Bvha7QhqyMcpEhfJMtRux1pad3t G7eQTyne1qc44aZFpd3yWlbxuIFUuNPSKRyxMwB2RWvnh203 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM8650 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 6fbdb3c1fac7 ("arm64: dts: qcom: sm8650: add initial SM8650 MTP dts") Fixes: a834911d50c1 ("arm64: dts: qcom: sm8650: add initial SM8650 QRD dts") Fixes: 01061441029e ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 2 +- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 2 +- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index f00bdff4280af22f6f8b23e33238f53c602bc169..d0912735b54e5090f9f213c2c9341e03effbbbff 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1113,7 +1113,7 @@ &sdhc_2 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 0db2cb03f252d19a1f8b171a562a8e06290c8a21..76ef43c10f77d8329ccf0a05c9d590a46372315f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -730,7 +730,7 @@ &sdhc_2 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index c5e8c3c2df91a49476f49832c0bd6418f4dfae3d..71033fba21b56bc63620dca3e453c14191739675 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1041,7 +1041,7 @@ &remoteproc_mpss { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &spi4 { From patchwork Tue Dec 24 10:17:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853498 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2A261DE3D1 for ; Tue, 24 Dec 2024 10:17:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 24 Dec 2024 02:17:54 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:53 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:17 +0200 Subject: [PATCH v3 18/21] arm64: dts: qcom: x1e80100: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-18-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=918; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=kWQwXDlbilsYXfDRPCbFZMxqzihzbNYaTbZjWDNNvZM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnaoojuGj4t4y9jz9TfDC1k/UctVHH2b1IkH6tp BapJmLDrvWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ2qKIwAKCRCLPIo+Aiko 1SKaB/0RrC19Nze0nL1jW+BMlXZ0c/AFqzNPuvga5fKWCPm9xIP+yhPL5doAPawCS621faj6q1z E4/UTs1rFnh7kU/TesQupFSZU3FD/VLjbXUU4Q0AUm1o8ZgQX39pSCkTGoByPWM6bfwb7ns26kt 9+PgHQ9bEB/HG4HxGbu/H88E+yWj6GDd0ixoCbdyEjaWVVapwcDzYfF5+vwLGIKzlDmtGX47wP/ FZ587VYL3rXrPzMf162S4YSTFiCFcdskFOJIt8HPCHypsKyfRxY7VkhpZ+ZCEoVL91/hS6RMfaS f4iLi+pxD+tl4mRVsyo0Sqb6fD+qqqdj9bIjYo03/gQ/klY8 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The X1E80100 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index f25e2d3af4a40125360831367830cb3d217883cf..bbc2bb2e9b9b3b5bd22b35a4fca085bfe2965d4a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -38,7 +38,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; From patchwork Tue Dec 24 10:17:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 853288 Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2254F1DE4F8 for ; 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Tue, 24 Dec 2024 02:17:57 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223600596sm1576865e87.92.2024.12.24.02.17.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:17:56 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 24 Dec 2024 12:17:18 +0200 Subject: [PATCH v3 19/21] arm64: dts: qcom: sc8180x: drop extra XO clock frequencies Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-fix-board-clocks-v3-19-e9b08fbeadd3@linaro.org> References: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> In-Reply-To: <20241224-fix-board-clocks-v3-0-e9b08fbeadd3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , Max Chen , Vincent Knecht , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Drop duplicate overrides from Primus and Lenovo Flex 5G DT files. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 4 ---- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 62de4774c556d3954a797287ba2ecb36d979dc9f..21c2d25a294506de41f6e8b7197be85c02d03568 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -681,10 +681,6 @@ &wifi { status = "okay"; }; -&xo_board_clk { - clock-frequency = <38400000>; -}; - /* PINCTRL */ &pmc8180c_gpios { diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 79b4d293ea1e70d68346e7c5458c94f7c2b6f1eb..7a4bd6955470338dd9c7a628c9f9a01de8b480ac 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -773,10 +773,6 @@ &wifi { status = "okay"; }; -&xo_board_clk { - clock-frequency = <38400000>; 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Follow the example of other platforms and move clock definitions to the sdm670.dtsi file. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts | 14 -------------- arch/arm64/boot/dts/qcom/sdm670.dtsi | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index 176b0119fe6d45d7d3fa584f1825f4e4e681c2e7..44b708c8a4e4ef5ee1d9110bba372d230fdd5b4b 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -49,20 +49,6 @@ framebuffer@9c000000 { }; }; - clocks { - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - }; - - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; - }; - gpio-keys { compatible = "gpio-keys"; autorepeat; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index c93dd06c0b7d6444aefd0e24201cea999dcb23a4..c4fd7598d1ca8d8baf4c3da0e20cb191f7883f0a 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -28,6 +28,20 @@ / { chosen { }; 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a=openpgp-sha256; l=2729; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=x2bm9LjU8gDnzSnTK9zY7r1UhakQ0COQvQ8bOcHGsI4=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ3pWl/KXh5Oz0rvu69ybk3Bv5tWTTcLs5/z+v7zC+qfU7 3/A1tXPOhmNWRgYuRhkxRRZfApapsZsSg77sGNqPcwgViaQKQxcnAIwkdjr7P+Tavjfu7oWmrR/ /MQvKhJ9aUO3V0WNv7GggGUp1zoxo2JBnrVx90IW/DnuEOfzdWfps3COlGoXId1N4nYxR1j7Kxb seKb2TTMxLyd7cnYZp6DCZJFXpbkSNWmzhDT48laa7H/zO7dnrZ7BkYd+32e28h3P75EwfcKk+v xB0X2ZsytrGyqOe1sLm4Z9/1FWcffg3fkbZRyEe7J7nI9K7Fd84d9h/GFqspLEb56QnLrzx/7O/ 13oq10+6f1VP7eQK5aXu3l3yKTUbKj9o7rjwjVxXi053+kWis0mXgwtX3cX3vl8+uub7k9JS39W hknKFywqquJi+654LThl7YeIDxECt+XvxGvl/XhoVfoNAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The QDU1000 and QRU1000 devices define XO and clocks completely in the board files, despite qdu1000.dtsi file referencing them directly. Follow the example of other platforms and move clock definitions to the qdu1000.dtsi file. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 14 -------------- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/qru1000-idp.dts | 14 -------------- 3 files changed, 14 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts index c73eda75faf8206181764df4d1ea32f96c9cfcd0..a36a56f03c2d112c6afdae1272b81edff890fca1 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -22,20 +22,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - clocks { - xo_board: xo-board-clk { - compatible = "fixed-clock"; - clock-frequency = <19200000>; - #clock-cells = <0>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32764>; - #clock-cells = <0>; - }; - }; - ppvar_sys: ppvar-sys-regulator { compatible = "regulator-fixed"; regulator-name = "ppvar_sys"; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 47c0dd31aaf2e42d6d85411956207b2509a605b0..30fa8f5f992ff5b440db9871a254b60acddbac94 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -21,6 +21,20 @@ / { chosen: chosen { }; + clocks { + xo_board: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts index 52ce51e56e2fdc51c05fb637ed4b1922801ff94b..f35e3111f516ca1ab59011f8a4145d3e21e0a221 100644 --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -22,20 +22,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - clocks { - xo_board: xo-board-clk { - compatible = "fixed-clock"; - clock-frequency = <19200000>; - #clock-cells = <0>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32764>; - #clock-cells = <0>; - }; - }; - ppvar_sys: ppvar-sys-regulator { compatible = "regulator-fixed"; regulator-name = "ppvar_sys";