From patchwork Thu Dec 26 10:24:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 853714 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7D3614C59B; Thu, 26 Dec 2024 10:25:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735208719; cv=none; b=DnLXRmLkbZ3IJ0TOcJaKPbi7S1IxqwF0+TO7E69/A64DxGhLFEIW+aKr2VvhNyz/zKOW59jFu515nkWkPUvImdvQnyBTruEY/8HgKRmUxAH3+ylWyxEJpXZHiqpmVepSqAGP2z5YorAa1fJqlnoqSJB/Yvih4H3XBeRm4d3Rh9A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735208719; c=relaxed/simple; bh=nSIx8RBTiODPfUfabQPnUu0E3on6iW2OJdomZ5MSg2o=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GdIbJuugM7D7/SG4eCJh5XH1iLwH+7mKiEl/k/lgmE0l+I1IO+r9bBYEWQ8ZHtiW7++Aild8ldtgbwe8V5uS0BOG1dbR3WVoksiWayebePx5wa3gtoUs2g2sKKKlxy9uJuVL+pqwIcJTnKKU6n1WUeR67+/qhh/4pINLYwcX8uQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=of5IrE/+; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="of5IrE/+" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BQ6uFwA005318; Thu, 26 Dec 2024 10:24:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= vG/xGFWLJs/sDNYCDJ+UgTVfpFPnRAO1Xwp3Z1u9Od0=; b=of5IrE/+voHD6uLR ctWACzfGQVWWBMNNkjE6NxLiIZRF/uQWFgJvPZr1qV45UhfctaN/rVtlOTvO2HpK r9PLyhYnML0y3LTClOV4ukLL7iPTcT2HVSp0V5w6pbSxJnGwlnqZboDRvzf3GBQZ O6j+rtCqMEU595KePiPzeiuef3komJaGouBbRynfYOj3PisjYLZ98x1hBX0eJTQG Zn1GpGzDsrx1z0CW8SETBttX8UxnkOqxyGWSUKP3oNwsE2ravs7zMAwN4tJHQOd1 broOCPs74AJBcZd2oOANONS+SOlibIHBXtFv+ws44gFPkZShk/f02aDXWV2pxAHK mKZEBA== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43s2a8sgxr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Dec 2024 10:24:58 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BQAOuwE029750 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Dec 2024 10:24:56 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 26 Dec 2024 02:24:51 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 1/5] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy Date: Thu, 26 Dec 2024 15:54:28 +0530 Message-ID: <20241226102432.3193366-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241226102432.3193366-1-quic_varada@quicinc.com> References: <20241226102432.3193366-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: yWNRHm6DZKQVeHV6F2Z6yGboHkdeeudv X-Proofpoint-ORIG-GUID: yWNRHm6DZKQVeHV6F2Z6yGboHkdeeudv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 priorityscore=1501 malwarescore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412260091 From: Nitheesh Sekar Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332. Signed-off-by: Nitheesh Sekar Signed-off-by: Varadarajan Narayanan --- v4: Remove reset-names as the resets are not used individually Remove clock-output-names as its usage is removed from driver Fix order in the 'required' section v3: Fix compatible string to be similar to other phys and rename file accordingly Fix clocks minItems -> maxItems Change one of the maintainer from Sricharan to Varadarajan v2: Rename the file to match the compatible Drop 'driver' from title Dropped 'clock-names' Fixed 'reset-names' --- .../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml new file mode 100644 index 000000000000..b6b3610ad436 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm UNIPHY PCIe 28LP PHY + +maintainers: + - Nitheesh Sekar + - Varadarajan Narayanan + +description: + PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC + +properties: + compatible: + enum: + - qcom,ipq5332-uniphy-gen3x1-pcie-phy + - qcom,ipq5332-uniphy-gen3x2-pcie-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + resets: + maxItems: 3 + + "#phy-cells": + const: 0 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + - "#phy-cells" + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + + pcie0_phy: phy@4b0000 { + compatible = "qcom,ipq5332-uniphy-gen3x1-pcie-phy"; + reg = <0x004b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; + + #clock-cells = <0>; + + #phy-cells = <0>; + }; From patchwork Thu Dec 26 10:24:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 853713 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C3CB1D5AA5; Thu, 26 Dec 2024 10:25:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735208724; cv=none; b=K1ok5subwHEpFlZU9G+hXP4xNsbH4WkYJ0+Mgw1lIZnEvt/wn3prVrnhvpU8IGwi2QlmqsTtmteelIXhBnxMv6uXZ/YlWgzDZ9U+Ctwndier4IcAgdd0ufD2ogU37nIazwOlfHpgEgIuuALduq0TC7bICLWj+ZJfm0KWoRMlWG8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735208724; c=relaxed/simple; bh=h2HQ9cYOjjtwnfFagM5Q/R8WupQ9pgWYDpk0erNS1DU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=vGdbeISimiDV45T1xv+wYfV5P5Ne1EZS4N045KBnKzd8ASgRbW/Kf1pB9/ETl3tLEwT5rc0rheVNTqXd96ik+YRi93DTM7L5JUXT8qH6BGQTq624r/8Rv0unAJucEKLYJ1wRpdDxpnlb2z47B/40XQmahrKpF7UZvCwu6O1XgOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=cM1LZ6SP; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="cM1LZ6SP" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BQ83hBp022945; Thu, 26 Dec 2024 10:25:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= M3tulqBo8stceLomZuImWVJE0IcBMsWJyfiahu+9toI=; b=cM1LZ6SPndYF6Asx D2Nr6TIFMsOV2bISq7n/dOC7zUJXqH/seq6ZsqUwoBX0g1Z8ZXKCjsnoOHTNJiqM RHjjoLOjk7g9771aXDY/IhqXWtc+SFKBIj1NmmkvzDdvr+WrHwB6IWEAwokHekNS 0sZbxbvmN/e4/nilkeaj3MGiSH+61tsiT7itf5dYD4OIMVpuWapdKma8Ho3vF5tS pzDenLdAOd2z35ILsgIf1NEOFXz8sZVTMtzywQpNsb6Vxrwd4mBfAoiwjFJD6hgO cBktwYwuVyS7XNiEJnEZBDNvPFyZHPJS/Gsu8zfwpwwfC3MOx0Edr4fnnJzC6ZZF qiY7NA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43s3a499kb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Dec 2024 10:25:09 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BQAP85u004388 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Dec 2024 10:25:08 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 26 Dec 2024 02:25:02 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 3/5] dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller Date: Thu, 26 Dec 2024 15:54:30 +0530 Message-ID: <20241226102432.3193366-4-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241226102432.3193366-1-quic_varada@quicinc.com> References: <20241226102432.3193366-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qupw0PX_LL0omkDDRCh-B4D2NCJG_yWr X-Proofpoint-ORIG-GUID: qupw0PX_LL0omkDDRCh-B4D2NCJG_yWr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1015 priorityscore=1501 spamscore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412260091 Document the PCIe controller on IPQ5332 platform. Signed-off-by: Varadarajan Narayanan --- v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332 * DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check and dt_binding_check flag errors. --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index bd87f6b49d68..ac920e435c73 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -165,7 +166,6 @@ allOf: enum: - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 - - qcom,pcie-ipq9574 then: properties: reg: @@ -206,6 +206,8 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5332 + - qcom,pcie-ipq9574 - qcom,pcie-sdx55 then: properties: @@ -407,6 +409,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq9574 then: properties: @@ -555,6 +558,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074 From patchwork Thu Dec 26 10:24:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 853712 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E09651D45EF; Thu, 26 Dec 2024 10:25:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735208738; cv=none; b=hg6AbmESuiY24CIGGhOwpZkrdMS5m3j6f0Ah+pS2tQuMia2fNDU530rA+gYVmNanlnIqpWutgbpUOqA29nolQQbR4K5HsYwNRgGZ73rqak+widz9EEDkjerxTaVOr9Jg1q/p4IjSVgaVOO1hAC1PViU3xBLdTx8ZRV8k0hC8Epo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735208738; c=relaxed/simple; bh=olBLtRWcjK9QZrWbC55qvfxjlLV90eGAgEXrYH5bXq4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=X+SeeveE24RCPzkKYlR66EK9VTw6/D9zBQGVBrHhGhOHVXZ5LpUiRBcZrhxk2nimZ3G/CpJBLK5IMEbogtbihP/BdAS/OjH5dDhbeG8U1Qds0/a/q8pHL7OPdPSd9FcicipdUWL9nk4D6aawNLPRvEvBDu04OvfG8lRjfgc+qr8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=oI2BugbV; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="oI2BugbV" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BQ0xYlm008985; Thu, 26 Dec 2024 10:25:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= UwRsylWneaLvu2ddzARrAikShK4o0zAFGbJPc00eBEE=; b=oI2BugbV6Xv0nTtA qcftdl+4DsO9Ha1fktxUf15dRaJ26gIg1wmZw+tTp/NNcPgsTg6BRVyM3jFH+Zgg qNITWuQgUZWbF1Or3x6MBgTLvFkH8edeUOifLybz5YyuUAr87BelBkSJixqAy0P1 FP0E4do/nrF8c8NZXM7GY8G9KQ6x4xPIDgEhkAXcV4MfaQUt9TjogNjzj5+k19YW ZtP2j29yMXom1BAUJtoVAg1r2wHJiZ5skSedT8DSyK0cvVhMAF8F7klzMnhHu6ub /t552gUaD4Edl+BJ6/wZWS6qFhBMU8Bhu5y9878ZXxUynoAm6hRbpBA+kM0SkPyT qW+eUg== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43rv8qtu8q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Dec 2024 10:25:21 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BQAPKRj030350 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Dec 2024 10:25:20 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 26 Dec 2024 02:25:14 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , CC: Praveenkumar I Subject: [PATCH v4 5/5] arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers Date: Thu, 26 Dec 2024 15:54:32 +0530 Message-ID: <20241226102432.3193366-6-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241226102432.3193366-1-quic_varada@quicinc.com> References: <20241226102432.3193366-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: KZIMCF8rJRZJbFrcSSoBaL7vukV1GN5j X-Proofpoint-ORIG-GUID: KZIMCF8rJRZJbFrcSSoBaL7vukV1GN5j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 impostorscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 adultscore=0 phishscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412260091 From: Praveenkumar I Enable the PCIe controller and PHY nodes for RDP 441. Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- v4: Fix nodes sort order Use property-n followed by property-names v3: Reorder nodes alphabetically Fix commit subject --- arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 846413817e9a..79ec77cfe552 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -32,6 +32,34 @@ &sdhc { status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + &tlmm { i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; @@ -40,6 +68,54 @@ i2c_1_pins: i2c-1-state { bias-pull-up; }; + pcie0_default: pcie0-default-state { + clkreq-n-pins { + pins = "gpio37"; + function = "pcie0_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio38"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio39"; + function = "pcie0_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio46"; + function = "pcie1_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio47"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio48"; + function = "pcie1_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio13";