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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436612008casm360093335e9.14.2024.12.30.07.39.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Dec 2024 07:39:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Stafford Horne , Zhao Liu , qemu-ppc@nongnu.org, Yanan Wang , Eduardo Habkost , Song Gao , Bernhard Beschow , qemu-arm@nongnu.org, Marcel Apfelbaum , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 1/3] accel/tcg: Remove pointless initialization of cflags_next_tb Date: Mon, 30 Dec 2024 16:39:27 +0100 Message-ID: <20241230153929.87137-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230153929.87137-1-philmd@linaro.org> References: <20241230153929.87137-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cflags_next_tb is always re-initialized in the CPU Reset() handler in cpu_common_reset_hold(), no need to initialize it in cpu_common_initfn(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240427155714.53669-13-philmd@linaro.org> --- hw/core/cpu-common.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 1edc16f65c8..10d34455a85 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -245,7 +245,6 @@ static void cpu_common_initfn(Object *obj) /* the default value is changed by qemu_init_vcpu() for system-mode */ cpu->nr_cores = 1; cpu->nr_threads = 1; - cpu->cflags_next_tb = -1; /* allocate storage for thread info, initialise condition variables */ cpu->thread = g_new0(QemuThread, 1); From patchwork Mon Dec 30 15:39:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 854248 Delivered-To: patch@linaro.org Received: by 2002:a5d:4888:0:b0:385:e875:8a9e with SMTP id g8csp6495072wrq; Mon, 30 Dec 2024 07:40:20 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVRHwP1tA8HvZDpsaNMaTNdriYpltlHMV1qZYJ3ABiuffUVQmp5iM2WSPhCBUNm7nXqH0qL2g==@linaro.org X-Google-Smtp-Source: AGHT+IHZ5TBwvN6kE9Jm3OKlIaFbjgv25p840ujmsjpF15WTRTxuFemzY1CpXQCZT0HYbTjz/EEm X-Received: by 2002:a05:6102:26cf:b0:4af:cb0c:390b with SMTP id ada2fe7eead31-4b2cd718373mr29611698137.7.1735573219721; Mon, 30 Dec 2024 07:40:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1735573219; cv=none; d=google.com; s=arc-20240605; b=Frlg4Y2wfDC3mIWrnqMs/QyGyTkp3WeoT6C19lFyakbm1PNU94L9skxx1e6hH/GIn0 1b7Jx/zppKFZue1ORgUEW6K/JpCf0nnaGUVVWoIdKxdRYuvt4ra3N2ZZdJIxoYDBY4Ov 6luKtOr7fjC1hArf9uG7fE71HNe4IHGA7ZzhkxgLDL3cZ1Hsek27GvEVBexmRGn85lPa 25UMxcRQesycEo0hPZkvteq0//LQWciMfaVIpPzks8lKoAUmTxZ3ZcjE2R6hBlCHEcjg fN+Vlu9eBaWzYIwYkzqfNVXEwCypIWvQBQqZKjJLzWP4sooKb9LtmZVjF71c/h/S6hfW 3L3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zaU9NBmAHybeYXgq1cwe95Tsd0YH1x8KfOWowQQlRh0=; fh=QAnqEm9+J4rk2BCSQNqmeCLLOXX1PKB5iRsrJ6bZAZg=; b=iBN2UtyjVzxaoDNn2/YxynvzkpFuenbTmYdE7iTm5nfad7ZJ39+K3ZFouGY03qnwFv qOvLg552/w/1oDVo3miL9MVRcatMJ7lY8QQDLpt/NdR3xgCa0HqVCPdvRAURCUy7+kxj gVmAtmDlzkM0e/f07gPaKN2BirzcE5kgEZWPUYGh0N1IJG6xXH8H8VYTkwALvm4JKM/j T5lOFstq4hHJy3FyiIPJrhbiJHQZwRAzJ3YiM3Pang/6rRGpX8sMakxBcOcbV+1yVJM0 bWhUUJfCTn7thVgB0mTAttzSgA7sItD6wsGbODpaobXKmBEHYnhMXD0WjaQjkVS++59C rsJQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JJDnIG7Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c89e126sm29890799f8f.65.2024.12.30.07.39.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Dec 2024 07:39:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Stafford Horne , Zhao Liu , qemu-ppc@nongnu.org, Yanan Wang , Eduardo Habkost , Song Gao , Bernhard Beschow , qemu-arm@nongnu.org, Marcel Apfelbaum , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 2/3] target/cpus: Remove pointless re-assignment of CPUState::exception_index Date: Mon, 30 Dec 2024 16:39:28 +0100 Message-ID: <20241230153929.87137-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230153929.87137-1-philmd@linaro.org> References: <20241230153929.87137-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The CPUState::exception_index field is always re-initialized by the parent CPU ResetHold() handler in cpu_common_reset_hold(), no need to have targets manually initializing it. Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/cpu.c | 1 - target/loongarch/cpu.c | 1 - target/openrisc/cpu.c | 1 - 3 files changed, 3 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6e5434a8e99..9b355bfe902 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -203,7 +203,6 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType type) if (scc->parent_phases.hold) { scc->parent_phases.hold(obj, type); } - cs->exception_index = -1; cs->halted = 0; cpu_set_pc(cs, 0xf0000004); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d611a604704..fd062d2e3e1 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -584,7 +584,6 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type) #ifdef CONFIG_TCG restore_fp_status(env); #endif - cs->exception_index = -1; } static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b7bab0d7abf..84aa9448256 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -101,7 +101,6 @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) cpu->env.pc = 0x100; cpu->env.sr = SR_FO | SR_SM; cpu->env.lock_addr = -1; - cs->exception_index = -1; cpu_set_fpcsr(&cpu->env, 0); set_float_detect_tininess(float_tininess_before_rounding, From patchwork Mon Dec 30 15:39:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 854250 Delivered-To: patch@linaro.org Received: by 2002:a5d:4888:0:b0:385:e875:8a9e with SMTP id g8csp6495377wrq; Mon, 30 Dec 2024 07:40:54 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXbS2dByVYlsBh1Vx8m0T4GCV1FZLSgEvPHKQIzy9zygAsgib7HlGCB2faRrbE0Uz+Royqsqg==@linaro.org X-Google-Smtp-Source: AGHT+IFstDBTJDk9TkxbIN7Z3irAjfKhRUsdtVMXczFENelB1z8rxPtpUdkQJFqxmbu41f5Ol3Cv X-Received: by 2002:a05:6102:50a7:b0:4b2:cbe5:fbc5 with SMTP id ada2fe7eead31-4b2cc462478mr28913717137.20.1735573254335; Mon, 30 Dec 2024 07:40:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1735573254; cv=none; d=google.com; s=arc-20240605; b=kT8MRRAMHV1+rC5BOdx4z0wD/R6pF0VxyNxEJzNRB6L3oEfDNP8f5QXtWB2V2qR7eN S2QgogMt2CCwZ06O1l4iFlvPpGQ49Amd5tuTRjn+2FyojLFPdZP3IuMh/OCj8L9LR5J0 qa7QwBGHE3rrIKUx+8HDV6JL7Odc4UHHQKZ27NH7XO0zYNNtc9WqMwSv4+MfyyTDUt/L TFU+lVV4Bmfo4czwQVZ9SM1qZDVMoLcjGTMn57sOTKtmFrERBdroyaZapcPDDa6YSI9F 3NioS8cKrlvEWpVuvqPomQWVDRS891Rnay6TtJYpN+PxtZ4c57ZjX7cUIPVHnR30WhTB jamA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=V4fyXlhxQAEqDO8KjATP3LRp5cmZQUPuZTn5SNaOG44=; fh=QAnqEm9+J4rk2BCSQNqmeCLLOXX1PKB5iRsrJ6bZAZg=; b=aectuPq46M37FbXXyLV732mo3T5KHYeg+n+GJU/LFEm0anZj/BRCKO2X6rdGul7d+F ZUh4WfTx8d5KFYvBlewezLO2cyOEHiZNsIj3dB0jHWNQ63k5ozonINLr04R/ihH0JbSl 38hiDZYdTUFYBmHLwG9l4kltzsJDmN0RWGtpnG7qGjxQOiaU96gGbKTb7uY1dgXmcovD PKsErHdziqs/ZGVHpSoTCf4w+uxKcxYg8XtYOKqJI2Xx0G5ubkPZ69JQmu0hj4mNc7bD fOnNOA1e0KksQkcFAsGeIEaYftCg4R925yAMApqphXP79ppRj+ppE7U6m33h17W6+WJT i2Rg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZwzI7iR5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4366127c4bbsm357117475e9.32.2024.12.30.07.39.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Dec 2024 07:39:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Stafford Horne , Zhao Liu , qemu-ppc@nongnu.org, Yanan Wang , Eduardo Habkost , Song Gao , Bernhard Beschow , qemu-arm@nongnu.org, Marcel Apfelbaum , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 3/3] target/cpus: Remove pointless re-assignment of CPUState::halted Date: Mon, 30 Dec 2024 16:39:29 +0100 Message-ID: <20241230153929.87137-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230153929.87137-1-philmd@linaro.org> References: <20241230153929.87137-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The CPUState::halted field is always re-initialized in cpu_common_reset_hold(), itself called by cpu_reset(). No need to have targets manually initializing it. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Bernhard Beschow --- hw/misc/mips_cpc.c | 1 - hw/ppc/e500.c | 1 - target/arm/arm-powerctl.c | 2 -- target/hppa/cpu.c | 1 - 4 files changed, 5 deletions(-) diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c index 772b8c0017d..4ec8226c416 100644 --- a/hw/misc/mips_cpc.c +++ b/hw/misc/mips_cpc.c @@ -38,7 +38,6 @@ static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data) MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr; cpu_reset(cs); - cs->halted = 0; cpc->vp_running |= 1ULL << cs->cpu_index; } diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 4551157c011..8b90b5b2448 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -785,7 +785,6 @@ static void ppce500_cpu_reset(void *opaque) cpu_reset(cs); /* Set initial guest state. */ - cs->halted = 0; env->gpr[1] = (16 * MiB) - 8; env->gpr[3] = bi->dt_base; env->gpr[4] = 0; diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 20c70c7d6bb..8e948171c7c 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -67,7 +67,6 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, /* Initialize the cpu we are turning on */ cpu_reset(target_cpu_state); arm_emulate_firmware_reset(target_cpu_state, info->target_el); - target_cpu_state->halted = 0; /* We check if the started CPU is now at the correct level */ assert(info->target_el == arm_current_el(&target_cpu->env)); @@ -194,7 +193,6 @@ static void arm_set_cpu_on_and_reset_async_work(CPUState *target_cpu_state, /* Initialize the cpu we are turning on */ cpu_reset(target_cpu_state); - target_cpu_state->halted = 0; /* Finally set the power status */ assert(bql_locked()); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9b355bfe902..b4092037888 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -203,7 +203,6 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType type) if (scc->parent_phases.hold) { scc->parent_phases.hold(obj, type); } - cs->halted = 0; cpu_set_pc(cs, 0xf0000004); memset(env, 0, offsetof(CPUHPPAState, end_reset_fields));