From patchwork Mon Jan 27 23:25:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860269 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106265wrx; Mon, 27 Jan 2025 15:26:45 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXM1CGgfpShnD+Rg2xDzVXUUzjHImgh+zaTjTj50LyA67+/Y7Ipegrxm7sR2TKoxdP4+YLj6w==@linaro.org X-Google-Smtp-Source: AGHT+IHfAt6liBLIXY8GnMkkj8DksAZuI+SkJRBkA9FhVazfX0wGUYBVgjYe6SDKUeE9eJ1ZIW2U X-Received: by 2002:a05:620a:2a13:b0:7b6:d8aa:7ef9 with SMTP id af79cd13be357-7be6320c0f9mr6686279985a.32.1738020405309; Mon, 27 Jan 2025 15:26:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020405; cv=none; d=google.com; s=arc-20240605; b=iCjh7ITgr8Z9XqfReXnB3TA8j4H57lH9GIdk5UYis/6Hjjrae9C7qxqxkWWuSt29LV 1sO7Ra5S7qDIQtg4TzEFzXaLNmPZdizDZf2zKjYm7kTVPjh+N2I3O1dSsfE4v8Ukr4ZS faf7CONeI260aRNLYeUxnZjlH9FF1ukYNvH9TaWCNqpSYa3ZCl0jrZoJ7CDg56wY9iXr imdPPCD/iNDV/06rHyrQXAxGhEMKH7yoQydXdr7Tx8rJzKn9NuzfUScCRCaBAHdMrnnb 7AtD6rZoNm+o/wUDZRFvyRs4/+k/W/UhuiaaUgmMlaj3Xknga5VTl68ll5YPwnDSDtlS A6jA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=B68aHUjgce2FHHqTRRu8gFQAPKi4L1+0pcChyOeMbAI=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=BLwES1anZimVVVut8EIWRPgxfXY8+KBls5dEnEHWErtouAv2GtmHLD3L3A8dhVNsHR AYf8kg0VA9GRUvfPV+L7SOIaxu1nnUsLl4TuMQyb49GroXrax85tw6kJqfRRGhJfdnd0 G66AdxFpO55j7qdG9Q+TqEe/nbjK7+AnB2m/Mc93VhEJZv/VKnfrMnlgow4Zc2KG6vMG g92A6eWU+rAw5ulYBtlpr99lAQ/Z3xTWHCTHzVVIY1GC8bvy7JmSSZZ3CKGs2XhN687v zzE5pO4LJ4tbhfMN3rKT6y8zFl0dnbkgZnfcOsLsshOe2wTPJmHiaoerBJpgwwDbQpiA 30Og==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zm6B4dB2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7be9aeee52csi1082589385a.427.2025.01.27.15.26.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:26:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zm6B4dB2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUg-0006Kg-5w; Mon, 27 Jan 2025 18:26:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUd-0006K2-RC for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:11 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUZ-0005W2-Tq for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:11 -0500 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2ef8c012913so6661975a91.3 for ; Mon, 27 Jan 2025 15:26:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020366; x=1738625166; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B68aHUjgce2FHHqTRRu8gFQAPKi4L1+0pcChyOeMbAI=; b=zm6B4dB2WswikHeDE8M2WNq7sdDPMUAfL+qoOJ2a4yUNnShUVU+9klnqE1KrBFKKmI sDjtg0EhNmLhfcI9AWIw7hqO+LTHOlVzHH/azbOaKy+nFX10WxgApdmyhLczgEZsa1SI GLm1VG8Sq/TCl4jEfM+c6bLpsIJZOrO6hyjoDmS8B7OpVHciz2k8ayXf14jPwtHBGIf4 RWddXsCgB6JxHT1SNfJNqETexzcPWMLWO9FRCU+vlDy5ZLz75EDHHV/42QyOMRDFJfWI dFz5Q0NnX95qQotsBbcDSe+Cg9OLKErjjjKYQ15h87WC7Qmw5ETKamutiqUnPpTXfFVj Ey9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020366; x=1738625166; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B68aHUjgce2FHHqTRRu8gFQAPKi4L1+0pcChyOeMbAI=; b=EZq1uVR0E7l4UX+ODK78fjgT7t7QWPmU9gjpeBA9sbYpm5SDfDkxWNej+OGreCEZeX vtM9cy8PU0nnZ5LMm3HTQL3h0WapvoQgOMnd5TFJI+SVumEKx7PLRPo4YjICMzdfrQZ+ MAOaQ9O7opra5YKaM/iIIoQc8PxPsXo9adwXISUGMdyvBsvzbEaMVruVAvuGARFBHWNn S5KSXwzRfiucCA7CaO0PvGTQFgQYACK37JhsWuFBOj5OUNStMAdI0Z5d/uGB8lj/qiN2 3NM+UiFEgPA13l9dL3p0AHtpZ8G0IZoN/6otqk6dH1VELacNg5Q0/9aNpCRZOGHol5iL oI+w== X-Gm-Message-State: AOJu0Yyj+n8yQaDLS7Mhhnd/mdqgGAutwx2Z+9tKvB/8z2GoJN/8FDsS X5+1FCduE00xMeRCECT2fn6SSCLMCzNlafszt6h9LfUJgPdsqxcEVVZbIBxQQlwSxnLHwG2qF2k + X-Gm-Gg: ASbGncuYUjmlqXjoq3pye5WfWIOtOiYJNpgjvjNtYHsYTqUv2bzQVSjzJxKCf+RqifA UuurGYZq+Hv2X6oZzE3hWnRrGG/8l7kg7blpknSPxMwP7x66zJlIQiFiGcqb3LtSTgMUTOQ+LOL 5+Y0gVz1136jOjz5ogrKUXFNSsK/21GVIvXNwNnJ0iTXykG0L33FOU9ZvfvDslIwN9bHVFzhJky U6LrcFfCBc7I/d6g28bdm9bMjxFLmsbG03wJfpUeNBoOHuYBfbaBKvkr0KzPECZG1g3tm4xv8EG E8dI2jqAKeSKtpfWjIT6DiynCqcnX8GrSLH4+FU= X-Received: by 2002:a17:90b:5448:b0:2ea:5dea:eb0a with SMTP id 98e67ed59e1d1-2f782c4d75cmr59181680a91.4.1738020366371; Mon, 27 Jan 2025 15:26:06 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 01/22] target/arm: Rename FPST_FPCR_A32 to FPST_A32 Date: Mon, 27 Jan 2025 15:25:43 -0800 Message-ID: <20250127232604.20386-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 6 ++-- target/arm/tcg/translate-vfp.c | 54 +++++++++++++++++----------------- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 59e780df2e..6ce2471aa6 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -674,7 +674,7 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) * Enum for argument to fpstatus_ptr(). */ typedef enum ARMFPStatusFlavour { - FPST_FPCR_A32, + FPST_A32, FPST_FPCR_A64, FPST_FPCR_F16_A32, FPST_FPCR_F16_A64, @@ -692,7 +692,7 @@ typedef enum ARMFPStatusFlavour { * been set up to point to the requested field in the CPU state struct. * The options are: * - * FPST_FPCR_A32 + * FPST_A32 * for AArch32 non-FP16 operations controlled by the FPCR * FPST_FPCR_A64 * for AArch64 non-FP16 operations controlled by the FPCR @@ -717,7 +717,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) int offset; switch (flavour) { - case FPST_FPCR_A32: + case FPST_A32: offset = offsetof(CPUARMState, vfp.fp_status_a32); break; case FPST_FPCR_A64: diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 8eebba0f27..4cc12a407b 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -462,7 +462,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) if (sz == 1) { fpst = fpstatus_ptr(FPST_FPCR_F16_A32); } else { - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); } tcg_rmode = gen_set_rmode(rounding, fpst); @@ -529,7 +529,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) if (sz == 1) { fpst = fpstatus_ptr(FPST_FPCR_F16_A32); } else { - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); } tcg_shift = tcg_constant_i32(0); @@ -1398,7 +1398,7 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, f0 = tcg_temp_new_i32(); f1 = tcg_temp_new_i32(); fd = tcg_temp_new_i32(); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); vfp_load_reg32(f0, vn); vfp_load_reg32(f1, vm); @@ -1517,7 +1517,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, f0 = tcg_temp_new_i64(); f1 = tcg_temp_new_i64(); fd = tcg_temp_new_i64(); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); vfp_load_reg64(f0, vn); vfp_load_reg64(f1, vm); @@ -2181,7 +2181,7 @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) /* VFNMA, VFNMS */ gen_vfp_negs(vd, vd); } - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); vfp_store_reg32(vd, a->vd); return true; @@ -2246,7 +2246,7 @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d) /* VFNMA, VFNMS */ gen_vfp_negd(vd, vd); } - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); vfp_store_reg64(vd, a->vd); return true; @@ -2429,12 +2429,12 @@ static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm) static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm) { - gen_helper_vfp_sqrts(vd, vm, fpstatus_ptr(FPST_FPCR_A32)); + gen_helper_vfp_sqrts(vd, vm, fpstatus_ptr(FPST_A32)); } static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm) { - gen_helper_vfp_sqrtd(vd, vm, fpstatus_ptr(FPST_FPCR_A32)); + gen_helper_vfp_sqrtd(vd, vm, fpstatus_ptr(FPST_A32)); } DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith) @@ -2565,7 +2565,7 @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a) return true; } - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); ahp_mode = get_ahp_flag(); tmp = tcg_temp_new_i32(); /* The T bit tells us if we want the low or high 16 bits of Vm */ @@ -2599,7 +2599,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) return true; } - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); ahp_mode = get_ahp_flag(); tmp = tcg_temp_new_i32(); /* The T bit tells us if we want the low or high 16 bits of Vm */ @@ -2623,7 +2623,7 @@ static bool trans_VCVT_b16_f32(DisasContext *s, arg_VCVT_b16_f32 *a) return true; } - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); tmp = tcg_temp_new_i32(); vfp_load_reg32(tmp, a->vm); @@ -2646,7 +2646,7 @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a) return true; } - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); ahp_mode = get_ahp_flag(); tmp = tcg_temp_new_i32(); @@ -2680,7 +2680,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) return true; } - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); ahp_mode = get_ahp_flag(); tmp = tcg_temp_new_i32(); vm = tcg_temp_new_i64(); @@ -2727,7 +2727,7 @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a) tmp = tcg_temp_new_i32(); vfp_load_reg32(tmp, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); gen_helper_rints(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); return true; @@ -2757,7 +2757,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) tmp = tcg_temp_new_i64(); vfp_load_reg64(tmp, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); gen_helper_rintd(tmp, tmp, fpst); vfp_store_reg64(tmp, a->vd); return true; @@ -2803,7 +2803,7 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a) tmp = tcg_temp_new_i32(); vfp_load_reg32(tmp, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst); gen_helper_rints(tmp, tmp, fpst); gen_restore_rmode(tcg_rmode, fpst); @@ -2836,7 +2836,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) tmp = tcg_temp_new_i64(); vfp_load_reg64(tmp, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst); gen_helper_rintd(tmp, tmp, fpst); gen_restore_rmode(tcg_rmode, fpst); @@ -2880,7 +2880,7 @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a) tmp = tcg_temp_new_i32(); vfp_load_reg32(tmp, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); gen_helper_rints_exact(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); return true; @@ -2910,7 +2910,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) tmp = tcg_temp_new_i64(); vfp_load_reg64(tmp, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); gen_helper_rintd_exact(tmp, tmp, fpst); vfp_store_reg64(tmp, a->vd); return true; @@ -2937,7 +2937,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) vm = tcg_temp_new_i32(); vd = tcg_temp_new_i64(); vfp_load_reg32(vm, a->vm); - gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_FPCR_A32)); + gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_A32)); vfp_store_reg64(vd, a->vd); return true; } @@ -2963,7 +2963,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) vd = tcg_temp_new_i32(); vm = tcg_temp_new_i64(); vfp_load_reg64(vm, a->vm); - gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_FPCR_A32)); + gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_A32)); vfp_store_reg32(vd, a->vd); return true; } @@ -3010,7 +3010,7 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) vm = tcg_temp_new_i32(); vfp_load_reg32(vm, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); if (a->s) { /* i32 -> f32 */ gen_helper_vfp_sitos(vm, vm, fpst); @@ -3044,7 +3044,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) vm = tcg_temp_new_i32(); vd = tcg_temp_new_i64(); vfp_load_reg32(vm, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); if (a->s) { /* i32 -> f64 */ gen_helper_vfp_sitod(vd, vm, fpst); @@ -3161,7 +3161,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) vd = tcg_temp_new_i32(); vfp_load_reg32(vd, a->vd); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); shift = tcg_constant_i32(frac_bits); /* Switch on op:U:sx bits */ @@ -3223,7 +3223,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) vd = tcg_temp_new_i64(); vfp_load_reg64(vd, a->vd); - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); shift = tcg_constant_i32(frac_bits); /* Switch on op:U:sx bits */ @@ -3307,7 +3307,7 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) return true; } - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); vm = tcg_temp_new_i32(); vfp_load_reg32(vm, a->vm); @@ -3347,7 +3347,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) return true; } - fpst = fpstatus_ptr(FPST_FPCR_A32); + fpst = fpstatus_ptr(FPST_A32); vm = tcg_temp_new_i64(); vd = tcg_temp_new_i32(); vfp_load_reg64(vm, a->vm); From patchwork Mon Jan 27 23:25:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860285 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp107099wrx; Mon, 27 Jan 2025 15:29:56 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCURWtmn0bH9TZQqMJcQq1zrHuANCZG4XiZW7F6pkIOYGlggwO6blX+uz32niNycYzsauLXPNA==@linaro.org X-Google-Smtp-Source: AGHT+IFgiK8419IedGcMnAMpvZMj8fHlK6oCEo7FBklGhbj9hPK2phLZON0zQ5/ZL2z0ZqZ6Npyp X-Received: by 2002:a05:6214:1302:b0:6d8:8d16:7cec with SMTP id 6a1803df08f44-6e1b2235e5dmr701272326d6.37.1738020596363; Mon, 27 Jan 2025 15:29:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020596; cv=none; d=google.com; s=arc-20240605; b=cobGU1yE0H4bct3nPigZMKq8G11XRXJmVaNOQFj8zw4Dr3iAHdcgs5+kb7rbHvxcsY NGunrvqQCogGAleGPqTwEIs+fhScROV5HAaeNzAulWLrVa4N1GOUWAA8QfGY4avMab0F YoA+xpxqk4nREi6HUJ35A2BxYl/H+Uo120xB1hBONS3r+VdSA1o41NAtsj0XY1M9AQZN gfFXXAFaK6fIjybxYCVPinMNVKxiBwfsypgc3jnSGgzd1cBeSxr2yH3rYrfi3j/9ci8V pX7+Czc6HoVALjrqqm34rwwuTRIsHi85Q3JqqnlVcB2FsNoBym5bFNMuN0wtpPw2edVq qPxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yghuBtj/DIiN8eRSXNAxvUfkjrNQffbHrvxPfCnEeII=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=ZgkXWt4YpnpIish9KJ6wwdB4y/TH6qSoMSI0cjW6LiFTHTuVeW2yucVMSJxbq6S1E2 vdWG6ZTsQqWubDLon5zsKY11WRvpHHQ8t8Nr4GPKiJvGJP0RSvWqDcEkXIJOnGrUohz3 Q8/bTXwQjEo/70xWXiyUWewz5hTx3I1I7yhIEuiF0QQr2vbKznaBLC/RVOCBsr3y/N5q r+yzH25c+7KdmeeOZxkLRcJLf7G+evLKMgNJcsFIb2eER/uigO4LB3Ao9+hfRIWkNZqz ko/rfA5auDRQH/l8mWPoqBH2fCTfm0yCOQbqBQV+TnZWniuGpj5NE7bLRsYs87NUp1NI sYPg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JTTU29WC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46e66b6b9a3si110689871cf.242.2025.01.27.15.29.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:29:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JTTU29WC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUq-0006Pi-22; Mon, 27 Jan 2025 18:26:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUf-0006Kf-8p for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:14 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUa-0005WM-OA for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:12 -0500 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-2ef28f07dbaso6913816a91.2 for ; Mon, 27 Jan 2025 15:26:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020367; x=1738625167; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yghuBtj/DIiN8eRSXNAxvUfkjrNQffbHrvxPfCnEeII=; b=JTTU29WC/Earg5aWjVcODge+9oaQXoBD8lwvRU5hp5c7ABmPGY5kMnSSGDkSjoZNwn Vf4zsMO6fD7/rVNOzy1q5MvIwAr8M+yGj4q9PUJ0HUg2pPaGUoNIFJpeqcaLqSGm2C2t Fb1XrdRAvvPGerrcOvPN2Xfn2ZYElvGSP5AMmcGWCMwW5jDo2D9J0HL3O8oS5ahjujkq QbtfyN2GBMs8DWBH2E83Q+Ded9uIjY+SeOKF5a2csx6qj++6lTPb0d7C6jwnpmhu0dVz Vng32JmTm2qhdV15q5HRRAJA/scBlBiQmoIo3uA9sAcjvv9UA1EUFMFzOF4ivybvNgAB TcJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020367; x=1738625167; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yghuBtj/DIiN8eRSXNAxvUfkjrNQffbHrvxPfCnEeII=; b=EQwVB+I0mpzwZ2v3tq3Fyr8jm2t1JzQ3CIm+oaxcqEQBlLwU3QDYoGE+mMjU4I+hCG 2QHvC/QWLTW4cwyI9nw7f7QVodRBe34rM+ZUZKEPnVNUlBlJc7cr+zG0IDev7s49v5Ia 08cZykjGxJBK1tVuZamCAkMJ93w2o4Qc9Hden1nD9CrdxApnlQa5MmA2G9MUVte/IqHz OyElfGDMjOf9k75P2k8IkZpV3OXZ8+uu0PokwcVsvirpUH2ELr+J/k5s5Oy1/r8KIua6 Y04SahqZX2Ub7NgQ/vDrS07PJbBGUOSu+WVfAKbEUmAujUK5PT1+l8EnLsjxXVozE1dD 3gEQ== X-Gm-Message-State: AOJu0YzuPl/NOe6W4kkd8FNZn3n+/gB86PhCJozVCiTUgcIPUkdwzREx dKIxQplqBPxt1cX37QSCxY8ari854WaBxcTy1a8jCC1kqsDAOYoekYFKHZ3XE0qCz1T7XNkLK/q 2 X-Gm-Gg: ASbGnctH0zCC1YSCUiGCcKoVTMbmXcAbpygehA5uiLBMPO6pCcC6A3XlzgyKIDtEd2i aIllicMv7frptNOoCZOuhZNMmPbJU6VKIK9k7cO27KhEZUM+lMZ4XkWhSzipF0FqH73Oc3WGJf+ jiy5SXxy16s0TSvWvBZeNtiMd9kz+L1PzqMWUOL1QoF9PsPDlWAWxiN+Irc3ONUDYKY5fyjh0LF RMJF2iKTmMVd5566R6Ccab8W1vEEGBFpy8h0isq/Xi1OGND2KubqOswHIS87aMltfFV5+AbRGnP MEtt3iacyiEypR0LneQAcBk0Orq+65r0nslJgpOmKcJ6owt4Wg== X-Received: by 2002:a17:90b:3547:b0:2f7:ef57:c7df with SMTP id 98e67ed59e1d1-2f7ef57c8fbmr32424351a91.7.1738020367208; Mon, 27 Jan 2025 15:26:07 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 02/22] target/arm: Rename FPST_FPCR_A64 to FPST_A64 Date: Mon, 27 Jan 2025 15:25:44 -0800 Message-ID: <20250127232604.20386-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 8 +-- target/arm/tcg/translate-a64.c | 78 +++++++++++++-------------- target/arm/tcg/translate-sme.c | 4 +- target/arm/tcg/translate-sve.c | 98 +++++++++++++++++----------------- 4 files changed, 94 insertions(+), 94 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 6ce2471aa6..2edb707b85 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -675,7 +675,7 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) */ typedef enum ARMFPStatusFlavour { FPST_A32, - FPST_FPCR_A64, + FPST_A64, FPST_FPCR_F16_A32, FPST_FPCR_F16_A64, FPST_FPCR_AH, @@ -694,7 +694,7 @@ typedef enum ARMFPStatusFlavour { * * FPST_A32 * for AArch32 non-FP16 operations controlled by the FPCR - * FPST_FPCR_A64 + * FPST_A64 * for AArch64 non-FP16 operations controlled by the FPCR * FPST_FPCR_F16_A32 * for AArch32 operations controlled by the FPCR where FPCR.FZ16 is to be used @@ -720,7 +720,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) case FPST_A32: offset = offsetof(CPUARMState, vfp.fp_status_a32); break; - case FPST_FPCR_A64: + case FPST_A64: offset = offsetof(CPUARMState, vfp.fp_status_a64); break; case FPST_FPCR_F16_A32: @@ -757,7 +757,7 @@ static inline ARMFPStatusFlavour select_fpst(DisasContext *s, MemOp esz) if (s->fpcr_ah) { return esz == MO_16 ? FPST_FPCR_AH_F16 : FPST_FPCR_AH; } else { - return esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64; + return esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64; } } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 3e2fe46464..bf17ecca80 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -5247,7 +5247,7 @@ static bool do_fp3_scalar(DisasContext *s, arg_rrr_e *a, const FPScalar *f, { return do_fp3_scalar_with_fpsttype(s, a, f, mergereg, a->esz == MO_16 ? - FPST_FPCR_F16_A64 : FPST_FPCR_A64); + FPST_FPCR_F16_A64 : FPST_A64); } static bool do_fp3_scalar_ah_2fn(DisasContext *s, arg_rrr_e *a, @@ -5506,9 +5506,9 @@ static bool do_fcmp0_s(DisasContext *s, arg_rr_e *a, TCGv_i64 t0 = read_fp_dreg(s, a->rn); TCGv_i64 t1 = tcg_constant_i64(0); if (swap) { - f->gen_d(t0, t1, t0, fpstatus_ptr(FPST_FPCR_A64)); + f->gen_d(t0, t1, t0, fpstatus_ptr(FPST_A64)); } else { - f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_FPCR_A64)); + f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_A64)); } write_fp_dreg(s, a->rd, t0); } @@ -5518,9 +5518,9 @@ static bool do_fcmp0_s(DisasContext *s, arg_rr_e *a, TCGv_i32 t0 = read_fp_sreg(s, a->rn); TCGv_i32 t1 = tcg_constant_i32(0); if (swap) { - f->gen_s(t0, t1, t0, fpstatus_ptr(FPST_FPCR_A64)); + f->gen_s(t0, t1, t0, fpstatus_ptr(FPST_A64)); } else { - f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_FPCR_A64)); + f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_A64)); } write_fp_sreg(s, a->rd, t0); } @@ -5768,7 +5768,7 @@ static bool do_fp3_vector(DisasContext *s, arg_qrrr_e *a, int data, { return do_fp3_vector_with_fpsttype(s, a, data, fns, a->esz == MO_16 ? - FPST_FPCR_F16_A64 :FPST_FPCR_A64); + FPST_FPCR_F16_A64 :FPST_A64); } static bool do_fp3_vector_2fn(DisasContext *s, arg_qrrr_e *a, int data, @@ -6135,7 +6135,7 @@ static bool trans_BFMLAL_v(DisasContext *s, arg_qrrr_e *a) if (fp_access_check(s)) { /* Q bit selects BFMLALB vs BFMLALT. */ gen_gvec_op4_fpst(s, true, a->rd, a->rn, a->rm, a->rd, - s->fpcr_ah ? FPST_FPCR_AH : FPST_FPCR_A64, a->q, + s->fpcr_ah ? FPST_FPCR_AH : FPST_A64, a->q, gen_helper_gvec_bfmlal); } return true; @@ -6174,7 +6174,7 @@ static bool trans_FCMLA_v(DisasContext *s, arg_FCMLA_v *a) } gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64, + a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64, a->rot, fn[a->esz]); return true; } @@ -6543,7 +6543,7 @@ static bool do_fp3_scalar_idx(DisasContext *s, arg_rrx_e *a, const FPScalar *f) TCGv_i64 t1 = tcg_temp_new_i64(); read_vec_element(s, t1, a->rm, a->idx, MO_64); - f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_FPCR_A64)); + f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_A64)); write_fp_dreg_merging(s, a->rd, a->rn, t0); } break; @@ -6553,7 +6553,7 @@ static bool do_fp3_scalar_idx(DisasContext *s, arg_rrx_e *a, const FPScalar *f) TCGv_i32 t1 = tcg_temp_new_i32(); read_vec_element_i32(s, t1, a->rm, a->idx, MO_32); - f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_FPCR_A64)); + f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_A64)); write_fp_sreg_merging(s, a->rd, a->rn, t0); } break; @@ -6592,7 +6592,7 @@ static bool do_fmla_scalar_idx(DisasContext *s, arg_rrx_e *a, bool neg) if (neg) { gen_vfp_maybe_ah_negd(s, t1, t1); } - gen_helper_vfp_muladdd(t0, t1, t2, t0, fpstatus_ptr(FPST_FPCR_A64)); + gen_helper_vfp_muladdd(t0, t1, t2, t0, fpstatus_ptr(FPST_A64)); write_fp_dreg_merging(s, a->rd, a->rd, t0); } break; @@ -6606,7 +6606,7 @@ static bool do_fmla_scalar_idx(DisasContext *s, arg_rrx_e *a, bool neg) if (neg) { gen_vfp_maybe_ah_negs(s, t1, t1); } - gen_helper_vfp_muladds(t0, t1, t2, t0, fpstatus_ptr(FPST_FPCR_A64)); + gen_helper_vfp_muladds(t0, t1, t2, t0, fpstatus_ptr(FPST_A64)); write_fp_sreg_merging(s, a->rd, a->rd, t0); } break; @@ -6721,7 +6721,7 @@ static bool do_fp3_vector_idx(DisasContext *s, arg_qrrx_e *a, } gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm, - esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64, + esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64, a->idx, fns[esz - 1]); return true; } @@ -6755,7 +6755,7 @@ static bool do_fmla_vector_idx(DisasContext *s, arg_qrrx_e *a, bool neg) } gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd, - esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64, + esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64, (s->fpcr_ah << 5) | (a->idx << 1) | neg, fns[esz - 1]); return true; @@ -6892,7 +6892,7 @@ static bool trans_BFMLAL_vi(DisasContext *s, arg_qrrx_e *a) if (fp_access_check(s)) { /* Q bit selects BFMLALB vs BFMLALT. */ gen_gvec_op4_fpst(s, true, a->rd, a->rn, a->rm, a->rd, - s->fpcr_ah ? FPST_FPCR_AH : FPST_FPCR_A64, + s->fpcr_ah ? FPST_FPCR_AH : FPST_A64, (a->idx << 1) | a->q, gen_helper_gvec_bfmlal_idx); } @@ -6921,7 +6921,7 @@ static bool trans_FCMLA_vi(DisasContext *s, arg_FCMLA_vi *a) } if (fp_access_check(s)) { gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64, + a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64, (a->idx << 2) | a->rot, fn); } return true; @@ -6941,7 +6941,7 @@ static bool do_fp3_scalar_pair(DisasContext *s, arg_rr_e *a, const FPScalar *f) read_vec_element(s, t0, a->rn, 0, MO_64); read_vec_element(s, t1, a->rn, 1, MO_64); - f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_FPCR_A64)); + f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_A64)); write_fp_dreg(s, a->rd, t0); } break; @@ -6952,7 +6952,7 @@ static bool do_fp3_scalar_pair(DisasContext *s, arg_rr_e *a, const FPScalar *f) read_vec_element_i32(s, t0, a->rn, 0, MO_32); read_vec_element_i32(s, t1, a->rn, 1, MO_32); - f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_FPCR_A64)); + f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_A64)); write_fp_sreg(s, a->rd, t0); } break; @@ -7109,7 +7109,7 @@ static bool do_fmadd(DisasContext *s, arg_rrrr_e *a, bool neg_a, bool neg_n) if (neg_n) { gen_vfp_maybe_ah_negd(s, tn, tn); } - fpst = fpstatus_ptr(FPST_FPCR_A64); + fpst = fpstatus_ptr(FPST_A64); gen_helper_vfp_muladdd(ta, tn, tm, ta, fpst); write_fp_dreg_merging(s, a->rd, a->ra, ta); } @@ -7127,7 +7127,7 @@ static bool do_fmadd(DisasContext *s, arg_rrrr_e *a, bool neg_a, bool neg_n) if (neg_n) { gen_vfp_maybe_ah_negs(s, tn, tn); } - fpst = fpstatus_ptr(FPST_FPCR_A64); + fpst = fpstatus_ptr(FPST_A64); gen_helper_vfp_muladds(ta, tn, tm, ta, fpst); write_fp_sreg_merging(s, a->rd, a->ra, ta); } @@ -7243,7 +7243,7 @@ static bool do_fp_reduction(DisasContext *s, arg_qrr_e *a, if (fp_access_check(s)) { MemOp esz = a->esz; int elts = (a->q ? 16 : 8) >> esz; - TCGv_ptr fpst = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + TCGv_ptr fpst = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); TCGv_i32 res = do_reduction_op(s, a->rn, esz, 0, elts, fpst, s->fpcr_ah ? fah : fnormal); write_fp_sreg(s, a->rd, res); @@ -7294,7 +7294,7 @@ static void handle_fp_compare(DisasContext *s, int size, bool cmp_with_zero, bool signal_all_nans) { TCGv_i64 tcg_flags = tcg_temp_new_i64(); - TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); if (size == MO_64) { TCGv_i64 tcg_vn, tcg_vm; @@ -8829,7 +8829,7 @@ static bool do_fp1_scalar(DisasContext *s, arg_rr_e *a, { return do_fp1_scalar_with_fpsttype(s, a, f, rmode, a->esz == MO_16 ? - FPST_FPCR_F16_A64 : FPST_FPCR_A64); + FPST_FPCR_F16_A64 : FPST_A64); } static bool do_fp1_scalar_ah(DisasContext *s, arg_rr_e *a, @@ -8866,7 +8866,7 @@ TRANS(FRINTX_s, do_fp1_scalar, a, &f_scalar_frintx, -1) static bool trans_BFCVT_s(DisasContext *s, arg_rr_e *a) { - ARMFPStatusFlavour fpsttype = s->fpcr_ah ? FPST_FPCR_AH : FPST_FPCR_A64; + ARMFPStatusFlavour fpsttype = s->fpcr_ah ? FPST_FPCR_AH : FPST_A64; TCGv_i32 t32; int check; @@ -8944,7 +8944,7 @@ static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *a) if (fp_access_check(s)) { TCGv_i32 tcg_rn = read_fp_sreg(s, a->rn); TCGv_i64 tcg_rd = tcg_temp_new_i64(); - TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR_A64); + TCGv_ptr fpst = fpstatus_ptr(FPST_A64); gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, fpst); write_fp_dreg_merging(s, a->rd, a->rd, tcg_rd); @@ -8957,7 +8957,7 @@ static bool trans_FCVT_s_hs(DisasContext *s, arg_rr *a) if (fp_access_check(s)) { TCGv_i32 tmp = read_fp_sreg(s, a->rn); TCGv_i32 ahp = get_ahp_flag(); - TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR_A64); + TCGv_ptr fpst = fpstatus_ptr(FPST_A64); gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); /* write_fp_hreg_merging is OK here because top half of result is zero */ @@ -8971,7 +8971,7 @@ static bool trans_FCVT_s_sd(DisasContext *s, arg_rr *a) if (fp_access_check(s)) { TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn); TCGv_i32 tcg_rd = tcg_temp_new_i32(); - TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR_A64); + TCGv_ptr fpst = fpstatus_ptr(FPST_A64); gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, fpst); write_fp_sreg_merging(s, a->rd, a->rd, tcg_rd); @@ -8985,7 +8985,7 @@ static bool trans_FCVT_s_hd(DisasContext *s, arg_rr *a) TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn); TCGv_i32 tcg_rd = tcg_temp_new_i32(); TCGv_i32 ahp = get_ahp_flag(); - TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR_A64); + TCGv_ptr fpst = fpstatus_ptr(FPST_A64); gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_hreg_merging is OK here because top half of tcg_rd is zero */ @@ -9029,7 +9029,7 @@ static bool do_cvtf_scalar(DisasContext *s, MemOp esz, int rd, int shift, TCGv_i32 tcg_shift, tcg_single; TCGv_i64 tcg_double; - tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); tcg_shift = tcg_constant_i32(shift); switch (esz) { @@ -9124,7 +9124,7 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz, TCGv_ptr tcg_fpstatus; TCGv_i32 tcg_shift, tcg_rmode, tcg_single; - tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); tcg_shift = tcg_constant_i32(shift); tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus); @@ -9290,7 +9290,7 @@ static bool trans_FJCVTZS(DisasContext *s, arg_FJCVTZS *a) } if (fp_access_check(s)) { TCGv_i64 t = read_fp_dreg(s, a->rn); - TCGv_ptr fpstatus = fpstatus_ptr(FPST_FPCR_A64); + TCGv_ptr fpstatus = fpstatus_ptr(FPST_A64); gen_helper_fjcvtzs(t, t, fpstatus); @@ -9550,7 +9550,7 @@ static bool trans_FCVTXN_s(DisasContext *s, arg_rr_e *a) */ TCGv_i64 src = read_fp_dreg(s, a->rn); TCGv_i32 dst = tcg_temp_new_i32(); - gen_helper_fcvtx_f64_to_f32(dst, src, fpstatus_ptr(FPST_FPCR_A64)); + gen_helper_fcvtx_f64_to_f32(dst, src, fpstatus_ptr(FPST_A64)); write_fp_sreg_merging(s, a->rd, a->rd, dst); } return true; @@ -9638,7 +9638,7 @@ static void gen_fcvtn_hs(TCGv_i64 d, TCGv_i64 n) { TCGv_i32 tcg_lo = tcg_temp_new_i32(); TCGv_i32 tcg_hi = tcg_temp_new_i32(); - TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR_A64); + TCGv_ptr fpst = fpstatus_ptr(FPST_A64); TCGv_i32 ahp = get_ahp_flag(); tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, n); @@ -9651,7 +9651,7 @@ static void gen_fcvtn_hs(TCGv_i64 d, TCGv_i64 n) static void gen_fcvtn_sd(TCGv_i64 d, TCGv_i64 n) { TCGv_i32 tmp = tcg_temp_new_i32(); - TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR_A64); + TCGv_ptr fpst = fpstatus_ptr(FPST_A64); gen_helper_vfp_fcvtsd(tmp, n, fpst); tcg_gen_extu_i32_i64(d, tmp); @@ -9664,7 +9664,7 @@ static void gen_fcvtxn_sd(TCGv_i64 d, TCGv_i64 n) * with von Neumann rounding (round to odd) */ TCGv_i32 tmp = tcg_temp_new_i32(); - gen_helper_fcvtx_f64_to_f32(tmp, n, fpstatus_ptr(FPST_FPCR_A64)); + gen_helper_fcvtx_f64_to_f32(tmp, n, fpstatus_ptr(FPST_A64)); tcg_gen_extu_i32_i64(d, tmp); } @@ -9683,7 +9683,7 @@ TRANS(FCVTXN_v, do_2misc_narrow_vector, a, f_scalar_fcvtxn) static void gen_bfcvtn_hs(TCGv_i64 d, TCGv_i64 n) { - TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR_A64); + TCGv_ptr fpst = fpstatus_ptr(FPST_A64); TCGv_i32 tmp = tcg_temp_new_i32(); gen_helper_bfcvt_pair(tmp, n, fpst); tcg_gen_extu_i32_i64(d, tmp); @@ -9773,7 +9773,7 @@ static bool do_fp1_vector(DisasContext *s, arg_qrr_e *a, return check == 0; } - fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); if (rmode >= 0) { tcg_rmode = gen_set_rmode(rmode, fpst); } @@ -9848,7 +9848,7 @@ static bool do_gvec_op2_fpst(DisasContext *s, MemOp esz, bool is_q, { return do_gvec_op2_fpst_with_fpsttype(s, esz, is_q, rd, rn, data, fns, esz == MO_16 ? FPST_FPCR_F16_A64 : - FPST_FPCR_A64); + FPST_A64); } static bool do_gvec_op2_ah_fpst(DisasContext *s, MemOp esz, bool is_q, @@ -10008,7 +10008,7 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a) TCGv_i32 tcg_op = tcg_temp_new_i32(); int srcelt = a->q ? 2 : 0; - fpst = fpstatus_ptr(FPST_FPCR_A64); + fpst = fpstatus_ptr(FPST_A64); for (pass = 0; pass < 2; pass++) { tcg_res[pass] = tcg_temp_new_i64(); diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 29bec7dd7b..fcbb350016 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -358,9 +358,9 @@ static bool do_outprod_env(DisasContext *s, arg_op *a, MemOp esz, TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_env, a, MO_32, gen_helper_sme_fmopa_h) TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, - MO_32, FPST_FPCR_A64, gen_helper_sme_fmopa_s) + MO_32, FPST_A64, gen_helper_sme_fmopa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, - MO_64, FPST_FPCR_A64, gen_helper_sme_fmopa_d) + MO_64, FPST_A64, gen_helper_sme_fmopa_d) TRANS_FEAT(BFMOPA, aa64_sme, do_outprod_env, a, MO_32, gen_helper_sme_bfmopa) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 454f7ff900..3cc678154a 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -191,7 +191,7 @@ static bool gen_gvec_fpst_arg_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn, arg_rrr_esz *a, int data) { return gen_gvec_fpst_zzz(s, fn, a->rd, a->rn, a->rm, data, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); } static bool gen_gvec_fpst_ah_arg_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn, @@ -404,7 +404,7 @@ static bool gen_gvec_fpst_arg_zpzz(DisasContext *s, gen_helper_gvec_4_ptr *fn, arg_rprr_esz *a) { return gen_gvec_fpst_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); } /* Invoke a vector expander on two Zregs and an immediate. */ @@ -3534,7 +3534,7 @@ static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub) }; return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, (s->fpcr_ah << 5) | (a->index << 1) | sub, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); } TRANS_FEAT(FMLA_zzxz, aa64_sve, do_FMLA_zzxz, a, false) @@ -3550,7 +3550,7 @@ static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = { }; TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz, fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64) + a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) /* *** SVE Floating Point Fast Reduction Group @@ -3583,7 +3583,7 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a, tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg)); - status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); fn(temp, t_zn, t_pg, status, t_desc); @@ -3659,7 +3659,7 @@ static bool do_ppz_fp(DisasContext *s, arg_rpr_esz *a, if (sve_access_check(s)) { unsigned vsz = vec_full_reg_size(s); TCGv_ptr status = - fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), @@ -3696,7 +3696,7 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] = { TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz, ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm | (s->fpcr_ah << 3), - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64) + a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) /* *** SVE Floating Point Accumulating Reduction Group @@ -3729,7 +3729,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a) t_pg = tcg_temp_new_ptr(); tcg_gen_addi_ptr(t_rm, tcg_env, vec_full_reg_offset(s, a->rm)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg)); - t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc); @@ -3829,7 +3829,7 @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16, tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, zn)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); - status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16_A64 : FPST_A64); desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); fn(t_zd, t_zn, t_pg, scalar, status, desc); } @@ -3902,7 +3902,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a, } if (sve_access_check(s)) { unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3935,7 +3935,7 @@ static gen_helper_gvec_4_ptr * const fcadd_fns[] = { }; TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz], a->rd, a->rn, a->rm, a->pg, a->rot | (s->fpcr_ah << 1), - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64) + a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) #define DO_FMLA(NAME, name, ah_name) \ static gen_helper_gvec_5_ptr * const name##_fns[4] = { \ @@ -3949,7 +3949,7 @@ TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz], TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_zzzzp, \ s->fpcr_ah ? name##_ah_fns[a->esz] : name##_fns[a->esz], \ a->rd, a->rn, a->rm, a->ra, a->pg, 0, \ - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64) + a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) /* We don't need an ah_fmla_zpzzz because fmla doesn't negate anything */ DO_FMLA(FMLA_zpzzz, fmla_zpzzz, fmla_zpzzz) @@ -3965,36 +3965,36 @@ static gen_helper_gvec_5_ptr * const fcmla_fns[4] = { }; TRANS_FEAT(FCMLA_zpzzz, aa64_sve, gen_gvec_fpst_zzzzp, fcmla_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->pg, a->rot, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64) + a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) static gen_helper_gvec_4_ptr * const fcmla_idx_fns[4] = { NULL, gen_helper_gvec_fcmlah_idx, gen_helper_gvec_fcmlas_idx, NULL }; TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->index * 4 + a->rot, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64) + a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) /* *** SVE Floating Point Unary Operations Predicated Group */ TRANS_FEAT(FCVT_sh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvt_sh, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvt_sh, a, 0, FPST_A64) TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hs, a, 0, FPST_FPCR_F16_A64) TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvt, a, 0, - s->fpcr_ah ? FPST_FPCR_AH : FPST_FPCR_A64) + s->fpcr_ah ? FPST_FPCR_AH : FPST_A64) TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvt_dh, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvt_dh, a, 0, FPST_A64) TRANS_FEAT(FCVT_hd, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hd, a, 0, FPST_FPCR_F16_A64) TRANS_FEAT(FCVT_ds, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvt_ds, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvt_ds, a, 0, FPST_A64) TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvt_sd, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvt_sd, a, 0, FPST_A64) TRANS_FEAT(FCVTZS_hh, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_hh, a, 0, FPST_FPCR_F16_A64) @@ -4010,22 +4010,22 @@ TRANS_FEAT(FCVTZU_hd, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_hd, a, 0, FPST_FPCR_F16_A64) TRANS_FEAT(FCVTZS_ss, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzs_ss, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvtzs_ss, a, 0, FPST_A64) TRANS_FEAT(FCVTZU_ss, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzu_ss, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvtzu_ss, a, 0, FPST_A64) TRANS_FEAT(FCVTZS_sd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzs_sd, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvtzs_sd, a, 0, FPST_A64) TRANS_FEAT(FCVTZU_sd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzu_sd, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvtzu_sd, a, 0, FPST_A64) TRANS_FEAT(FCVTZS_ds, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzs_ds, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvtzs_ds, a, 0, FPST_A64) TRANS_FEAT(FCVTZU_ds, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzu_ds, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvtzu_ds, a, 0, FPST_A64) TRANS_FEAT(FCVTZS_dd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzs_dd, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvtzs_dd, a, 0, FPST_A64) TRANS_FEAT(FCVTZU_dd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzu_dd, a, 0, FPST_FPCR_A64) + gen_helper_sve_fcvtzu_dd, a, 0, FPST_A64) static gen_helper_gvec_3_ptr * const frint_fns[] = { NULL, @@ -4034,7 +4034,7 @@ static gen_helper_gvec_3_ptr * const frint_fns[] = { gen_helper_sve_frint_d }; TRANS_FEAT(FRINTI, aa64_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz], - a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64) + a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) static gen_helper_gvec_3_ptr * const frintx_fns[] = { NULL, @@ -4043,7 +4043,7 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] = { gen_helper_sve_frintx_d }; TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz], - a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, ARMFPRounding mode, gen_helper_gvec_3_ptr *fn) @@ -4060,7 +4060,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, } vsz = vec_full_reg_size(s); - status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64); + status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); tmode = gen_set_rmode(mode, status); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), @@ -4095,7 +4095,7 @@ static gen_helper_gvec_3_ptr * const fsqrt_fns[] = { gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d, }; TRANS_FEAT(FSQRT, aa64_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz], - a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64) + a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) TRANS_FEAT(SCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_hh, a, 0, FPST_FPCR_F16_A64) @@ -4105,14 +4105,14 @@ TRANS_FEAT(SCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_dh, a, 0, FPST_FPCR_F16_A64) TRANS_FEAT(SCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_scvt_ss, a, 0, FPST_FPCR_A64) + gen_helper_sve_scvt_ss, a, 0, FPST_A64) TRANS_FEAT(SCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_scvt_ds, a, 0, FPST_FPCR_A64) + gen_helper_sve_scvt_ds, a, 0, FPST_A64) TRANS_FEAT(SCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_scvt_sd, a, 0, FPST_FPCR_A64) + gen_helper_sve_scvt_sd, a, 0, FPST_A64) TRANS_FEAT(SCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_scvt_dd, a, 0, FPST_FPCR_A64) + gen_helper_sve_scvt_dd, a, 0, FPST_A64) TRANS_FEAT(UCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_hh, a, 0, FPST_FPCR_F16_A64) @@ -4122,14 +4122,14 @@ TRANS_FEAT(UCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_dh, a, 0, FPST_FPCR_F16_A64) TRANS_FEAT(UCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_ucvt_ss, a, 0, FPST_FPCR_A64) + gen_helper_sve_ucvt_ss, a, 0, FPST_A64) TRANS_FEAT(UCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_ucvt_ds, a, 0, FPST_FPCR_A64) + gen_helper_sve_ucvt_ds, a, 0, FPST_A64) TRANS_FEAT(UCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_ucvt_sd, a, 0, FPST_FPCR_A64) + gen_helper_sve_ucvt_sd, a, 0, FPST_A64) TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_ucvt_dd, a, 0, FPST_FPCR_A64) + gen_helper_sve_ucvt_dd, a, 0, FPST_A64) /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group @@ -7011,10 +7011,10 @@ DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz) TRANS_FEAT_NONSTREAMING(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s, a->rd, a->rn, a->rm, a->ra, - 0, FPST_FPCR_A64) + 0, FPST_A64) TRANS_FEAT_NONSTREAMING(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d, a->rd, a->rn, a->rm, a->ra, - 0, FPST_FPCR_A64) + 0, FPST_A64) static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = { NULL, gen_helper_sve2_sqdmlal_zzzw_h, @@ -7130,18 +7130,18 @@ TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a) TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz, - gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR_A64) + gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) TRANS_FEAT(FCVTNT_ds, aa64_sve2, gen_gvec_fpst_arg_zpz, - gen_helper_sve2_fcvtnt_ds, a, 0, FPST_FPCR_A64) + gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64) TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvtnt, a, 0, - s->fpcr_ah ? FPST_FPCR_AH : FPST_FPCR_A64) + s->fpcr_ah ? FPST_FPCR_AH : FPST_A64) TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz, - gen_helper_sve2_fcvtlt_hs, a, 0, FPST_FPCR_A64) + gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64) TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz, - gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR_A64) + gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64) TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a, FPROUNDING_ODD, gen_helper_sve_fcvt_ds) @@ -7153,7 +7153,7 @@ static gen_helper_gvec_3_ptr * const flogb_fns[] = { gen_helper_flogb_s, gen_helper_flogb_d }; TRANS_FEAT(FLOGB, aa64_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz], - a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_FPCR_A64) + a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel) { @@ -7198,7 +7198,7 @@ static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) { return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal, a->rd, a->rn, a->rm, a->ra, sel, - s->fpcr_ah ? FPST_FPCR_AH : FPST_FPCR_A64); + s->fpcr_ah ? FPST_FPCR_AH : FPST_A64); } TRANS_FEAT(BFMLALB_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, false) @@ -7209,7 +7209,7 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal_idx, a->rd, a->rn, a->rm, a->ra, (a->index << 1) | sel, - s->fpcr_ah ? FPST_FPCR_AH : FPST_FPCR_A64); + s->fpcr_ah ? FPST_FPCR_AH : FPST_A64); } TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) From patchwork Mon Jan 27 23:25:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860282 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp107088wrx; Mon, 27 Jan 2025 15:29:54 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX+WfxuM9CIsgCxwc/FoBZq0nweXoqdH/WlkkS8JAVaebTO/0Tjhq714ogcIWOSP1u8klTYUA==@linaro.org X-Google-Smtp-Source: AGHT+IEOZnkWESN40Wo8TRy4LGEQeONGUiSrJYXVGWIXSgXtGv4dRIx2+85U1vlhyvh1e7ShcDML X-Received: by 2002:a05:620a:2b9b:b0:7b6:d1e1:a239 with SMTP id af79cd13be357-7be631e58d9mr6079891485a.2.1738020594346; Mon, 27 Jan 2025 15:29:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020594; cv=none; d=google.com; s=arc-20240605; b=Pt9u8GfzPoJ8T0Z7Lyzz79Nsms8A+0vFedsZ1fHvvXXhfiBSFOAL9CpIxfcQULX0Px ZxR8B7n4E2uZUrUVmKLKHrnMBFVGvI8KsxKyRSrnVwacjkEhD0lC32o6/8ZrGyhtlk1s WakjSHaspuXAO98WfP9YHm3bqpPXFxIdemNY/UuT/exHWXKNHZbIBPHSDK4xhNJLfzed J3WWTHeMeKplCDrdu6RU4mbrhUE5veg64T+lPxHeLI/dTfQcQvTNYKDinoJ5T+iRQmT3 lIHdwOuyli1cwKuPDAFuq13woKgK+RYfZCAXxRXb8rtrMADlc/+npXF5e08XeH30Pi/l oy/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cEKr8gn5r7dTPdnjanNubYZRqYeexGmGHnTnYnhCaJY=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=iNdDJC4hi19nWzJm5VxWrgU8oBj6AAyDRAwLzvGUC7KpyON0bfdmYvT4yu0bwYvJVU WIWF1NF6JFMY3BkhUkQy8PXFlpZqVNBMDavorGPHHpAjA3nKJqzqEj82njRHoW2n6dLu IzEM9tIsfJguuZQP4ot2p4zPMVMvcZqqr268mTMmNF0myqyhHi7WAqyOXqEMgfrgPqZ6 0KSZcBy8gexef9roCiOtWpiNhSsca/H9BnP46uQA72NzhAMJ7IznAPWKYt6svTVPk+t4 0NQpTW6lGvElpy0pwx94wPFWvUm/+ll89/IhTpe140vrwgJx+w6QctXQv48AsucN/4zU F9bQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PSlkFC3Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7be9af2af50si1066485985a.645.2025.01.27.15.29.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:29:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PSlkFC3Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUq-0006QM-62; Mon, 27 Jan 2025 18:26:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUf-0006Kh-Cu for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:14 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUb-0005We-KB for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:13 -0500 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2f43d17b0e3so8865411a91.0 for ; Mon, 27 Jan 2025 15:26:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020368; x=1738625168; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cEKr8gn5r7dTPdnjanNubYZRqYeexGmGHnTnYnhCaJY=; b=PSlkFC3Z2EqKhl6nuMtDF77SUd6tdoT41TluYEP0jltinzEL7jbdel9SCMJWZNLp3t cnSNyTnjhqni9bsIWSbG6Oi/XI3dPQXS8b+WW9y+IUl7B+/kyKrCF38wJT72L31lFQrr S3OKNbZXjX1MzujaYaoZAQBtgFmpoxq98EUw92Ul3ak2vSmq015UTueDAoHHELjRtrLe EjtHsdZUFj1YO6QddhNzw/TlgIygNdyC0GbxwjgX6uKSRLWn7eghP2Flzp4Ytw5MsrQB PayBUMqZYozXjVXf7inA3qNVO60ZblIHbKZ4eiy8Glz8q/rvqXAnGQqoLYZiHB2xOfZk +K4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020368; x=1738625168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cEKr8gn5r7dTPdnjanNubYZRqYeexGmGHnTnYnhCaJY=; b=uPq/NRuKlDEL+JH05tEslwU4P6G+I7y09QtYcTnTk9v3GJ9Nof4g91Ko4YiqUO7GUt LNR+npCUsvJrwQOm8MH2kgnpA+D0VBxcM6GucOzVI1WjlDsL5xV65Q9N1RtMQLLrwCK5 0dGdHXiYGXkli2iJ60Gn2v23HQGrggVaYoZ1SfWQ0PTJuFuytIoJU920rCY6dYqmqGqA 4QUQaJKll9IiwVP1+Qnb7U+ZDuGHJNA11hUM/QTW2V60PQWQBBiMzYjJsGSo+csbDgTB HptrYVr32OVhBSku9TDLzb4PsCpKJ8HfQv1RV+UdD8JlNm2UtXOXPtVBaEPYkpebz7zH HlpQ== X-Gm-Message-State: AOJu0YyQo5KrxZPH7O8EYJfXwpcCSTKoQozymHh5y2kjzSpoAWA/EaGM 9hCxjzEbEcbAr5p12InVakbrm8W9Fmzg4IQVLaYwWmRu3i8SPd52lb5lX0P8Zd5nMLQueAoQ3aQ Q X-Gm-Gg: ASbGncvJT4Pu6WiQ/a6lzYSKPK5T12TFFjm83aiWgNUA4tdkcPZCztbplIwW54AJuKQ aJ1Q58cU/x3LoKbwFPWGRqYlkSAmsStXHyUxRnHeZBvIlUYpI1ctrFg4V71oHCIW62GnldIZdu9 noCy2oJ1kfzUnA0S/jAB2CugiXb+EKPSdDA19esd2q69F/HIkl2UWUdkk1QTc+EPdtJxTO9gJRr tEA1vJCtR371nv/0MlTWSGPb943/FLjKEPaOJlNLUqnA5GltVp57E3Dqy+8q6yn+eweRc9mJeNn u0aJ8jMx2lKywURWWcsM+YFBNOkJiFn5DX8X/Ek= X-Received: by 2002:a17:90b:3bc3:b0:2ee:9b2c:3253 with SMTP id 98e67ed59e1d1-2f782d97961mr62019512a91.30.1738020368100; Mon, 27 Jan 2025 15:26:08 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 03/22] target/arm: Rename FPST_FPCR_F16_A32 to FPST_A32_F16 Date: Mon, 27 Jan 2025 15:25:45 -0800 Message-ID: <20250127232604.20386-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 6 +++--- target/arm/tcg/translate-vfp.c | 24 ++++++++++++------------ 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 2edb707b85..adf6eb8b91 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -676,7 +676,7 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) typedef enum ARMFPStatusFlavour { FPST_A32, FPST_A64, - FPST_FPCR_F16_A32, + FPST_A32_F16, FPST_FPCR_F16_A64, FPST_FPCR_AH, FPST_FPCR_AH_F16, @@ -696,7 +696,7 @@ typedef enum ARMFPStatusFlavour { * for AArch32 non-FP16 operations controlled by the FPCR * FPST_A64 * for AArch64 non-FP16 operations controlled by the FPCR - * FPST_FPCR_F16_A32 + * FPST_A32_F16 * for AArch32 operations controlled by the FPCR where FPCR.FZ16 is to be used * FPST_FPCR_F16_A64 * for AArch64 operations controlled by the FPCR where FPCR.FZ16 is to be used @@ -723,7 +723,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) case FPST_A64: offset = offsetof(CPUARMState, vfp.fp_status_a64); break; - case FPST_FPCR_F16_A32: + case FPST_A32_F16: offset = offsetof(CPUARMState, vfp.fp_status_f16_a32); break; case FPST_FPCR_F16_A64: diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 4cc12a407b..8d9d1ab877 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -460,7 +460,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) } if (sz == 1) { - fpst = fpstatus_ptr(FPST_FPCR_F16_A32); + fpst = fpstatus_ptr(FPST_A32_F16); } else { fpst = fpstatus_ptr(FPST_A32); } @@ -527,7 +527,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) } if (sz == 1) { - fpst = fpstatus_ptr(FPST_FPCR_F16_A32); + fpst = fpstatus_ptr(FPST_A32_F16); } else { fpst = fpstatus_ptr(FPST_A32); } @@ -1433,7 +1433,7 @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn, /* * Do a half-precision operation. Functionally this is * the same as do_vfp_3op_sp(), except: - * - it uses the FPST_FPCR_F16_A32 + * - it uses the FPST_A32_F16 * - it doesn't need the VFP vector handling (fp16 is a * v8 feature, and in v8 VFP vectors don't exist) * - it does the aa32_fp16_arith feature test @@ -1456,7 +1456,7 @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn, f0 = tcg_temp_new_i32(); f1 = tcg_temp_new_i32(); fd = tcg_temp_new_i32(); - fpst = fpstatus_ptr(FPST_FPCR_F16_A32); + fpst = fpstatus_ptr(FPST_A32_F16); vfp_load_reg16(f0, vn); vfp_load_reg16(f1, vm); @@ -2122,7 +2122,7 @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) /* VFNMA, VFNMS */ gen_vfp_negh(vd, vd); } - fpst = fpstatus_ptr(FPST_FPCR_F16_A32); + fpst = fpstatus_ptr(FPST_A32_F16); gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst); vfp_store_reg32(vd, a->vd); return true; @@ -2424,7 +2424,7 @@ DO_VFP_2OP(VNEG, dp, gen_vfp_negd, aa32_fpdp_v2) static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm) { - gen_helper_vfp_sqrth(vd, vm, fpstatus_ptr(FPST_FPCR_F16_A32)); + gen_helper_vfp_sqrth(vd, vm, fpstatus_ptr(FPST_A32_F16)); } static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm) @@ -2706,7 +2706,7 @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a) tmp = tcg_temp_new_i32(); vfp_load_reg16(tmp, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_F16_A32); + fpst = fpstatus_ptr(FPST_A32_F16); gen_helper_rinth(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); return true; @@ -2779,7 +2779,7 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a) tmp = tcg_temp_new_i32(); vfp_load_reg16(tmp, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_F16_A32); + fpst = fpstatus_ptr(FPST_A32_F16); tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst); gen_helper_rinth(tmp, tmp, fpst); gen_restore_rmode(tcg_rmode, fpst); @@ -2859,7 +2859,7 @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a) tmp = tcg_temp_new_i32(); vfp_load_reg16(tmp, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_F16_A32); + fpst = fpstatus_ptr(FPST_A32_F16); gen_helper_rinth_exact(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); return true; @@ -2983,7 +2983,7 @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a) vm = tcg_temp_new_i32(); vfp_load_reg32(vm, a->vm); - fpst = fpstatus_ptr(FPST_FPCR_F16_A32); + fpst = fpstatus_ptr(FPST_A32_F16); if (a->s) { /* i32 -> f16 */ gen_helper_vfp_sitoh(vm, vm, fpst); @@ -3105,7 +3105,7 @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a) vd = tcg_temp_new_i32(); vfp_load_reg32(vd, a->vd); - fpst = fpstatus_ptr(FPST_FPCR_F16_A32); + fpst = fpstatus_ptr(FPST_A32_F16); shift = tcg_constant_i32(frac_bits); /* Switch on op:U:sx bits */ @@ -3273,7 +3273,7 @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a) return true; } - fpst = fpstatus_ptr(FPST_FPCR_F16_A32); + fpst = fpstatus_ptr(FPST_A32_F16); vm = tcg_temp_new_i32(); vfp_load_reg16(vm, a->vm); From patchwork Mon Jan 27 23:25:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860277 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106823wrx; Mon, 27 Jan 2025 15:28:50 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXVNP9Ub/uJz8hKjFO6mvMLA0XixN4PDYArHBMlTAVkTGeu8PCNhTHE8olZeKJtB7NKDB49AQ==@linaro.org X-Google-Smtp-Source: AGHT+IHrVzPCmiPEc6Ba5bB4QiSDjpnsNHCRgGynSeHhnRGlGRt2X/G64l2j3F/Bq9NI2XzNIJIC X-Received: by 2002:a05:620a:4892:b0:7b6:dfbb:3227 with SMTP id af79cd13be357-7be6320fa7dmr6337455485a.10.1738020529866; Mon, 27 Jan 2025 15:28:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020529; cv=none; d=google.com; s=arc-20240605; b=lNbsWvzmrSNHkmgbKuj5fLAidr9uFCP89DenMxVPmCBwLlW9c08XzLr+piLcQ/bIn1 RMmxwFmQePM/WU0xOM5XoF4NO113Z1MHHqbnmDx+isu35lBXPV0CeR6pyENCfk86c9xh dZOsRBsv7CHvD61cyZwYGNPrZmBywBonDj4JR37/2aPYnDLPdGzb2dHahG7o49SKwXHb mu+yjTIIV/TV+cQ2bQD9hYxPZ9/dRmDMTyWe6uDKXELwyiH5S8nE6GqPqn1vT7ebQqU+ kc6NXK6RFepntGh3xwRyf7yXCRaYm/1ggUCED3G+ExOEq7i/ckuCpqZE81AsEAR34IRi DQ0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yk4nAud5otRzQ3dxne70+kFMJfAxDBcEqlullUGNgUE=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=OMCsU6x56MRrocplLrljRcVKZZKBCqx6xy7D3DZiBON2Fxdb6pfB+Io1dL+DR3oNwh JlSCj7hQhTwDUmgr51+PWEBf34GU+6wmOzAx7MlUZkUyj5pACX9Hhm6bnelZD5HfMgXq rzzaEPcQTMbBO+mxbMoXZKKd6/vIQ76m6TIlSjRFa8iWdDiCZFvQFimAtNIXbQS4RqvF pyWmqKRYRiQm2UYW5Y6mWYkGK+fgwBgL4y9ZTEbe7hg8WsVy5dVBLLOHBK0KZZDImn+E jC/ogyh+g0r4VDZF/oRZ1995YCYCyRZw8Ao7YA/QjEIdRpg2GfaKgx4WfHMQM3VnTvGK Oe0g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rQPYryXj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7be9aee0890si1057146585a.231.2025.01.27.15.28.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:28:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rQPYryXj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUr-0006Rp-EG; Mon, 27 Jan 2025 18:26:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUg-0006LO-MV for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:15 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUc-0005Wz-L3 for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:14 -0500 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2ee46851b5eso6656700a91.1 for ; Mon, 27 Jan 2025 15:26:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020369; x=1738625169; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yk4nAud5otRzQ3dxne70+kFMJfAxDBcEqlullUGNgUE=; b=rQPYryXj5R7EmOj9Xuc3NLw5eo+lMh089TT+gzvwGiaA8beDnnz4qt5gZIWm/07Ryp 8K0FGlv5F8VxZKnB0wev+OFHfRzW3wiMTe6HoCUgpCnqh9XToScHwDvO7CK6bwJ9XHxm Co+pNtLueNdMWfm6FDY8RMDiTY1oWppdooV6i4+pNWHoryxkgBq4ij/4P9K3AAJkJ9cY kdzJ4jXAayMedaL3QAxqPDB8b531X+2M5gwkqJ61VGqrqXSxjYgi8dWHhaQU6WYI4uEM rxDVLBB7TiY7O95p4Wjf9If9Cho+vGkzC+v9hKf0kK6XFVtmb+bOLhq4EIuV6xzsetIk RhPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020369; x=1738625169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yk4nAud5otRzQ3dxne70+kFMJfAxDBcEqlullUGNgUE=; b=t7Hco4YJPdRwTuod8wte+xA5zSDWNGFnhZfx7wZUgAlsrGNKSIgRFefMn0TGgJael7 UZ7QcfLDKBFGeAvXUjaB4S4ZFN2XsUKS+0I/OLi88KuzLNfAd6G2aiUUMHrZC2AoyjAX opc955GEipDVhhcLdvn3YdF1yND+f0IphfDkSGq6sILrHXFLv+qp7kuoWYhkX3jCM+wb ToukFzeOSOwlrLD3qxgACb0q0XqS124e4t6O51AkMA0IsFkweqEPvAbO+3XrtE0//TR5 DBMdv2DNGHe2hqkknytQ2ArLDZiO6OgoKesQOoGvjda/kzbhnXv0sd3gpnhAXKfyKf6c z+fw== X-Gm-Message-State: AOJu0YzdOZUn5OuU+SmGjHFw9e6j43LAFtx33rBntHir9a03sjJxBagh NqbK+k3AuldYIUKKm7t2ZH/TIjTEW6r/5x/li96tovhxCYhoCvm1LuVv50/hXpRvdIDdJbf4inP H X-Gm-Gg: ASbGncuaCVIkao7xtLZXv5faQUoDxGTu8w8Vso9g2fSKT6FF2MQA7EMRep561BeCMmR uocbxa5BnoDMbChssgDReKmTHYeEsGqm95/DylPKWoN7410dye4FEdlwixf7GtEKQUw1PIVs+sq 9YNf4PdUlHDHVHVfciQz8C1TpP7YwTbQIHPeRBIfXzPR1rSWB7BiyBkOSCxgeVIq8lLZu94+EUK k4FdLKFgLt7OoCQps7jxxlHVeKHdUqgjYA80sqX2+3UyR7FaSQ1U23nxGHPLjxTxUPsfznHhLlR o2tzcSFlOyqsPos8bp3lH3vtdnQlOKRUy+ImAzc= X-Received: by 2002:a17:90b:2b86:b0:2ee:accf:9685 with SMTP id 98e67ed59e1d1-2f782c50be4mr61030363a91.4.1738020368872; Mon, 27 Jan 2025 15:26:08 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 04/22] target/arm: Rename FPST_FPCR_F16_A64 to FPST_A64_F16 Date: Mon, 27 Jan 2025 15:25:46 -0800 Message-ID: <20250127232604.20386-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 8 ++--- target/arm/tcg/translate-a64.c | 44 +++++++++++------------ target/arm/tcg/translate-sve.c | 66 +++++++++++++++++----------------- 3 files changed, 59 insertions(+), 59 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index adf6eb8b91..cc753419ed 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -677,7 +677,7 @@ typedef enum ARMFPStatusFlavour { FPST_A32, FPST_A64, FPST_A32_F16, - FPST_FPCR_F16_A64, + FPST_A64_F16, FPST_FPCR_AH, FPST_FPCR_AH_F16, FPST_STD, @@ -698,7 +698,7 @@ typedef enum ARMFPStatusFlavour { * for AArch64 non-FP16 operations controlled by the FPCR * FPST_A32_F16 * for AArch32 operations controlled by the FPCR where FPCR.FZ16 is to be used - * FPST_FPCR_F16_A64 + * FPST_A64_F16 * for AArch64 operations controlled by the FPCR where FPCR.FZ16 is to be used * FPST_FPCR_AH: * for AArch64 operations which change behaviour when AH=1 (specifically, @@ -726,7 +726,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) case FPST_A32_F16: offset = offsetof(CPUARMState, vfp.fp_status_f16_a32); break; - case FPST_FPCR_F16_A64: + case FPST_A64_F16: offset = offsetof(CPUARMState, vfp.fp_status_f16_a64); break; case FPST_FPCR_AH: @@ -757,7 +757,7 @@ static inline ARMFPStatusFlavour select_fpst(DisasContext *s, MemOp esz) if (s->fpcr_ah) { return esz == MO_16 ? FPST_FPCR_AH_F16 : FPST_FPCR_AH; } else { - return esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64; + return esz == MO_16 ? FPST_A64_F16 : FPST_A64; } } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index bf17ecca80..35d409685c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -5247,7 +5247,7 @@ static bool do_fp3_scalar(DisasContext *s, arg_rrr_e *a, const FPScalar *f, { return do_fp3_scalar_with_fpsttype(s, a, f, mergereg, a->esz == MO_16 ? - FPST_FPCR_F16_A64 : FPST_A64); + FPST_A64_F16 : FPST_A64); } static bool do_fp3_scalar_ah_2fn(DisasContext *s, arg_rrr_e *a, @@ -5533,9 +5533,9 @@ static bool do_fcmp0_s(DisasContext *s, arg_rr_e *a, TCGv_i32 t0 = read_fp_hreg(s, a->rn); TCGv_i32 t1 = tcg_constant_i32(0); if (swap) { - f->gen_h(t0, t1, t0, fpstatus_ptr(FPST_FPCR_F16_A64)); + f->gen_h(t0, t1, t0, fpstatus_ptr(FPST_A64_F16)); } else { - f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16_A64)); + f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16)); } write_fp_sreg(s, a->rd, t0); } @@ -5768,7 +5768,7 @@ static bool do_fp3_vector(DisasContext *s, arg_qrrr_e *a, int data, { return do_fp3_vector_with_fpsttype(s, a, data, fns, a->esz == MO_16 ? - FPST_FPCR_F16_A64 :FPST_A64); + FPST_A64_F16 :FPST_A64); } static bool do_fp3_vector_2fn(DisasContext *s, arg_qrrr_e *a, int data, @@ -6174,7 +6174,7 @@ static bool trans_FCMLA_v(DisasContext *s, arg_FCMLA_v *a) } gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64, + a->esz == MO_16 ? FPST_A64_F16 : FPST_A64, a->rot, fn[a->esz]); return true; } @@ -6566,7 +6566,7 @@ static bool do_fp3_scalar_idx(DisasContext *s, arg_rrx_e *a, const FPScalar *f) TCGv_i32 t1 = tcg_temp_new_i32(); read_vec_element_i32(s, t1, a->rm, a->idx, MO_16); - f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16_A64)); + f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16)); write_fp_hreg_merging(s, a->rd, a->rn, t0); } break; @@ -6624,7 +6624,7 @@ static bool do_fmla_scalar_idx(DisasContext *s, arg_rrx_e *a, bool neg) gen_vfp_maybe_ah_negh(s, t1, t1); } gen_helper_advsimd_muladdh(t0, t1, t2, t0, - fpstatus_ptr(FPST_FPCR_F16_A64)); + fpstatus_ptr(FPST_A64_F16)); write_fp_hreg_merging(s, a->rd, a->rd, t0); } break; @@ -6721,7 +6721,7 @@ static bool do_fp3_vector_idx(DisasContext *s, arg_qrrx_e *a, } gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm, - esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64, + esz == MO_16 ? FPST_A64_F16 : FPST_A64, a->idx, fns[esz - 1]); return true; } @@ -6755,7 +6755,7 @@ static bool do_fmla_vector_idx(DisasContext *s, arg_qrrx_e *a, bool neg) } gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd, - esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64, + esz == MO_16 ? FPST_A64_F16 : FPST_A64, (s->fpcr_ah << 5) | (a->idx << 1) | neg, fns[esz - 1]); return true; @@ -6921,7 +6921,7 @@ static bool trans_FCMLA_vi(DisasContext *s, arg_FCMLA_vi *a) } if (fp_access_check(s)) { gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64, + a->esz == MO_16 ? FPST_A64_F16 : FPST_A64, (a->idx << 2) | a->rot, fn); } return true; @@ -6966,7 +6966,7 @@ static bool do_fp3_scalar_pair(DisasContext *s, arg_rr_e *a, const FPScalar *f) read_vec_element_i32(s, t0, a->rn, 0, MO_16); read_vec_element_i32(s, t1, a->rn, 1, MO_16); - f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16_A64)); + f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16)); write_fp_sreg(s, a->rd, t0); } break; @@ -7148,7 +7148,7 @@ static bool do_fmadd(DisasContext *s, arg_rrrr_e *a, bool neg_a, bool neg_n) if (neg_n) { gen_vfp_maybe_ah_negh(s, tn, tn); } - fpst = fpstatus_ptr(FPST_FPCR_F16_A64); + fpst = fpstatus_ptr(FPST_A64_F16); gen_helper_advsimd_muladdh(ta, tn, tm, ta, fpst); write_fp_hreg_merging(s, a->rd, a->ra, ta); } @@ -7243,7 +7243,7 @@ static bool do_fp_reduction(DisasContext *s, arg_qrr_e *a, if (fp_access_check(s)) { MemOp esz = a->esz; int elts = (a->q ? 16 : 8) >> esz; - TCGv_ptr fpst = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + TCGv_ptr fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64); TCGv_i32 res = do_reduction_op(s, a->rn, esz, 0, elts, fpst, s->fpcr_ah ? fah : fnormal); write_fp_sreg(s, a->rd, res); @@ -7294,7 +7294,7 @@ static void handle_fp_compare(DisasContext *s, int size, bool cmp_with_zero, bool signal_all_nans) { TCGv_i64 tcg_flags = tcg_temp_new_i64(); - TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_A64_F16 : FPST_A64); if (size == MO_64) { TCGv_i64 tcg_vn, tcg_vm; @@ -8829,7 +8829,7 @@ static bool do_fp1_scalar(DisasContext *s, arg_rr_e *a, { return do_fp1_scalar_with_fpsttype(s, a, f, rmode, a->esz == MO_16 ? - FPST_FPCR_F16_A64 : FPST_A64); + FPST_A64_F16 : FPST_A64); } static bool do_fp1_scalar_ah(DisasContext *s, arg_rr_e *a, @@ -8999,7 +8999,7 @@ static bool trans_FCVT_s_sh(DisasContext *s, arg_rr *a) if (fp_access_check(s)) { TCGv_i32 tcg_rn = read_fp_hreg(s, a->rn); TCGv_i32 tcg_rd = tcg_temp_new_i32(); - TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_FPCR_F16_A64); + TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_A64_F16); TCGv_i32 tcg_ahp = get_ahp_flag(); gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); @@ -9013,7 +9013,7 @@ static bool trans_FCVT_s_dh(DisasContext *s, arg_rr *a) if (fp_access_check(s)) { TCGv_i32 tcg_rn = read_fp_hreg(s, a->rn); TCGv_i64 tcg_rd = tcg_temp_new_i64(); - TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_FPCR_F16_A64); + TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_A64_F16); TCGv_i32 tcg_ahp = get_ahp_flag(); gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); @@ -9029,7 +9029,7 @@ static bool do_cvtf_scalar(DisasContext *s, MemOp esz, int rd, int shift, TCGv_i32 tcg_shift, tcg_single; TCGv_i64 tcg_double; - tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64); tcg_shift = tcg_constant_i32(shift); switch (esz) { @@ -9124,7 +9124,7 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz, TCGv_ptr tcg_fpstatus; TCGv_i32 tcg_shift, tcg_rmode, tcg_single; - tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64); tcg_shift = tcg_constant_i32(shift); tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus); @@ -9773,7 +9773,7 @@ static bool do_fp1_vector(DisasContext *s, arg_qrr_e *a, return check == 0; } - fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64); if (rmode >= 0) { tcg_rmode = gen_set_rmode(rmode, fpst); } @@ -9847,7 +9847,7 @@ static bool do_gvec_op2_fpst(DisasContext *s, MemOp esz, bool is_q, gen_helper_gvec_2_ptr * const fns[3]) { return do_gvec_op2_fpst_with_fpsttype(s, esz, is_q, rd, rn, data, fns, - esz == MO_16 ? FPST_FPCR_F16_A64 : + esz == MO_16 ? FPST_A64_F16 : FPST_A64); } @@ -10024,7 +10024,7 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a) TCGv_i32 tcg_res[4]; TCGv_i32 ahp = get_ahp_flag(); - fpst = fpstatus_ptr(FPST_FPCR_F16_A64); + fpst = fpstatus_ptr(FPST_A64_F16); for (pass = 0; pass < 4; pass++) { tcg_res[pass] = tcg_temp_new_i32(); diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 3cc678154a..3811316a2d 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -191,7 +191,7 @@ static bool gen_gvec_fpst_arg_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn, arg_rrr_esz *a, int data) { return gen_gvec_fpst_zzz(s, fn, a->rd, a->rn, a->rm, data, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + a->esz == MO_16 ? FPST_A64_F16 : FPST_A64); } static bool gen_gvec_fpst_ah_arg_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn, @@ -404,7 +404,7 @@ static bool gen_gvec_fpst_arg_zpzz(DisasContext *s, gen_helper_gvec_4_ptr *fn, arg_rprr_esz *a) { return gen_gvec_fpst_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + a->esz == MO_16 ? FPST_A64_F16 : FPST_A64); } /* Invoke a vector expander on two Zregs and an immediate. */ @@ -3534,7 +3534,7 @@ static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub) }; return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, (s->fpcr_ah << 5) | (a->index << 1) | sub, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + a->esz == MO_16 ? FPST_A64_F16 : FPST_A64); } TRANS_FEAT(FMLA_zzxz, aa64_sve, do_FMLA_zzxz, a, false) @@ -3550,7 +3550,7 @@ static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = { }; TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz, fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) + a->esz == MO_16 ? FPST_A64_F16 : FPST_A64) /* *** SVE Floating Point Fast Reduction Group @@ -3583,7 +3583,7 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a, tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg)); - status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + status = fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64); fn(temp, t_zn, t_pg, status, t_desc); @@ -3659,7 +3659,7 @@ static bool do_ppz_fp(DisasContext *s, arg_rpr_esz *a, if (sve_access_check(s)) { unsigned vsz = vec_full_reg_size(s); TCGv_ptr status = - fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64); tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), @@ -3696,7 +3696,7 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] = { TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz, ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm | (s->fpcr_ah << 3), - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) + a->esz == MO_16 ? FPST_A64_F16 : FPST_A64) /* *** SVE Floating Point Accumulating Reduction Group @@ -3729,7 +3729,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a) t_pg = tcg_temp_new_ptr(); tcg_gen_addi_ptr(t_rm, tcg_env, vec_full_reg_offset(s, a->rm)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg)); - t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64); t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc); @@ -3829,7 +3829,7 @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16, tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, zn)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); - status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16_A64 : FPST_A64); + status = fpstatus_ptr(is_fp16 ? FPST_A64_F16 : FPST_A64); desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); fn(t_zd, t_zn, t_pg, scalar, status, desc); } @@ -3902,7 +3902,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a, } if (sve_access_check(s)) { unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64); tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3935,7 +3935,7 @@ static gen_helper_gvec_4_ptr * const fcadd_fns[] = { }; TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz], a->rd, a->rn, a->rm, a->pg, a->rot | (s->fpcr_ah << 1), - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) + a->esz == MO_16 ? FPST_A64_F16 : FPST_A64) #define DO_FMLA(NAME, name, ah_name) \ static gen_helper_gvec_5_ptr * const name##_fns[4] = { \ @@ -3949,7 +3949,7 @@ TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz], TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_zzzzp, \ s->fpcr_ah ? name##_ah_fns[a->esz] : name##_fns[a->esz], \ a->rd, a->rn, a->rm, a->ra, a->pg, 0, \ - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) + a->esz == MO_16 ? FPST_A64_F16 : FPST_A64) /* We don't need an ah_fmla_zpzzz because fmla doesn't negate anything */ DO_FMLA(FMLA_zpzzz, fmla_zpzzz, fmla_zpzzz) @@ -3965,14 +3965,14 @@ static gen_helper_gvec_5_ptr * const fcmla_fns[4] = { }; TRANS_FEAT(FCMLA_zpzzz, aa64_sve, gen_gvec_fpst_zzzzp, fcmla_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->pg, a->rot, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) + a->esz == MO_16 ? FPST_A64_F16 : FPST_A64) static gen_helper_gvec_4_ptr * const fcmla_idx_fns[4] = { NULL, gen_helper_gvec_fcmlah_idx, gen_helper_gvec_fcmlas_idx, NULL }; TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->index * 4 + a->rot, - a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) + a->esz == MO_16 ? FPST_A64_F16 : FPST_A64) /* *** SVE Floating Point Unary Operations Predicated Group @@ -3981,7 +3981,7 @@ TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz], TRANS_FEAT(FCVT_sh, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_sh, a, 0, FPST_A64) TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvt_hs, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16) TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvt, a, 0, @@ -3990,24 +3990,24 @@ TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_dh, a, 0, FPST_A64) TRANS_FEAT(FCVT_hd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvt_hd, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_fcvt_hd, a, 0, FPST_A64_F16) TRANS_FEAT(FCVT_ds, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_ds, a, 0, FPST_A64) TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_sd, a, 0, FPST_A64) TRANS_FEAT(FCVTZS_hh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzs_hh, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_fcvtzs_hh, a, 0, FPST_A64_F16) TRANS_FEAT(FCVTZU_hh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzu_hh, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_fcvtzu_hh, a, 0, FPST_A64_F16) TRANS_FEAT(FCVTZS_hs, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzs_hs, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_fcvtzs_hs, a, 0, FPST_A64_F16) TRANS_FEAT(FCVTZU_hs, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzu_hs, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_fcvtzu_hs, a, 0, FPST_A64_F16) TRANS_FEAT(FCVTZS_hd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzs_hd, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_fcvtzs_hd, a, 0, FPST_A64_F16) TRANS_FEAT(FCVTZU_hd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzu_hd, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_fcvtzu_hd, a, 0, FPST_A64_F16) TRANS_FEAT(FCVTZS_ss, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_ss, a, 0, FPST_A64) @@ -4034,7 +4034,7 @@ static gen_helper_gvec_3_ptr * const frint_fns[] = { gen_helper_sve_frint_d }; TRANS_FEAT(FRINTI, aa64_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz], - a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) + a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64) static gen_helper_gvec_3_ptr * const frintx_fns[] = { NULL, @@ -4043,7 +4043,7 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] = { gen_helper_sve_frintx_d }; TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz], - a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64); static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, ARMFPRounding mode, gen_helper_gvec_3_ptr *fn) @@ -4060,7 +4060,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, } vsz = vec_full_reg_size(s); - status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64); + status = fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64); tmode = gen_set_rmode(mode, status); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), @@ -4095,14 +4095,14 @@ static gen_helper_gvec_3_ptr * const fsqrt_fns[] = { gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d, }; TRANS_FEAT(FSQRT, aa64_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz], - a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) + a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64) TRANS_FEAT(SCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_scvt_hh, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_scvt_hh, a, 0, FPST_A64_F16) TRANS_FEAT(SCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_scvt_sh, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_scvt_sh, a, 0, FPST_A64_F16) TRANS_FEAT(SCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_scvt_dh, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_scvt_dh, a, 0, FPST_A64_F16) TRANS_FEAT(SCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_ss, a, 0, FPST_A64) @@ -4115,11 +4115,11 @@ TRANS_FEAT(SCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_dd, a, 0, FPST_A64) TRANS_FEAT(UCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_ucvt_hh, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_ucvt_hh, a, 0, FPST_A64_F16) TRANS_FEAT(UCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_ucvt_sh, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_ucvt_sh, a, 0, FPST_A64_F16) TRANS_FEAT(UCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_ucvt_dh, a, 0, FPST_FPCR_F16_A64) + gen_helper_sve_ucvt_dh, a, 0, FPST_A64_F16) TRANS_FEAT(UCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_ss, a, 0, FPST_A64) @@ -7153,7 +7153,7 @@ static gen_helper_gvec_3_ptr * const flogb_fns[] = { gen_helper_flogb_s, gen_helper_flogb_d }; TRANS_FEAT(FLOGB, aa64_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz], - a, 0, a->esz == MO_16 ? FPST_FPCR_F16_A64 : FPST_A64) + a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64) static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel) { From patchwork Mon Jan 27 23:25:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860274 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106596wrx; Mon, 27 Jan 2025 15:27:57 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWkcknC2op6bzTsGMVF/Ox78t/WzULvrKwHFA4lnAuphYQi6FeqsQRcM2vfW+dGUeUE41HV0g==@linaro.org X-Google-Smtp-Source: AGHT+IGU0rm73vahsw4/DkGbMycbfTD2Md/IFapoiRiuBwhmDnTYjyR1rCCPlKsEfne8CAbHKmQF X-Received: by 2002:a05:622a:18a6:b0:46c:77bc:ce57 with SMTP id d75a77b69052e-46e12b7646bmr635560191cf.36.1738020477044; Mon, 27 Jan 2025 15:27:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020477; cv=none; d=google.com; s=arc-20240605; b=PKpGlnQ7Y4kqPHqBIq25PKi3jBzRQI2E2zHE+0lb4yvEGFqVBcdNr883uEvAndeu4i 2FIGM0Tp5GjkYkP4EuNsyAkcLB16GNnRGkepYWgPY3ea34ci5e+xItAsMq6sTVWNkVtX YZ8hExL5RZ2XNRrQORUAa1TUB7KVUY3ezA5qdbiin2VDpyQK3Z9dQuKNBzHD5V9doEWe PF3pKqKGxPtEueP2RzgfkZlq7aM5AQ9Jb45iaJoeP1Wkoz2HHLGb+kROOryQ5uUohW5/ 4gV5zg1t+t0BJdJLCoPsoiRJ740TxD2yf3ffTRw1HK8WdyxhcOqk4qDgfJyEiUdyZTiT 144Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hnjx8Waa96G3DLJHBV92lDnt+x0jZGLfU8ED3iHDbpE=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=WLBfcYjc/5Sx/Uj271IDbA8lE6owt2x/iTQA7NSggziBvb/Yq+WGmNs/uzNZPHTbLQ I0irJaVbaxLiM+L4wInW1fY0b645wv2yXfdzRkk/f6QL5rDKrjXCgQZ6WUbgsOnU2zOJ VUCNF0+6m8HoWq76fEQeJFWdq8d6LMVVncPPS9XFo5SrzhfFurIk483Jq40q8ozBMK65 qsJAEelZUiDe09cZdPdMyl6WrAOURnPSbI8WAhE9T0NMbiPjMkNHOTOtrHhzYVzCdK02 ANGz5b/jmldqqaxKoi1cHnkGRmLV0HbcKY3X7YtRMYKczrHnHiD6/02Yh+RNRcbQZrYq EYiQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nTS8vb05; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46e66b8b5f9si115953011cf.441.2025.01.27.15.27.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:27:57 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nTS8vb05; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUt-0006Sc-9z; Mon, 27 Jan 2025 18:26:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUh-0006LU-3d for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:15 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUd-0005XE-7G for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:14 -0500 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-2f441791e40so6622017a91.3 for ; Mon, 27 Jan 2025 15:26:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020370; x=1738625170; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hnjx8Waa96G3DLJHBV92lDnt+x0jZGLfU8ED3iHDbpE=; b=nTS8vb05LdYEEDfJ7gtcFi2h37MHPZs6OS/XDBi6qUPgJJmhvtveaV3KQtrzdjLvcj n9uuZg3QJcHxdx0KByCpN+KlIggVVculUOksnrmMQxOtVsS6D9G+S0idV/zJ5DzPFqMh 1CVxN3zNWeoWBPx3ykg5zw40Es8tM9YKCdLm3xrJMnZ7Kks5WR8xNWiGU+iKlUFpLHaR 3w/V0BtQzXPAZdH/V3KfKGR/E3TbY2kc/t+bwciwM6Ry2YK1Btxa3M3lmrxHQEjxtPZC 27u4833fBbn6IP+mLGcOUpNv69s1PTB3j76I3glPyZdWNnlLJKDt/l1RfvAIXNUKB5Zl hRuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020370; x=1738625170; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hnjx8Waa96G3DLJHBV92lDnt+x0jZGLfU8ED3iHDbpE=; b=B/tERWCdCmaF/C55gPh8AhmgjpXFi07J+xv1mOf/zUaiM9N1KoCoYdG5qieggocTh6 f/ZkMwMO0YsCNwaH0UnuMNyKcjQwPi6vBv7bNBMwkbVozjaC9rul36z+l+7mXMpEmiHB kxu7QgBLWvE8stNdRFcIUntIjnl1zEBcQK775578YuW8v6Hdj80CboJ7NsaoC1j5pPIN K2QbytTgm+PzVWMAzL3Xmz2Dp9firMCC1DvjoL1R9gzpxf4n++GYSg5062dg3FjF1VL9 yvO+gVUMs+4jBKUWNr3v2OCGx4gW5XCyjnTCfxiCeJ4dnvWC+ad+yKZcVrffIUiWSo4X HHwg== X-Gm-Message-State: AOJu0YyvhhDPAXqWkGsUOhfA9aG9if02jOhvGPqp+4xJN+BsLUxbQaeX Ll8rEGa6YPplc/tAuoU/YaWmgozj5hGsJQLBaNxuHYjq1rRZCkWA/irKG4K+buofdC6+qgm+WSk 8 X-Gm-Gg: ASbGncup/aCLFPH38Ilhtu+pcfqTi5/Pad1zVZPkrCGEPKXWj35A8jXDROfE13ZUddl zd0gduVJfPDnB/rppmb5aGIdBkAvsMQBJXbs0SYpuZu8iQvOx+QzX0yDJSatA7AyCABfvprUx7/ cpAyA7zuQHPszP5utBsE1rA1AZLREEP853ks/jNJrxBBS6Tv84kMHnHauZXvu23SiefsOFVHm5O naRvVoDNF54oI89OKwMZ4ySp1G4YZviCYfAnQx24bQozasuPmGDOx7ssg7t08Wicv48+kn0z4LB rVPrCLihDJP21Ek6pWt+Zqr7NqmwFzI165HYc1CY9EGo5t9lgA== X-Received: by 2002:a17:90b:3a0e:b0:2ee:b4bf:2d06 with SMTP id 98e67ed59e1d1-2f782cb9fe6mr57602224a91.19.1738020369660; Mon, 27 Jan 2025 15:26:09 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 05/22] target/arm: Rename FPST_FPCR_AH* to FPST_AH* Date: Mon, 27 Jan 2025 15:25:47 -0800 Message-ID: <20250127232604.20386-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 14 +++++++------- target/arm/tcg/translate-a64.c | 8 ++++---- target/arm/tcg/translate-sve.c | 8 ++++---- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index cc753419ed..d4ae39c469 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -678,8 +678,8 @@ typedef enum ARMFPStatusFlavour { FPST_A64, FPST_A32_F16, FPST_A64_F16, - FPST_FPCR_AH, - FPST_FPCR_AH_F16, + FPST_AH, + FPST_AH_F16, FPST_STD, FPST_STD_F16, } ARMFPStatusFlavour; @@ -700,11 +700,11 @@ typedef enum ARMFPStatusFlavour { * for AArch32 operations controlled by the FPCR where FPCR.FZ16 is to be used * FPST_A64_F16 * for AArch64 operations controlled by the FPCR where FPCR.FZ16 is to be used - * FPST_FPCR_AH: + * FPST_AH: * for AArch64 operations which change behaviour when AH=1 (specifically, * bfloat16 conversions and multiplies, and the reciprocal and square root * estimate/step insns) - * FPST_FPCR_AH_F16: + * FPST_AH_F16: * ditto, but for half-precision operations * FPST_STD * for A32/T32 Neon operations using the "standard FPSCR value" @@ -729,10 +729,10 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) case FPST_A64_F16: offset = offsetof(CPUARMState, vfp.fp_status_f16_a64); break; - case FPST_FPCR_AH: + case FPST_AH: offset = offsetof(CPUARMState, vfp.ah_fp_status); break; - case FPST_FPCR_AH_F16: + case FPST_AH_F16: offset = offsetof(CPUARMState, vfp.ah_fp_status_f16); break; case FPST_STD: @@ -755,7 +755,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) static inline ARMFPStatusFlavour select_fpst(DisasContext *s, MemOp esz) { if (s->fpcr_ah) { - return esz == MO_16 ? FPST_FPCR_AH_F16 : FPST_FPCR_AH; + return esz == MO_16 ? FPST_AH_F16 : FPST_AH; } else { return esz == MO_16 ? FPST_A64_F16 : FPST_A64; } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 35d409685c..715760a17b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6135,7 +6135,7 @@ static bool trans_BFMLAL_v(DisasContext *s, arg_qrrr_e *a) if (fp_access_check(s)) { /* Q bit selects BFMLALB vs BFMLALT. */ gen_gvec_op4_fpst(s, true, a->rd, a->rn, a->rm, a->rd, - s->fpcr_ah ? FPST_FPCR_AH : FPST_A64, a->q, + s->fpcr_ah ? FPST_AH : FPST_A64, a->q, gen_helper_gvec_bfmlal); } return true; @@ -6892,7 +6892,7 @@ static bool trans_BFMLAL_vi(DisasContext *s, arg_qrrx_e *a) if (fp_access_check(s)) { /* Q bit selects BFMLALB vs BFMLALT. */ gen_gvec_op4_fpst(s, true, a->rd, a->rn, a->rm, a->rd, - s->fpcr_ah ? FPST_FPCR_AH : FPST_A64, + s->fpcr_ah ? FPST_AH : FPST_A64, (a->idx << 1) | a->q, gen_helper_gvec_bfmlal_idx); } @@ -8866,7 +8866,7 @@ TRANS(FRINTX_s, do_fp1_scalar, a, &f_scalar_frintx, -1) static bool trans_BFCVT_s(DisasContext *s, arg_rr_e *a) { - ARMFPStatusFlavour fpsttype = s->fpcr_ah ? FPST_FPCR_AH : FPST_A64; + ARMFPStatusFlavour fpsttype = s->fpcr_ah ? FPST_AH : FPST_A64; TCGv_i32 t32; int check; @@ -9691,7 +9691,7 @@ static void gen_bfcvtn_hs(TCGv_i64 d, TCGv_i64 n) static void gen_bfcvtn_ah_hs(TCGv_i64 d, TCGv_i64 n) { - TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR_AH); + TCGv_ptr fpst = fpstatus_ptr(FPST_AH); TCGv_i32 tmp = tcg_temp_new_i32(); gen_helper_bfcvt_pair(tmp, n, fpst); tcg_gen_extu_i32_i64(d, tmp); diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 3811316a2d..cb6bb27622 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -3985,7 +3985,7 @@ TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz, TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvt, a, 0, - s->fpcr_ah ? FPST_FPCR_AH : FPST_A64) + s->fpcr_ah ? FPST_AH : FPST_A64) TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_dh, a, 0, FPST_A64) @@ -7136,7 +7136,7 @@ TRANS_FEAT(FCVTNT_ds, aa64_sve2, gen_gvec_fpst_arg_zpz, TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvtnt, a, 0, - s->fpcr_ah ? FPST_FPCR_AH : FPST_A64) + s->fpcr_ah ? FPST_AH : FPST_A64) TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64) @@ -7198,7 +7198,7 @@ static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) { return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal, a->rd, a->rn, a->rm, a->ra, sel, - s->fpcr_ah ? FPST_FPCR_AH : FPST_A64); + s->fpcr_ah ? FPST_AH : FPST_A64); } TRANS_FEAT(BFMLALB_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, false) @@ -7209,7 +7209,7 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal_idx, a->rd, a->rn, a->rm, a->ra, (a->index << 1) | sel, - s->fpcr_ah ? FPST_FPCR_AH : FPST_A64); + s->fpcr_ah ? FPST_AH : FPST_A64); } TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) From patchwork Mon Jan 27 23:25:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860284 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp107095wrx; Mon, 27 Jan 2025 15:29:55 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUhF626HMSgdz2wqiH77ZyyxX7mjbfadPssQlxcnYvxJG/9zSQndiX7B2Jinf9t1JPnk6K3KA==@linaro.org X-Google-Smtp-Source: AGHT+IE5h9jQJfppUsNoQ/5McYrKn4KwXwe2I8TUZ4GljJCkJt9HFGvLM6lh49SysySgHE248XZu X-Received: by 2002:a05:620a:25cf:b0:7be:3965:7452 with SMTP id af79cd13be357-7be6320d293mr6522044785a.32.1738020595393; Mon, 27 Jan 2025 15:29:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020595; cv=none; d=google.com; s=arc-20240605; b=KW90CA2JrrMAeZn+fhsuREFU1PGrkjr++BXoc8+NuIWjiijLtZ3MajF+G8fFXHMMMH hYEC7J1CRs4mJ3S/p6v880r8zciYUhtCvMnsP2GkZ3wvqOLuX9o2DM83eJoOfArENz/N OuntiaVMcG+8JD0nejFMfOvHcwKC6vderIg872BHxpku65Za4YRg7QKxaUOpTBXH2rx+ ZZkhwHypi09c21GIiuK/FYkFRZ2TvAlNob8Fhp9LNyq/FQfHQF0skZVHTvZ3IUZx4lQX q449JfAidOg81o8iTssP0+k5LH38ptwENbD739L154xfvxmrrNT7Ar/B/+b88GMaYdSq N+zQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6vVvCoSEED6StCi5sBDfcgbMdG6XA3WhhdL8usKsqm8=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=ZZ8nOaK/1zTLMpcZyhODu5eOLp72fdK6mUfDx3IbNAfzqtjuCRbH4kdViYvyhYgkD8 YsoAEzpVa7vfNPaEVEpudmntzkP/k+thiMO3l3Y+Rnc5HP+SpzkND8v2Fx7QCiLIpivO HrgZiabA+t/bj2uRqnGplkqn+dRPpGh78xWss2UHMVoGNdLVtNkvRUcnqic7Kl/6rG3C dB3EL1ip7NONw+8Ihv+e7qUAmG0wPuYrTI3uyuHxCuoDUGDmhDIWrjMhrBLqk/+ELHQ9 2TOtT0EqupPkxYolUdMu10Ylzpl/IuC4SWHRc9m2Sc3nL96/IXc6xHMNiCqjveheZXV6 FSFQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b3Say35n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7be9aee1525si1215433285a.211.2025.01.27.15.29.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:29:55 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b3Say35n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUr-0006Rr-Gq; Mon, 27 Jan 2025 18:26:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUh-0006LX-5l for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:15 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUd-0005XZ-LT for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:14 -0500 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2ee709715d9so6948913a91.3 for ; Mon, 27 Jan 2025 15:26:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020370; x=1738625170; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6vVvCoSEED6StCi5sBDfcgbMdG6XA3WhhdL8usKsqm8=; b=b3Say35nkh5LlZ4EeLZIf7j3CmlNnU2mTQNIKs+sA3jYP8YbqhPCWfOtIzGRtou/JE V83LZidyEBIXpgVmycYPDVxHo2qwfrnkzWCNUOAxI0qHzF0rdrfRgLYKjdGipAhTbTSO YYlnaWNN1d56vQ6glKJG9sTV8UlF9y6nqJQprUPzUfSA/RR5caC8mDzwRS4ESKL4br1W Pbjce1Ly3To1l7lIgFJE1zn7WcN0/e0i+eVK2Ysrx2BMFxtOKTKDi/vg6QO4c/26o241 /0H4oZ4WuABymSJhQ8ck7Hzn7tHpPKgJMbV0SzBWKuAoUp+xI0/JRWo2rZ6YidxWdl42 8JRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020370; x=1738625170; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6vVvCoSEED6StCi5sBDfcgbMdG6XA3WhhdL8usKsqm8=; b=abp+qHHYxhmKsd8BzwNNwo/wLbwJoQm5MhcfgXzsVeL41BN7NZ1u2KCb2+PsfFBGXX XOux2hZMLoaLykTMFSRDNbeEVu2QbAbpcX48gDcpKIKZqSH0oryxMBnXV092Jm3SRpDl /YGXeuWybaz3POQOgv2f0DZrtrNZlBBGE7tVx4vvBYsdrpj7/stSx3tqDMwqaW5Dpjkr dVRKC3QBg2nxVzIo8J6xKLDiuSBaTojvzU2qxuzP9zapqYT0K+peiAHTYFEFRp8g+aJz LgtH/ine9f7yiFrbki6nwbvyQjU/9NY4FatvcV3xyk97MeOH4t2FAW3Ncfu4tTvHyAsk BdWg== X-Gm-Message-State: AOJu0YxbiB17U3b6PBGBAUjbDSZMAjW7tMjA2oBX7uZxXxZ3Jxj9aNXl mQkq2dt3djRY5SBjHDMgPdUOfdC3VqBCEqVZz/uJ1EmZqJAFjssTp2apOdoNNTWQ+8xqNn0Bh1W j X-Gm-Gg: ASbGncvKxeiGSzHyShkY7zGQhsSxyGd4IhZnbsUs+ZtNprKtpkOUc8Vvyr1TiiJROsi BqgiCNI/QMxvY7cl+VEBHSaGCmZ5uV4+snlFJz0JR2Y+KXYzoETxWPZprPkHSK8MnLHpEnRQzVE 3Ozka/Z8XvMEOgIdcAhSz4rRVy6H2+BPFyhXAab2gskZ9gAL7UBsVJVCWVx0oJ1fyP917zwt5pD 6QsiOw0s6nTxUbMwNpwMxHRxhbbTQDxRSwYLvuVlNP8MG5YJqAhGfVyMMYj+Qd8PmR5A0ZzfVxd P4T/hEKI9EpePX0l2oU0QtHEdoH0BHL9WGqWbHI= X-Received: by 2002:a17:90b:534b:b0:2f6:f107:fae6 with SMTP id 98e67ed59e1d1-2f782d32397mr51458002a91.23.1738020370305; Mon, 27 Jan 2025 15:26:10 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 06/22] target/arm: Introduce CPUARMState.vfp.fp_status[] Date: Mon, 27 Jan 2025 15:25:48 -0800 Message-ID: <20250127232604.20386-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move ARMFPStatusFlavour to cpu.h with which to index this array. For now, place the array in an anonymous union with the existing structures. Adjust the order of the existing structures to match the enum. Simplify fpstatus_ptr() using the new array. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 119 +++++++++++++++++++++---------------- target/arm/tcg/translate.h | 64 +------------------- 2 files changed, 70 insertions(+), 113 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f562e0687c..c025649ff2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -202,6 +202,61 @@ typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; typedef struct NVICState NVICState; +/* + * Enum for indexing vfp.fp_status[]. + * + * FPST_A32: is the "normal" fp status for AArch32 insns + * FPST_A64: is the "normal" fp status for AArch64 insns + * FPST_A32_F16: used for AArch32 half-precision calculations + * FPST_A64_F16: used for AArch64 half-precision calculations + * FPST_STD: the ARM "Standard FPSCR Value" + * FPST_STD_F16: used for half-precision + * calculations with the ARM "Standard FPSCR Value" + * FPST_AH: used for the A64 insns which change behaviour + * when FPCR.AH == 1 (bfloat16 conversions and multiplies, + * and the reciprocal and square root estimate/step insns) + * FPST_AH_F16: used for the A64 insns which change behaviour + * when FPCR.AH == 1 (bfloat16 conversions and multiplies, + * and the reciprocal and square root estimate/step insns); + * for half-precision + * + * Half-precision operations are governed by a separate + * flush-to-zero control bit in FPSCR:FZ16. We pass a separate + * status structure to control this. + * + * The "Standard FPSCR", ie default-NaN, flush-to-zero, + * round-to-nearest and is used by any operations (generally + * Neon) which the architecture defines as controlled by the + * standard FPSCR value rather than the FPSCR. + * + * The "standard FPSCR but for fp16 ops" is needed because + * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than + * using a fixed value for it. + * + * The ah_fp_status is needed because some insns have different + * behaviour when FPCR.AH == 1: they don't update cumulative + * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and + * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16, + * which means we need an ah_fp_status_f16 as well. + * + * To avoid having to transfer exception bits around, we simply + * say that the FPSCR cumulative exception flags are the logical + * OR of the flags in the four fp statuses. This relies on the + * only thing which needs to read the exception flags being + * an explicit FPSCR read. + */ +typedef enum ARMFPStatusFlavour { + FPST_A32, + FPST_A64, + FPST_A32_F16, + FPST_A64_F16, + FPST_AH, + FPST_AH_F16, + FPST_STD, + FPST_STD_F16, +} ARMFPStatusFlavour; +#define FPST_COUNT 8 + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -631,56 +686,20 @@ typedef struct CPUArchState { /* Scratch space for aa32 neon expansion. */ uint32_t scratch[8]; - /* There are a number of distinct float control structures: - * - * fp_status_a32: is the "normal" fp status for AArch32 insns - * fp_status_a64: is the "normal" fp status for AArch64 insns - * fp_status_fp16_a32: used for AArch32 half-precision calculations - * fp_status_fp16_a64: used for AArch64 half-precision calculations - * standard_fp_status : the ARM "Standard FPSCR Value" - * standard_fp_status_fp16 : used for half-precision - * calculations with the ARM "Standard FPSCR Value" - * ah_fp_status: used for the A64 insns which change behaviour - * when FPCR.AH == 1 (bfloat16 conversions and multiplies, - * and the reciprocal and square root estimate/step insns) - * ah_fp_status_f16: used for the A64 insns which change behaviour - * when FPCR.AH == 1 (bfloat16 conversions and multiplies, - * and the reciprocal and square root estimate/step insns); - * for half-precision - * - * Half-precision operations are governed by a separate - * flush-to-zero control bit in FPSCR:FZ16. We pass a separate - * status structure to control this. - * - * The "Standard FPSCR", ie default-NaN, flush-to-zero, - * round-to-nearest and is used by any operations (generally - * Neon) which the architecture defines as controlled by the - * standard FPSCR value rather than the FPSCR. - * - * The "standard FPSCR but for fp16 ops" is needed because - * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than - * using a fixed value for it. - * - * The ah_fp_status is needed because some insns have different - * behaviour when FPCR.AH == 1: they don't update cumulative - * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and - * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16, - * which means we need an ah_fp_status_f16 as well. - * - * To avoid having to transfer exception bits around, we simply - * say that the FPSCR cumulative exception flags are the logical - * OR of the flags in the four fp statuses. This relies on the - * only thing which needs to read the exception flags being - * an explicit FPSCR read. - */ - float_status fp_status_a32; - float_status fp_status_a64; - float_status fp_status_f16_a32; - float_status fp_status_f16_a64; - float_status standard_fp_status; - float_status standard_fp_status_f16; - float_status ah_fp_status; - float_status ah_fp_status_f16; + /* There are a number of distinct float control structures. */ + union { + float_status fp_status[FPST_COUNT]; + struct { + float_status fp_status_a32; + float_status fp_status_a64; + float_status fp_status_f16_a32; + float_status fp_status_f16_a64; + float_status ah_fp_status; + float_status ah_fp_status_f16; + float_status standard_fp_status; + float_status standard_fp_status_f16; + }; + }; uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index d4ae39c469..6f854f1031 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -670,80 +670,18 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) return (CPUARMTBFlags){ tb->flags, tb->cs_base }; } -/* - * Enum for argument to fpstatus_ptr(). - */ -typedef enum ARMFPStatusFlavour { - FPST_A32, - FPST_A64, - FPST_A32_F16, - FPST_A64_F16, - FPST_AH, - FPST_AH_F16, - FPST_STD, - FPST_STD_F16, -} ARMFPStatusFlavour; - /** * fpstatus_ptr: return TCGv_ptr to the specified fp_status field * * We have multiple softfloat float_status fields in the Arm CPU state struct * (see the comment in cpu.h for details). Return a TCGv_ptr which has * been set up to point to the requested field in the CPU state struct. - * The options are: - * - * FPST_A32 - * for AArch32 non-FP16 operations controlled by the FPCR - * FPST_A64 - * for AArch64 non-FP16 operations controlled by the FPCR - * FPST_A32_F16 - * for AArch32 operations controlled by the FPCR where FPCR.FZ16 is to be used - * FPST_A64_F16 - * for AArch64 operations controlled by the FPCR where FPCR.FZ16 is to be used - * FPST_AH: - * for AArch64 operations which change behaviour when AH=1 (specifically, - * bfloat16 conversions and multiplies, and the reciprocal and square root - * estimate/step insns) - * FPST_AH_F16: - * ditto, but for half-precision operations - * FPST_STD - * for A32/T32 Neon operations using the "standard FPSCR value" - * FPST_STD_F16 - * as FPST_STD, but where FPCR.FZ16 is to be used */ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) { TCGv_ptr statusptr = tcg_temp_new_ptr(); - int offset; + int offset = offsetof(CPUARMState, vfp.fp_status[flavour]); - switch (flavour) { - case FPST_A32: - offset = offsetof(CPUARMState, vfp.fp_status_a32); - break; - case FPST_A64: - offset = offsetof(CPUARMState, vfp.fp_status_a64); - break; - case FPST_A32_F16: - offset = offsetof(CPUARMState, vfp.fp_status_f16_a32); - break; - case FPST_A64_F16: - offset = offsetof(CPUARMState, vfp.fp_status_f16_a64); - break; - case FPST_AH: - offset = offsetof(CPUARMState, vfp.ah_fp_status); - break; - case FPST_AH_F16: - offset = offsetof(CPUARMState, vfp.ah_fp_status_f16); - break; - case FPST_STD: - offset = offsetof(CPUARMState, vfp.standard_fp_status); - break; - case FPST_STD_F16: - offset = offsetof(CPUARMState, vfp.standard_fp_status_f16); - break; - default: - g_assert_not_reached(); - } tcg_gen_addi_ptr(statusptr, tcg_env, offset); return statusptr; } From patchwork Mon Jan 27 23:25:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860281 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp107037wrx; Mon, 27 Jan 2025 15:29:43 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXRPZc7KUJaeTbLdflsIbBOj3qGyMrbbNzaPFv9LY2aVP7tHkxidv9JWxtsRlkHgJNxVNnWHQ==@linaro.org X-Google-Smtp-Source: AGHT+IFiLkcu2OkRJeH1B9cE+bDSIQ4MfUlC3zqysxTHg1hCAsqhRR+3QbHLd8ChK4SUm8x4xcmK X-Received: by 2002:a05:622a:4c:b0:463:6bc4:2a23 with SMTP id d75a77b69052e-46e12861f3emr581824961cf.0.1738020583583; Mon, 27 Jan 2025 15:29:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020583; cv=none; d=google.com; s=arc-20240605; b=gTogzviSW7PcaUeQXTXzrR/TztyiLpZ7D3qfnXgORxkDmMFfHbM49BzfyjYF3t/M1k GaFks07eoXYm3d7ceYgU3Wbb0kqywgcyI4I9r2aE665IHPkY3F5xe7RJ3ADEA4fNVgs9 s3nP/c7uTUPBcvU1seLUnL6OwcP5UlrJIdj3lDQUqGz0PW2BsMC8Rsj5isMOS1BrJZhi x8jPnjwBzSUUcPiiUfCK+YZ9FZmzsfUJRv8mWTcbT0d3rlQ8Z9gXUpxgZnHOYbqF25Ve 9PhOuxiL0bko8yrEmMDNbuU0WBdHRxaNT08SbQl1QBBp+OtX7uHEDn1hgYYG//ZaXPph JkwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/sdwLV8iKeS70T4jE5aOB3XPO2jkT8fDK3S2SuLEEx4=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=brnHP9PtZ6ZZZPHV7Sn3LhZ+LEW3IKElbCdKzwC2nk6CYwaIlV9yyzaAwwA+JXHhdr fgXC9BNZbk0U5lZ/DSy5c6tbk7GWOH+jOPNO8MhaUYmXeCHWUOeH263cJmptFQvEpFS5 tGRJreUrrA9ZkqG+GzW6A+VjUr/fXQTC6a/XbO+JfCiMnbwoinYbJ5Df2GJOumdAe5KX sQuhx7AjtKgcSJ708EAGqg56o1ha4wWg2r+XZfxvAimeyhmOdBrEyK9B/22ZrThEecPu I8omX64aXoo+TxbImzH8vt9Q9evS9zZB2qknmnTrvuEwaECOS2EPjbBaf2ClRBoSj9jg PhIg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zVxfAI7n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46e66ba579dsi120508641cf.481.2025.01.27.15.29.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:29:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zVxfAI7n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUr-0006Rq-GD; Mon, 27 Jan 2025 18:26:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUi-0006MV-Q4 for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:19 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUe-0005Xp-Et for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:16 -0500 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-2ee67e9287fso8638659a91.0 for ; Mon, 27 Jan 2025 15:26:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020371; x=1738625171; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/sdwLV8iKeS70T4jE5aOB3XPO2jkT8fDK3S2SuLEEx4=; b=zVxfAI7nuE7oQwB7Gw38SnqENV6q89lAmaLvD0nQGTQhPQqqY09eiVaciwir7U9wtm 31PXpKSTOBfSJqgl70ihvTYGKwHQbQR5p/PMxNs549qVG4gSfEoIGZWM1raGMWJ/vsPG AsbbZ6R2LORAaNT3qOMaF9Tkl9GEIV3VEswu290ufroy7WbfGrnbOHdenNcn/v+mhUrA EKFkU0POapQd/+82mKFCeqJpKAPt32cimYqdq+tU3vhNdvKjO8DFDquHpQ7CsZ3FwAjb 95CyL4CEdVREyDavuBFk9gXvd0hR9ZFPScL2vaeMG20fFyvGjkAAXPcJhF2dxJ45stfg KBYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020371; x=1738625171; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/sdwLV8iKeS70T4jE5aOB3XPO2jkT8fDK3S2SuLEEx4=; b=aHj/wb/hczplKt3dD7M450oakuG0Tpf48kvevqej/tB+SYhJGDeLfP0vYFT/aGcg7E wCKC2g2Wb25sJD5nldB0pmkVo13QXUqTJgP5eXVfP71P7o+LAKWVssjBDx07xtyUajMq dkcqMf2zNmA+SkAKFL8N5fllqXnDui7PeQVc76YWyfBEuF4W+YC+MoFXqaQl1nJpnj2V d/OPqCWrajw/1kX1prj5gzGCBMQk2Go2cvE7ZicqbkXu9jAPZYvLr0b2uXk4gBFDQbuv dnCwTzx4PZy7wq8cF+GSfQrRbGfxTkGJBML0I0Eb3YcrMEf0wnV4rHOXUBdAmv7Rvg+D kvdQ== X-Gm-Message-State: AOJu0YzMrzidOGfIicb6GTFtx3YNTKnEoYFhrYF7XMfn5yB9gIBPhxqE CtX92e6An7ncoOuVy5iEgC+bP+I1TyCogUgZAhuQ5KYAsC5e0wsgMXNLWddzfAqoXeROw1l40sW x X-Gm-Gg: ASbGncvpBiJuJQF+uukN06H9JsnC2biNx5Fzw19gC2n50UwVB10+474bJ0zKcu6WDQd +PxTfFNOvzS+o4ybt3nKNKFTueTS+gAROxz5IfVvShzK7RLzh7at52NMTioCi6OpysJx5erUucK 98uCXacg8HHu/0FCfWKxcjJ4KkJlG+sWK4aUAdQd3UjWPFzcjLR4udMtC0PMpFh9ONxuZh27Kip hf0Kx2Rd0WuamkFgQ6oAvI4/6QHgF0yvqsgrzpVKQbWWwzS3yNz0ZaYoR6arsEKwGsl7ldCzYdK tG2lsmKlGpz24dLt5ckn/G0k07sZMvgq626yKMM= X-Received: by 2002:a17:90b:540b:b0:2f2:8bdd:cd8b with SMTP id 98e67ed59e1d1-2f782d972a2mr59914566a91.29.1738020371067; Mon, 27 Jan 2025 15:26:11 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 07/22] target/arm: Remove standard_fp_status_f16 Date: Mon, 27 Jan 2025 15:25:49 -0800 Message-ID: <20250127232604.20386-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace with fp_status[FPST_STD_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 - target/arm/cpu.c | 4 ++-- target/arm/tcg/mve_helper.c | 24 ++++++++++++------------ target/arm/vfp_helper.c | 8 ++++---- 4 files changed, 18 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c025649ff2..893a2cdd0a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -697,7 +697,6 @@ typedef struct CPUArchState { float_status ah_fp_status; float_status ah_fp_status_f16; float_status standard_fp_status; - float_status standard_fp_status_f16; }; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8fa220a716..b887edf1d1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -549,13 +549,13 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type) set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); set_default_nan_mode(1, &env->vfp.standard_fp_status); - set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); + set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status_a32); arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); arm_set_default_fp_behaviours(&env->vfp.standard_fp_status); arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a32); arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64); - arm_set_default_fp_behaviours(&env->vfp.standard_fp_status_f16); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); arm_set_ah_fp_behaviours(&env->vfp.ah_fp_status); set_flush_to_zero(1, &env->vfp.ah_fp_status); set_flush_inputs_to_zero(1, &env->vfp.ah_fp_status); diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 03ebef5ef2..911a53a23a 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -2814,7 +2814,7 @@ DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \ + fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ @@ -2888,7 +2888,7 @@ DO_2OP_FP_ALL(vminnma, minnuma) r[e] = 0; \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \ + fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ if (!(tm & 1)) { \ /* We need the result but without updating flags */ \ @@ -2926,7 +2926,7 @@ DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \ + fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ @@ -2964,7 +2964,7 @@ DO_VFMA(vfmss, 4, float32, true) if ((mask & MAKE_64BIT_MASK(0, ESIZE * 2)) == 0) { \ continue; \ } \ - fpst0 = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \ + fpst0 = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ fpst1 = fpst0; \ if (!(mask & 1)) { \ @@ -3049,7 +3049,7 @@ DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \ + fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ @@ -3084,7 +3084,7 @@ DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \ + fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ @@ -3117,7 +3117,7 @@ DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) TYPE *m = vm; \ TYPE ra = (TYPE)ra_in; \ float_status *fpst = (ESIZE == 2) ? \ - &env->vfp.standard_fp_status_f16 : \ + &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ if (mask & 1) { \ @@ -3168,7 +3168,7 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) if ((mask & emask) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \ + fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ if (!(mask & (1 << (e * ESIZE)))) { \ /* We need the result but without updating flags */ \ @@ -3202,7 +3202,7 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) if ((mask & emask) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \ + fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ if (!(mask & (1 << (e * ESIZE)))) { \ /* We need the result but without updating flags */ \ @@ -3267,7 +3267,7 @@ DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \ + fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ @@ -3301,7 +3301,7 @@ DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) float_status *fpst; \ float_status scratch_fpst; \ float_status *base_fpst = (ESIZE == 2) ? \ - &env->vfp.standard_fp_status_f16 : \ + &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ uint32_t prev_rmode = get_float_rounding_mode(base_fpst); \ set_float_rounding_mode(rmode, base_fpst); \ @@ -3427,7 +3427,7 @@ void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \ + fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ &env->vfp.standard_fp_status; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index e63455c4bb..28c2b40bd8 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -122,7 +122,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) /* FZ16 does not generate an input denormal exception. */ a32_flags |= (get_float_exception_flags(&env->vfp.fp_status_f16_a32) & ~float_flag_input_denormal_flushed); - a32_flags |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16) + a32_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_STD_F16]) & ~float_flag_input_denormal_flushed); a64_flags |= get_float_exception_flags(&env->vfp.fp_status_a64); @@ -158,7 +158,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env) set_float_exception_flags(0, &env->vfp.fp_status_f16_a32); set_float_exception_flags(0, &env->vfp.fp_status_f16_a64); set_float_exception_flags(0, &env->vfp.standard_fp_status); - set_float_exception_flags(0, &env->vfp.standard_fp_status_f16); + set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD_F16]); set_float_exception_flags(0, &env->vfp.ah_fp_status); set_float_exception_flags(0, &env->vfp.ah_fp_status_f16); } @@ -205,11 +205,11 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) bool ftz_enabled = val & FPCR_FZ16; set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64); - set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); set_flush_to_zero(ftz_enabled, &env->vfp.ah_fp_status_f16); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64); - set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.ah_fp_status_f16); } if (changed & FPCR_FZ) { From patchwork Mon Jan 27 23:25:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860275 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106683wrx; Mon, 27 Jan 2025 15:28:17 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV2lx95Qh5WPmNcgzNzOnBFa7poFtUWsYiioILo5MUr7PSb9pYUQOLKEaNhXx0uFeLrxz/HyA==@linaro.org X-Google-Smtp-Source: AGHT+IHDkpFba69jE3mXlVD6NifGwYjPmOCUtfT8DOoNzfQgWLhlQE+6wHrT9LEY/TB8xPQHnKzB X-Received: by 2002:a05:620a:3913:b0:7b6:7970:6506 with SMTP id af79cd13be357-7be6327cfd5mr6190231985a.38.1738020497438; Mon, 27 Jan 2025 15:28:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020497; cv=none; d=google.com; s=arc-20240605; b=WBEr8kdHQxMfu6moX0gZG2deIKZZLtbirAwWC3RR+mFKHelW8TZ4Db1HBeu0VHruSh ZiTnKV74nk3tsgPuvSMu1dLWiOnkbPdz5PksOYu98yBBaezC8hSegKq3yd5LgSWsD+8p B7HYggHq3nDVn1X8aiCy/nAN6GFhYlZrRtRtjbM6eRIxMM6/Dlb2FTm713NU5XGScZxf xTQfRIr3S2/Y6ydMWmtdztYC/b9IbV1tDlLo1Z39Q77CiOmiQwyuyWunGAkVCL3D/ASc ZZjJ/dAPF/b8EI93lTu6k9PLGOcFth+gog9C30Oy8E6HbMpbVUEhVbOxEywguO5yyZFM h4/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/o3PZF+VYx9BlUZcSvSihlV0semqIWO9oR/VySJrxZU=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=Z4dpnUxFK6yPd1ioX6Yf3VhTUcd1zANc2XBSc+8rlTLGChT9Obnxvgfc+FtKcla0BN quQaraugDy3GuTXHtrdJHwyT24BKV+AG1pxbYPTJIwsRP6cpU4hwkMV7l/DZRGkQxqT+ LCFmFCBtfv9LNEuOSSnob8oHR9+pEsO+SELhkFsVVES7vQBPIdEPOSAFgkXLVl3APYXh 2URAnlyR6ZHq4oB4AOYh69yBQx812bF3fYq19YsnMDgP8RA3ydAeTbqVPe1yYjjuuhrY 1iPQMYwY+XW3Ut7jiPVmtcY6Wf4ZHCf/8fab9VKpPmhszxYVaTqO9MYGVYKD9dS/ObYl H4cA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Rzb15ux/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7be9ae9457csi1094954385a.185.2025.01.27.15.28.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:28:17 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Rzb15ux/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUz-0006Wi-6B; Mon, 27 Jan 2025 18:26:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUj-0006My-3z for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:19 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUf-0005YJ-4b for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:16 -0500 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-2ee51f8c47dso6926210a91.1 for ; Mon, 27 Jan 2025 15:26:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020372; x=1738625172; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/o3PZF+VYx9BlUZcSvSihlV0semqIWO9oR/VySJrxZU=; b=Rzb15ux/7EOLJ3GAR4OQv5DXtEUzx+sKvE0HQsvA/vo8y7OjpdxGAkmWgw2zNN3XGO IE7sacTamWvdFFKryOu/X6KXYehsKLvuTEaaTOOAq+ToZjZsrRtCN1cCV1zzE5/Wf6NB +j4JA5If9jhRM6OcW/vB4qM/4x1+ta/AsaTeJQfiP+Lo7x3oqitgsIHJwJpZ/WuzEgZk OBPDUsIcGPmi1zcCJzDFTvhd8f+4MUdoKVBuK5IwugNVM69dDdFQ9CPBfpc7EdUDWTH9 2jhbTiSv4+BkBtCdRA5QZWG/yLkA9FR4Wk9bNWgL6Q2TBNxE49J6UhYisUiToRVtY481 3Kkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020372; x=1738625172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/o3PZF+VYx9BlUZcSvSihlV0semqIWO9oR/VySJrxZU=; b=xLGTg8EMwljLI13IRXB8qjzFFhhf9MILbAXJ/oCccGZXJOIJhYCld2bdEO0O1lS+O2 tBlni/CEvUvzyf12xm+EEY1JxUeWgPLtwsv+VL+dcUtSL9VRve3Srs21JC1U/vey68y/ pp99zJJnf93264bNitYA+ECixLM8f2RbkTSw0vctLtI/TmSqUFSL5QB05OIDTy/AwEfw b7yFG9KityrhY0e798ZIzK3Ep/8rdmCgp+x9fHUxH+83JNU5HeGSapiBzPm8JrhTDDGt OIrh/CF1mluxvFN9H1/RKT3YbeW3bgSeskPQaIehDqlLs1BudYt6mWdCIRj6nmSQguQR VHvw== X-Gm-Message-State: AOJu0Yw9MXPbro0Fr9WAyaucmzlNZMjP9o/SFaL0hcE22IAHk8bXvxHH dStJI6Aaj/4eH3jTdDwuflc1UEUNbiPav93Aq91L5UDtG5OcsyjKm7bkVpM9qrLGcq+8AkbqDqc U X-Gm-Gg: ASbGncvDYfjuOlyH/vd64W/cLSpzSEMYqoTYm1datLr3VTArdlV+UtHmeS/jnBxL8HN e9sJx98Vciajm/ZuH2I/vDj7e1OJk4PX865ESap/JiOysotwHbRclRtQ+Hn2zf32Fu5ts1WKfMA kJt/tzugcBnJ4ojNbPE9nSSS1iHGnsO6DFpNX3NSsAd0t80u9pNks8hT/cMOE66ZubCKDlrXSos ku4308usC52IESeFrECzv1Pfw3beo4ioeciJIBH0ZGS7HgjftugQ9G+iLFnnHK3qFWSEgt3eZnE FTt2bd56nYigRd/JQCe5lHP6JU3ayFOJYbVIKMA= X-Received: by 2002:a17:90b:17d0:b0:2ee:e518:c1d8 with SMTP id 98e67ed59e1d1-2f782d972b9mr62185463a91.30.1738020371729; Mon, 27 Jan 2025 15:26:11 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 08/22] target/arm: Remove standard_fp_status Date: Mon, 27 Jan 2025 15:25:50 -0800 Message-ID: <20250127232604.20386-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace with fp_status[FPST_STD]. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 - target/arm/cpu.c | 8 ++++---- target/arm/tcg/mve_helper.c | 28 ++++++++++++++-------------- target/arm/tcg/vec_helper.c | 4 ++-- target/arm/vfp_helper.c | 4 ++-- 5 files changed, 22 insertions(+), 23 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 893a2cdd0a..18afff8509 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -696,7 +696,6 @@ typedef struct CPUArchState { float_status fp_status_f16_a64; float_status ah_fp_status; float_status ah_fp_status_f16; - float_status standard_fp_status; }; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b887edf1d1..26e3465a4b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -546,13 +546,13 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type) env->sau.ctrl = 0; } - set_flush_to_zero(1, &env->vfp.standard_fp_status); - set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); - set_default_nan_mode(1, &env->vfp.standard_fp_status); + set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]); + set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]); + set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status_a32); arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); - arm_set_default_fp_behaviours(&env->vfp.standard_fp_status); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a32); arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 911a53a23a..3763d71e20 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -2815,7 +2815,7 @@ DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) continue; \ } \ fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -2889,7 +2889,7 @@ DO_2OP_FP_ALL(vminnma, minnuma) continue; \ } \ fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ if (!(tm & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -2927,7 +2927,7 @@ DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) continue; \ } \ fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -2965,7 +2965,7 @@ DO_VFMA(vfmss, 4, float32, true) continue; \ } \ fpst0 = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ fpst1 = fpst0; \ if (!(mask & 1)) { \ scratch_fpst = *fpst0; \ @@ -3050,7 +3050,7 @@ DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) continue; \ } \ fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -3085,7 +3085,7 @@ DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) continue; \ } \ fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -3118,7 +3118,7 @@ DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) TYPE ra = (TYPE)ra_in; \ float_status *fpst = (ESIZE == 2) ? \ &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ if (mask & 1) { \ TYPE v = m[H##ESIZE(e)]; \ @@ -3169,7 +3169,7 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) continue; \ } \ fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ if (!(mask & (1 << (e * ESIZE)))) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -3203,7 +3203,7 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) continue; \ } \ fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ if (!(mask & (1 << (e * ESIZE)))) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -3268,7 +3268,7 @@ DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) continue; \ } \ fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -3302,7 +3302,7 @@ DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) float_status scratch_fpst; \ float_status *base_fpst = (ESIZE == 2) ? \ &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ uint32_t prev_rmode = get_float_rounding_mode(base_fpst); \ set_float_rounding_mode(rmode, base_fpst); \ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ @@ -3347,7 +3347,7 @@ static void do_vcvt_sh(CPUARMState *env, void *vd, void *vm, int top) unsigned e; float_status *fpst; float_status scratch_fpst; - float_status *base_fpst = &env->vfp.standard_fp_status; + float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; bool old_fz = get_flush_to_zero(base_fpst); set_flush_to_zero(false, base_fpst); for (e = 0; e < 16 / 4; e++, mask >>= 4) { @@ -3377,7 +3377,7 @@ static void do_vcvt_hs(CPUARMState *env, void *vd, void *vm, int top) unsigned e; float_status *fpst; float_status scratch_fpst; - float_status *base_fpst = &env->vfp.standard_fp_status; + float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; bool old_fiz = get_flush_inputs_to_zero(base_fpst); set_flush_inputs_to_zero(false, base_fpst); for (e = 0; e < 16 / 4; e++, mask >>= 4) { @@ -3428,7 +3428,7 @@ void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm) continue; \ } \ fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.standard_fp_status; \ + &env->vfp.fp_status[FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index b369c9f45b..60839ae560 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2177,7 +2177,7 @@ static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst, void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) { - do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc, + do_fmlal(vd, vn, vm, &env->vfp.fp_status[FPST_STD], desc, get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a32)); } @@ -2239,7 +2239,7 @@ static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst, void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) { - do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc, + do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status[FPST_STD], desc, get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a32)); } diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 28c2b40bd8..93db713a40 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -118,7 +118,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) uint32_t a32_flags = 0, a64_flags = 0; a32_flags |= get_float_exception_flags(&env->vfp.fp_status_a32); - a32_flags |= get_float_exception_flags(&env->vfp.standard_fp_status); + a32_flags |= get_float_exception_flags(&env->vfp.fp_status[FPST_STD]); /* FZ16 does not generate an input denormal exception. */ a32_flags |= (get_float_exception_flags(&env->vfp.fp_status_f16_a32) & ~float_flag_input_denormal_flushed); @@ -157,7 +157,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env) set_float_exception_flags(0, &env->vfp.fp_status_a64); set_float_exception_flags(0, &env->vfp.fp_status_f16_a32); set_float_exception_flags(0, &env->vfp.fp_status_f16_a64); - set_float_exception_flags(0, &env->vfp.standard_fp_status); + set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD_F16]); set_float_exception_flags(0, &env->vfp.ah_fp_status); set_float_exception_flags(0, &env->vfp.ah_fp_status_f16); From patchwork Mon Jan 27 23:25:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860289 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp107292wrx; Mon, 27 Jan 2025 15:30:27 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUMK3i4gh+KN2U7ipijn3aEmM+X9pOfTJPQujwlViSjKnbVO+XiqBX1bd2rSIFHdhRpNT1Rlw==@linaro.org X-Google-Smtp-Source: AGHT+IHs2+fGiiwGGjOysA4aCGJw7kEi/+Hl9BicaVJSWryBtDsXXtKefdJ6pMWuNOAldyY+K3tG X-Received: by 2002:a67:ff07:0:b0:4b6:8cf4:9a23 with SMTP id ada2fe7eead31-4b7529c704bmr1286952137.0.1738020627644; Mon, 27 Jan 2025 15:30:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020627; cv=none; d=google.com; s=arc-20240605; b=kuImd+prPgUKsXUYGTi+17+YjPFyot1UjlKSbNwWUyy0I6vPi4xJG5Ts+eLKcI3yiH QYtO1nk/4/kyvNZHuXx3nOc/jeZ5WspKWHQI9AngLAL4EBc+B23/a2pE8n0ycbbIDh+G iK7q49XvR3COue7sO1t2SoTnLghRJ3w+KMtyl/xjzbOmWqShLForvYVNKHeT2MnvaS/D Y3YhEz0B26K8/JQAclfQH92WXijskC7vSC4MYMIMbvWmyvmOiQy+h9HPCJJtuAO+7aij PTn4bSF1mBEy1/GSZZEDRMPuPllLzQqZk8wR83r0pz4qv5byoKVzRUdc3sFNuEr6cBK3 96BA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Rv/vufPtN4qZGgCEixmno+0BEOkC6dlLbTtJbkkFI6Y=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=beeH7gmXLs0klohlWKc4sh71vK4EmLul2XAi2gRJEa6yRqtttR0PF0769maIee9HiQ oSA0ak+tbQqrbZtP+eD+E1aim4juc3Ozx48JNCSWABfg/F9kaMMyHiu5Xp1nx5DZh06I VMdKUq13MSJgRB8j6TvLArZ3wGbx6HdGy/qbSO4lRzCpFhYihHUrQUYtvpfr1xxlO6ld Y9csxYuL92UQQCge2NHHkJyqNIeX8zDJ15we04VGsUUE/X3ojRJjr5pttaaqzly/hF7N ThnzwNLm4nAnp2MMpgODgoQ+e/zqFsD+xA/M1XjPRAuvysNCgwUFgFBpO7WJEIB/mXVT 6OmA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uqkh5ZaX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a1e0cc1a2514c-864a9cd81f5si2536814241.119.2025.01.27.15.30.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:30:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uqkh5ZaX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUv-0006TY-2P; Mon, 27 Jan 2025 18:26:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUj-0006N2-Vs for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:19 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUg-0005Yj-1b for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:17 -0500 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2ee50ffcf14so9434183a91.0 for ; Mon, 27 Jan 2025 15:26:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020372; x=1738625172; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rv/vufPtN4qZGgCEixmno+0BEOkC6dlLbTtJbkkFI6Y=; b=uqkh5ZaXC1uGs9NXy+bYk8dl/tzOOokYSfdG7vd+Bd2nFdcoTIHp7KxEAxcz8spydw rnAt7UJrTABAb+FJIngrMsZeV27buKruzwaCd4I6QerpsKflgFc1GdWaFHgo95r6nhKf Bb0fnxYa8lyx24Ddew9dSnz6O4sKNR9s3vn7xvGT6EpiBlrIDYbtt1n97SZ/UTrO1J6o e4Y3smYLPpfKJi4zy8lbWc+1G5cJXTXL3Ts5idhDo0ijUmBFXMWkTkVRcHzRIF82NLFU srll4eHhbdxLmFrtnS3k00CBOG9dFfGTiJz/UHMSX+3kaeIT66JxjKQgEoaaAYjobD5l 690Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020372; x=1738625172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rv/vufPtN4qZGgCEixmno+0BEOkC6dlLbTtJbkkFI6Y=; b=eCVp0BX1OMMaGx+iDcionLl13QyYD7qKc5u5hUkHjS0FJEwRRFiR+LxG3XiluBH+cn RM5Op2Hod4qE1JuvfcNm9TsYRtbw7CDQnEsau6i2CcCayMj5Jq65S4H793qC6J5fah1f ed6PUBUc5w4GpbX+vlk8FK/79FJXjb3AbTPhf4Ea1AGHeEEL6fZWXDnxF9uDVG6G+cLs 0+sQTFs4RaDnzNVvUVaTHhSLlVTApFOe+CkDVqVCEdicg70qvJHXRIrPkt71f0pIPO/N fgsb6bZxltqngKY8azJOzBztlp6a6w7guw0kfe1QtNBCKeI9Mvidm/hoSRGSuwummpAt jwhA== X-Gm-Message-State: AOJu0YzQTGfUKEAxMzHb1WB07uyRvrCTnjvl1DSDRlEGFY2YrpvgfEcx XvLYt5RMW/XBJitiQNPcGknm3xEH56lcnHOFwiT9VYrcwSfn1bsGPqIsBDj+QamtDx+s8M1ze1I / X-Gm-Gg: ASbGncty6WfHfH6z3DlWRcaEchBgp+wUr9rb3G4fynplToHKrslzk4/O9Yq6yDJo1l7 aa1StJQ0ypH7she/FqeCkuU5pMCV1AKj+yIKDHVg2EvUcysf68VYUcFckvcdn8DEhy513/KYSxK T5AXH9HMR1sQd7X+kZQ89GeA013j7AJ6qX79EAMCdEA1DOkIfOtwjXXzaaPvC9TzM4yhd1t54m7 uh1dGbzl2w2a9jYY+wqz0pj8R6Z131Bw5V2uuWER69NnUJhwXAnZHo5LGxtuvxTFUnsrRjIeqIX BX3AWDTkdVfl4NgwUGttH/pHn4Xz5Zs63SFNWyQ= X-Received: by 2002:a17:90b:2f46:b0:2f4:4431:51d4 with SMTP id 98e67ed59e1d1-2f82bff6fcdmr1777822a91.6.1738020372524; Mon, 27 Jan 2025 15:26:12 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 09/22] target/arm: Remove ah_fp_status_f16 Date: Mon, 27 Jan 2025 15:25:51 -0800 Message-ID: <20250127232604.20386-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace with fp_status[FPST_AH_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 +-- target/arm/cpu.c | 2 +- target/arm/vfp_helper.c | 10 +++++----- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 18afff8509..0f7d5d5430 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -237,7 +237,7 @@ typedef struct NVICState NVICState; * behaviour when FPCR.AH == 1: they don't update cumulative * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16, - * which means we need an ah_fp_status_f16 as well. + * which means we need an FPST_AH_F16 as well. * * To avoid having to transfer exception bits around, we simply * say that the FPSCR cumulative exception flags are the logical @@ -695,7 +695,6 @@ typedef struct CPUArchState { float_status fp_status_f16_a32; float_status fp_status_f16_a64; float_status ah_fp_status; - float_status ah_fp_status_f16; }; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 26e3465a4b..ffb2151de5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -559,7 +559,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type) arm_set_ah_fp_behaviours(&env->vfp.ah_fp_status); set_flush_to_zero(1, &env->vfp.ah_fp_status); set_flush_inputs_to_zero(1, &env->vfp.ah_fp_status); - arm_set_ah_fp_behaviours(&env->vfp.ah_fp_status_f16); + arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]); #ifndef CONFIG_USER_ONLY if (kvm_enabled()) { diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 93db713a40..d8dc58098b 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -129,7 +129,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) a64_flags |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64) & ~(float_flag_input_denormal_flushed | float_flag_input_denormal_used)); /* - * We do not merge in flags from ah_fp_status or ah_fp_status_f16, because + * We do not merge in flags from ah_fp_status or FPST_AH_F16, because * they are used for insns that must not set the cumulative exception bits. */ @@ -160,7 +160,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env) set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD_F16]); set_float_exception_flags(0, &env->vfp.ah_fp_status); - set_float_exception_flags(0, &env->vfp.ah_fp_status_f16); + set_float_exception_flags(0, &env->vfp.fp_status[FPST_AH_F16]); } static void vfp_sync_and_clear_float_status_exc_flags(CPUARMState *env) @@ -206,11 +206,11 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); - set_flush_to_zero(ftz_enabled, &env->vfp.ah_fp_status_f16); + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); - set_flush_inputs_to_zero(ftz_enabled, &env->vfp.ah_fp_status_f16); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]); } if (changed & FPCR_FZ) { bool ftz_enabled = val & FPCR_FZ; @@ -235,7 +235,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a32); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a64); set_default_nan_mode(dnan_enabled, &env->vfp.ah_fp_status); - set_default_nan_mode(dnan_enabled, &env->vfp.ah_fp_status_f16); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH_F16]); } if (changed & FPCR_AH) { bool ah_enabled = val & FPCR_AH; From patchwork Mon Jan 27 23:25:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860283 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp107091wrx; Mon, 27 Jan 2025 15:29:55 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWKzTtPP0b88FnrpXAZxwcY2yTU4jrELegCsWY3t2HYECrknKuk2UQqSe/ZzUmrKhZPFp8VCg==@linaro.org X-Google-Smtp-Source: AGHT+IExYFqJdnmprdBUtWpuxonGLuS/qJ/5NFeAwvZVZzoi0bTNAU1/e3c+yt7FY9Mx04JiEKDS X-Received: by 2002:ac8:7f86:0:b0:467:57fc:3905 with SMTP id d75a77b69052e-46e12b76121mr615017831cf.36.1738020594983; Mon, 27 Jan 2025 15:29:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020594; cv=none; d=google.com; s=arc-20240605; b=Dg1Im/hZAqvAO8hjQFMHe2jq8GjG7RamCB969DRkQZLQM6FyBMUwJAB4/ybMULP2fl MNFXM6tRm49+nXpEdSY5lFKD9YqmPLLXEeHRivpj+7GDoBwHdeSYHeu2qdw3LfU50upd ydqKOhuN03Mg04qvvTNzJtpD2jn5ZhAwFm9nPDgMjNWV6Q7ivR4Tr+dqMXhy+ycEGj7w ZkQna14VLgZgWDzADqValihPVphpX22LUSFfa8X2KarQc0ErG7qihEEmqiy0SXJw3TI3 ojhYmj6xz5CDU6z1wUoNhKQgiymLJ5qbJE/BYWsTO0wztS9SyU54ZLGHxTNpueNZGAVd qltg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZfZtm3bb0qleKGnPCMaYzFO4MuQ+NRuP+QrpJs1NXm0=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=jc5scefqfvJ6TfsGHyDUiuVWNjdISRukHlTfSzJy5yz3QuJ7w4zq+xwDYkS0K1UtMw Gf9wVuQ8of4EcStNeQ4V6IgBAqYudg5v6mOdISXW5/vNZVug3zgPpMEhIpAHQABZMKx5 G9U7APo+SyCKSWDTcmYAYWSjPXkltZz1frJmCkeBARocgWVPha+/hYJjfXsgfy+hnu51 Gg3ZG/TEV4anlz/I+RWWegPacoamqRfCcYuZY6CXb6s6I73pd3EMntJt4PMxugMFRTka BVt5f0fxe3tQqyjijRTJBvV1xlbqYZylfZgH9aySw3hYqngWFXwFy3ecDNNb2K4v3Kk1 73PQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=se4WTDzi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46e6686d178si108517791cf.127.2025.01.27.15.29.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:29:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=se4WTDzi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYV0-0006ZK-It; Mon, 27 Jan 2025 18:26:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUk-0006N8-KD for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:19 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUg-0005ZB-Jl for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:18 -0500 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2ee9a780de4so6691225a91.3 for ; Mon, 27 Jan 2025 15:26:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020373; x=1738625173; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZfZtm3bb0qleKGnPCMaYzFO4MuQ+NRuP+QrpJs1NXm0=; b=se4WTDzixwYFq9X0Dx1zk6qbiOBrMhYZI5taW8j6VWTvoPi3bVr9XSih6vMCNXf5ds jXZeadKstR/VIJIFP5/gwlauhWFJG/oCx+3R1JANRXkcqg0AvyIUEc6ytykJFgnWvyyR 3XuuNv1U7HHtp97otMyaIwRQqwm8NPRGzDLthvZdbf9hCucuGKMEd79m/9l92BscSuYy TZ/fIhkYP3lh06N/3vYsOl7ens6qgCCgFO3xlXAECu33JUMslTUJffPbip95NFaVrfyR YFJ0igDkrwbS1dFMehfhv4YU9AY32P9G00Yhxrvs6bcNmSxj6MQtn4CNOlypZNHE9+ZI VxCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020373; x=1738625173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZfZtm3bb0qleKGnPCMaYzFO4MuQ+NRuP+QrpJs1NXm0=; b=JTI+uLmGGNMk6wbc+9nw6B3Dle579rG7pH3ajJn9BuH969Y4RbxUNaJ05awSF5y4dd XQYmh+Gsm2vXJCqGXcj+14uohl6sfvEuSnEnQIOvo4RCAPkJPBNa3PqeyTX95vUmOCML 5GRs8Q9WtZMxigx2izOp5sxrBjozDw0d79MCCOAgjfF98FMY39QOkzGAQ3FiLWOXEhXy f+5gSrmDY+kIIXKQM3qAMFSQnxxdIizZsSMQEhcFXFvRzVywDmMuCh7MP0+eN/bRziDq bEDeACoXXjdbuVHLsMRnlpStQ8J/cIzaYZwzVgvHKDU2QGO5YEVKdH589CoZVaowZgVd fkhw== X-Gm-Message-State: AOJu0Yxy98gJV/E7jwIuYEB6CkNrlOaQoOsK0DTWRtFjRvDkAzCd8DG2 rxce8ErKSVli4Z9qs7r2eTlT2CoaGuZ96PTu2wDXR85glSSupnfwd8H8p/gF8sAjJTBLMKz5Fhr Y X-Gm-Gg: ASbGncs6JufnTY8uxibg1tkcu4vf/Gd+AwSWTUEnAs3mGIHIt+zg1eGJDvdfaKlLZSQ Bqu7DeXmRHE4N/J/MQmR46mIl1bBV4TteiTfXXWzpX2dvxgrVoXABcXgwU1x3PkJoVNYcX54CHD t6Am+7aMgWRcV+p2Efgj3/wOAADsTxGFw2o/shauKO0oNWUJUSyyKnODtPyxK+HydWGFc2gSC22 5StkO6TUwH00uylaKSDVJaerbBEwyaWUpD8+VTTABkma4qh0/jmDCkcthKcqjMU0MLjgPq7DcRZ 4i7K9J8C85m7mF7UsBbQ2dsKsf3dNplSDqODZQ8= X-Received: by 2002:a17:90b:2c84:b0:2ef:31a9:95c6 with SMTP id 98e67ed59e1d1-2f782c7de14mr69490958a91.14.1738020373329; Mon, 27 Jan 2025 15:26:13 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 10/22] target/arm: Remove ah_fp_status Date: Mon, 27 Jan 2025 15:25:52 -0800 Message-ID: <20250127232604.20386-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace with fp_status[FPST_AH]. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 +-- target/arm/cpu.c | 6 +++--- target/arm/vfp_helper.c | 6 +++--- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0f7d5d5430..5e3d952588 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -233,7 +233,7 @@ typedef struct NVICState NVICState; * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than * using a fixed value for it. * - * The ah_fp_status is needed because some insns have different + * FPST_AH is needed because some insns have different * behaviour when FPCR.AH == 1: they don't update cumulative * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16, @@ -694,7 +694,6 @@ typedef struct CPUArchState { float_status fp_status_a64; float_status fp_status_f16_a32; float_status fp_status_f16_a64; - float_status ah_fp_status; }; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ffb2151de5..01a0428c6e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -556,9 +556,9 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type) arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a32); arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); - arm_set_ah_fp_behaviours(&env->vfp.ah_fp_status); - set_flush_to_zero(1, &env->vfp.ah_fp_status); - set_flush_inputs_to_zero(1, &env->vfp.ah_fp_status); + arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); + set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); + set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]); arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]); #ifndef CONFIG_USER_ONLY diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index d8dc58098b..78be434caf 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -129,7 +129,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) a64_flags |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64) & ~(float_flag_input_denormal_flushed | float_flag_input_denormal_used)); /* - * We do not merge in flags from ah_fp_status or FPST_AH_F16, because + * We do not merge in flags from FPST_AH or FPST_AH_F16, because * they are used for insns that must not set the cumulative exception bits. */ @@ -159,7 +159,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env) set_float_exception_flags(0, &env->vfp.fp_status_f16_a64); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD_F16]); - set_float_exception_flags(0, &env->vfp.ah_fp_status); + set_float_exception_flags(0, &env->vfp.fp_status[FPST_AH]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_AH_F16]); } @@ -234,7 +234,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a32); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a64); - set_default_nan_mode(dnan_enabled, &env->vfp.ah_fp_status); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH_F16]); } if (changed & FPCR_AH) { From patchwork Mon Jan 27 23:25:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860270 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106269wrx; Mon, 27 Jan 2025 15:26:45 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUAVqndtC6jIGcqaIz5647yFViQI1u/RFJ7ZtcLkPUX26UKx6KtdbOEF48ybuXbvP+ME5Ac5g==@linaro.org X-Google-Smtp-Source: AGHT+IHxA0jwJh3TSslruZ/I9D8Kif7jnuIm4gzOAwzpaHpKAmNQJhK1R9SorCllwxIJJGNcjrm6 X-Received: by 2002:a05:622a:1116:b0:467:59f6:3e56 with SMTP id d75a77b69052e-46e12b56ef7mr665937261cf.36.1738020405603; Mon, 27 Jan 2025 15:26:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020405; cv=none; d=google.com; s=arc-20240605; b=X+JTqMTwXCKP7ptcrAeY3Pvpgz52jkP15c5BuJ9z0ov6tlx/gaJB9G+w1e122DWqCo OQZdOFKEDeIWmbuawUSN5NdYyS2foQSm1Snbo7H25PkS1JFlA75FpUWJPj3sY3YcAlvJ 8TL1JhR5esbVwNEXZYvCGITciVX8Dn/k1mAx3tpOlccapF/VjS9DAlaJ7ad/9MSRiAVh 7j/u74yfrLrs2j2CRy/3eqbW1DWwkzCKXS0CeC1UuaBlVbZR1dkNLLUQx+dWRw+jAO9K T6UsQcAJa5LZ6YTHu4fEifRG9sIwVyJF7IKYOumQ0VHl7jMLv3UxT66W2q/xOtIrnXFF JMSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=l8VYMWiplic3kZJLmX14exYupN5jn8vNAASn/D9iwtU=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=CQrm4FLW+wgJ9xWZQakpI/WTBmmPBCUnfgQNjuk59TABBBhHKlv4qYT5FFnSRpNkJD 6TWtLfqEgz1XRLNTlINHW1Vd5jZZyF8QrTU6wnlXcmSajfPd6m42RRV5bE9BcXJKjOvA DZMwLEFjNLNk3vCbd/6PX+Uv6nYUlSGgjLQMbS+a9nDchEy8XLEJmib8WHZLQvEI6qQe dvqF5t8DBe8Zoq6uBIQqlYE5hPscK6tJDcsnBtfjsJBD9d28C7Q4w2Aj+yMGMYJKilce kq0OhWeBBdLesHuhYXGkm2tFE3bktdrubUaza2Z28NugmriRstCNGrcO60ir/NZkZjoi 5ZCg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VQSXQch1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46e66b6e169si112162651cf.248.2025.01.27.15.26.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:26:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VQSXQch1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYV4-0006bw-DO; Mon, 27 Jan 2025 18:26:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUl-0006Nf-IN for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:21 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUi-0005Zy-7j for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:19 -0500 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-2eed82ca5b4so8527770a91.2 for ; Mon, 27 Jan 2025 15:26:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020374; x=1738625174; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l8VYMWiplic3kZJLmX14exYupN5jn8vNAASn/D9iwtU=; b=VQSXQch1dP9vRo5ZbHbdZnaNGazramPeFhNqfu/wyb8M+K5daNfnytqUv4aa/28c2K fz9m7P8F9zKRlYsh3gL8bWUuPWjmotRiTyX7a4LkzCmm8CXDaA3mzXgy0xFyrnbcQDTf yPiYYTLSwGm7Yr7Y9R8KWW5DgrxZvawdn8JvLiRmq/mnjLo5g+ihX0m6v7Gfn+aO1Ca/ 4PpSOHM55WAxtxoGiSh6iKoZynW2MDO7cTYos6qyyil0D7PtPEFFfQv221I2wsh8NLBS kxqJNl4zw6TaCFQIG9Bd3f7HkvCeWmqqiMQ6DPRx4WNASw8aBABzt6Z5BVn8eoS268Sc BKYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020374; x=1738625174; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l8VYMWiplic3kZJLmX14exYupN5jn8vNAASn/D9iwtU=; b=RDvLf17cNzqYIdzXjZuMC6a5xaG5tMidZ9sbF6assLsZ6e9KypwyxlRSNsiZhIFRSC RruaU0H0YAk+/JTrrA322K+Ium3ey2SJ5nD9J6WW1gshREIfQwbpqe4JzcJsBlPDEl7e u+gpcF2TLVyOS+Bc8WsxrvpM8dxTZ5W9xmVgJxysEn8G8nobVvXlTFlg8WqqNtjJHCmL na7vzhng2m99V/jO0Ly8Hgm0sTng2pZ8vmDR+1+q0fSRS0xViSZMFK/08yBTok573jOc ItwJUSayLa0WSi+Q0a1a3wanTFTeemKuGD+F3NlhCmREb08lEb/lR8CqEXopF42i/ASf P6VA== X-Gm-Message-State: AOJu0YxURX4WfdgX6iGl7Mq735UC59/PJqnhEQurRhEL0l65dNvhp+n5 7g4WiTPCuw1OWX4C/hqhIjmiXRvqRc3jYBExz1HrVYWD5fJugseLkYwcNr50CIkS8syK4htCbIX B X-Gm-Gg: ASbGncsDsSw8pUmP+l/7lzs5yJzthpfZz7+uSfXJZawpiVQeLTzXT/CM7F1OAVIyypg zCgOXQPBCVPPCJs5BlnIZXfRke08cLZ6rwIE3xXiPatQc54kF5vcgHPLtIkJehUTmumk3eI2B90 6kyV+qGjRjQcCMzrkjuXogDTkIlao1eerYOldc27siIaSqXhqQPJgcsV5KnwGntzMAju077xT9k ciUMzo/x2FnKkvgbeecNjL/nsuoHY11rnXtW2ALGUmR4NU9SOiIMlbU0LIFmVYrKFQ5HklcRN4g DYKKeYxhmeC6eA3GMqwQ9rgLHpHP8izm2ocoSJ4= X-Received: by 2002:a17:90b:3d45:b0:2ee:c91a:acf7 with SMTP id 98e67ed59e1d1-2f782c4bddfmr61264175a91.4.1738020374630; Mon, 27 Jan 2025 15:26:14 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 11/22] target/arm: Remove fp_status_f16_a64 Date: Mon, 27 Jan 2025 15:25:53 -0800 Message-ID: <20250127232604.20386-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace with fp_status[FPST_A64_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 - target/arm/cpu.c | 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/vec_helper.c | 8 ++++---- target/arm/vfp_helper.c | 16 ++++++++-------- 5 files changed, 14 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5e3d952588..9e39c8d0d3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -693,7 +693,6 @@ typedef struct CPUArchState { float_status fp_status_a32; float_status fp_status_a64; float_status fp_status_f16_a32; - float_status fp_status_f16_a64; }; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 01a0428c6e..4fc1d00d60 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -554,7 +554,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type) arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a32); - arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 727c085f37..6e336e10c6 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1043,7 +1043,7 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, * produces default NaNs. We also need a second copy of fp_status with * round-to-odd -- see above. */ - fpst_f16 = env->vfp.fp_status_f16_a64; + fpst_f16 = env->vfp.fp_status[FPST_A64_F16]; fpst_std = env->vfp.fp_status_a64; set_default_nan_mode(true, &fpst_std); set_default_nan_mode(true, &fpst_f16); diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 60839ae560..927dece4c1 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2185,7 +2185,7 @@ void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) { do_fmlal(vd, vn, vm, &env->vfp.fp_status_a64, desc, - get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64)); + get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16])); } void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va, @@ -2195,7 +2195,7 @@ void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va, uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15; intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16); float_status *status = &env->vfp.fp_status_a64; - bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64); + bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]); for (i = 0; i < oprsz; i += sizeof(float32)) { float16 nn_16 = *(float16 *)(vn + H1_2(i + sel)) ^ negn; @@ -2247,7 +2247,7 @@ void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) { do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status_a64, desc, - get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64)); + get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16])); } void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va, @@ -2258,7 +2258,7 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va, intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16); intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16); float_status *status = &env->vfp.fp_status_a64; - bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64); + bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]); for (i = 0; i < oprsz; i += 16) { float16 mm_16 = *(float16 *)(vm + i + idx); diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 78be434caf..bcb05d7ff9 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -126,7 +126,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) & ~float_flag_input_denormal_flushed); a64_flags |= get_float_exception_flags(&env->vfp.fp_status_a64); - a64_flags |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64) + a64_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_A64_F16]) & ~(float_flag_input_denormal_flushed | float_flag_input_denormal_used)); /* * We do not merge in flags from FPST_AH or FPST_AH_F16, because @@ -156,7 +156,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env) set_float_exception_flags(0, &env->vfp.fp_status_a32); set_float_exception_flags(0, &env->vfp.fp_status_a64); set_float_exception_flags(0, &env->vfp.fp_status_f16_a32); - set_float_exception_flags(0, &env->vfp.fp_status_f16_a64); + set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64_F16]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD_F16]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_AH]); @@ -199,16 +199,16 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) set_float_rounding_mode(i, &env->vfp.fp_status_a32); set_float_rounding_mode(i, &env->vfp.fp_status_a64); set_float_rounding_mode(i, &env->vfp.fp_status_f16_a32); - set_float_rounding_mode(i, &env->vfp.fp_status_f16_a64); + set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]); } if (changed & FPCR_FZ16) { bool ftz_enabled = val & FPCR_FZ16; set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); - set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64); + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64_F16]); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); - set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64_F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]); } @@ -233,7 +233,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a32); - set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a64); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64_F16]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH_F16]); } @@ -243,10 +243,10 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) if (ah_enabled) { /* Change behaviours for A64 FP operations */ arm_set_ah_fp_behaviours(&env->vfp.fp_status_a64); - arm_set_ah_fp_behaviours(&env->vfp.fp_status_f16_a64); + arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); } else { arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); - arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); } } /* From patchwork Mon Jan 27 23:25:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860272 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106515wrx; Mon, 27 Jan 2025 15:27:40 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU9tkEqy9kKiOvTUCVa+QJfnWmqX5V036QFzaaSx1BQNQ6dBbcAR8Ug3TjO8i7UYZOdIJ+AfQ==@linaro.org X-Google-Smtp-Source: AGHT+IEx8Uva17wnFvaOmaSUQmGPIVz+WmI2K8EpWZr4H0Ec56hgcj1vXyLSFukPsxvAhnTgkMEs X-Received: by 2002:a05:622a:1a91:b0:467:5ad8:a042 with SMTP id d75a77b69052e-46e12a9afffmr618930411cf.26.1738020460280; Mon, 27 Jan 2025 15:27:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020460; cv=none; d=google.com; s=arc-20240605; b=JCO403XbXQLh/TVNCnlkwrkO1PZ4YcBYOwz0oeuRmxopLhDLBZnZYauCNMlnlGwwah MFgCyKNK5eR6Vu4DKagcqC2sEnh1mJbdhgADtE5CgaCEP7fBoa4Y2Rv1KcQocrgC3hhx Kuf61GCdBPHqXAcGtDC6NPkQ/xVF6DbCFjgV38FAzm3fzLxfKFiTr1n3Oft8pGI+2plj uJjeQTewyU82KhFCRTRhe4WHVvldHoYPQYYsD0QasOKPj6Y2upb08ehtAEWwTyLI8o9/ LD+0EbOsLttvWQgrCTtl4FLWddEpwGOqgovw4hnBIF2R7VfWtNxe0YnG+Uq/tImiD5z2 P5LA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+sflSr/TdauAR3s9EgE90A0mkYRYsheBOwJCWqm7/4c=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=Cv+nXI8IpK5aDV2yTc+DcLrPpnQ+pFt0dJtWlMpPXbtTOVFgdOmTUJstsVMTGknzIX ZIE7iiX02X0kO6xffPvbgzWgGz7CcOiO+gMhCrQK/RqcHzrObCfW1SfErOe87e6pg/eY c+vbmoN1oeFXjJ3X9dSvxVq5S6be+1NnTUuBqzGoXFSxVE/beQZrElI5CzFPA9AShWYh gxdsU20PXx5jGUSWX9RcljtUnFEQPCrDQhS5UqQsI9GnNfZZeCfx6LMTdR40hTPpQgSG binEW7ZaFVqiGUR2ijiThWh5Lc+IlmnjK0AoRg+iL2VwfudwplpH3MvEgYHrET8kPnA2 B6mw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CkcVSP9R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46e66b64e85si107274611cf.278.2025.01.27.15.27.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:27:40 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CkcVSP9R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYV1-0006aV-RW; Mon, 27 Jan 2025 18:26:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUm-0006Nr-19 for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:21 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUi-0005aJ-My for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:19 -0500 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2ef6c56032eso6693870a91.2 for ; Mon, 27 Jan 2025 15:26:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020375; x=1738625175; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+sflSr/TdauAR3s9EgE90A0mkYRYsheBOwJCWqm7/4c=; b=CkcVSP9RWVyWNAF7zNATwMnevemFfkGeZBLIf7Ac/M7/ZJJUNmfKg84MGBCZA8nOaJ vOKArdBtF5nx0L6cxDQ40UgOFnDxY42/dOwirLGvbNQnYRb63cPP56Fetl876K6voahm r8lof1Vj72Mw7sCOkuoKWX4k7lKMUPbgnz6xkNl2LHCXWNaVCv6xyNCEpy9qmtQU1BkL 3E1ywfkFrimTDbLD//wrBLbRdXQOAUfVSoBScF8YpWF226gW60V5EjBvdktjqktE9tQ+ hAdYTl6cc//HHWOs6WgWSVnU9obOD4whf2UVlRai/uZ1mefYF5ub0i38OSUilL9Lzhnd URfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020375; x=1738625175; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+sflSr/TdauAR3s9EgE90A0mkYRYsheBOwJCWqm7/4c=; b=Gx50+AO7QpIylvIdiFRtDiAGTNPWEs8AFXPgcZ5YXLeC2i3wmEKPN04sBXXHJ3fIMf 5m95HVi0luh6Pq1Zv7Js70lyZ4M+0zbM9urFcP9gwRZ+MIDWlwSZNFpgCCqNemvSDRT/ Srq+PLzIVO2MVEgknkZOPriQ2WsgkbUnnrz1zBmgBN6i63BhTKKl1FHZxYKmL5VbR9h9 /7MmwCh0fKxjoQBC4oAVbd2EjZ23wbrHcjptOnTnCgtdBjH8tC4swginIEgAGz500BBb EgruH/CsIIgTnnxH/gKYML7bUCTrUjK8AZkrIYCdg4HAtnrdVR3u0dK1I6zNcsW1YavV PTow== X-Gm-Message-State: AOJu0Yz0LNI9xaoq1TkUXCqoIbdpZ9idw1hcUxJ7ecpGNDDKMO+pByqX SgkbK1FpDfdfNWIbZKSyQCk/xKv3RBt+lSTLVraFdZvaDJ4JqKUF9O1T6qYyy8Toe5e3Izlx73N / X-Gm-Gg: ASbGncuGvajgrShNsxlsUXoC0teuM6smxcxAnPVr1TOqU/ZkKEtFRff9zqvLTLxE1fY UO8B2QJ190c5lJV6GQA9zRHmj8thpSodi+7MZ3coHidDwNyWw1I3LuZCfjCMgo7PiIYlxFAJ1w3 aXA6yDNgYleEKWZR/4QXjkX73V1AOh10LR0JsGCKj2YgCpOMzTt6TKH6hHF58YNtmaDbxtM0sZ5 BoxbOZEr2Y2dlsGYFJ8wdgeMSOP7ooMS+Z2KlnQMNkbrN6rRnqQKvor9mM5fuW5F8h+KBkD+viz 13B6Oe2mUI8fgvjOwI6+n8iKHfG2SlRuONBeFGQ= X-Received: by 2002:a17:90b:2748:b0:2ea:59e3:2d2e with SMTP id 98e67ed59e1d1-2f782c73b7fmr65245544a91.10.1738020375393; Mon, 27 Jan 2025 15:26:15 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 12/22] target/arm: Remove fp_status_f16_a32 Date: Mon, 27 Jan 2025 15:25:54 -0800 Message-ID: <20250127232604.20386-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace with fp_status[FPST_A32_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 - target/arm/cpu.c | 2 +- target/arm/tcg/vec_helper.c | 4 ++-- target/arm/vfp_helper.c | 14 +++++++------- 4 files changed, 10 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9e39c8d0d3..06dbee5725 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -692,7 +692,6 @@ typedef struct CPUArchState { struct { float_status fp_status_a32; float_status fp_status_a64; - float_status fp_status_f16_a32; }; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4fc1d00d60..ceb2dcb3fb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -553,7 +553,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type) arm_set_default_fp_behaviours(&env->vfp.fp_status_a32); arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); - arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a32); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 927dece4c1..61f268efad 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2178,7 +2178,7 @@ void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) { do_fmlal(vd, vn, vm, &env->vfp.fp_status[FPST_STD], desc, - get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a32)); + get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A32_F16])); } void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm, @@ -2240,7 +2240,7 @@ void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) { do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status[FPST_STD], desc, - get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a32)); + get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A32_F16])); } void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm, diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index bcb05d7ff9..6a6eb48530 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -120,7 +120,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) a32_flags |= get_float_exception_flags(&env->vfp.fp_status_a32); a32_flags |= get_float_exception_flags(&env->vfp.fp_status[FPST_STD]); /* FZ16 does not generate an input denormal exception. */ - a32_flags |= (get_float_exception_flags(&env->vfp.fp_status_f16_a32) + a32_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_A32_F16]) & ~float_flag_input_denormal_flushed); a32_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_STD_F16]) & ~float_flag_input_denormal_flushed); @@ -155,7 +155,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env) */ set_float_exception_flags(0, &env->vfp.fp_status_a32); set_float_exception_flags(0, &env->vfp.fp_status_a64); - set_float_exception_flags(0, &env->vfp.fp_status_f16_a32); + set_float_exception_flags(0, &env->vfp.fp_status[FPST_A32_F16]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64_F16]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD_F16]); @@ -198,16 +198,16 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) } set_float_rounding_mode(i, &env->vfp.fp_status_a32); set_float_rounding_mode(i, &env->vfp.fp_status_a64); - set_float_rounding_mode(i, &env->vfp.fp_status_f16_a32); + set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32_F16]); set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]); } if (changed & FPCR_FZ16) { bool ftz_enabled = val & FPCR_FZ16; - set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32_F16]); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64_F16]); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]); - set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32_F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64_F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]); @@ -232,7 +232,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) bool dnan_enabled = val & FPCR_DN; set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64); - set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a32); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A32_F16]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64_F16]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH_F16]); @@ -494,7 +494,7 @@ void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ softfloat_to_vfp_compare(env, \ FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \ } -DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16_a32) +DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status[FPST_A32_F16]) DO_VFP_cmp(s, float32, float32, fp_status_a32) DO_VFP_cmp(d, float64, float64, fp_status_a32) #undef DO_VFP_cmp From patchwork Mon Jan 27 23:25:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860288 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp107260wrx; Mon, 27 Jan 2025 15:30:23 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUgY3YOWmpSZH3ix5u/5BNaeI/sGGya8Fa7+s7HJcOQ/xaAtQVLF/limSPqRnFKrDVbli1Ozg==@linaro.org X-Google-Smtp-Source: AGHT+IER4u0d37P7VdXx9G2JHkhyUBE/RjiWRTWCmdC5SyL5/Q+rBq/NZMeBoXRR8zwRPGmsmXqv X-Received: by 2002:a05:620a:4894:b0:7b6:6b88:cc00 with SMTP id af79cd13be357-7be631e71a2mr7312734685a.5.1738020623212; Mon, 27 Jan 2025 15:30:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020623; cv=none; d=google.com; s=arc-20240605; b=PSzymKkzN2OmJu/j835brrlauwfaej67xuFSF79CS4EOIhQJPtWF5rA9GdT5b1xMmz s/UemL1pfrLRb2bmRj2pqzhbwpTR0ofNhoa74JUWmHqeUh298JFmiQDuiPvoU86WAOMi wU8rAEaSpJyTa5alt1IjISDeqLI7gGEtJOc6/m5PxNcgU7Qpk7jLdO4Yzfv0p2B2Ybkp gGJrAJJIZoiTNDFqvIkbSHYOXQDfmrZkjk2WdeFZLsHaYilK1clm+dv04ZFJ0O49Tcox i53Cnt+Nh5d6KR5l83Pgdom/3MLPqtA40sCZPAfPDFUJMmnd86yBC7BbvIZfCanosJKU 32vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=weeu4pGBnKKliPk8DdBFAKHVxY9v63/VAYgurHgBoNI=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=ayN06c0VEYTDIy6e0n0Z5TEutWGR7lTt/ODBfthZlMmqTBCUpEuvPqxWnP4NnHwpfU Z3Qk+vojDUzwBRzrVvqQmEb/dDtdVk+MZb6bnoh3d7rB1Ao5tA/qnp3Uum4VT3RYoy7C /z7jScx12CFs9DswvrZRdNrEz4bLpt1lEkdiBEE8QZyht4gJL9iJJntF5pHWWrPey1GD MdO7ZIhVsFWb8rpO/2HhUchxh/Ncd48anL76VLTghLe6nA8PztAh0yXIO1MSWh4fa1gy 0mTiAkQPForACYa435CMjyjcGEuG/bDuR/QseO3FQatUb8MPiayFdGOWMgONiecUh++L 8Bqw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DMXsuQVZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7be9aee1381si1060377985a.315.2025.01.27.15.30.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:30:23 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DMXsuQVZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUv-0006Tl-5h; Mon, 27 Jan 2025 18:26:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUm-0006Ns-99 for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:21 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUj-0005b8-VI for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:20 -0500 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2ee67e9287fso8638738a91.0 for ; Mon, 27 Jan 2025 15:26:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020376; x=1738625176; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=weeu4pGBnKKliPk8DdBFAKHVxY9v63/VAYgurHgBoNI=; b=DMXsuQVZvLXmEZ5aNq8E1dKbADKgudE0GuWHvmmR6vFZ3JkrCjATHakoDZhi4OTW9D b4iH8cuBTc/fD2N2QCJVJWqGXcSt7SZbNwx8wowz2ETCIGxPfXgYSUvmNzF2pZDjOFUp s+wcXTSNj6JVa/Cxo4Rp38T6kpyOJjtTaQa1egHfJfE/Cw/n6OcK0HOiO4AQQs3QXC2b OKI2fHS7Q2TI72xAZPne9BB5iPeRsHiCyRj04uhcl/CjPLZj1x6bsGDRYw0qStGa+ODo ZnsZqa6V1gulbHC5kPUTtaMekCQaZs8ZiBWGDMyq8+1yPI26aj0ZCr4w+O/CKa1K75ow Khgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020376; x=1738625176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=weeu4pGBnKKliPk8DdBFAKHVxY9v63/VAYgurHgBoNI=; b=jjsYMQEQZ1DcvDio7oGywuaX0ib3omE4PG0Shsu2M3efD5wdXsRWcSG33J9trXslwp IQFCKrTnKKVqLTlHm1RFZNk3GIgmfeNI0L7A1NISAnOzrCkBXgqioqNPhDMqD9vmYHXg s7+3kJJPXI2ZHQnytOf+V4tkIWf6U5CxnZz8u2E4FQH+Um1j6ToeFyCSgSfW2H7ZDCgM M782xFbH1XkSkwngCZwZozfp14I7hmEiAc9RKit9x7sjrmoV5QmKiElp19U5IUQEwXTi ualGpfUQcqEbLR2/S5raU1LBtQTK1w5keP5SW4U86Yydw/SbMMWtIJVB8P1WwGAnGQ1R VqQA== X-Gm-Message-State: AOJu0Yz7vW+YCnfrMgm5XlnsWb0VGF1cnMWyw5fEYqZO2HOF2Cx3sONj JgWNuakvOCxao/UQyYnZhNm8za+ZSV6U/V37bXmJIE/djFx/+sHj0Fwwb/xe6e/QrCpuEbCUVi6 w X-Gm-Gg: ASbGncvOg4E0uB1Z3KRYYOBAr6ZeFI7Sxc+kmfFiBet/0q0oYWof09U2GssGT/2OLBi Dj+Qk1OEKz4hR5wLDH3isf2BDwPxhAhP7gatpq+fhXzC18N8LoIDIWCjUVP/UvBMPIhph8tEJqB CjN30U0mMeZu8fEyWkmF2Kn8XgmnGRmp+GpJR1xvsGyf+wQ90RHHUrm2Iac6MCbaZfd+3bUNJEW 5ABKZuqPnwTIYGr796y93+s1reg1rWO27L/fQr9DrdO3X7Ik4Z1vdB4YYRY56lG73YvDthKpsgW tAJmSJo4aME8+b4jSWHEN2nNDlk4XCsJKj5q0wM= X-Received: by 2002:a17:90b:54cb:b0:2ee:dcf6:1c8f with SMTP id 98e67ed59e1d1-2f782cb4d3fmr69542291a91.16.1738020376638; Mon, 27 Jan 2025 15:26:16 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 13/22] target/arm: Remove fp_status_a64 Date: Mon, 27 Jan 2025 15:25:55 -0800 Message-ID: <20250127232604.20386-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace with fp_status[FPST_A64]. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 - target/arm/cpu.c | 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/vec_helper.c | 10 +++++----- target/arm/vfp_helper.c | 16 ++++++++-------- 5 files changed, 15 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 06dbee5725..05a58de045 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -691,7 +691,6 @@ typedef struct CPUArchState { float_status fp_status[FPST_COUNT]; struct { float_status fp_status_a32; - float_status fp_status_a64; }; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ceb2dcb3fb..777e5f5dd8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -551,7 +551,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type) set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status_a32); - arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 6e336e10c6..dcc48e43db 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1044,7 +1044,7 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, * round-to-odd -- see above. */ fpst_f16 = env->vfp.fp_status[FPST_A64_F16]; - fpst_std = env->vfp.fp_status_a64; + fpst_std = env->vfp.fp_status[FPST_A64]; set_default_nan_mode(true, &fpst_std); set_default_nan_mode(true, &fpst_f16); fpst_odd = fpst_std; diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 61f268efad..9ed04b1b0a 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2184,7 +2184,7 @@ void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm, void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) { - do_fmlal(vd, vn, vm, &env->vfp.fp_status_a64, desc, + do_fmlal(vd, vn, vm, &env->vfp.fp_status[FPST_A64], desc, get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16])); } @@ -2194,7 +2194,7 @@ void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va, intptr_t i, oprsz = simd_oprsz(desc); uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15; intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16); - float_status *status = &env->vfp.fp_status_a64; + float_status *status = &env->vfp.fp_status[FPST_A64]; bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]); for (i = 0; i < oprsz; i += sizeof(float32)) { @@ -2246,7 +2246,7 @@ void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm, void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) { - do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status_a64, desc, + do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status[FPST_A64], desc, get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16])); } @@ -2257,7 +2257,7 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va, uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15; intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16); intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16); - float_status *status = &env->vfp.fp_status_a64; + float_status *status = &env->vfp.fp_status[FPST_A64]; bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]); for (i = 0; i < oprsz; i += 16) { @@ -2936,7 +2936,7 @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) */ bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF; - *statusp = env->vfp.fp_status_a64; + *statusp = env->vfp.fp_status[FPST_A64]; set_default_nan_mode(true, statusp); if (ebf) { diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 6a6eb48530..e0d0623097 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -125,7 +125,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) a32_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_STD_F16]) & ~float_flag_input_denormal_flushed); - a64_flags |= get_float_exception_flags(&env->vfp.fp_status_a64); + a64_flags |= get_float_exception_flags(&env->vfp.fp_status[FPST_A64]); a64_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_A64_F16]) & ~(float_flag_input_denormal_flushed | float_flag_input_denormal_used)); /* @@ -154,7 +154,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env) * be the architecturally up-to-date exception flag information first. */ set_float_exception_flags(0, &env->vfp.fp_status_a32); - set_float_exception_flags(0, &env->vfp.fp_status_a64); + set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_A32_F16]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64_F16]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]); @@ -197,7 +197,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) break; } set_float_rounding_mode(i, &env->vfp.fp_status_a32); - set_float_rounding_mode(i, &env->vfp.fp_status_a64); + set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64]); set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32_F16]); set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]); } @@ -215,7 +215,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) if (changed & FPCR_FZ) { bool ftz_enabled = val & FPCR_FZ; set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a32); - set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a64); + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64]); /* FIZ is A64 only so FZ always makes A32 code flush inputs to zero */ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a32); } @@ -226,12 +226,12 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) */ bool fitz_enabled = (val & FPCR_FIZ) || (val & (FPCR_FZ | FPCR_AH)) == FPCR_FZ; - set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status_a64); + set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status[FPST_A64]); } if (changed & FPCR_DN) { bool dnan_enabled = val & FPCR_DN; set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32); - set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A32_F16]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64_F16]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH]); @@ -242,10 +242,10 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) if (ah_enabled) { /* Change behaviours for A64 FP operations */ - arm_set_ah_fp_behaviours(&env->vfp.fp_status_a64); + arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64]); arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); } else { - arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); } } From patchwork Mon Jan 27 23:25:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860273 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106551wrx; Mon, 27 Jan 2025 15:27:48 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWQtgI54mJhkBHDtnISURrFIWdoZeGghp/dyQ/P+z0eBiFvhj86bMfxzm6kZOY8kS26m25Dhw==@linaro.org X-Google-Smtp-Source: AGHT+IG/3C1nwVAsqizjntAbRuZXO/yVClwubLxjR6m00Qirb6SCta3ZygFOcAIngKU6rQ091IOk X-Received: by 2002:a05:620a:410a:b0:7b6:a793:4223 with SMTP id af79cd13be357-7be6321c2b2mr5793717585a.24.1738020468014; Mon, 27 Jan 2025 15:27:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020468; cv=none; d=google.com; s=arc-20240605; b=Li4Erzc9jWGlUR03+Ph2Be6SiPENU5bRX4BBRCHi02DPbYd8EdLpZXkYq0rv7+BgXI gkjAA9x0bDMi+A5MHB4uTnReGfAWJ3Iqqr+VZuNtDTvZI5vlU8I/AQgVqG69jRrhGbus DZRMQQovPO5iXbW2VR/eknoT5wFSrOnmsDrCb/vMHECJvT2h7G1Ksw4QWITUsgax1nZs 7ffnzCVKyBOexRP9YTOk8/0w+76vQsnvaFpVD5f9Rr1PUUcUtk3GJptesOnry6n4zKMY NXwv2f1o/DimF4XpZyBIRYRzLyPncu4vFm/forqYWrITWG/5RxH1jMywpcajCai6YHEW 6r6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=irI8P1SvOCgzRxiQPiYVSipG0XrpLXOcoub7PbBmjSc=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=K519B7M+dufQDQWHYyCQA4d1AAz0nLFTPtc+A9hksO+uQG1USCNZduPYFLGXHY4hiq Msc1tMvajS7hPknK/lAzgRT5wKNVtUi9vkKJmwubrEQDOPvCmXxDeZN+6nF3L2eXIoHb 8v0aqCvC4BrYLIFvokfbw7biVPdALkdRvnfZjM93Gg5bmV1AuqYdd7yq7G8ZOLXGi3nn 8LZco4F0U74AA/l95gQsahlqomhw90YAXc1vs7eDtCdHfMPMLuGWC6ghC06tEXJ+8VAc 4ZZ8yAyl/vw568iPaHNKviPoS7f34wNpFXYhoaiGe/AC7K57GXJ3sSQK8vU/78yeO5MD cKpw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p0l7aAM0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7be9ae81c02si1075694285a.40.2025.01.27.15.27.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:27:47 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p0l7aAM0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYV2-0006b4-Qx; Mon, 27 Jan 2025 18:26:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUn-0006PC-Sx for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:23 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUk-0005bd-PP for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:20 -0500 Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-2f44353649aso6677529a91.0 for ; Mon, 27 Jan 2025 15:26:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020377; x=1738625177; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=irI8P1SvOCgzRxiQPiYVSipG0XrpLXOcoub7PbBmjSc=; b=p0l7aAM0QFI77tgWNLudYX/wZvL1K9uKMZAfndGJzD6NzTGNCySGuBm+PKnvGXbI+H XGTIteIXQ5xd5iSh1F4sOIA3h5xwS2WwTofhFPkrA0nIEEEGxXDSmh7KimVBPvcAfhcH Ul0HAvZ2u+QMSi9/mOMIiU7Amt7PahooMM1RdGZ0qYu9FyuZBNSg8bVLV9/3GmBiRCqp crDl0rrG0xHLCGmBXlt650Khms+Q1WxOHFtZYUOQyhmopSFOimSoiB1leQVzX4XNMOQT fKduoqyg0BGL3xF8Zii1E2SEtZ7VIVUABrbDEozLGeyvVfPBD3LsISvtQ2VS4ZUjAGmT cakA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020377; x=1738625177; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=irI8P1SvOCgzRxiQPiYVSipG0XrpLXOcoub7PbBmjSc=; b=XJrhwD+wlMqynGbcXM+zrZBMVxt9IvGJyzYR7C+gWQnfXkc91GPr6s6EYVONir5nDt CSvUZMZxmQAVn17iuIpH6xGJRCv87H72FoXV9/YsfyVn+fkURty+3aNdyDPUG2bygQRM zeNb5RjHh2b+jR7LZrEAVLw1SO1jYMyLAXXIu/ZtHovUgdbYlTP/dUw683sJ7UgOvvnb pil/zMB1+We+N1lZ2ppIzCtuTbT2CLYJHRIRWZo4J92fyngL9R0rCP56ySdQqDxLTKk4 d9j5TXnrHuxIJFbJiFTtrzdVysOKM4aZbtezlgTuOOFsk8io6v6p22T774REYLJgKOzZ VO/g== X-Gm-Message-State: AOJu0YznpjAq3iNxXvdxTgoFc4ZZab50a99WHJIx5cBTNMP6n46ezVDY n/y6VSzl8zpE0R88IEaMXmuNYJlTGK5IlF2W0MOqjKYREqvDs/K2gCQO3iXCBtKE+76jsegcGnx K X-Gm-Gg: ASbGnctLGztriOHi6+Xi4CR+wkxjUWYU/hmydjoRUGc29DG8KlPyA9Ww/Hvf5MHv72j sNqqey6fnHB7Vue2yzrVB8tmYSBD0neB7wwh7WFVBLo4N3awllh7U/JOhMsUxirfp/umD0bXZKP nTI8bCL2gVAUuaJOqenCUYUMxJ0G4J9TLMqIS+OzIuTRphjs7Ae7wdfXwzVlyVjdHEqssNaQVgy Evfp7ZAvzq7vqO1sw2FgdzUZI2vypwj+nFn5IWMVTuFuyztUy3eF8q5d3JyWfh+cFbtv5EMfUqg 0RVfH3JX6R6lM6mWnZ1csx1V0GDCkCniOoWT+WE= X-Received: by 2002:a17:90b:540d:b0:2ea:3f34:f190 with SMTP id 98e67ed59e1d1-2f782d36025mr59846369a91.25.1738020377423; Mon, 27 Jan 2025 15:26:17 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 14/22] target/arm: Remove fp_status_a32 Date: Mon, 27 Jan 2025 15:25:56 -0800 Message-ID: <20250127232604.20386-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace with fp_status[FPST_A32]. As this was the last of the old structures, we can remove the anonymous union and struct. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 +------ target/arm/cpu.c | 2 +- target/arm/vfp_helper.c | 18 +++++++++--------- 3 files changed, 11 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05a58de045..e6513ef1e5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -687,12 +687,7 @@ typedef struct CPUArchState { uint32_t scratch[8]; /* There are a number of distinct float control structures. */ - union { - float_status fp_status[FPST_COUNT]; - struct { - float_status fp_status_a32; - }; - }; + float_status fp_status[FPST_COUNT]; uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 777e5f5dd8..180e11c5d7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -550,7 +550,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type) set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]); set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); - arm_set_default_fp_behaviours(&env->vfp.fp_status_a32); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index e0d0623097..a2775a2e8d 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -117,7 +117,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) { uint32_t a32_flags = 0, a64_flags = 0; - a32_flags |= get_float_exception_flags(&env->vfp.fp_status_a32); + a32_flags |= get_float_exception_flags(&env->vfp.fp_status[FPST_A32]); a32_flags |= get_float_exception_flags(&env->vfp.fp_status[FPST_STD]); /* FZ16 does not generate an input denormal exception. */ a32_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_A32_F16]) @@ -153,7 +153,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env) * values. The caller should have arranged for env->vfp.fpsr to * be the architecturally up-to-date exception flag information first. */ - set_float_exception_flags(0, &env->vfp.fp_status_a32); + set_float_exception_flags(0, &env->vfp.fp_status[FPST_A32]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_A32_F16]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64_F16]); @@ -196,7 +196,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) i = float_round_to_zero; break; } - set_float_rounding_mode(i, &env->vfp.fp_status_a32); + set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32]); set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64]); set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32_F16]); set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]); @@ -214,10 +214,10 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) } if (changed & FPCR_FZ) { bool ftz_enabled = val & FPCR_FZ; - set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a32); + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32]); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64]); /* FIZ is A64 only so FZ always makes A32 code flush inputs to zero */ - set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a32); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32]); } if (changed & (FPCR_FZ | FPCR_AH | FPCR_FIZ)) { /* @@ -230,7 +230,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) } if (changed & FPCR_DN) { bool dnan_enabled = val & FPCR_DN; - set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A32]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A32_F16]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64_F16]); @@ -495,8 +495,8 @@ void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \ } DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status[FPST_A32_F16]) -DO_VFP_cmp(s, float32, float32, fp_status_a32) -DO_VFP_cmp(d, float64, float64, fp_status_a32) +DO_VFP_cmp(s, float32, float32, fp_status[FPST_A32]) +DO_VFP_cmp(d, float64, float64, fp_status[FPST_A32]) #undef DO_VFP_cmp /* Integer to float and float to integer conversions */ @@ -1383,7 +1383,7 @@ uint64_t HELPER(fjcvtzs)(float64 value, float_status *status) uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) { - uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status_a32); + uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status[FPST_A32]); uint32_t result = pair; uint32_t z = (pair >> 32) == 0; From patchwork Mon Jan 27 23:25:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860280 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106920wrx; Mon, 27 Jan 2025 15:29:10 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU0CzdIHdEY/ye5VZPr03A46QxIAQXwEQ0qqJgPNOz6rNYQVBWt3L6hIpebWIYHhWx4m24f2A==@linaro.org X-Google-Smtp-Source: AGHT+IF9TcdwlFkhWzyG/Eb1Vl1xEs95DlMXELtN1RoiYZ41SSGqcpZvtc4Hd+pEcO9v+AjbOqA9 X-Received: by 2002:a05:620a:408c:b0:7b7:142d:53d4 with SMTP id af79cd13be357-7be632480c8mr6203589885a.39.1738020550302; Mon, 27 Jan 2025 15:29:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020550; cv=none; d=google.com; s=arc-20240605; b=Ky9FwcKBp4DdHm2hLSYZF99ozMbJyipQPScVfUhFykgRhvLmCtJ0T5FlvmCm345QMX YMqbmubCP92/hIbDOhDqe9T/LGstC0isiEIqIV1B3H3biyMiEvR6igv715v3dOXOsCC9 PkncPEKT4XCaQnNcSbaLlu8RD+e91UsPoQYCOl1GmFRSU7iUqxlcKPJMXOk+1dNNZltD ZPc7wNjGXDyqkwudMRtUQ90amnzZTisY8pRZJ6RExbiJLSmhkM0dBk73c+lLUubz7TIO BM8sVF7HSHjDYiy2zA/a9xPZBJxQOEfEAJoiZsNX3OCgrA/5FrSB8ZyeUnyWJsEzbx0v ZSug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=b7xWXB+eng8DnKFn3D01/tYMXRHmURU0wtcrE+/Ypck=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=Uh3FWKAemlocYCYAAxCDL1/WLC2CrI3Z+ZuUpIELqJdOnekCFfqF9GDlADaQcwbWWg 4v0YLCrYNG729wR0I+vur6jRmbLjXyUgRUJau+KA7NwxV4tKCBqUa0IZwZtn8w0UpCUG FNd1HI8Xv8ssJXfUtN+d3BqSZNNkItYGp1itI876dIhOSJjZleANifiwm58xKQJAdnKx MoK3N8S+iVkgG8nkVExKic+Yqk/mpPK9FDse44tPKW13I/HFSiragFG3v1qEEllZ7VZ8 4XKLl2MuXCLlEKlBpqYVt5Qnaoh2XDxjduWkPfp9atoBtg86vvmWDu6zZlo0/oWnXmmh GzaA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jpUWg1Ca; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7be9af113b9si1080471085a.478.2025.01.27.15.29.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:29:10 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jpUWg1Ca; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUw-0006Uh-Iv; Mon, 27 Jan 2025 18:26:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUn-0006PI-Su for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:23 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUl-0005cB-MV for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:21 -0500 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2ee397a82f6so8822029a91.2 for ; Mon, 27 Jan 2025 15:26:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020378; x=1738625178; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b7xWXB+eng8DnKFn3D01/tYMXRHmURU0wtcrE+/Ypck=; b=jpUWg1Cau8kzRH6zebyOnYMWMTWMdrE3syO9Bc5xidBvpUatoAt1QHndAHRZ5lMeji sJoR5aAYrm+bcl0/Ug19F2RDOcdv0A+kt6cMoJtLPy9KB8qrGsqgsJqUfrE4q1qk5SgC MzNmjMJTVDpCm3AeRRYnI6u8O77vorxqt+6YPFSxuyyyXypGxlDJKoFwpeAQP5/nETd8 5tMYa8rv4XYze60k/qhF/jsfKdCjUulqD5yCOfIhLaYMyYyMjdPIJ5Jv4Wg5XskYQ1qQ cN5k0gdeG4GMR0+gMlvJoYrMb1VabuOHYBy5dSxfissPJw6mhUdLN9lNZVtvLAPCTgWj mMOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020378; x=1738625178; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b7xWXB+eng8DnKFn3D01/tYMXRHmURU0wtcrE+/Ypck=; b=BkQRXKQBjgogLLS+gan2M733HpFvWrTTXCEMqRFRHbAwx868UHpw3b+W6qMcoNgnHt TrmZ2YXiLcXqw+rDkoJvqrOGrU1b7OunXb2EOIXCszEwr+Cw7iUxRmW181xqhuR/FGay dWjQK0CkJ9lu5Q/2py7cYMKMF7EmDJfV86pOj1ysRg50zJ0JaWnD8PYQXBrwam2FV73U Fx8edJDB+10WmPLtKJ3ioi5YsfNK7sdTY7a+VRosDQTtIVMOVzYfXzbeOiNxH8D8hsPy W8k5b43fdr3cRTEX630rEyK7rVEUYpM2YwpLiZfgHVu9W65GjvqojgmD5n0t5363LHSZ LZdg== X-Gm-Message-State: AOJu0Yzy5qlDEphllVvrN7uTkDac6ueMYaWJ/2QGJB4E4aZZDDc/9nn3 yvuGbHNZFvwq+yngL9jEeuotP/m8KyIkF7cXfbhsGbfxKdkWH3livrvAwd7j9BB8h8JVYkqo/hf w X-Gm-Gg: ASbGncvK+k1pPjIYJ7Pja6yMP7wG8TtpLs5xV2P9ZG/fFo4wEQKphqLEUpg1+xMBFK4 3ADYOkCGBTjPbdh73smJVSfQRqDyEAF4AsoiA9/+Dda0FTuhCQMzHLUBHhbeIQlxDzAn0jOAAAV GSimSNW4W03Nhj6tCwb4MFy/hlMyu9TLaItAGgfsIhDxZrrFeJVj6+z5II1iNNuMRvzLZsInnHG lEsGqk537wHzMDQIXKbGCUpGnfhHGP5LUQ6tXKhphC8pO0nF1UdfVF8p9K5t4SwWE0Pn5jdVJBo Z9voXN2ZBFyTAgnYfnaqXxuMxidNwwRqPzbQ3rg= X-Received: by 2002:a17:90a:c88c:b0:2ee:c059:7de3 with SMTP id 98e67ed59e1d1-2f782cc01f5mr70851429a91.18.1738020378131; Mon, 27 Jan 2025 15:26:18 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 15/22] target/arm: Simplify fp_status indexing in mve_helper.c Date: Mon, 27 Jan 2025 15:25:57 -0800 Message-ID: <20250127232604.20386-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Select on index instead of pointer. No functional change. Signed-off-by: Richard Henderson --- target/arm/tcg/mve_helper.c | 40 +++++++++++++------------------------ 1 file changed, 14 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 3763d71e20..274003e2e5 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -2814,8 +2814,7 @@ DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -2888,8 +2887,7 @@ DO_2OP_FP_ALL(vminnma, minnuma) r[e] = 0; \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ if (!(tm & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -2926,8 +2924,7 @@ DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -2964,8 +2961,7 @@ DO_VFMA(vfmss, 4, float32, true) if ((mask & MAKE_64BIT_MASK(0, ESIZE * 2)) == 0) { \ continue; \ } \ - fpst0 = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + fpst0 = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ fpst1 = fpst0; \ if (!(mask & 1)) { \ scratch_fpst = *fpst0; \ @@ -3049,8 +3045,7 @@ DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -3084,8 +3079,7 @@ DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -3116,9 +3110,8 @@ DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) unsigned e; \ TYPE *m = vm; \ TYPE ra = (TYPE)ra_in; \ - float_status *fpst = (ESIZE == 2) ? \ - &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + float_status *fpst = \ + &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ if (mask & 1) { \ TYPE v = m[H##ESIZE(e)]; \ @@ -3168,8 +3161,7 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) if ((mask & emask) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ if (!(mask & (1 << (e * ESIZE)))) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -3202,8 +3194,7 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) if ((mask & emask) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ if (!(mask & (1 << (e * ESIZE)))) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -3267,8 +3258,7 @@ DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ @@ -3300,9 +3290,8 @@ DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) unsigned e; \ float_status *fpst; \ float_status scratch_fpst; \ - float_status *base_fpst = (ESIZE == 2) ? \ - &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + float_status *base_fpst = \ + &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ uint32_t prev_rmode = get_float_rounding_mode(base_fpst); \ set_float_rounding_mode(rmode, base_fpst); \ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ @@ -3427,8 +3416,7 @@ void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm) if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ continue; \ } \ - fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \ - &env->vfp.fp_status[FPST_STD]; \ + fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ if (!(mask & 1)) { \ /* We need the result but without updating flags */ \ scratch_fpst = *fpst; \ From patchwork Mon Jan 27 23:25:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860276 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106749wrx; Mon, 27 Jan 2025 15:28:34 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWPmmSeq6Hk9flyn6ok7FLIc1/SQPblfcadI5SZa9Qiprpbpd/A1HVeTZOKPxhPAJreJZslWA==@linaro.org X-Google-Smtp-Source: AGHT+IF9hmu8Vyc9/eChhsHCuasVSoLe253WkTAW7grv+wVyFvs2jHxYksRJa4iYU2bGLvpbzAH9 X-Received: by 2002:a05:622a:4c:b0:468:f722:d44c with SMTP id d75a77b69052e-46e12a3fa99mr685770171cf.21.1738020514089; Mon, 27 Jan 2025 15:28:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020514; cv=none; d=google.com; s=arc-20240605; b=V5lfhuaao2XEvZTpC4u93zOoJXOTyMd3G8f//Uw7NwAAqtkCq1t/0MgYjmcqB/hLTv iEX//1aEmA1jkITpyJX/nNA/FVl/NY7t0AnVRe/ZsSuOreFmbEz34TjC2LHwhWYKNsRl pq3hPjkWYTlaJCBoyy/Bo38k515b9nP96T2LvBN0Mk17Jksa0j5aHJn0EAGPZHU/uutS Jj0gRa7Z+MqTk5mprJaBB0/xF+zy860VOswfnCD0MF1zmQVbuNiKpx+T2bh3S/FF/7QP KM4ZLZdhM8h4IhRlcYCgsol04kDAhf0Nth0iITKYwy8SeJfxJH5K+hthepWwD4hQk0ng z2cA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=N9C9MHfxTmFfsV2AIVVMljAT4X/LA6EAwI6JuJhSI5E=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=Bm9nqeResB+qmDfh1n17EqdNDvPcGJ1JSpdeW5sJBZLXZ3450onbE0BRYgtVmccJBA FiPabw/CVDQ3EfaqTndV714akWp2z5dNmqflrRHQcON+OBz9wzAlfxarnCOAEkgS5HFT DHMUAsnovwHOB7LnsohRCCXDkn5qJFuJZKtIBu5F9Wvt1oO72Ci6/JqlpOeQPm5vBTZd 62xX7A8AvzVOcTXt8V+DP+MoxwcK0K9BSCW0RGCpqoIrpmh2ZIBhKTdAhKQNLVvuBe8R 7D8sB3kJjd8dwXIgHenUHj3kGRU+EGAu9pmlpCHgmRxQZLZG+hoEql1ELvYz0L3jabbL 6pOA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="iubO/aNM"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46e66b6b130si121467501cf.322.2025.01.27.15.28.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:28:34 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="iubO/aNM"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUx-0006VU-Jc; Mon, 27 Jan 2025 18:26:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUo-0006Pl-QF for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:23 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUm-0005cO-1H for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:22 -0500 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2eed82ca5b4so8527832a91.2 for ; Mon, 27 Jan 2025 15:26:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020379; x=1738625179; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N9C9MHfxTmFfsV2AIVVMljAT4X/LA6EAwI6JuJhSI5E=; b=iubO/aNMQtUHz0F35lKgY41nw1w3E8LIH37G6AGVfGnQ1tW3DRqmIMdJpFH3Yhye08 H1JMteBjumh77v3y008ax6LfyKW0U6YRmlQf/lDyHiqGWSih8/gKEWb8V5ACKobIghFq Fw+Wj0jebGEU/+AcomWcaqTNMt+5EAe5Q/caY+XMUDDIbYJ86IQuAK09vUr1QDHdODxQ yGlQE7+vG4alL2VqQonXPv/7T8N7Xoq3HqcF7lRoS0NvHLPVEoqOoW7daf9BsumwFghh 26sYW9rVInqiIy21KGA705rDm/2k6HJAD2MUcFsnrnid6EBlSl/rBeP1NNMmB8gu3jan HvHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020379; x=1738625179; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N9C9MHfxTmFfsV2AIVVMljAT4X/LA6EAwI6JuJhSI5E=; b=pm/qf3+Uv80ds51GJrODM/gS8zMyuyb8iVp2dAWCxWd26ILD60aawCS0j6bNBrMeFg MLqap9VY880DegUhI9Uvn/9s8aQsxYttHTD8fHlXo+LMVADRl+mZB5We41nF28cegtyb fRqZTYgPobYjoVGHXC9S4wzYlgvGtAy081Wmn/9JFDlzlgjEish82SH6BfYZDR/+za2F dYjdBwmzTCV4eV3Ylfg0zuCLeV3YkNd6n+MxYxbVrgp1YrS7NW8W+JoOMbf1C2YcTFeB J2Gzmu/0DsT8e7kPBMy8Dn1Kzi7XDcBE/60V898nBBns/nFy1ql5FRKR2CNSOEf4cc4O Gl9Q== X-Gm-Message-State: AOJu0YxHPMBgUYjG+Hf1slKn4bFmkHx1cboXXSde104gRCJtYiWyEFWf BCxc0rgnuWrjjiDiPgDYsY4tjzh+e9JTE9Pz6J2x6R7GxenI4xNV0Gj+LLUJD3oq1WQvF8ONA57 5 X-Gm-Gg: ASbGncsgp99s2NlpjnASUEkFouFi5xg2IqcHiqOB95vx5xyi5Iw9vCANCB5y/8Co0Iv OyweX8JCc1e8w4jVGpATdWq9FCZXdT+N3VQZ9in8lI1sOKfF53jABcumW60Qm7IicbtLhBnGJr+ xaSBdNDruQpBcHkKsXucO9Mub0mz7Og5ZMsuMyGID7SP+3pU0zjC+BGYNoycC1w7wwGueibdq8x l8pqSuy6pRyZooumOWmeJuQFZVWHD8pL+WS3DJpQ0tktaZyWQ62K7HWPB50LlqS5TG193zfTUCX SQ8VyYPJNQUfRnNGm/J1nUf9zGcOL49F92zIOQU= X-Received: by 2002:a17:90b:258c:b0:2ee:c9b6:c266 with SMTP id 98e67ed59e1d1-2f782c71d97mr62404058a91.13.1738020378764; Mon, 27 Jan 2025 15:26:18 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 16/22] target/arm: Simplify DO_VFP_cmp in vfp_helper.c Date: Mon, 27 Jan 2025 15:25:58 -0800 Message-ID: <20250127232604.20386-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass ARMFPStatusFlavour index instead of fp_status[FOO]. Signed-off-by: Richard Henderson --- target/arm/vfp_helper.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index a2775a2e8d..4e242275e7 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -487,16 +487,16 @@ static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp) void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ { \ softfloat_to_vfp_compare(env, \ - FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \ + FLOATTYPE ## _compare_quiet(a, b, &env->vfp.fp_status[FPST])); \ } \ void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ { \ softfloat_to_vfp_compare(env, \ - FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \ + FLOATTYPE ## _compare(a, b, &env->vfp.fp_status[FPST])); \ } -DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status[FPST_A32_F16]) -DO_VFP_cmp(s, float32, float32, fp_status[FPST_A32]) -DO_VFP_cmp(d, float64, float64, fp_status[FPST_A32]) +DO_VFP_cmp(h, float16, dh_ctype_f16, FPST_A32_F16) +DO_VFP_cmp(s, float32, float32, FPST_A32) +DO_VFP_cmp(d, float64, float64, FPST_A32) #undef DO_VFP_cmp /* Integer to float and float to integer conversions */ From patchwork Mon Jan 27 23:25:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860279 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106914wrx; Mon, 27 Jan 2025 15:29:10 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXlO+ulHElmeyFXm1zViCt7VqqNDb9S7KQ7Eao8lVe4CMUoZMRteASHPdzM4f4X2VkPAMTsoA==@linaro.org X-Google-Smtp-Source: AGHT+IEjmr0bw7jFMqH9QOaxzNYLLYM9UQnCqEGxhtn/S9h5LRGvj6FdNa25h44FLIbqZ+Duo8MP X-Received: by 2002:a05:620a:288c:b0:7b6:ebc6:181a with SMTP id af79cd13be357-7be6324cfb8mr7040019385a.41.1738020549988; Mon, 27 Jan 2025 15:29:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020549; cv=none; d=google.com; s=arc-20240605; b=d+92fq0lJaRMOM1mUTc8dakKnmoMfq+rL9sR+HkNVHHwjP0BxfRJ0AnYU8IorVMxFZ 5VnvHibUoipYP81/Pysg59LuCYwMczVFoeCc7CFbKVPjRdyteSvvhFNOfeAhiqCtESDw AvPfCXfEVgDoFICZntbARBqfGK1xNUma4s74bUUC7Eb1KCKJYkO34g5mjdJ9opatUUYP 9J84AuJnMlNIJ1x19UAbaDcr5aDu3OfMmjC5tP302DBnEvIRf2CPvUekEptJbErWGDL9 zTBf0cjWVDX7ZLzCnj2PxdUDOT9eGol4bKwWSCgRXxiPvKGTHh+z/inrMK1+V8HfS8vl Nxwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GA8OMBaKoWm1dr2kAwaJfnYaqSkCIQYp9JiJNnvOmTg=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=XRNwvQHCSqTLvC1s+rWoz1MllCS19e6RfgzN89ZbbMQr27l7gm2bFzjZ1LYy6H5xnS WgpI8wXCDeh3vJeiqiKdxP7DOElnTWhmMqIAnRbxun75hPgpLzmQlstJSStZECDUGq+S aRAnYP8y5dbqlUt8TywEFRducxBEQdJ/VYC+GIa+9BELhuvhtZH1FmDPMIs0PsNHqwEu 1OBEqNZwXutWNpIR9sqg+owR5RFFxvy5FyQ4wrQ2Ldll8wXleBrQ4Pm85eW3BXtb2Bc5 7zcM//Q6ApY+025nfPnk/ptccxHWOrprLaF+q/pu/WFf97zHzzkdLrC7erPTRydM3Fn0 rTMQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aLg6F0KI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7be9aee016esi1231980785a.203.2025.01.27.15.29.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:29:09 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aLg6F0KI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYV3-0006b6-2b; Mon, 27 Jan 2025 18:26:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUp-0006Pn-56 for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:23 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUm-0005cz-TE for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:22 -0500 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-2efe25558ddso6664626a91.2 for ; Mon, 27 Jan 2025 15:26:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020379; x=1738625179; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GA8OMBaKoWm1dr2kAwaJfnYaqSkCIQYp9JiJNnvOmTg=; b=aLg6F0KIigLpi7r1VWb8KqsJOUeN46EAZufzL4pEwo8dBOwDA7ak0YZregDcNZw4EW 2g1x0eWFZkY7TU+pwmHn8rx4X59WdZlFKjZcU0olgCyb2u+6eSxtuNy/n0p35ZzcIddH AXAyxv6sOqA2gY1Nx5a4K7a5S405PpqqstFlBGQS7x6SX6f+zO893ZF6Wd6P+bL6/PNe ZGo8GNLp2XwARm4BWM1DGWLKSPfD2IPycL3TqF6dY1wSFY9hKwuM1Cr6ehZQUk9YR2yR 1qoQ0LCet3Sj7l+WhfV4wy5uWTZwNCN8PZ2hrNsbGT7zzbk8B3E2Obh38n1CvQ8Z6K/w p4hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020379; x=1738625179; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GA8OMBaKoWm1dr2kAwaJfnYaqSkCIQYp9JiJNnvOmTg=; b=jjZQ2+ObNQ05gtEPmdziswf/aUqmCsZFz9J0uBGT2l96qXGNvVQjQX2IxLkNvg+Otz XrZxBahZKTucnffSHMD6sk4l5SVX/wyL7gtCeunDIiaOsezfGR11R+H8hRRVevoahd++ Dgu7nGvEPu/jzQPtkqzJbDvjrteO9zoF1UKhvuhoStnprxNNLXDSX87J1PacQQwrgm0H 53LmEJYgXT2g8Z6XxiFjVUz4klJIM43UzsZZ7HBnVN+zh7/oVml+T+9UViDgOwI0HbgZ fSEJ5B58vqHVoRN4jQ+W5CJ4UeQ2gq7/uleV4nWjWily2piWslbb6do1S+Zmxwc5H5kX nxsA== X-Gm-Message-State: AOJu0Yyj4RW4+iATMm8YgGKwxF1nBDwheG0iCYCJmdpzRrcfqbHrpzcA xd8K4b2B/dCTh+Fxe7B65UgpWe21jSFUKPcVZ0wuuARyCLZ/zFqajIiqT6d54w5v5FeLAv5SYUP + X-Gm-Gg: ASbGncuKZtztkrAKQdXGmmMjMwTmuALUS+DMEsyDtbfhaTgjqaSWZ4hM6EIKjtqJuCm VvUx8OwH5vi9pbBcdWN7PQlb3sDqd2mzDyH/8DubMDcohY9SZOk3EcrwTff6swyEvw3OkSOsuwu OSP+lDaYtosh1guco697mLi+f+w4O2nlAV7AG30EcTmTReo9YxL8nPhgZK4rsnX3WAMchGsk5Wi OY7qHjzSiLawSa2u3uWzIw7B/5FZRZ/B96eHc5F4YmISzb3e969ewivOtz8AmeddIbKK2A9KmIG 6modb5JmX/rYYWrY8Q4wnXWWa9AQZZZxvenEG5A= X-Received: by 2002:a17:90a:7187:b0:2f7:e201:a8cc with SMTP id 98e67ed59e1d1-2f7e201ab8fmr41113910a91.18.1738020379539; Mon, 27 Jan 2025 15:26:19 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 17/22] target/arm: Move float*_ah_chs to vec_internal.h Date: Mon, 27 Jan 2025 15:25:59 -0800 Message-ID: <20250127232604.20386-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/vec_internal.h | 20 ++++++++++++++++++++ target/arm/tcg/helper-a64.c | 15 +-------------- 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index 094f5c169c..a673935f48 100644 --- a/target/arm/tcg/vec_internal.h +++ b/target/arm/tcg/vec_internal.h @@ -20,6 +20,8 @@ #ifndef TARGET_ARM_VEC_INTERNAL_H #define TARGET_ARM_VEC_INTERNAL_H +#include "fpu/softfloat.h" + /* * Note that vector data is stored in host-endian 64-bit chunks, * so addressing units smaller than that needs a host-endian fixup. @@ -265,4 +267,22 @@ float32 bfdotadd_ebf(float32 sum, uint32_t e1, uint32_t e2, */ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp); +/* + * Negate as for FPCR.AH=1 -- do not negate NaNs. + */ +static inline float16 float16_ah_chs(float16 a) +{ + return float16_is_any_nan(a) ? a : float16_chs(a); +} + +static inline float32 float32_ah_chs(float32 a) +{ + return float32_is_any_nan(a) ? a : float32_chs(a); +} + +static inline float64 float64_ah_chs(float64 a) +{ + return float64_is_any_nan(a) ? a : float64_chs(a); +} + #endif /* TARGET_ARM_VEC_INTERNAL_H */ diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index ba21efd0bb..dc96c92a21 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -38,6 +38,7 @@ #ifdef CONFIG_USER_ONLY #include "user/page-protection.h" #endif +#include "vec_internal.h" /* C2.4.7 Multiply and divide */ /* special cases for 0 and LLONG_MIN are mandated by the standard */ @@ -208,20 +209,6 @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, float_status *fpst) return -float64_lt(b, a, fpst); } -static float16 float16_ah_chs(float16 a) -{ - return float16_is_any_nan(a) ? a : float16_chs(a); -} - -static float32 float32_ah_chs(float32 a) -{ - return float32_is_any_nan(a) ? a : float32_chs(a); -} - -static float64 float64_ah_chs(float64 a) -{ - return float64_is_any_nan(a) ? a : float64_chs(a); -} /* * Reciprocal step and sqrt step. Note that unlike the A32/T32 * versions, these do a fully fused multiply-add or From patchwork Mon Jan 27 23:26:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860268 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106262wrx; Mon, 27 Jan 2025 15:26:45 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXqM8PCqwOs5h11DCOjxbsn6C6brnTofbQ0VnWuuOFiMyYJzFCdIwMEKrEiju7CFFVa9iNQuw==@linaro.org X-Google-Smtp-Source: AGHT+IHXagbddqfplT4/KBpOdVfH3jktYxJaqNVCFAf1Qdlu1tDY+A3hxrVch4Ons9pLNQDKx/sq X-Received: by 2002:a05:622a:1a1e:b0:458:5716:fbd8 with SMTP id d75a77b69052e-46e12b6874cmr645461711cf.32.1738020405141; Mon, 27 Jan 2025 15:26:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020405; cv=none; d=google.com; s=arc-20240605; b=a6HEz5L6QT8nyuJd+7LIS5l7RRU0PLeMdbDx++WCP1HS2YtvlICRYHjvgzWX39/Pyl xqDvvKYc5iD+khDzGOspQFh5L/KU5AxwaiGi/ozNaE3eyyaJuLTwLKG9xnYpr9DweA+H 5eRan4vhdQ4DbyTwU9zjNiqB6p8+fKkbvRE4f9Svgy78Nsfni2rOb+5/uHXJ6Hc/JLAj ctqMEWXpe57xJ7YGClvcmHA2cVMw3odMJ2v1qdZc/scD7QNQ+s6L8VJ8sUpAD2B5sxiu jFs9Q9j9w/iZEVQqescS6ZgUEM3ftQHodkV0HuI2MzBhzwZ+R3pqEmH4bHLqMwLZp61h zrSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TizWhFZw5JvY75vssZ/TpOwGEzqE+NmThakWyt0pk6I=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=M57HDsAMTFjXL4P5jfIKRu0U1WLqiDe6xKtZ1smovAXRCTmA4LhL8Di+JTSbs2XS5F PfoRQsemL+wRolCSFVEi3Os16naHY5y08Qly1E58oc+Hs9BIhTYaZmS31ERofIwy8Aha UJ4od1a4Vzu1/pjqj8fIRSHzxJmuvtS8Gz0/EslG08TeiejWIcx/IBnT7MVnwKAhHWvJ Lf0hRVqDhALU8Osg7GWaPOt2tERpscaXDIGU6A7nNtDA7pyCz86arIHzKv/D4hOY1BCO p2a3reo3pj+CXQ9GsVsyL82ziLDWR45J+aFUuNfFtnJhi0ofXi3YCrgBhOOqH7B/ZYpE W3Cw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xUR5UQEm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46e66ba85aesi120755911cf.584.2025.01.27.15.26.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:26:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xUR5UQEm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYUy-0006WB-7L; Mon, 27 Jan 2025 18:26:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUq-0006Q2-1q for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:24 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUo-0005dJ-Iq for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:23 -0500 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-2ee8aa26415so8614068a91.1 for ; Mon, 27 Jan 2025 15:26:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020380; x=1738625180; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TizWhFZw5JvY75vssZ/TpOwGEzqE+NmThakWyt0pk6I=; b=xUR5UQEmekFH9j9tUCpnwqjXSp83stB2naM+WCf0SbdQFH0znz0o7ddV9/hmrGaVss RtBMpt9YWe/oc+jMLh9m+mtqE+d3K8wUhfjrqwLf34dW9iGVvsCA8lQs09d4xb8EiwR5 MJnFhI/HYoaVFisyMwY/bQSN+I6g7Bg8xcBsFFA16DJ8u2TI8/LSqaJ4r4MIGIUbZwIT wzcLLY0I+6BlcQdHkFTFfSGatPMPUOPWP1XNQl25Y6LmvHYpqIe0mwRXcZxx/h1OnkY/ huJVOag3AUKHyZ4+v8/vsjWejOhShz6KmJWz/IYXhAhpbiyqkY+BFEPMY+VZugIJqJXP NHgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020380; x=1738625180; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TizWhFZw5JvY75vssZ/TpOwGEzqE+NmThakWyt0pk6I=; b=f8gmHzNzFcdYFs/4iHspPKSn+Gy5O4/q1TvZopSFSF3ei4QDjGtFO3D74vNfv9X0mE 3MwlRHkpF3TGTSERUKloGicjhUEj9FNdHH+C687lb/QWjNHGYhTNywqMjBpV3koiuShI ip532aRRN29zW/fcr1VrMhJZZ65kTJ3KzkMWXDQ4JJiPil0NnBm32uZeOpNYepWyirh7 uRDtiGLUe2MVGL9VhsZfyub+njMKjU7BS5N5L55Rl2uWKRb4NCP2nJoboacSyt0e+XmE PAVgE1VPn7lHxsAykWFK83bwagwRUqPpoQ5wmEDPbt/LwX72M9zLUudUFGb22+xxWB9H RO3w== X-Gm-Message-State: AOJu0Ywo529uIw0nOaJ9PyUCheIFIpiMkXO1kBEzwT0oNl2vXSkt5XFU mM0X1ADgk5v5G4ADXNg3MAvjtwx7tRAdz1pTDTNfJJ0Q42pvAZO59uKNQ0xFEMP1GWHaKe5CO7X O X-Gm-Gg: ASbGncuVKlcVIi6cX0a+QPeFb9uhL/UB/vAWysQwriyt1khwaHSqCSdKl2bYRpL+yzS mg1ETcmfzLgZwHgfken0tPDEfZh+g+rlrTWuwA2B3LtRNK/a/jPYtdSnnSVzxC7LlWp8bGvIFRA dTktl4hbnAh9FXOd/1Ks5sG4vrF2xhjWphAqC7s0srUBGqrsiLjS0Q49a4urvFhJ3gQBF9AOH8U pw42y+3tpkphKEw1+TG7to8rf0Uj6UujCXEuvwsEp8IrN7FSPehGRn6XEt0f/Hx4i5Z3BAmSZz2 6w3lTR0MNYAPYKHcukgf76WTOF3ELmt/6m/3iZw= X-Received: by 2002:a17:90b:17d0:b0:2ee:6d04:9dac with SMTP id 98e67ed59e1d1-2f782d9eb7emr56653302a91.32.1738020380282; Mon, 27 Jan 2025 15:26:20 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 18/22] target/arm: Introduce float*_maybe_ah_chs Date: Mon, 27 Jan 2025 15:26:00 -0800 Message-ID: <20250127232604.20386-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add versions of float*_ah_chs which takes fpcr_ah. These will help simplify some usages. Signed-off-by: Richard Henderson --- target/arm/tcg/vec_internal.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index a673935f48..6b93b5aeb9 100644 --- a/target/arm/tcg/vec_internal.h +++ b/target/arm/tcg/vec_internal.h @@ -285,4 +285,19 @@ static inline float64 float64_ah_chs(float64 a) return float64_is_any_nan(a) ? a : float64_chs(a); } +static inline float16 float16_maybe_ah_chs(float16 a, bool fpcr_ah) +{ + return fpcr_ah && float16_is_any_nan(a) ? a : float16_chs(a); +} + +static inline float32 float32_maybe_ah_chs(float32 a, bool fpcr_ah) +{ + return fpcr_ah && float32_is_any_nan(a) ? a : float32_chs(a); +} + +static inline float64 float64_maybe_ah_chs(float64 a, bool fpcr_ah) +{ + return fpcr_ah && float64_is_any_nan(a) ? a : float64_chs(a); +} + #endif /* TARGET_ARM_VEC_INTERNAL_H */ From patchwork Mon Jan 27 23:26:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860278 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106898wrx; Mon, 27 Jan 2025 15:29:07 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX35KJoyyMH7Sltkfkys82hL4DtVahkmA9tog8yieqHagwh/N5UGAb9kQhnWV4ZpMOJ/+cEng==@linaro.org X-Google-Smtp-Source: AGHT+IG08+oN0MsTclijMMcjruhRo4cCGM1uRgJkGBjvJv44PCf3JYbywQ4E/7DhhIaYXZDrL+eQ X-Received: by 2002:a05:620a:2a13:b0:7b6:da2d:73d8 with SMTP id af79cd13be357-7be6320ceb0mr5401529585a.28.1738020547305; Mon, 27 Jan 2025 15:29:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020547; cv=none; d=google.com; s=arc-20240605; b=hqDmDWMT+fnI6nsHdUbbjajRoCCklm/n5c6FmdPog0g45HKgjIxJlcYurZRtr+PyRv MZojjN09W+ukUZIz8XlVE4O8UmSiTkPauRnAadolDEY/nmM27Gglq5ZDhlPcEbXAKE1T Sc9Qy8iIRZohLyY9wr0LoRR7BjZg+1XTyp+qsa7lorGi8DXiFD3jJaCIE/A7SJm4XQBx 25Wxrjw1VS7QY3tkSscP8r7P/Qu+oYZUaoUgUW1EFSUBlYQBBCpn1dztYrCnDvblndEx 3bJBFoKO4NCk7K99l4nONoxrOdZklufsi2drugsA+0ckBr7pyWqnWbxZAQ/e+inb5z0m cmzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=p8BKUORijGQS50f4GtdAn/sy3ElbIpcuj5zDOx8ZwZA=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=VeOOithv3wX1j6/NF32nlIiXEi894Eghj6AeGYagRYk3EUgu2NxDclwO+BsD5d+5e0 jNYS2Y3XJxPgs/SHuSE1k4RNOV5Zb5MdrSdhBu2c6j491BLeqnNWobjYgm6TBEDXsU0G CRJse0qBEWmro7ypTd1ypWUMVqdIQxxZJu3zr7XzBWMacoladum0lvYVlJeuwum39Zya A6grSU9Y5QmsqvzWoR9dLgddGAqQO4R7tqH2+FnnaA1ybDlJqgjMQ6SoWh5fXStsr4lA 53WNQ9NJZVQvKZWMbo/LamVky226NNIpVOLMJAyVMC/vuJgwIYIA8oLPSGqq/DaS68y0 LN7A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dIbGkUQO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7be9ae9459fsi1071532185a.181.2025.01.27.15.29.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:29:07 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dIbGkUQO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYV3-0006bT-Vy; Mon, 27 Jan 2025 18:26:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUq-0006RW-Q7 for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:24 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUo-0005di-J5 for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:24 -0500 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-2ef72924e53so8596034a91.3 for ; Mon, 27 Jan 2025 15:26:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020381; x=1738625181; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p8BKUORijGQS50f4GtdAn/sy3ElbIpcuj5zDOx8ZwZA=; b=dIbGkUQOx1eDZI1o8T0KzdGViWUXXrVXDMKr2VW6YHi1hwzKvJNmGMnLX4Qvk9Ha3K pVqwfOZ9n2Vz1damJyPIVRF8H2s7RFW/H2ZMIR5pQerWG8DRvUQ7IhJCBdcg2XKr51ex A+WQhYBrvu0DWnmNrOWK7l5uydJakA8wVB25t3RAdHaEjwbOMP6DdNvS8S5wMJxSgt2D LFbbccd9MFDXOc0MOysipqBLGFU4yQJrobVxq0oWVS/HeXU/a1TYGyEooJbNvcaDzXfM UPejnNXh5rutiijbFZeGppJhw+yKSJ7G4ewmcuxgkvWGCvMAhmOrHJ8mYIFqm5kqc+1Y 0oMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020381; x=1738625181; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p8BKUORijGQS50f4GtdAn/sy3ElbIpcuj5zDOx8ZwZA=; b=Qj8oqPFJrfiMS5lcu1sAr55zUO9CL9+WQxD24lWcrPY9ZNW/A4CegrHKcdpruvliYT 8KES3UnPKMUAQ+iqgSnp0ZNvwxEwQ/ObvHdY7d8Ob9i74UjVM8f8w+ZikJrxQtiZm+U7 aPQcoq6gLmreTpDNI0c1sHA+gGUYIUnWcHjSDJz5ASZySFuiSUzAVLiaHG+YcmAkd7Vf i9XVGvjd86ZhGjf48PCtgBjA7gauvYA8KIZbzRF8/T6eGSVDyU8gl+7GnJCIgEfuQEkz FwsHTNRH1NhTgP8ppNOQQtp3bNgZljHtUr1nkahsBJp/ndV8lurQQTzSXOl7jKSwpYJj kNZg== X-Gm-Message-State: AOJu0YxpKSU3yvm4Gf60d4sh90GrrDivKxAaru/2lPzmRo9EMuBXssj7 kg53p9glfp5TjxR3+suioBbExFLYk967Km4FZKEFgRdpZLiFbNcDv3eMD0vuDq4p1kBkoheYrMB W X-Gm-Gg: ASbGncsJ5fiVdZ+81uB7WE3KYz0alcp7GESJ7+kLi8cg5SjeS5amfcTj6vXGuc7QV6p iaST8qUfXhu/yd6mwKyGVmyvYX9k5YF2eyqMmbvy+IwMBmTRjy38VANkuDOpTG0zz0fSW2iFIMB toogcz3cdYBkb39auCb9bAyzAkZpEI9c9a65Z+MAqHOK7fvaEf0/l7BeAl+PitjelqoKyNV0ZBs xJy92O/3glpwy1MuH5dd/ZK80yshgB9ZmQvmILI+AXXYbdhe0KT10fQfnRYfZIcIoZBgJv1OJyB /8PIfhymf3pfJvMfPKwgIAvELwaEt3FMdraQP/M= X-Received: by 2002:a17:90b:53c6:b0:2ee:fa0c:cebc with SMTP id 98e67ed59e1d1-2f782cb690amr63804771a91.20.1738020380898; Mon, 27 Jan 2025 15:26:20 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 19/22] target/arm: Use float*_maybe_ah_chs in sve_ftssel_* Date: Mon, 27 Jan 2025 15:26:01 -0800 Message-ID: <20250127232604.20386-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/sve_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 3f38e07829..a2ff3b7f11 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -2563,8 +2563,8 @@ void HELPER(sve_ftssel_h)(void *vd, void *vn, void *vm, uint32_t desc) if (mm & 1) { nn = float16_one; } - if ((mm & 2) && !(fpcr_ah && float16_is_any_nan(nn))) { - nn ^= (1 << 15); + if (mm & 2) { + nn = float16_maybe_ah_chs(nn, fpcr_ah); } d[i] = nn; } @@ -2581,8 +2581,8 @@ void HELPER(sve_ftssel_s)(void *vd, void *vn, void *vm, uint32_t desc) if (mm & 1) { nn = float32_one; } - if ((mm & 2) && !(fpcr_ah && float32_is_any_nan(nn))) { - nn ^= (1U << 31); + if (mm & 2) { + nn = float32_maybe_ah_chs(nn, fpcr_ah); } d[i] = nn; } @@ -2599,8 +2599,8 @@ void HELPER(sve_ftssel_d)(void *vd, void *vn, void *vm, uint32_t desc) if (mm & 1) { nn = float64_one; } - if ((mm & 2) && !(fpcr_ah && float64_is_any_nan(nn))) { - nn ^= (1ULL << 63); + if (mm & 2) { + nn = float64_maybe_ah_chs(nn, fpcr_ah); } d[i] = nn; } From patchwork Mon Jan 27 23:26:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860286 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp107118wrx; Mon, 27 Jan 2025 15:30:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUO1i670cOoZFlmHwibesXUeOyt7cKRJTC8f0kqSxNVeNBqxv8+hrLIihoE70HC8kNJ+pblrg==@linaro.org X-Google-Smtp-Source: AGHT+IEN8UTMZm8OqA103czukoyAsUb/QjU3/atPOESopSayoqr4A3GYnzVcVpRRU4wyCIr/tm/f X-Received: by 2002:ac8:5907:0:b0:467:5e4f:3d1 with SMTP id d75a77b69052e-46e12b90bc8mr650485531cf.33.1738020601094; Mon, 27 Jan 2025 15:30:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020601; cv=none; d=google.com; s=arc-20240605; b=ZgJHqAnPUhFZ7ROw9C52MCzw/AE300mxbqpM/zbDNPZsxir/8vfecIYNMoo3eTKVn8 V8QOiifUuowRay2y5YvXj6czr8NxyPRktNoHaBBuNEoSoDTJ0LupAB1a4Eanluwc40ss TZamGH2UQMPzlS+qTbZoZCsrOxOThxw5GoesDNSLyAaq/P8USX0UYm22pDrYWmIViegx /6ZNl+bDU8UPl0drRLS7EJXAe9IUwR9l54H548fqZrjMDHlKAE7TRiQJ0ppRbPxrdZn6 rf6R+3HPVkthvKGlORawZ9SK4VN+Q0ek4IVU78Ffd791lOq4hbaPDzn098GydY+NhMQS A9XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rk7p3KoLMaA8jIVTStdirSWe3SnWd0+FSfM/mtBWd+A=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=YdCqIpf+fbZQPGT1IBo+XKSav62fqMQvld+WFJ53axVEAx68Ct4SE6pHkUZ2CJxkq4 u+RnSR9cLQDS6+udCXg1TXi1ozI1wex+kFdhXqWh4+aViyQqo2GL8BrxSIVJTjKcGFTc 7grjDyBk2Usb7UXvkTL8R+WkL91ZHuQWXYhe+aAVlW1HmYV97we4YHddPIEDPabI67Zi ANAZy3toWw5OtUTicLJhECy1qwn3+y3w0aUAMmY2iIToBIKg63ZFBUzvM4G3S1Efgdt9 eIgm7nQs0VrXw5MtAiBMhjgWTmShKksZSYDXEXjTOsBth57AckH189gDGXQhiYQJxtkb egVA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nwKEgd41; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46e66b67bd9si118249751cf.226.2025.01.27.15.30.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:30:01 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nwKEgd41; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYV6-0006eI-Gm; Mon, 27 Jan 2025 18:26:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUq-0006RS-O9 for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:24 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUo-0005eE-NZ for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:24 -0500 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2f441904a42so8838740a91.1 for ; Mon, 27 Jan 2025 15:26:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020381; x=1738625181; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rk7p3KoLMaA8jIVTStdirSWe3SnWd0+FSfM/mtBWd+A=; b=nwKEgd41n42P9Z/QJibebnIX2HxAlpXQcQNxebz2zAwvvlLywnEg2utCEBJRP/UDCI WhEqfabPHoeYFdQntw5G4hPCv5jn7ifvO+0Ykr5m6J/64FeM7udrs3MmICSW10MYvGT7 JIXOzkwu9Cicn+Zd1h8t1DXSlekQTEVV9G0pA7WMBoJf3LiK4zOwR7Ji3YVdlBD4ZgMs vhei0TbL0iWm+YfZQzy3NWFlibEdDWcIDpHYuKzhoc3B9OZRWEbd8GuzVjE6Oho7PouJ bPd0445KQuORt1hnruJaor04aP+r2DUFK/jy6kZ2Hg9e587kleEmdWTJfP+fhgd2ThBy 8QTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020381; x=1738625181; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rk7p3KoLMaA8jIVTStdirSWe3SnWd0+FSfM/mtBWd+A=; b=lpGL3uKiDmpAqFzrDuIawZoyUq3UvIoe0r6/XvM4QjKJ7NfZTpZHETe6uFsZzYMHMS EP5B0ivWh6q3sFR3euCTiplXw0NcZZtMo92KUhNOpKsgi21SLJAtW145tySZNPDEkRXe R4ThtxvO/R3L0mvzCV+RK9sHdIfVUy6Bjgh7HKBoqXdU3JhZ/Q5YmP55NGibLZfy5+VG q3vRj3NXqxfx0dsOzK0YVhfz6+A0vZ//SyDu6nu7K1//enQJexYI0NXzmfk+fyi9n1HL MHFYXKBhswUU/dqH6x5NHcPIsMs7OzixCqogM89PYytS2piT5swKURdYR3kgCxZDbjzQ 7nxg== X-Gm-Message-State: AOJu0YzdX85i2ad2RivVf3ZLs9klHbcCYY495GS26J58t7gFxUi1ltVc iKm607UROap2r3KQWj+oABDWuBH9k5DQvpTjy8S4/K2fAIh4oWMUJbjEBl/Yv7V/A8vrE5qTlgr x X-Gm-Gg: ASbGncu/29vVoxr1YP7kXPREvqEUEupPhe9of9d66oCSWZutVJcZEwiSCHV0FlvN1sW +9qClrHqBfgBY4edEGK9Jkx7Pl76Wog+hnXMD1IUfIz9koNEBLLsXzMO0kG2F+hQP2HjzKIrWqs gRs0Q5+Ah4H+BPaGBe89p3vF511/QnHw5bRO7GXO/sq26GedPo6tHHbT+HV3SvH2dVUcmzDtjF7 f7YTy10NnvNl9yWBOTLARMpYAQfSyE3zp6qB5kUIRwLrtzzEZLxq9LkopzEfTWFXCU4Y3JSkiSW bEfVuAHsaHKQ8Ps1kQ7jcApe2ylnFQ0ifjef7yM= X-Received: by 2002:a17:90b:2dcd:b0:2ee:df70:1ff3 with SMTP id 98e67ed59e1d1-2f782b17a01mr74838549a91.0.1738020381450; Mon, 27 Jan 2025 15:26:21 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 20/22] target/arm: Use float*_maybe_ah_chs in sve_ftmad_* Date: Mon, 27 Jan 2025 15:26:02 -0800 Message-ID: <20250127232604.20386-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since we know the operand is negative, absolute value can be had by negating rather than abs per se. Signed-off-by: Richard Henderson --- target/arm/tcg/sve_helper.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index a2ff3b7f11..970947e1ca 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -5150,9 +5150,7 @@ void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, float16 mm = m[i]; intptr_t xx = x; if (float16_is_neg(mm)) { - if (!(fpcr_ah && float16_is_any_nan(mm))) { - mm = float16_abs(mm); - } + mm = float16_maybe_ah_chs(mm, fpcr_ah); xx += 8; } d[i] = float16_muladd(n[i], mm, coeff[xx], 0, s); @@ -5176,9 +5174,7 @@ void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, float32 mm = m[i]; intptr_t xx = x; if (float32_is_neg(mm)) { - if (!(fpcr_ah && float32_is_any_nan(mm))) { - mm = float32_abs(mm); - } + mm = float32_maybe_ah_chs(mm, fpcr_ah); xx += 8; } d[i] = float32_muladd(n[i], mm, coeff[xx], 0, s); @@ -5206,9 +5202,7 @@ void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, float64 mm = m[i]; intptr_t xx = x; if (float64_is_neg(mm)) { - if (!(fpcr_ah && float64_is_any_nan(mm))) { - mm = float64_abs(mm); - } + mm = float64_maybe_ah_chs(mm, fpcr_ah); xx += 8; } d[i] = float64_muladd(n[i], mm, coeff[xx], 0, s); From patchwork Mon Jan 27 23:26:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860271 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp106516wrx; Mon, 27 Jan 2025 15:27:40 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUFeyzVVvEGybQaS4Uu8SkPUklIwNUGLu5HOC4zzl6iCimCJ3xjrQMUqbHZrTPn7EAf9Udhag==@linaro.org X-Google-Smtp-Source: AGHT+IGW3prnVfgS+BB/+B3O13WzMc104/MELR2onn0VzTUE3d0lhBCgsOd+IA3c21+hw6ck2N6N X-Received: by 2002:a05:6214:487:b0:6d8:9660:8877 with SMTP id 6a1803df08f44-6e1b2183435mr687508846d6.18.1738020460329; Mon, 27 Jan 2025 15:27:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020460; cv=none; d=google.com; s=arc-20240605; b=MBmKR7oeFcj0Dfh+IqKihOXDV1A3YGf4dPjGh59Ot+KzgjqD10xy1ODxjSRKTwKLDq uD4eGmBUUtv6/QcENwnLlK1k3P7y/T7Mx0Eux0G/0YqGACJKFsSNOL4hhjmgooPGPf5l eHSy4kKrxj3pz+/k7qk4mJvqQQuoZGWCd2GOZ44wEjpVw9TkBG5YwBVr/cGf7LTpbmuI AVRHYCRxYb4Y/IkoONlNdPMNux2dMjnE5wBwFA/6mNau8SNMSxrORygPBsPB1DZxQp07 f0shVZu7c7Xd7tRsDH2YGAaZIFuVJgyxSYsPUOPmxJn+i6Tx7GMAJ0Y+LZa22eyCNpuy tvXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mdGVKX0T2Z/m16C6XyQIYLgpEZaPtHKKAWekkwATeW8=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=FV3fCx+oDpNG9JjgUB6UIMi17Ou6Zu4/WV1KO+2P35bp68vYKwbz7d53XVpRvqtPNZ iahdNNkx2xXE9UezBYSnL3WMVDgSDdxiL6qS5vDlvdhzsNvncKaJR3qjKzO36Z/FIZn+ wb+dZ/yrSsiER1Zy7ocOpWgUuvlXI4rvjUvM1nxfKnSQGeKL9+mUetSjYtHAYq421fMT NvMfrEiYGQzC8NfpoXRSHvpvQd7QgFMAEevltzoqohu2/xtoYYTPPsp7H9MEUTzwZZHl R0m/cp9DRSAvk80tOgI/O52W2kFeOei2/0FVhj2nT+4rxsNEgfQ6SSyFbAIPPs8wa88B PBrg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vprVtK6e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46e66b8b29dsi107580171cf.435.2025.01.27.15.27.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:27:40 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vprVtK6e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYV7-0006f3-6Z; Mon, 27 Jan 2025 18:26:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUr-0006S9-TF for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:25 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUp-0005eh-EA for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:25 -0500 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-2ef28f07dbaso6914026a91.2 for ; Mon, 27 Jan 2025 15:26:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020382; x=1738625182; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mdGVKX0T2Z/m16C6XyQIYLgpEZaPtHKKAWekkwATeW8=; b=vprVtK6eTGgUDuzNwbyzQ9FkfVZ7UkjxjBougCGaXhsA3W7S0ZBadbwhrlbqYcC4HQ G2wnX8psAqgBgxDW/9C5nMG/hRroAKJ5AnWUCgC5pL+aYgMUFbi+NZLn/enIlfeVTWo7 eRiXN/CR/FfBSefSP4lJRN5AzBGOOTeVKpctPBg5VZY0w42btDrWICBZt/vhVgBUJBDk KWwOqyG1O0y0CmjsxfQ2jx0sfCjYv7VgcMXkdWrJiRXDPutdeGz0KaxOMoZgr1cObdQS oxUQ+bws3mTlCBl48uGUH61Fdtf+yNQtNWhZvUKktfrYVKko0rZ0R12CQGGegWDfvAnM LAxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020382; x=1738625182; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mdGVKX0T2Z/m16C6XyQIYLgpEZaPtHKKAWekkwATeW8=; b=jdvCal4kDvDtRoQCyfyj0ZboyWh3WsRHwbK9+jrBj5be3QOzMdL7symwXSwHw8YkMe YqOBCH0MDcu5L85DsTOahprYLlsE+jhyy0Tlg7r1iC1bzRxJ3NNCdwNIdTPOEfvRE7f8 ihzGmF+FYS7S+c76Z2S232JYiC+ugwQIqxCviJmtdNc5lbkRsfcQZNKgu+Qa+eazz+sc 4UcwsJicJG74rVbOXuvyJdkz+iE/Z4AtJtnMHBXOJJFGkjak33k04rz8UyZBzfTTKFAs KLlWvpfVL9W0JXtUupFtUriumLHbJeke6APFrYBfonO4KUJF9qfaerK+PWTugpbSVDAu 341A== X-Gm-Message-State: AOJu0Ywk400B5y5mzz+9rX5FgqBgpatIRN3ifYPGcBRiggMQ8a/SJqhd VdN4ieEUBd4yQo1bL9W9/n1EU8YQ77PvUtyNpcLtwy2tFBiBq+OS3UvdWuBwaUXyKZtrXlYwEyD Q X-Gm-Gg: ASbGncsUVa1FMFVEHGczyUpybjjGBxpV/wnLwepxQS6vmH/ypmBPJZRYpiGg1lFgFn/ m6WS/Vz3lFdmkNmcyENam6HVo/BT1QEq/IV7nVDLMTatGE68oHfoFKcVTJIq2pB7GH4MeF+SPoI HLsn/R8QOz9VKwEgS0uBtsumQhFMY8xGD9GQ/ORZWmb0mfok7wHVYXkjpKP9Jhy6NcX295gq3CK J+RL3Zt9iwi3mvhp55O4BKZ6SeSEfwGj5j7zPWzSPnsvT8y1EHfPqHtClrXXnkL2Bu7MuvwEoxd VUzlFi/AHHXPBqJ8ebfYM2+5lTz7/HYxjCUf4Y4= X-Received: by 2002:a17:90b:4b8c:b0:2f4:9e8b:6aad with SMTP id 98e67ed59e1d1-2f782b11be1mr74792758a91.0.1738020382112; Mon, 27 Jan 2025 15:26:22 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 21/22] target/arm: Use float*_maybe_ah_chs in sve_ftmad_* Date: Mon, 27 Jan 2025 15:26:03 -0800 Message-ID: <20250127232604.20386-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The construction of neg_imag and neg_real were done to make it easy to apply both in parallel with two simple logical operations. This changed with FPCR.AH, which is more complex than that. Note that there was a naming issue with neg_imag and neg_real. They were named backward, with neg_imag being non-zero for rot=1, and vice versa. This was combined with reversed usage within the loop, so that the negation in the end turned out correct. Using the rot variable introduced with fpcr_ah, it's easier to match the pseudocode for the instruction. Signed-off-by: Richard Henderson --- target/arm/tcg/sve_helper.c | 33 ++++++++++++--------------------- 1 file changed, 12 insertions(+), 21 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 970947e1ca..6a5bfa0e59 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -5220,8 +5220,6 @@ void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg, uint64_t *g = vg; bool rot = extract32(desc, SIMD_DATA_SHIFT, 1); bool fpcr_ah = extract32(desc, SIMD_DATA_SHIFT + 1, 1); - float16 neg_imag = float16_set_sign(0, rot); - float16 neg_real = float16_chs(neg_imag); do { uint64_t pg = g[(i - 1) >> 6]; @@ -5237,11 +5235,10 @@ void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg, e2 = *(float16 *)(vn + H1_2(j)); e3 = *(float16 *)(vm + H1_2(i)); - if (neg_real && !(fpcr_ah && float16_is_any_nan(e1))) { - e1 ^= neg_real; - } - if (neg_imag && !(fpcr_ah && float16_is_any_nan(e3))) { - e3 ^= neg_imag; + if (rot) { + e3 = float16_maybe_ah_chs(e3, fpcr_ah); + } else { + e1 = float16_maybe_ah_chs(e1, fpcr_ah); } if (likely((pg >> (i & 63)) & 1)) { @@ -5261,8 +5258,6 @@ void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg, uint64_t *g = vg; bool rot = extract32(desc, SIMD_DATA_SHIFT, 1); bool fpcr_ah = extract32(desc, SIMD_DATA_SHIFT + 1, 1); - float32 neg_imag = float32_set_sign(0, rot); - float32 neg_real = float32_chs(neg_imag); do { uint64_t pg = g[(i - 1) >> 6]; @@ -5278,11 +5273,10 @@ void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg, e2 = *(float32 *)(vn + H1_2(j)); e3 = *(float32 *)(vm + H1_2(i)); - if (neg_real && !(fpcr_ah && float32_is_any_nan(e1))) { - e1 ^= neg_real; - } - if (neg_imag && !(fpcr_ah && float32_is_any_nan(e3))) { - e3 ^= neg_imag; + if (rot) { + e3 = float32_maybe_ah_chs(e3, fpcr_ah); + } else { + e1 = float32_maybe_ah_chs(e1, fpcr_ah); } if (likely((pg >> (i & 63)) & 1)) { @@ -5302,8 +5296,6 @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg, uint64_t *g = vg; bool rot = extract32(desc, SIMD_DATA_SHIFT, 1); bool fpcr_ah = extract32(desc, SIMD_DATA_SHIFT + 1, 1); - float64 neg_imag = float64_set_sign(0, rot); - float64 neg_real = float64_chs(neg_imag); do { uint64_t pg = g[(i - 1) >> 6]; @@ -5319,11 +5311,10 @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg, e2 = *(float64 *)(vn + H1_2(j)); e3 = *(float64 *)(vm + H1_2(i)); - if (neg_real && !(fpcr_ah && float64_is_any_nan(e1))) { - e1 ^= neg_real; - } - if (neg_imag && !(fpcr_ah && float64_is_any_nan(e3))) { - e3 ^= neg_imag; + if (rot) { + e3 = float64_maybe_ah_chs(e3, fpcr_ah); + } else { + e1 = float64_maybe_ah_chs(e1, fpcr_ah); } if (likely((pg >> (i & 63)) & 1)) { From patchwork Mon Jan 27 23:26:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 860287 Delivered-To: patch@linaro.org Received: by 2002:a5d:6b8c:0:b0:385:e875:8a9e with SMTP id n12csp107189wrx; Mon, 27 Jan 2025 15:30:13 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXssa/sxbvuHiYJ3obNphMppE2ci5KE9muihbu35p9siqxXi/TD6uwBdHsBCOfathJkOVLSTQ==@linaro.org X-Google-Smtp-Source: AGHT+IG0qaOVUM5yMnXdrRfrFWF4+/GDfn9PKToOnuAPFwsqgKV2fqHjFnnrkgiVtW5/+9yK6CUE X-Received: by 2002:ad4:5f4a:0:b0:6d9:2e4a:64ee with SMTP id 6a1803df08f44-6e1b218094cmr652063896d6.22.1738020612701; Mon, 27 Jan 2025 15:30:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738020612; cv=none; d=google.com; s=arc-20240605; b=jBBmQ/IgTg7QwNRWcyEa/P82RgUb0tn58UK6tKw+3tgvY1jIzpF+HPtyI3Y303U6vR Fh3EMBswmICF0FF6oL4XJUT46gVApk9LCQyhjw5kU69VA1m9hGeOEWCm5EOQKffX/zS7 U7obW0VosHjuITwXDP6qZWkFml897ktdQIIApKEv7VO1Xv31CnJFRUMKt2bPNJOSzqLI 0hsULH2qbKzxhxk6z2Ov6k6luZ4Q3WYsoep6aBSUP2YVG0FpVrvDZ8chXWle9fBrxJKf Sqi7DKZR9UmZs/0WZNh2Pi6MJLAHedGShcHi77HjV7s9K6GHoSYqnFGF1SrK4i4gjsml fXeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2GDxHDUfDEHJ5sXsQfC9s6zGTEGY5YOTfZmfjmgVvKc=; fh=igfKki9zV5i/IfmDn/Sk23mhfaq7a0iqiBvPmqdBsis=; b=HiBBT5nqdv0iNU3I6TUOg/iX/vQzNKYw/mLCf5P9cOYW3orPbUHXe87caBHvnxuxqh K/oyk5ZBF3TZndQwZZkQGozNzcWuFM0dt38U2A+bN+A76/O55S6kIXQA89OFPCTY5tpw e08UaeBrk9kNaPmoiKH8e6y/SMXgsAaAjdYffZwG06LpgghhW85MexF5ubUqNn5xZ581 GXtB5ar5tzqsWnqf5Os/TTZ+dQCPCCnWt2+mL3i/frr5VIUt/OaSQJsT+yhLZZ865I3n Yu5gEyiuDQN8knBeYYeqSkXqQO0UTivKpgnte+EHtaixJvqO2rVCeEUxJGsT6dEN6a9x Avrw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=prK1VNR1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6e20601ed66si120977426d6.381.2025.01.27.15.30.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jan 2025 15:30:12 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=prK1VNR1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcYV5-0006d0-7U; Mon, 27 Jan 2025 18:26:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcYUs-0006SX-FB for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:27 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tcYUq-0005fA-5L for qemu-devel@nongnu.org; Mon, 27 Jan 2025 18:26:26 -0500 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2eed82ca5b4so8527885a91.2 for ; Mon, 27 Jan 2025 15:26:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738020383; x=1738625183; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2GDxHDUfDEHJ5sXsQfC9s6zGTEGY5YOTfZmfjmgVvKc=; b=prK1VNR1Bor4WZCUyYx9DU4xyvR00YL0GnhicrBUeY4R1TCa0sgMP1bw+IesUr/4vx KxkmrzOBPCh/XxI1niKFGBgZY7/i03mfaTAKaF/U7xED0mHhC/VGAK+dIerMyjhADH8p ciA431Kb+JEYGxqoQw0tD0HWFw3K2TpA7o2YKNLlaFnpWhUx1lXTpfuOOdh7KytqkW60 4fwl2m/zfEdwvOlnABf66gJ7mQYIwAAfDOYt1tgmfU1S0t/ex+Ia1g+kBfgL3TcDYfm1 ax2oiSH/3fxHeUGDcuzj1dtVZ8OzjwsSTtJxbyPIVD+/l47i+1wKCqGFDb/TUUwcxgUZ bHAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738020383; x=1738625183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2GDxHDUfDEHJ5sXsQfC9s6zGTEGY5YOTfZmfjmgVvKc=; b=toru4VDLWaJ3pYNJ9kxvL5lIH8rsvlp3JxZ4AnEFS8ZFLvpXFc0rVka4XvvTp20oI8 MsbgpEbBVP+0Em/63VJRZhR57WNI4JsNrkIO77y/4RstaBPhxvD6614PKEd0lO0uWid0 cxTSvriE9ExGsch/UL64f0SXtQNEj/UYss4/QHHGjo05LZVyVcJPKLhfTdc2yPRSEnhZ jT0kFERAdIcjleGt0AJXlCLAHKUHUu4v4bfzrLjwWWCcNfLS9YiipKQneAsbr16qI97r qCSRSSUOIqSm8Ya7hInZMfV5nZHlxA23vXacegDFppEFDQjXZwrNEmWCA3j4azFuGGlF 8eAg== X-Gm-Message-State: AOJu0Yze3xV5rq5kqL0644X/x6LnfcSEFo0lSi1ECKC3JNk0Dbv+86QS GLAzkCKngbCtAuZM3EiXV/CbNcSH0xmGpiB8l6Bp7i42M3X8lJl5a9Uk8z43HdzVh1TftUZpr6K b X-Gm-Gg: ASbGnctfUx2GKaV8wHXNhmY/98ATX8D4aInqKc7tlo/9K5sOIY5y/X/DN5uOML3yY5z DIdO9gORmOO7ReoocU7s/z6Ppt/bYaKSOXTRRf/ytqh0ZEicDk/z0xobbXu4aDqEVY/sR60NLxY hXJRa0IRUNG6aApDK+6EgOZJYaaO5cxBWSn3DJg0KDFAXh0H+BUGpZ9Kie2A055bcvEnHwjGZiW rmlLewqUdU9oJv/mJdmsuxY7Psodxnkl5DrSlLX0RSOk3JsSCTii3jjjeXnw/kwbRM3MUj7WHDl NyfA9Uwcd0FMbGDw/Ultp+6VotKETt+ED4DmHjo= X-Received: by 2002:a17:90b:2dc2:b0:2ee:6db1:21d3 with SMTP id 98e67ed59e1d1-2f782d323a6mr59729663a91.25.1738020382797; Mon, 27 Jan 2025 15:26:22 -0800 (PST) Received: from stoup.. (174-21-71-127.tukw.qwest.net. [174.21.71.127]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffb1b31esm7833000a91.47.2025.01.27.15.26.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 15:26:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 22/22] target/arm: Use flags for AH negation in do_fmla_zpzzz_* Date: Mon, 27 Jan 2025 15:26:04 -0800 Message-ID: <20250127232604.20386-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127232604.20386-1-richard.henderson@linaro.org> References: <20250127232604.20386-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The float*_muladd functions have a flags argument that can perform optional negation of various operand. We don't use that for "normal" arm fmla, because the muladd flags are not applied when an input is a NaN. But since FEAT_AFP does not negate NaNs, this behaviour is exactly what we need. Since we have separate helper entry points for the various fmla, fmls, fnmla, fnmls instructions, it's easy to just pass down the exact values required so that no conditional branch is required within the inner loop. Signed-off-by: Richard Henderson --- target/arm/tcg/sve_helper.c | 93 +++++++++++++++++-------------------- 1 file changed, 42 insertions(+), 51 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 6a5bfa0e59..4fdc98cd98 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -4814,7 +4814,7 @@ DO_ZPZ_FP(flogb_d, float64, H1_8, do_float64_logb_as_int) static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc, - uint16_t neg1, uint16_t neg3, bool fpcr_ah) + uint16_t neg1, uint16_t neg3, int flags) { intptr_t i = simd_oprsz(desc); uint64_t *g = vg; @@ -4826,16 +4826,10 @@ static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg, if (likely((pg >> (i & 63)) & 1)) { float16 e1, e2, e3, r; - e1 = *(uint16_t *)(vn + H1_2(i)); + e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1; e2 = *(uint16_t *)(vm + H1_2(i)); - e3 = *(uint16_t *)(va + H1_2(i)); - if (neg1 && !(fpcr_ah && float16_is_any_nan(e1))) { - e1 ^= neg1; - } - if (neg3 && !(fpcr_ah && float16_is_any_nan(e3))) { - e3 ^= neg3; - } - r = float16_muladd(e1, e2, e3, 0, status); + e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3; + r = float16_muladd(e1, e2, e3, flags, status); *(uint16_t *)(vd + H1_2(i)) = r; } } while (i & 63); @@ -4845,48 +4839,51 @@ static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg, void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0, false); + do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0, 0); } void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0, false); + do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0, 0); } void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000, false); + do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000, 0); } void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000, false); + do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000, 0); } void HELPER(sve_ah_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0, true); + do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0, + float_muladd_negate_product); } void HELPER(sve_ah_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000, true); + do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0, + float_muladd_negate_product | float_muladd_negate_c); } void HELPER(sve_ah_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000, true); + do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0, + float_muladd_negate_c); } static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc, - uint32_t neg1, uint32_t neg3, bool fpcr_ah) + uint32_t neg1, uint32_t neg3, int flags) { intptr_t i = simd_oprsz(desc); uint64_t *g = vg; @@ -4898,16 +4895,10 @@ static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg, if (likely((pg >> (i & 63)) & 1)) { float32 e1, e2, e3, r; - e1 = *(uint32_t *)(vn + H1_4(i)); + e1 = *(uint32_t *)(vn + H1_4(i)) ^ neg1; e2 = *(uint32_t *)(vm + H1_4(i)); - e3 = *(uint32_t *)(va + H1_4(i)); - if (neg1 && !(fpcr_ah && float32_is_any_nan(e1))) { - e1 ^= neg1; - } - if (neg3 && !(fpcr_ah && float32_is_any_nan(e3))) { - e3 ^= neg3; - } - r = float32_muladd(e1, e2, e3, 0, status); + e3 = *(uint32_t *)(va + H1_4(i)) ^ neg3; + r = float32_muladd(e1, e2, e3, flags, status); *(uint32_t *)(vd + H1_4(i)) = r; } } while (i & 63); @@ -4917,48 +4908,51 @@ static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg, void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0, false); + do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0, 0); } void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0, false); + do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0, 0); } void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000, false); + do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000, 0); } void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000, false); + do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000, 0); } void HELPER(sve_ah_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0, true); + do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0, + float_muladd_negate_product); } void HELPER(sve_ah_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000, true); + do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0, + float_muladd_negate_product | float_muladd_negate_c); } void HELPER(sve_ah_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000, true); + do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0, + float_muladd_negate_c); } static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc, - uint64_t neg1, uint64_t neg3, bool fpcr_ah) + uint64_t neg1, uint64_t neg3, int flags) { intptr_t i = simd_oprsz(desc); uint64_t *g = vg; @@ -4970,16 +4964,10 @@ static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg, if (likely((pg >> (i & 63)) & 1)) { float64 e1, e2, e3, r; - e1 = *(uint64_t *)(vn + i); + e1 = *(uint64_t *)(vn + i) ^ neg1; e2 = *(uint64_t *)(vm + i); - e3 = *(uint64_t *)(va + i); - if (neg1 && !(fpcr_ah && float64_is_any_nan(e1))) { - e1 ^= neg1; - } - if (neg3 && !(fpcr_ah && float64_is_any_nan(e3))) { - e3 ^= neg3; - } - r = float64_muladd(e1, e2, e3, 0, status); + e3 = *(uint64_t *)(va + i) ^ neg3; + r = float64_muladd(e1, e2, e3, flags, status); *(uint64_t *)(vd + i) = r; } } while (i & 63); @@ -4989,43 +4977,46 @@ static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg, void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0, false); + do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0, 0); } void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0, false); + do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0, 0); } void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN, false); + do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN, 0); } void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN, false); + do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN, 0); } void HELPER(sve_ah_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0, true); + do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0, + float_muladd_negate_product); } void HELPER(sve_ah_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN, true); + do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0, + float_muladd_negate_product | float_muladd_negate_c); } void HELPER(sve_ah_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void *vg, float_status *status, uint32_t desc) { - do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN, true); + do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0, + float_muladd_negate_c); } /* Two operand floating-point comparison controlled by a predicate.