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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 01/14] meson: Drop tcg as a module Date: Sun, 2 Feb 2025 19:18:08 -0800 Message-ID: <20250203031821.741477-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The fact that this is only enabled for x86 probably means it was done incorrectly. Certainly the set of files selected to go into the module is woefully incomplete. Drop it for now. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/meson.build | 11 ++++------- meson.build | 18 +----------------- 2 files changed, 5 insertions(+), 24 deletions(-) diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index aef80de967..69f4808ac4 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -21,16 +21,13 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', 'watchpoint.c', + 'tcg-accel-ops.c', + 'tcg-accel-ops-mttcg.c', + 'tcg-accel-ops-icount.c', + 'tcg-accel-ops-rr.c', )) system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', )) - -tcg_module_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( - 'tcg-accel-ops.c', - 'tcg-accel-ops-mttcg.c', - 'tcg-accel-ops-icount.c', - 'tcg-accel-ops-rr.c', -)) diff --git a/meson.build b/meson.build index 2c9ac9cfe1..b72114819b 100644 --- a/meson.build +++ b/meson.build @@ -322,12 +322,6 @@ if cpu in ['x86', 'x86_64'] } endif -modular_tcg = [] -# Darwin does not support references to thread-local variables in modules -if host_os != 'darwin' - modular_tcg = ['i386-softmmu', 'x86_64-softmmu'] -endif - ################## # Compiler flags # ################## @@ -3279,11 +3273,6 @@ foreach target : target_dirs if sym == 'CONFIG_TCG' or target in accelerator_targets.get(sym, []) config_target += { sym: 'y' } config_all_accel += { sym: 'y' } - if target in modular_tcg - config_target += { 'CONFIG_TCG_MODULAR': 'y' } - else - config_target += { 'CONFIG_TCG_BUILTIN': 'y' } - endif target_kconfig += [ sym + '=y' ] endif endforeach @@ -3642,7 +3631,6 @@ util_ss = ss.source_set() # accel modules qtest_module_ss = ss.source_set() -tcg_module_ss = ss.source_set() modules = {} target_modules = {} @@ -3803,11 +3791,7 @@ subdir('tests/qtest/libqos') subdir('tests/qtest/fuzz') # accel modules -tcg_real_module_ss = ss.source_set() -tcg_real_module_ss.add_all(when: 'CONFIG_TCG_MODULAR', if_true: tcg_module_ss) -specific_ss.add_all(when: 'CONFIG_TCG_BUILTIN', if_true: tcg_module_ss) -target_modules += { 'accel' : { 'qtest': qtest_module_ss, - 'tcg': tcg_real_module_ss }} +target_modules += { 'accel' : { 'qtest': qtest_module_ss }} ############################################## # Internal static_libraries and dependencies # From patchwork Mon Feb 3 03:18:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861541 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp1832112wrr; Sun, 2 Feb 2025 19:20:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVgmzW8B2GeJj3T5cOm3DPyn2f6oe8CPv7Y69N1YdtEgNw8j2ijkzs6J+bKUvSWVmAeI8v/nw==@linaro.org X-Google-Smtp-Source: AGHT+IEyqA0SIFmVyV1GbbAs2jKgah6UBm+9Tp9GVIT1LItjlmeDZ4/qoQfEBApl8HX4olLf3bp6 X-Received: by 2002:a05:6214:242f:b0:6e1:7b35:a0d5 with SMTP id 6a1803df08f44-6e243b909b1mr318597336d6.7.1738552800840; Sun, 02 Feb 2025 19:20:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738552800; cv=none; d=google.com; s=arc-20240605; b=a6PraiD3M8epYqjvOQarKJ29HhybqybJPkCCp1WP6DLxi7UuK2ispMtIc89RfddJyc RZmY3jGB8Rk/lMQc7M55A0jyIYLWvJYl9KfQFsq7asUhUg9eC7HBMMYR5WdHy8VEfx40 k1IMxEjIqWx/sN1xJwNRaVFGCdITP02xsnTsC3KUltLT1FLDO/5mEJH5emee0aBBRgvL lHHqQZO11mGay1ZunaSFfRwKSe1P1joxiF84BWMEQ4KR4/SWeX6fqpHmfpIurictwBps Vo6a1x2D2n90IAQs6mFm5ETj1ggEG+EiN+HrB7AQx/j+0SL3of0SZ+cwySKnRoBsKIVw 1FRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=p1C9JfQ7GmNodpDRLscChLFNi4X9hLYpSI+5VG9BaRA=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=T+ziovN70tkZIjEvXNSqWfk13jbvILOWZS+CruhXeJ6vPzz/5nJIjj/rYM+MOADVyZ djgzgpkvfzYzAQAiqxmSXT8hB+9C1HJ1GSXg0g+WP9jMJ+s9OZIMxZu+pB2eGpQGHF9x NErUZv62d3WioTiwi3z+PKHlBk5lWnMvcf42bNtGgsZ3+I3DVkpXtD11+7+iGjE0Qsus Doy0ISgDwLZRdbgNCKVlZfFJ1hlQIOtRP4ce3pfLJmmlm1tCDRAmHJsDJjFyV3OU7130 xtHnlOq0/4pw5jT1/JLoBNWC48K4uXPmTesZbo4F9KvWbNXRJnEemkdE8YzSHRXqd35e fmUQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d1nHx79h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 02/14] tcg: Move stubs in tcg/perf.h to tcg/perf-stubs.c Date: Sun, 2 Feb 2025 19:18:09 -0800 Message-ID: <20250203031821.741477-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org These are not called so frequently as to be performance sensitive. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée --- include/tcg/perf.h | 23 ----------------------- tcg/perf-stubs.c | 26 ++++++++++++++++++++++++++ tcg/meson.build | 2 ++ 3 files changed, 28 insertions(+), 23 deletions(-) create mode 100644 tcg/perf-stubs.c diff --git a/include/tcg/perf.h b/include/tcg/perf.h index c96b5920a3..050ba855ab 100644 --- a/include/tcg/perf.h +++ b/include/tcg/perf.h @@ -7,7 +7,6 @@ #ifndef TCG_PERF_H #define TCG_PERF_H -#if defined(CONFIG_TCG) && defined(CONFIG_LINUX) /* Start writing perf-.map. */ void perf_enable_perfmap(void); @@ -23,27 +22,5 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock *tb, /* Stop writing perf-.map and/or jit-.dump. */ void perf_exit(void); -#else -static inline void perf_enable_perfmap(void) -{ -} - -static inline void perf_enable_jitdump(void) -{ -} - -static inline void perf_report_prologue(const void *start, size_t size) -{ -} - -static inline void perf_report_code(uint64_t guest_pc, TranslationBlock *tb, - const void *start) -{ -} - -static inline void perf_exit(void) -{ -} -#endif #endif diff --git a/tcg/perf-stubs.c b/tcg/perf-stubs.c new file mode 100644 index 0000000000..ce2dd1a4b7 --- /dev/null +++ b/tcg/perf-stubs.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* TCG perf stubs */ + +#include "qemu/osdep.h" +#include "tcg/perf.h" + +void perf_enable_perfmap(void) +{ +} + +void perf_enable_jitdump(void) +{ +} + +void perf_report_prologue(const void *start, size_t size) +{ +} + +void perf_report_code(uint64_t guest_pc, TranslationBlock *tb, + const void *start) +{ +} + +void perf_exit(void) +{ +} diff --git a/tcg/meson.build b/tcg/meson.build index 69ebb4908a..2977df5862 100644 --- a/tcg/meson.build +++ b/tcg/meson.build @@ -25,6 +25,8 @@ endif tcg_ss.add(when: libdw, if_true: files('debuginfo.c')) if host_os == 'linux' tcg_ss.add(files('perf.c')) +else + tcg_ss.add(files('perf-stubs.c')) endif tcg_ss = tcg_ss.apply({}) From patchwork Mon Feb 3 03:18:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861536 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp1831945wrr; Sun, 2 Feb 2025 19:19:17 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUbOF5PBY5cp+VuBLkMZbvIgQSEns1vn+Pd1jAN6Psav+qoDdoHMd5pBIGhvDH62QHKpLaZyA==@linaro.org X-Google-Smtp-Source: AGHT+IFBq1duyONHUsQGXPWVa/srRoS+tPHACpE1QZxyOojubCuEt8mYwSNrIwZBpEuURusIMEUM X-Received: by 2002:a05:622a:2b07:b0:46e:2a18:939d with SMTP id d75a77b69052e-46fdd36eedfmr269988441cf.11.1738552756860; Sun, 02 Feb 2025 19:19:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738552756; cv=none; d=google.com; s=arc-20240605; b=W+ATbJOVnDkgaE08GWxmvOdxKdbUULu5dwbDjVMqKWd4sQTkVcsnKnacDEAem8kjTV yxLnZ+osQLbdMMrryH7LbcoVvwUgd9Fb00Ye4IkgzxUOdoyaZQFoM46Ck8hy52/S2wDK +00m5Hoo7GH0WIeZAKCAKvWC8+87W9Cbkh0+ddw75QxkNGxEirYO99EWpTZhxszGLzqR QlFAd5eMqk3r6dD0ypxIEMfwPOMcfeZqjApdW2f7esmX9IlJak8Dmme4lP0dSAe5SVDS +7gguydKIfu3sUwfWFGVUus4h51z9+tcJr78BmhFR6sPM22sBKG5BuBNxqcul/XvvZ98 ri9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vbrezDzCPzYJZE+sgCbEQwq19lroZqcdNTLKZBRXWvg=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=kqqPciHTxTS1IFlT7FXECXx4lEUlGxXb0JM6PHtPTVn1LtV779z91nL1F7VrSbKEhX N217xe6MqDShAmaLdbgFXibqcm0HVq/wmIAAm5FOcxWgZmoejs5RMycARqYiqSAPbgKY kEJId2qx3J2amF+hL0s0O18irIgv4aCiVf7B3cpnwbp4Nf2RwvK8ypBAq7cseeWwHpEJ gouuHaI6eR5OHyu2kmw5dqzcYiznToz8YkrQkQezfOsCBz39X98m33tfwEKr9bY6lsFp ZQtMCtr+yxRksZZJ3BM5dpFqgItSlSF3+A85vEpnGsYqve/eZL8ffl2yDBM6CuHAwyzp XxvQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PzL1PtNh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 03/14] plugins: Uninline qemu_plugin_add_opts Date: Sun, 2 Feb 2025 19:18:10 -0800 Message-ID: <20250203031821.741477-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org No need to expand this function inline. Unexport qemu_plugin_opts to match. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée --- include/qemu/plugin.h | 9 +-------- plugins/loader.c | 7 ++++++- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h index 9726a9ebf3..3efded6a3e 100644 --- a/include/qemu/plugin.h +++ b/include/qemu/plugin.h @@ -11,7 +11,6 @@ #include "qemu/qemu-plugin.h" #include "qemu/error-report.h" #include "qemu/queue.h" -#include "qemu/option.h" #include "qemu/plugin-event.h" #include "qemu/bitmap.h" #include "exec/memopidx.h" @@ -44,13 +43,7 @@ get_plugin_meminfo_rw(qemu_plugin_meminfo_t i) } #ifdef CONFIG_PLUGIN -extern QemuOptsList qemu_plugin_opts; - -static inline void qemu_plugin_add_opts(void) -{ - qemu_add_opts(&qemu_plugin_opts); -} - +void qemu_plugin_add_opts(void); void qemu_plugin_opt_parse(const char *optstr, QemuPluginList *head); int qemu_plugin_load_list(QemuPluginList *head, Error **errp); diff --git a/plugins/loader.c b/plugins/loader.c index ebc01da9c6..35680bfc13 100644 --- a/plugins/loader.c +++ b/plugins/loader.c @@ -55,7 +55,7 @@ struct qemu_plugin_parse_arg { struct qemu_plugin_desc *curr; }; -QemuOptsList qemu_plugin_opts = { +static QemuOptsList qemu_plugin_opts = { .name = "plugin", .implied_opt_name = "file", .head = QTAILQ_HEAD_INITIALIZER(qemu_plugin_opts.head), @@ -65,6 +65,11 @@ QemuOptsList qemu_plugin_opts = { }, }; +void qemu_plugin_add_opts(void) +{ + qemu_add_opts(&qemu_plugin_opts); +} + typedef int (*qemu_plugin_install_func_t)(qemu_plugin_id_t, const qemu_info_t *, int, char **); extern struct qemu_plugin_state plugin; From patchwork Mon Feb 3 03:18:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861531 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp1831855wrr; Sun, 2 Feb 2025 19:18:52 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUA24BoUqUZ01mPHCWaHKG50ay1/3xPCiR3lkR2WxTKB44JxdfpQTpEbAEuHdH+AgWRWHFO+g==@linaro.org X-Google-Smtp-Source: AGHT+IGMptsrnBQwWT+1ZNtIMn9EMJO8XYt7yvfdHOBA/daUzdM96mS9Z268MHV+YYFc8dR09LKo X-Received: by 2002:a0c:b4da:0:b0:6e2:4575:6bd5 with SMTP id 6a1803df08f44-6e245756ccamr183189326d6.12.1738552731942; Sun, 02 Feb 2025 19:18:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738552731; cv=none; d=google.com; s=arc-20240605; b=Aubfes0wRTn30OSsu5mQ40aegZqO++/GOLEOMH5eOjFthtyL6eb341kfxRF2Jj+05u bZhOp9/6NLQIWjzCI9xkb1R4HIxugMQTRztnPUmwLk4CbBr+RUjq6AlfkCZbTDnw+2HZ 3O/40a7Trvlz4/BBU4liIX64xg7YttwJ5ZEFwpvzSvReS2fVzDKiZNR6MGVBT+0pPRr4 0+T3W3a4dEZrc3kN55weZWdjzc44D+ot9M/TiQhzcdrw5onZf5W0Cjqqj0bdl6nnWuio ate1PypbMxbnCYe/6pR8xG8jHdM4mq38f+aAJZv4VixMuDmruEmQ/x4uktzOGOombU2s MDZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wE+iKDowkpEPg8wCdcVqa4FtJfGiWYCtzRF3aZf/Z+U=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=bHk7L/SawYaGdOO7k72h0Gptr873SC1h7ZRSDAfYzWiH5NEnMA1Dskh3t7SwFeOT1p U+QbeVexfUbLziBUPW/ZroQLr6WU468HDg8TChq4Kts0xCnGK7eARjQ22RgGzGYtjj1U DnMci75URCoJ5tAwe61P6TSQ0IFGQeor/9ijZatsO83x/Yy43DKZDHvPlkqkzSmlpFSw KkoYRwxeATsQrQrGhfFdCuiz4zHXV5O87AlyUnNvUVHfbF/HR3GkulNiNBS5/tOFJTd3 oettardG8mhpCteR08vHhbLTRNGWGBKtRwrYAwE1h5ot1oPmF3QJxdq05432i8+H54hv qlEg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JxnFg4CJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 04/14] meson: Introduce CONFIG_TCG_TARGET Date: Sun, 2 Feb 2025 19:18:11 -0800 Message-ID: <20250203031821.741477-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use CONFIG_TCG as a project-wide flag to indicate that TCG is enabled for *some* target. Use CONFIG_TCG_TARGET to indicate that TCG is enabled for a specific target. Within a specific compilation unit, we can remap CONFIG_TCG based on CONFIG_TCG_TARGET. This allows us to avoid changes to the bulk of the code base. Within meson.build, while CONFIG_TCG may be set in config_host_data, it may not be set within config_target. Thus all references to CONFIG_TCG in source_set 'when:' need not be updated. For the moment, CONFIG_TCG and CONFIG_TCG_TARGET are identical. Signed-off-by: Richard Henderson --- include/qemu/osdep.h | 7 +++++++ meson.build | 11 +++++++---- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 112ebdff21..1f6f73a148 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -34,9 +34,16 @@ #include "config-host.h" #ifdef COMPILING_PER_TARGET #include CONFIG_TARGET +# ifdef CONFIG_TCG_TARGET +# undef CONFIG_TCG_TARGET +# else +# undef CONFIG_TCG +# endif #else #include "exec/poison.h" #endif +#pragma GCC poison CONFIG_TCG_TARGET + /* * HOST_WORDS_BIGENDIAN was replaced with HOST_BIG_ENDIAN. Prevent it from diff --git a/meson.build b/meson.build index b72114819b..5ca3cc3f34 100644 --- a/meson.build +++ b/meson.build @@ -3270,11 +3270,14 @@ foreach target : target_dirs target_kconfig = [] foreach sym: accelerators - if sym == 'CONFIG_TCG' or target in accelerator_targets.get(sym, []) - config_target += { sym: 'y' } - config_all_accel += { sym: 'y' } - target_kconfig += [ sym + '=y' ] + if sym == 'CONFIG_TCG' + config_target += { 'CONFIG_TCG_TARGET': 'y' } + elif target not in accelerator_targets.get(sym, []) + continue endif + config_target += { sym: 'y' } + config_all_accel += { sym: 'y' } + target_kconfig += [ sym + '=y' ] endforeach if target_kconfig.length() == 0 if default_targets From patchwork Mon Feb 3 03:18:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861535 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp1831908wrr; Sun, 2 Feb 2025 19:19:05 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXU8ZaID+00IamnzN18RiFt7E0Ufky4hUtmlzGnlH54C0GeWKXoXWCCWDyCB9mtoXRvX+raKg==@linaro.org X-Google-Smtp-Source: AGHT+IE50TrlfCpaAp6pr3lxjVH8w7kMsAPPmyou4ymhMw4lMf04cYUjcYz+79Q/dAtxVssnpIGx X-Received: by 2002:ad4:596f:0:b0:6d4:36ff:4358 with SMTP id 6a1803df08f44-6e243bf672emr329819176d6.25.1738552745604; Sun, 02 Feb 2025 19:19:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738552745; cv=none; d=google.com; s=arc-20240605; b=cwCj+pXUSwSIy9VtRJ3voaAf2toaZP1rVbvinEoh/eIEeLt+HYm2ZhFrMFQPo4m6N4 iTaH+3QBsF5Q9aP6q5miF5O2lZKj5i/c+zxGnrk6EWeOLx9kvLSUKpqDZNguSXO8IJ9D GqaFyaa0IMwVeKq46cj+GqluSobARVxqU6GaDN/k0Nj7PUMl2C5kOyG3iS3uU13WSOue buebRU4X8RUYwatCAP6b715COdB7GbQS1EWPpNNyc9TpW4sVe4mLcjW/aVCX2SeTD99Q sw6EnDVUkJkJPwqddN0jYAnESpuBGpJcvrw+ll9+NL63ajIZ/TgrjUsZwF5ix0TuVVl/ 8+jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SAfl37xDnFz/0zdZPRXfsa8UPn/22lXCD6HUC3zbL6A=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=SHDXuxQU4TsuFCkhsvQN9LVivFFEV8BUrWhalSoLTeIGA3b90njZugfGS1gBJLu7sG JzjLdvCGHUWAhSBGtjnKAwWHpQJVvTDx7bWUa4zCBbDA/CGvsM1pmHKD8ZVdQsskvo+R 5/I472UN1eL7kWWu7NU9kIfweHYcmegcUdbckxGE8BQcyRgWVe8q+4FfNP9m9UzErrJI LPDtiLwY/kdhv6RqlpYGTJuBqovV8XBC8MUHlz3oUz+1uaF6MgoHA/cpNAbLaDzHqSOq CLhEGkJYwC4QFS6c7lq0bxpEZmvfX27rRY4x2vzc8rcac4oHD/cnTdxZqHkkAF6pUe1m tDmg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IP5uwkmM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 05/14] tcg: Link only when required in system mode Date: Sun, 2 Feb 2025 19:18:12 -0800 Message-ID: <20250203031821.741477-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than unconditional linkage via system_ss, conditinally include the static library via specific_ss. This will elide the code when CONFIG_TCG is disabled for a specific target. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée --- tcg/meson.build | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tcg/meson.build b/tcg/meson.build index 2977df5862..8266bcb324 100644 --- a/tcg/meson.build +++ b/tcg/meson.build @@ -49,4 +49,8 @@ libtcg_system = static_library('tcg_system', tcg_system = declare_dependency(objects: libtcg_system.extract_all_objects(recursive: false), dependencies: tcg_ss.dependencies()) -system_ss.add(tcg_system) + +specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: tcg_system) +if host_os == 'linux' + specific_ss.add(when: 'CONFIG_TCG', if_false: files('perf-stubs.c')) +endif From patchwork Mon Feb 3 03:18:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861532 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp1831857wrr; Sun, 2 Feb 2025 19:18:52 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW1VQD6Zjk8jDxRfFYW7iVzXf6ncuRvxWJUBpLGQljzuzOHWPnprfFkijl/aIP+FohdxBB3nQ==@linaro.org X-Google-Smtp-Source: AGHT+IGO4Mk6RSAODnZt9k5BiPlRPYuYPtu6Ha46cf6wUubgEb6klS5pVkhwyD/fe8UiMcujWrGP X-Received: by 2002:a0c:aa10:0:b0:6e2:43d1:5fd0 with SMTP id 6a1803df08f44-6e243d1617bmr265884446d6.31.1738552731951; Sun, 02 Feb 2025 19:18:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738552731; cv=none; d=google.com; s=arc-20240605; b=ItBJx7QlZIdgfHfyh86n01q3IR9hxA/8mPKdNsQ/ZtuusJ2mzaBLi/S9clwIJYT90w MGor/ba5fXod9yAYCP7gcPe+C/JOQllymhDGGwExIHqtaq6lasg/Z8FMw5KY/fllZ7zw U+z1f5XdPbZBypLK1vk+QuZaoOJWQrYHbsTa9sz/w2Oi0NS3brjAvzbyhfkjnViCMsDQ qw/Iv/USu0I+XF3tUDQ+92fpL/XMoODC+gNuK2oLSF3s1P/MKAtlK3rECZEFxEIIKt/c Y/N6Q4f6GlXKe1hdcKIgBiVO2nMzCzVGOyzc46P9AecVwxDAzFLCCCUnRIR+HJh5f+7G 8PuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=buZLA0qUirjW027SjrYQXL+U33fLGsXttbSr8L05NfY=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=lRfuRaP5/pwgvow2d9RyQ1lHalgvn9H8MGddj9mys33b98t3zNuZHL4t7Ryc1qFmyc irYc6bFKTOO2E8zljXReeZblYDgJNBxoSwG5MK1Cgm+EAqBZnVXucYYm72TfgHXQgtQj bRF2nzTkAYfgzOL5EnVeXwg+DbfGwDotOk68oPgqoaxD80rmGhtIDhX+Q1Ry2SXykHOU 0gIj51b+vygI/P8o+B9ykdfTQiOTcMAkg7F63CIc7o2klvFHdeFFmU/eolZYa++IvbqO b+Z/mdbYbCdtgLWXVRMcb8Iz2JmhpcjM9GPFo7i6LOiOHISytEF0PTpPt+9r2YOyqV+E 4wtA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hAwnu63h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 06/14] plugins: Link only when required in system mode Date: Sun, 2 Feb 2025 19:18:13 -0800 Message-ID: <20250203031821.741477-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Provide out-of-line versions of some of the qemu/plugin.h API. These will be referenced with --enable-plugin, but CONFIG_TCG is disabled for a specific target. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée --- plugins/stubs.c | 49 +++++++++++++++++++++++++++++++++++++++++++++ plugins/meson.build | 5 ++++- 2 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 plugins/stubs.c diff --git a/plugins/stubs.c b/plugins/stubs.c new file mode 100644 index 0000000000..57af8357e4 --- /dev/null +++ b/plugins/stubs.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Stubs for when CONFIG_PLUGIN is enabled generally, but + * CONFIG_TCG_TARGET is disabled for a specific target. + * This will only be the case for 64-bit guests on 32-bit hosts + * when an alternate accelerator is enabled. + */ + +#include "qemu/osdep.h" +#include "qemu/plugin.h" +#include "qapi/error.h" + + +void qemu_plugin_add_opts(void) +{ +} + +void qemu_plugin_opt_parse(const char *optstr, QemuPluginList *head) +{ + error_report("plugin interface not enabled in this build"); + exit(1); +} + +int qemu_plugin_load_list(QemuPluginList *head, Error **errp) +{ + return 0; +} + +void qemu_plugin_vcpu_init_hook(CPUState *cpu) +{ +} + +void qemu_plugin_vcpu_exit_hook(CPUState *cpu) +{ +} + +void qemu_plugin_vcpu_idle_cb(CPUState *cpu) +{ +} + +void qemu_plugin_vcpu_resume_cb(CPUState *cpu) +{ +} + +CPUPluginState *qemu_plugin_create_vcpu_state(void) +{ + /* Protected by tcg_enabled() */ + g_assert_not_reached(); +} diff --git a/plugins/meson.build b/plugins/meson.build index d60be2a4d6..42442fe22b 100644 --- a/plugins/meson.build +++ b/plugins/meson.build @@ -57,8 +57,11 @@ if host_os == 'windows' command: dlltool_cmd ) endif -specific_ss.add(files( + +specific_ss.add(when: 'CONFIG_TCG', if_true: files( 'loader.c', 'core.c', 'api.c', +), if_false: files( + 'stubs.c' )) From patchwork Mon Feb 3 03:18:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861537 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp1832066wrr; Sun, 2 Feb 2025 19:19:48 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXEVRqKN51zks+bMiDFGFOZ/04Clt5WHPlrr/70X9wrADdc9LFNsV1Xe9Jp0n74O4b9vobfRQ==@linaro.org X-Google-Smtp-Source: AGHT+IEzXU50k8hpOmJPO2bcuDlffYiNs9occOrlzEx+GDX9ctCnTpdyH6p29BGVrzHKanEoQ9EE X-Received: by 2002:a05:620a:1b88:b0:7b3:3657:9e5b with SMTP id af79cd13be357-7c0097c1d17mr2390644785a.26.1738552788595; Sun, 02 Feb 2025 19:19:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738552788; cv=none; d=google.com; s=arc-20240605; b=CrbW5t0gLJUD5xM2lOs+CI3wPP4LjDEjhF3qSi0PRLnAzm3Ef9QA1xe4U/c0Ir9cPs uJ4o4c8SYuuyaeAQgUd2fnsIgH0oj7v4FFePRMqWo+LoVd/t4xVP5jCtolGpOfp7hi2u TWHteuuIGk0kJBFyhYFLuSn4o2OmkCUFn6Bu8Pi3b6nErTn4aHN/vlRl0RuOGCNv72EB OQdae1AQw/3oHl7+tGan844EK5edODw14NnuqxsgPtZ+4QUAAEJRpyUJaf0zwZ6hHN24 R+qBGAXS3skHeJ6oNy9rZIcia9kseKC+C3aNcYYvNVQtH+eXjjvmGnqT9mGij+C9+O1J ex0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iJ8koAp3lno99JhZwLI7fXS72dpOl8VJ910HFJ9faM0=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=JLhpvClL3oOFdqeKD081htw/0zkrha9/iIT3sbNPqKYcXRVm+uYl9YSfltJt1sPV9U dr+kd2ZAN1ZSKfceFUOiEs+p7AZhIakzLRzwuCVBUkCHK3a/ro69gMBSEZFuJTXciRTC j1ohLn989xbg7L+FxbZquTNJmeBuGKEImaYRLGYKUgSsUi7AW5WYMNqJUKCD7D7RsMVS sJLPr2Z8ifGWGiSdqGV7UXSf4x3dYeFtu3w4flFZxyRcbOnYpXa3rUMHiedIZLwkI1ge p3G/+qg53wcYJpJsv9uwfuGxI+GkGxzrHiGaNJGMKK9UOLH3asOkLhBi5IkvAsVKyxm9 cSDA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ztN2hvLR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 07/14] accel/stubs: Expand stubs for TCG Date: Sun, 2 Feb 2025 19:18:14 -0800 Message-ID: <20250203031821.741477-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add tcg_allowed, qmp_x_query_jit, qmp_x_query_opcount. These are referenced when CONFIG_TCG is enabled globally, but not for a specific target. Signed-off-by: Richard Henderson --- accel/stubs/tcg-stub.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index 7f4208fddf..9c2e2dc6e1 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -13,6 +13,18 @@ #include "qemu/osdep.h" #include "exec/tb-flush.h" #include "exec/exec-all.h" +#include "qapi/error.h" + +/* + * This file *ought* to be built once and linked only when required. + * However, it is built per-target, which means qemu/osdep.h has already + * undef'ed CONFIG_TCG, which hides the auto-generated declaration. + */ +#define CONFIG_TCG +#include "qapi/qapi-commands-machine.h" + + +const bool tcg_allowed = false; void tb_flush(CPUState *cpu) { @@ -27,3 +39,15 @@ G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc) { g_assert_not_reached(); } + +HumanReadableText *qmp_x_query_jit(Error **errp) +{ + error_setg(errp, "JIT information is only available with accel=tcg"); + return NULL; +} + +HumanReadableText *qmp_x_query_opcount(Error **errp) +{ + error_setg(errp, "Opcode count information is only available with accel=tcg"); + return NULL; +} From patchwork Mon Feb 3 03:18:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861539 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp1832090wrr; Sun, 2 Feb 2025 19:19:55 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWRuGhf3VWeZCjbLBjCHAWp7FrvmHJvHej4nc5zQTo2r349Jkpk1WaXZww88qHfh5zEvOldAg==@linaro.org X-Google-Smtp-Source: AGHT+IF88El8KoP8wVu2I4xd5Jsdlw/c3Du74BSwWYpQbAwCLGA7a3BDVujuPxbi5KSGJcG3oDoK X-Received: by 2002:a05:620a:1912:b0:7b6:e8d4:9b86 with SMTP id af79cd13be357-7bffcd9ffe6mr3035803985a.57.1738552795614; Sun, 02 Feb 2025 19:19:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738552795; cv=none; d=google.com; s=arc-20240605; b=XBGca5xP8W7MsTSaqbG+nHZVOIFTSQGLgLMctYmhZD8H1wqHXUb5ne/BIW5GloOPIO fjTl3sR70sjzCjodWYpCqn6nt09+YSp1cY8a0/svnbjiidiAH388Dpcv3nPxrFAlZ1Tz AD6Xi8fHG7mcIl02ItDRC2C/Vh0dC5egGBwJ8pAsZl7LlEBRIknHWkDfZ33301Vt6BHV g3t8eV5BmZQxDKSIIdbdE6SEis18lBVjCM2PTqy4AYRO71eml0iwrT1XQi2/d5sM1UQu xCxIifnwZEsendaw2SWLJQWPxuWkv5kIDQstTnP7lIgQtS3fZgg9J7+TWva5dvjiApMa Zq+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YOiNmgCG27GGUfQ2A+akEblYYk9R7T+pJq3Iu4mV5EA=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=Z+JU4TM3fVwEGTLYLC7r1FMbiNMmRL2NIKVRLFA4pVRJye8xsCpD1bdwAbF8fBV3CZ ImhSQmxVgLA7sWpypmb/FTSG7tXX2M81BkZYZTzH8PhbgbF/zZfChRlcGkQn2EGLDukw YjGqHRAZM+uAKk/mRK9tUtNAwBoW9VLhV6AiE5h6z5SE1FYHQ+QtF0CK52dICFoabFPv TQkPHKvgO5DIRadlZxbqMBqfALfP2V7itvKQWgtyWceCWm+SNXBf3xWOyKJVYqYkCSwv UaFtt5PaBVhKKjRftrmpdLaoS6dg5/XGRqXM3cy+j52+/9NE9c2nwp0pYKgGN7Uyqc7x dZeA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lp8MYQt8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 08/14] target/mips: Protect objects with CONFIG_TCG Date: Sun, 2 Feb 2025 19:18:15 -0800 Message-ID: <20250203031821.741477-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Hack around mips32 host allowing kvm acceleration of mips64 guest, but tcg is disabled. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth --- target/mips/tcg/meson.build | 4 ++-- target/mips/tcg/system/meson.build | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index fff9cd6c7f..e5574f177b 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -10,7 +10,7 @@ gen = [ ] mips_ss.add(gen) -mips_ss.add(files( +mips_ss.add(when: 'CONFIG_TCG', if_true: files( 'dsp_helper.c', 'exception.c', 'fpu_helper.c', @@ -26,7 +26,7 @@ mips_ss.add(files( 'vr54xx_helper.c', 'vr54xx_translate.c', )) -mips_ss.add(when: 'TARGET_MIPS64', if_true: files( +mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files( 'tx79_translate.c', 'octeon_translate.c', 'lcsr_translate.c', diff --git a/target/mips/tcg/system/meson.build b/target/mips/tcg/system/meson.build index 911341ac37..606ccacebc 100644 --- a/target/mips/tcg/system/meson.build +++ b/target/mips/tcg/system/meson.build @@ -1,12 +1,12 @@ -mips_system_ss.add(files( +mips_system_ss.add(when: 'CONFIG_TCG', if_true: files( 'cp0_helper.c', 'special_helper.c', 'tlb_helper.c', )) -mips_system_ss.add(when: ['CONFIG_SEMIHOSTING'], +mips_system_ss.add(when: ['CONFIG_TCG', 'CONFIG_SEMIHOSTING'], if_true: files('mips-semi.c'), if_false: files('semihosting-stub.c') ) -mips_system_ss.add(when: 'TARGET_MIPS64', if_true: files( +mips_system_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files( 'lcsr_helper.c', )) From patchwork Mon Feb 3 03:18:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861534 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp1831896wrr; Sun, 2 Feb 2025 19:19:02 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWQ4yR63Gj8Rq4KKMRthrOqAXviEJj1MwF+kn024S7Kwz+oysxCFgyFyiSgfi20uWM4a4opRA==@linaro.org X-Google-Smtp-Source: AGHT+IH9FwYBzmTF5QGOLBvL0Am4fgjoHVCHw0TKsuKEEKWF1NhDPeeYWHpL/pUFKzUTzlSCkdzy X-Received: by 2002:a05:622a:5108:b0:45d:8be9:b0e6 with SMTP id d75a77b69052e-46fd0b92332mr327398641cf.43.1738552742341; Sun, 02 Feb 2025 19:19:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738552742; cv=none; d=google.com; s=arc-20240605; b=gYfcdOqJG7PilIHnHeQQWzbm15wSFb4AtIYKpjuI0stjIcLtbwt4N+kKM6H255OVEb q8xEYMRqoI7WgoK/9nckiRrQ433cm8656ZsTabZzCvO74a0Fptb33MBizT+Jb+F1DpTt dd4nwdn0vVISuCBTot383GlRHHYhgksysT56EQ/YFVf2pRwkH8ZHmeZIOI19VbZP9MIW c7O3SJfN5/q8Mma1ePORHEGdf8SaVkYmtO/ZglwbEAhFDlZ+0LZMoL9lASZIK/SK2hDR Z7Ie4aYFDtEUq8TOM7VHZidBGiYtUQhTjKQtbUd0GWIIwPK0tJtNkQOWB86kNHMF1UEB Ya1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wgGWKoRbIU40nf+pgjk4xuoPstQyTD/DlLIN5LNZmQ8=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=aSF9L9Nvhb0w/XQKNDWi4TkigovuwSCJtS6KHkXQYG/R9MNUzF5nGnIfdo7uN7Jcrp ZgI7kFeNLuQRzGRY4HOKvO5TRUIpJTGg0l7R5nLrH+z7XBjC8tUV9fhOvyxtTVE/2EMc FSFU6MVplOuc2IqiI7d56mrI7wdsUWnOFVT3aouHQgCz6kVU4sX7W5lsV3abVnhAyg/6 RjG/WArI68UQi2mv6b/IyX3IMAbH7y5pR3M/5FOh8/U39L0tka0IBch5hdrNGVCamSFQ 98dsoMD+IUv56PiT9tap0kRaSJ+X6nMWIKPMJI0+Dow4k4UFIx6foNV5iUPrx/AdS8+V tfLQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SGH+HAns; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 09/14] gitlab: Replace aarch64 with arm in cross-i686-tci build Date: Sun, 2 Feb 2025 19:18:16 -0800 Message-ID: <20250203031821.741477-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Configuration of 64-bit host on 32-bit guest will shortly be denied. Use a 32-bit guest instead. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée --- .gitlab-ci.d/crossbuilds.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 95dfc39224..7ae0f966f1 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -61,7 +61,7 @@ cross-i686-tci: variables: IMAGE: debian-i686-cross ACCEL: tcg-interpreter - EXTRA_CONFIGURE_OPTS: --target-list=i386-softmmu,i386-linux-user,aarch64-softmmu,aarch64-linux-user,ppc-softmmu,ppc-linux-user --disable-plugins --disable-kvm + EXTRA_CONFIGURE_OPTS: --target-list=i386-softmmu,i386-linux-user,arm-softmmu,arm-linux-user,ppc-softmmu,ppc-linux-user --disable-plugins --disable-kvm # Force tests to run with reduced parallelism, to see whether this # reduces the flakiness of this CI job. The CI # environment by default shows us 8 CPUs and so we From patchwork Mon Feb 3 03:18:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861543 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp1832133wrr; Sun, 2 Feb 2025 19:20:06 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWeCJ1Hp/HpfG5hg4J81J0spR41DBxovqeyTzlsQhVHQH/cfAXWFy5oS3kIHmj63ZR2tqHQlQ==@linaro.org X-Google-Smtp-Source: AGHT+IG3/MEuBRORgaNSitNt58e+lKM0EMLqE1qNjie9KPdFavONsjPtxMjWTM7oFi8y3dEXWqWW X-Received: by 2002:a05:620a:45a8:b0:7b6:d5cb:43b7 with SMTP id af79cd13be357-7bffcd0887fmr2575463485a.26.1738552806102; Sun, 02 Feb 2025 19:20:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738552806; cv=none; d=google.com; s=arc-20240605; b=Gv++5kokn+iXIOb5i3Ejw1jq3k2wTHmeBOFQ9G04Dg5vNXcpBj+QKlkdER7Dcw7nIf ZMSDG4/0LSCsMje8cg2HZBmsqCKZSQQff/6pJ/wW2VflUBfqj+uDXrcQU2Mni4roiDtJ lPWLBbacbJ3EWlfXL3eSzURhu+4B/pCC4m+Ousw+9d0A4FxE2kEq7ULLaTbnusMC94At bFavnvGx2r1i3bsb4jnNT2bffgOEcceqdJTUwmwIXT1+urwCY2RlC2Hm9uqRDT5Gbx2h SAbIGiDph2bWceME7GCOySt0Z+UTJ8Tgpbzl3wG7z7qeQv9VZ1zcowrD3m+13wDtJaFk Gp9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=C6BKUQ6lWt0wf4CgfZ0i4ebGJ7t+iM6Zy9ttJiWbmWA=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=NVlnAXlgw8j3hSAWMDZaz71Q3R/WNTQm3mwnODVZmhnedsYnY4v+4rwSKdufE0Gl4x gLryFTldRgkyFjNQOnI5gkusTloLYUbFM8+2vG/4mlVVyGFYECl1f8nd8Z1dg5c86VJe eF7Yyjhx/ghLQKdL4gDULl+B4yyuFDybUwtVXHTY7w8vLPYGEgVEwoB1mUcLrB/TiOMy dgEKLns8/1XLmSyLQoi58P4hGEUV7pecqmrS0OKsq0hpYr9xERyquiOGlsHtkIgxZCm1 G71F2jXNwHtwM3ytRiPIEGD3ttymaZ/st8qa79RtS1+6CbtXcpI3mcXTw4BO2Qbhlh05 KGzA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PiCtx89g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 10/14] configure: Define TARGET_LONG_BITS in configs/targets/*.mak Date: Sun, 2 Feb 2025 19:18:17 -0800 Message-ID: <20250203031821.741477-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define TARGET_LONG_BITS in each target's configure fragment. Do this without removing the define in target/*/cpu-param.h so that errors are caught like so: In file included from .../src/include/exec/cpu-defs.h:26, from ../src/target/hppa/cpu.h:24, from ../src/linux-user/qemu.h:4, from ../src/linux-user/hppa/cpu_loop.c:21: ../src/target/hppa/cpu-param.h:11: error: "TARGET_LONG_BITS" redefined [-Werror] 11 | #define TARGET_LONG_BITS 64 | In file included from .../src/include/qemu/osdep.h:36, from ../src/linux-user/hppa/cpu_loop.c:20: ./hppa-linux-user-config-target.h:32: note: this is the location of the previous definition 32 | #define TARGET_LONG_BITS 32 | cc1: all warnings being treated as errors Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé --- configs/targets/aarch64-bsd-user.mak | 1 + configs/targets/aarch64-linux-user.mak | 1 + configs/targets/aarch64-softmmu.mak | 1 + configs/targets/aarch64_be-linux-user.mak | 1 + configs/targets/alpha-linux-user.mak | 1 + configs/targets/alpha-softmmu.mak | 1 + configs/targets/arm-bsd-user.mak | 1 + configs/targets/arm-linux-user.mak | 1 + configs/targets/arm-softmmu.mak | 1 + configs/targets/armeb-linux-user.mak | 1 + configs/targets/avr-softmmu.mak | 1 + configs/targets/hexagon-linux-user.mak | 1 + configs/targets/hppa-linux-user.mak | 2 ++ configs/targets/hppa-softmmu.mak | 1 + configs/targets/i386-bsd-user.mak | 1 + configs/targets/i386-linux-user.mak | 1 + configs/targets/i386-softmmu.mak | 1 + configs/targets/loongarch64-linux-user.mak | 1 + configs/targets/loongarch64-softmmu.mak | 1 + configs/targets/m68k-linux-user.mak | 1 + configs/targets/m68k-softmmu.mak | 1 + configs/targets/microblaze-linux-user.mak | 1 + configs/targets/microblaze-softmmu.mak | 3 +++ configs/targets/microblazeel-linux-user.mak | 1 + configs/targets/microblazeel-softmmu.mak | 3 +++ configs/targets/mips-linux-user.mak | 1 + configs/targets/mips-softmmu.mak | 1 + configs/targets/mips64-linux-user.mak | 1 + configs/targets/mips64-softmmu.mak | 1 + configs/targets/mips64el-linux-user.mak | 1 + configs/targets/mips64el-softmmu.mak | 1 + configs/targets/mipsel-linux-user.mak | 1 + configs/targets/mipsel-softmmu.mak | 1 + configs/targets/mipsn32-linux-user.mak | 1 + configs/targets/mipsn32el-linux-user.mak | 1 + configs/targets/or1k-linux-user.mak | 1 + configs/targets/or1k-softmmu.mak | 1 + configs/targets/ppc-linux-user.mak | 1 + configs/targets/ppc-softmmu.mak | 1 + configs/targets/ppc64-linux-user.mak | 1 + configs/targets/ppc64-softmmu.mak | 1 + configs/targets/ppc64le-linux-user.mak | 1 + configs/targets/riscv32-linux-user.mak | 1 + configs/targets/riscv32-softmmu.mak | 1 + configs/targets/riscv64-bsd-user.mak | 1 + configs/targets/riscv64-linux-user.mak | 1 + configs/targets/riscv64-softmmu.mak | 1 + configs/targets/rx-softmmu.mak | 1 + configs/targets/s390x-linux-user.mak | 1 + configs/targets/s390x-softmmu.mak | 1 + configs/targets/sh4-linux-user.mak | 1 + configs/targets/sh4-softmmu.mak | 1 + configs/targets/sh4eb-linux-user.mak | 1 + configs/targets/sh4eb-softmmu.mak | 1 + configs/targets/sparc-linux-user.mak | 1 + configs/targets/sparc-softmmu.mak | 1 + configs/targets/sparc32plus-linux-user.mak | 1 + configs/targets/sparc64-linux-user.mak | 1 + configs/targets/sparc64-softmmu.mak | 1 + configs/targets/tricore-softmmu.mak | 1 + configs/targets/x86_64-bsd-user.mak | 1 + configs/targets/x86_64-linux-user.mak | 1 + configs/targets/x86_64-softmmu.mak | 1 + configs/targets/xtensa-linux-user.mak | 1 + configs/targets/xtensa-softmmu.mak | 1 + configs/targets/xtensaeb-linux-user.mak | 1 + configs/targets/xtensaeb-softmmu.mak | 1 + 67 files changed, 72 insertions(+) diff --git a/configs/targets/aarch64-bsd-user.mak b/configs/targets/aarch64-bsd-user.mak index 8aaa5d8c80..f99c73377a 100644 --- a/configs/targets/aarch64-bsd-user.mak +++ b/configs/targets/aarch64-bsd-user.mak @@ -1,3 +1,4 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak index 4c6570f56a..b779ac3b4a 100644 --- a/configs/targets/aarch64-linux-user.mak +++ b/configs/targets/aarch64-linux-user.mak @@ -6,3 +6,4 @@ CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=common,64,renameat,rlimit,memfd_secret TARGET_SYSTBL=syscall_64.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak index 84cb32dc2f..82cb72cb83 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -5,3 +5,4 @@ TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml # needed by boot.c TARGET_NEED_FDT=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak index dcef597a80..ef9be02290 100644 --- a/configs/targets/aarch64_be-linux-user.mak +++ b/configs/targets/aarch64_be-linux-user.mak @@ -7,3 +7,4 @@ CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=common,64,renameat,rlimit,memfd_secret TARGET_SYSTBL=syscall_64.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/alpha-linux-user.mak b/configs/targets/alpha-linux-user.mak index f7d3fb4afa..ef8e365b09 100644 --- a/configs/targets/alpha-linux-user.mak +++ b/configs/targets/alpha-linux-user.mak @@ -1,3 +1,4 @@ TARGET_ARCH=alpha TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-softmmu.mak index 9dbe160740..89f3517aca 100644 --- a/configs/targets/alpha-softmmu.mak +++ b/configs/targets/alpha-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=alpha TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/arm-bsd-user.mak b/configs/targets/arm-bsd-user.mak index cb143e6426..472a4f9fb1 100644 --- a/configs/targets/arm-bsd-user.mak +++ b/configs/targets/arm-bsd-user.mak @@ -1,2 +1,3 @@ TARGET_ARCH=arm TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/arm-linux-user.mak b/configs/targets/arm-linux-user.mak index 7f5d65794c..bf35ded7fe 100644 --- a/configs/targets/arm-linux-user.mak +++ b/configs/targets/arm-linux-user.mak @@ -5,3 +5,4 @@ TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak index bf390b7a8d..afc64f5927 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -3,3 +3,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml # needed by boot.c TARGET_NEED_FDT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/armeb-linux-user.mak b/configs/targets/armeb-linux-user.mak index 943d0d87bf..35fa4d91b3 100644 --- a/configs/targets/armeb-linux-user.mak +++ b/configs/targets/armeb-linux-user.mak @@ -6,3 +6,4 @@ TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/avr-softmmu.mak b/configs/targets/avr-softmmu.mak index e3f921c019..b6157fc465 100644 --- a/configs/targets/avr-softmmu.mak +++ b/configs/targets/avr-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=avr TARGET_XML_FILES= gdb-xml/avr-cpu.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/hexagon-linux-user.mak b/configs/targets/hexagon-linux-user.mak index b912045bd3..aec1a04d1b 100644 --- a/configs/targets/hexagon-linux-user.mak +++ b/configs/targets/hexagon-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=hexagon TARGET_XML_FILES=gdb-xml/hexagon-core.xml gdb-xml/hexagon-hvx.xml TARGET_SYSTBL=syscall.tbl TARGET_SYSTBL_ABI=common,32,hexagon,time32,stat64,rlimit,renameat +TARGET_LONG_BITS=32 diff --git a/configs/targets/hppa-linux-user.mak b/configs/targets/hppa-linux-user.mak index 8e0a80492f..4295cf384e 100644 --- a/configs/targets/hppa-linux-user.mak +++ b/configs/targets/hppa-linux-user.mak @@ -3,3 +3,5 @@ TARGET_ABI32=y TARGET_SYSTBL_ABI=common,32 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y +# Compromise to ease maintainence vs system mode +TARGET_LONG_BITS=64 diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmmu.mak index a41662aa99..63ca74ed5e 100644 --- a/configs/targets/hppa-softmmu.mak +++ b/configs/targets/hppa-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=hppa TARGET_BIG_ENDIAN=y TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/i386-bsd-user.mak b/configs/targets/i386-bsd-user.mak index 0283bb62a0..70e098da49 100644 --- a/configs/targets/i386-bsd-user.mak +++ b/configs/targets/i386-bsd-user.mak @@ -1,2 +1,3 @@ TARGET_ARCH=i386 TARGET_XML_FILES= gdb-xml/i386-32bit.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/i386-linux-user.mak b/configs/targets/i386-linux-user.mak index b72a156473..ea68a266fc 100644 --- a/configs/targets/i386-linux-user.mak +++ b/configs/targets/i386-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=i386 TARGET_SYSTBL_ABI=i386 TARGET_SYSTBL=syscall_32.tbl TARGET_XML_FILES= gdb-xml/i386-32bit.xml gdb-xml/i386-32bit-linux.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmmu.mak index 2eb0e86250..5dd8921756 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -3,3 +3,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-32bit.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/loongarch64-linux-user.mak b/configs/targets/loongarch64-linux-user.mak index dfded79dfa..249a26a798 100644 --- a/configs/targets/loongarch64-linux-user.mak +++ b/configs/targets/loongarch64-linux-user.mak @@ -4,3 +4,4 @@ TARGET_BASE_ARCH=loongarch TARGET_XML_FILES=gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml TARGET_SYSTBL=syscall.tbl TARGET_SYSTBL_ABI=common,64 +TARGET_LONG_BITS=64 diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak index ce19ab6a16..351341132f 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -5,3 +5,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml # all boards require libfdt TARGET_NEED_FDT=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/m68k-linux-user.mak b/configs/targets/m68k-linux-user.mak index 579b5d299c..2d9bae2270 100644 --- a/configs/targets/m68k-linux-user.mak +++ b/configs/targets/m68k-linux-user.mak @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_XML_FILES= gdb-xml/cf-core.xml gdb-xml/cf-fp.xml gdb-xml/m68k-core.xml gdb-xml/m68k-fp.xml TARGET_HAS_BFLT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/m68k-softmmu.mak b/configs/targets/m68k-softmmu.mak index bbcd0bada6..bacc52e96a 100644 --- a/configs/targets/m68k-softmmu.mak +++ b/configs/targets/m68k-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=m68k TARGET_BIG_ENDIAN=y TARGET_XML_FILES= gdb-xml/cf-core.xml gdb-xml/cf-fp.xml gdb-xml/m68k-core.xml gdb-xml/m68k-fp.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/microblaze-linux-user.mak b/configs/targets/microblaze-linux-user.mak index 0a2322c249..3772779769 100644 --- a/configs/targets/microblaze-linux-user.mak +++ b/configs/targets/microblaze-linux-user.mak @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_HAS_BFLT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/microblaze-softmmu.mak index eea266d4f3..99a33ed44a 100644 --- a/configs/targets/microblaze-softmmu.mak +++ b/configs/targets/microblaze-softmmu.mak @@ -4,3 +4,6 @@ TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml +# System mode can address up to 64 bits via lea/sea instructions. +# TODO: These bypass the mmu, so we could emulate these differently. +TARGET_LONG_BITS=64 diff --git a/configs/targets/microblazeel-linux-user.mak b/configs/targets/microblazeel-linux-user.mak index 270743156a..a51a05488d 100644 --- a/configs/targets/microblazeel-linux-user.mak +++ b/configs/targets/microblazeel-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl TARGET_HAS_BFLT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/microblazeel-softmmu.mak index 77b968acad..52cdeae1a2 100644 --- a/configs/targets/microblazeel-softmmu.mak +++ b/configs/targets/microblazeel-softmmu.mak @@ -3,3 +3,6 @@ TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml +# System mode can address up to 64 bits via lea/sea instructions. +# TODO: These bypass the mmu, so we could emulate these differently. +TARGET_LONG_BITS=64 diff --git a/configs/targets/mips-linux-user.mak b/configs/targets/mips-linux-user.mak index b4569a9893..69bdc459b6 100644 --- a/configs/targets/mips-linux-user.mak +++ b/configs/targets/mips-linux-user.mak @@ -3,3 +3,4 @@ TARGET_ABI_MIPSO32=y TARGET_SYSTBL_ABI=o32 TARGET_SYSTBL=syscall_o32.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/mips-softmmu.mak b/configs/targets/mips-softmmu.mak index d34b4083fc..b62a088249 100644 --- a/configs/targets/mips-softmmu.mak +++ b/configs/targets/mips-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=mips TARGET_BIG_ENDIAN=y TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/mips64-linux-user.mak b/configs/targets/mips64-linux-user.mak index d2ff509a11..04e82b3ab1 100644 --- a/configs/targets/mips64-linux-user.mak +++ b/configs/targets/mips64-linux-user.mak @@ -4,3 +4,4 @@ TARGET_BASE_ARCH=mips TARGET_SYSTBL_ABI=n64 TARGET_SYSTBL=syscall_n64.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/mips64-softmmu.mak b/configs/targets/mips64-softmmu.mak index 12d9483bf0..7202655fca 100644 --- a/configs/targets/mips64-softmmu.mak +++ b/configs/targets/mips64-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=mips64 TARGET_BASE_ARCH=mips TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/mips64el-linux-user.mak b/configs/targets/mips64el-linux-user.mak index f9efeec8ea..27f4169426 100644 --- a/configs/targets/mips64el-linux-user.mak +++ b/configs/targets/mips64el-linux-user.mak @@ -3,3 +3,4 @@ TARGET_ABI_MIPSN64=y TARGET_BASE_ARCH=mips TARGET_SYSTBL_ABI=n64 TARGET_SYSTBL=syscall_n64.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/mips64el-softmmu.mak b/configs/targets/mips64el-softmmu.mak index 3864daa736..3ebeadb29e 100644 --- a/configs/targets/mips64el-softmmu.mak +++ b/configs/targets/mips64el-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=mips64 TARGET_BASE_ARCH=mips +TARGET_LONG_BITS=64 diff --git a/configs/targets/mipsel-linux-user.mak b/configs/targets/mipsel-linux-user.mak index e8d7241d31..8b7e86ab28 100644 --- a/configs/targets/mipsel-linux-user.mak +++ b/configs/targets/mipsel-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=mips TARGET_ABI_MIPSO32=y TARGET_SYSTBL_ABI=o32 TARGET_SYSTBL=syscall_o32.tbl +TARGET_LONG_BITS=32 diff --git a/configs/targets/mipsel-softmmu.mak b/configs/targets/mipsel-softmmu.mak index 0829659fc2..620ec68178 100644 --- a/configs/targets/mipsel-softmmu.mak +++ b/configs/targets/mipsel-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=mips TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/mipsn32-linux-user.mak b/configs/targets/mipsn32-linux-user.mak index 206095da64..39ae214633 100644 --- a/configs/targets/mipsn32-linux-user.mak +++ b/configs/targets/mipsn32-linux-user.mak @@ -5,3 +5,4 @@ TARGET_BASE_ARCH=mips TARGET_SYSTBL_ABI=n32 TARGET_SYSTBL=syscall_n32.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/mipsn32el-linux-user.mak b/configs/targets/mipsn32el-linux-user.mak index ca2a3ed753..d9b61d6990 100644 --- a/configs/targets/mipsn32el-linux-user.mak +++ b/configs/targets/mipsn32el-linux-user.mak @@ -4,3 +4,4 @@ TARGET_ABI32=y TARGET_BASE_ARCH=mips TARGET_SYSTBL_ABI=n32 TARGET_SYSTBL=syscall_n32.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/or1k-linux-user.mak b/configs/targets/or1k-linux-user.mak index eecb1e2241..810567a98f 100644 --- a/configs/targets/or1k-linux-user.mak +++ b/configs/targets/or1k-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=openrisc TARGET_BIG_ENDIAN=y TARGET_SYSTBL_ABI=common,32,or1k,time32,stat64,rlimit,renameat TARGET_SYSTBL=syscall.tbl +TARGET_LONG_BITS=32 diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmmu.mak index 0341cb2a6b..adfddb1a8a 100644 --- a/configs/targets/or1k-softmmu.mak +++ b/configs/targets/or1k-softmmu.mak @@ -3,3 +3,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_BIG_ENDIAN=y # needed by boot.c and all boards TARGET_NEED_FDT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/ppc-linux-user.mak b/configs/targets/ppc-linux-user.mak index cc0439a528..970d04a5ba 100644 --- a/configs/targets/ppc-linux-user.mak +++ b/configs/targets/ppc-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common,nospu,32 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_XML_FILES= gdb-xml/power-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/ppc-softmmu.mak b/configs/targets/ppc-softmmu.mak index 53120dab41..9bfa7df6c3 100644 --- a/configs/targets/ppc-softmmu.mak +++ b/configs/targets/ppc-softmmu.mak @@ -2,3 +2,4 @@ TARGET_ARCH=ppc TARGET_BIG_ENDIAN=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/power-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/ppc64-linux-user.mak b/configs/targets/ppc64-linux-user.mak index 4d81969f4a..461f1c67d1 100644 --- a/configs/targets/ppc64-linux-user.mak +++ b/configs/targets/ppc64-linux-user.mak @@ -5,3 +5,4 @@ TARGET_SYSTBL_ABI=common,nospu,64 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/ppc64-softmmu.mak b/configs/targets/ppc64-softmmu.mak index 40881d9396..7cee0e97f4 100644 --- a/configs/targets/ppc64-softmmu.mak +++ b/configs/targets/ppc64-softmmu.mak @@ -6,3 +6,4 @@ TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml # all boards require libfdt TARGET_NEED_FDT=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/ppc64le-linux-user.mak b/configs/targets/ppc64le-linux-user.mak index 426d5a28d6..cf9d8a400d 100644 --- a/configs/targets/ppc64le-linux-user.mak +++ b/configs/targets/ppc64le-linux-user.mak @@ -4,3 +4,4 @@ TARGET_ABI_DIR=ppc TARGET_SYSTBL_ABI=common,nospu,64 TARGET_SYSTBL=syscall.tbl TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/riscv32-linux-user.mak b/configs/targets/riscv32-linux-user.mak index 0dbaf5210a..a0ef03c0c3 100644 --- a/configs/targets/riscv32-linux-user.mak +++ b/configs/targets/riscv32-linux-user.mak @@ -7,3 +7,4 @@ CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=32 TARGET_SYSTBL_ABI=common,32,riscv,memfd_secret TARGET_SYSTBL=syscall.tbl +TARGET_LONG_BITS=32 diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak index 338182d5b8..c828066ce6 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -4,3 +4,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64-bsd-user.mak index 191c2c483f..c6348a7962 100644 --- a/configs/targets/riscv64-bsd-user.mak +++ b/configs/targets/riscv64-bsd-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/riscv64-linux-user.mak b/configs/targets/riscv64-linux-user.mak index 477cd4523e..aac7568305 100644 --- a/configs/targets/riscv64-linux-user.mak +++ b/configs/targets/riscv64-linux-user.mak @@ -7,3 +7,4 @@ CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=64 TARGET_SYSTBL_ABI=common,64,riscv,rlimit,memfd_secret TARGET_SYSTBL=syscall.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak index 6c5de72e03..09f613d24a 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -5,3 +5,4 @@ TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/rx-softmmu.mak b/configs/targets/rx-softmmu.mak index 706bbe6062..1c250a6450 100644 --- a/configs/targets/rx-softmmu.mak +++ b/configs/targets/rx-softmmu.mak @@ -2,3 +2,4 @@ TARGET_ARCH=rx TARGET_XML_FILES= gdb-xml/rx-core.xml # all boards require libfdt TARGET_NEED_FDT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/s390x-linux-user.mak b/configs/targets/s390x-linux-user.mak index 24c04c8589..68c2f28872 100644 --- a/configs/targets/s390x-linux-user.mak +++ b/configs/targets/s390x-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common,64 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-softmmu.mak index b22218aacc..5242ebe7c2 100644 --- a/configs/targets/s390x-softmmu.mak +++ b/configs/targets/s390x-softmmu.mak @@ -3,3 +3,4 @@ TARGET_BIG_ENDIAN=y TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/sh4-linux-user.mak b/configs/targets/sh4-linux-user.mak index 9908887566..d58c5471b7 100644 --- a/configs/targets/sh4-linux-user.mak +++ b/configs/targets/sh4-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=sh4 TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl TARGET_HAS_BFLT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/sh4-softmmu.mak b/configs/targets/sh4-softmmu.mak index f9d62d91e4..787d349b50 100644 --- a/configs/targets/sh4-softmmu.mak +++ b/configs/targets/sh4-softmmu.mak @@ -1 +1,2 @@ TARGET_ARCH=sh4 +TARGET_LONG_BITS=32 diff --git a/configs/targets/sh4eb-linux-user.mak b/configs/targets/sh4eb-linux-user.mak index 9db6b3609c..99007f0f2d 100644 --- a/configs/targets/sh4eb-linux-user.mak +++ b/configs/targets/sh4eb-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_HAS_BFLT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/sh4eb-softmmu.mak b/configs/targets/sh4eb-softmmu.mak index 226b1fc698..cdea2c61c5 100644 --- a/configs/targets/sh4eb-softmmu.mak +++ b/configs/targets/sh4eb-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=sh4 TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/sparc-linux-user.mak b/configs/targets/sparc-linux-user.mak index abcfb8fc62..4ff4b7287d 100644 --- a/configs/targets/sparc-linux-user.mak +++ b/configs/targets/sparc-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=sparc TARGET_SYSTBL_ABI=common,32 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak index a5d9200382..78c2e25bd1 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=sparc TARGET_BIG_ENDIAN=y TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/sparc32plus-linux-user.mak b/configs/targets/sparc32plus-linux-user.mak index 6cc8fa516b..7a16934fd1 100644 --- a/configs/targets/sparc32plus-linux-user.mak +++ b/configs/targets/sparc32plus-linux-user.mak @@ -5,3 +5,4 @@ TARGET_ABI_DIR=sparc TARGET_SYSTBL_ABI=common,32 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/sparc64-linux-user.mak b/configs/targets/sparc64-linux-user.mak index 52f05ec000..64ea04e3e2 100644 --- a/configs/targets/sparc64-linux-user.mak +++ b/configs/targets/sparc64-linux-user.mak @@ -4,3 +4,4 @@ TARGET_ABI_DIR=sparc TARGET_SYSTBL_ABI=common,64 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak index 36ca64ec41..f7bab97a00 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -2,3 +2,4 @@ TARGET_ARCH=sparc64 TARGET_BASE_ARCH=sparc TARGET_BIG_ENDIAN=y TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/tricore-softmmu.mak b/configs/targets/tricore-softmmu.mak index 96b10af853..781ce49a62 100644 --- a/configs/targets/tricore-softmmu.mak +++ b/configs/targets/tricore-softmmu.mak @@ -1 +1,2 @@ TARGET_ARCH=tricore +TARGET_LONG_BITS=32 diff --git a/configs/targets/x86_64-bsd-user.mak b/configs/targets/x86_64-bsd-user.mak index 799cd4acd4..d62d656f2c 100644 --- a/configs/targets/x86_64-bsd-user.mak +++ b/configs/targets/x86_64-bsd-user.mak @@ -1,3 +1,4 @@ TARGET_ARCH=x86_64 TARGET_BASE_ARCH=i386 TARGET_XML_FILES= gdb-xml/i386-64bit.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/x86_64-linux-user.mak b/configs/targets/x86_64-linux-user.mak index 86042814d3..b093ab5a16 100644 --- a/configs/targets/x86_64-linux-user.mak +++ b/configs/targets/x86_64-linux-user.mak @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=i386 TARGET_SYSTBL_ABI=common,64 TARGET_SYSTBL=syscall_64.tbl TARGET_XML_FILES= gdb-xml/i386-64bit.xml gdb-xml/i386-64bit-linux.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-softmmu.mak index 920e9a4200..1ceefde131 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -4,3 +4,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-64bit.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/xtensa-linux-user.mak b/configs/targets/xtensa-linux-user.mak index 420b30a68d..cbec6e368a 100644 --- a/configs/targets/xtensa-linux-user.mak +++ b/configs/targets/xtensa-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=xtensa TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl TARGET_HAS_BFLT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/xtensa-softmmu.mak b/configs/targets/xtensa-softmmu.mak index f075557bfa..65845df4ff 100644 --- a/configs/targets/xtensa-softmmu.mak +++ b/configs/targets/xtensa-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=xtensa TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/xtensaeb-linux-user.mak b/configs/targets/xtensaeb-linux-user.mak index bce2d1d65d..f455b1c780 100644 --- a/configs/targets/xtensaeb-linux-user.mak +++ b/configs/targets/xtensaeb-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 11/14] target/*: Remove TARGET_LONG_BITS from cpu-param.h Date: Sun, 2 Feb 2025 19:18:18 -0800 Message-ID: <20250203031821.741477-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is now handled by the configs/targets/*.mak fragment. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- target/alpha/cpu-param.h | 2 -- target/arm/cpu-param.h | 2 -- target/avr/cpu-param.h | 1 - target/hexagon/cpu-param.h | 1 - target/hppa/cpu-param.h | 2 -- target/i386/cpu-param.h | 2 -- target/loongarch/cpu-param.h | 1 - target/m68k/cpu-param.h | 1 - target/microblaze/cpu-param.h | 2 -- target/mips/cpu-param.h | 5 ----- target/openrisc/cpu-param.h | 1 - target/ppc/cpu-param.h | 2 -- target/riscv/cpu-param.h | 2 -- target/rx/cpu-param.h | 1 - target/s390x/cpu-param.h | 1 - target/sh4/cpu-param.h | 1 - target/sparc/cpu-param.h | 2 -- target/tricore/cpu-param.h | 1 - target/xtensa/cpu-param.h | 1 - 19 files changed, 31 deletions(-) diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index c21ddf1afd..ff06e41497 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -8,8 +8,6 @@ #ifndef ALPHA_CPU_PARAM_H #define ALPHA_CPU_PARAM_H -#define TARGET_LONG_BITS 64 - /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ #define TARGET_PHYS_ADDR_SPACE_BITS 44 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index bed29613c8..896b35bd6d 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -9,11 +9,9 @@ #define ARM_CPU_PARAM_H #ifdef TARGET_AARCH64 -# define TARGET_LONG_BITS 64 # define TARGET_PHYS_ADDR_SPACE_BITS 52 # define TARGET_VIRT_ADDR_SPACE_BITS 52 #else -# define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 40 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 93c2f470d0..81f3f49ee1 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -21,7 +21,6 @@ #ifndef AVR_CPU_PARAM_H #define AVR_CPU_PARAM_H -#define TARGET_LONG_BITS 32 /* * TARGET_PAGE_BITS cannot be more than 8 bits because * 1. all IO registers occupy [0x0000 .. 0x00ff] address range, and they diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 71b4a9b83e..45ee7b4640 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -19,7 +19,6 @@ #define HEXAGON_CPU_PARAM_H #define TARGET_PAGE_BITS 16 /* 64K pages */ -#define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_VIRT_ADDR_SPACE_BITS 32 diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index ef3200f0f3..7ed6b5741e 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -8,8 +8,6 @@ #ifndef HPPA_CPU_PARAM_H #define HPPA_CPU_PARAM_H -#define TARGET_LONG_BITS 64 - #if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32) # define TARGET_PHYS_ADDR_SPACE_BITS 32 # define TARGET_VIRT_ADDR_SPACE_BITS 32 diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 8c75abe141..b0e884c5d7 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -9,7 +9,6 @@ #define I386_CPU_PARAM_H #ifdef TARGET_X86_64 -# define TARGET_LONG_BITS 64 # define TARGET_PHYS_ADDR_SPACE_BITS 52 /* * ??? This is really 48 bits, sign-extended, but the only thing @@ -18,7 +17,6 @@ */ # define TARGET_VIRT_ADDR_SPACE_BITS 47 #else -# define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index db5ad1c69f..52437946e5 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -8,7 +8,6 @@ #ifndef LOONGARCH_CPU_PARAM_H #define LOONGARCH_CPU_PARAM_H -#define TARGET_LONG_BITS 64 #define TARGET_PHYS_ADDR_SPACE_BITS 48 #define TARGET_VIRT_ADDR_SPACE_BITS 48 diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 5bbe623ba7..7afbf6d302 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -8,7 +8,6 @@ #ifndef M68K_CPU_PARAM_H #define M68K_CPU_PARAM_H -#define TARGET_LONG_BITS 32 /* * Coldfire Linux uses 8k pages * and m68k linux uses 4k pages diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 00efb509e3..c866ec6c14 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -17,11 +17,9 @@ * of address space. */ #ifdef CONFIG_USER_ONLY -#define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 #else -#define TARGET_LONG_BITS 64 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 #endif diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index f3a37e2dbe..11b3ac0ac6 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -7,11 +7,6 @@ #ifndef MIPS_CPU_PARAM_H #define MIPS_CPU_PARAM_H -#ifdef TARGET_MIPS64 -# define TARGET_LONG_BITS 64 -#else -# define TARGET_LONG_BITS 32 -#endif #ifdef TARGET_ABI_MIPSN64 #define TARGET_PHYS_ADDR_SPACE_BITS 48 #define TARGET_VIRT_ADDR_SPACE_BITS 48 diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 6169ed9f55..37627f2c39 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -8,7 +8,6 @@ #ifndef OPENRISC_CPU_PARAM_H #define OPENRISC_CPU_PARAM_H -#define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 13 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 9c481b9f6c..6c4525fdf3 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -9,7 +9,6 @@ #define PPC_CPU_PARAM_H #ifdef TARGET_PPC64 -# define TARGET_LONG_BITS 64 /* * Note that the official physical address space bits is 62-M where M * is implementation dependent. I've not looked up M for the set of @@ -27,7 +26,6 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 64 # endif #else -# define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index 25686192c0..fba30e966a 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -9,11 +9,9 @@ #define RISCV_CPU_PARAM_H #if defined(TARGET_RISCV64) -# define TARGET_LONG_BITS 64 # define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ # define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ #elif defined(TARGET_RISCV32) -# define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index 521d669bdf..ef1970a09e 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -19,7 +19,6 @@ #ifndef RX_CPU_PARAM_H #define RX_CPU_PARAM_H -#define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 12 #define TARGET_PHYS_ADDR_SPACE_BITS 32 diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index a05ffcf78d..5c331ec424 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -8,7 +8,6 @@ #ifndef S390_CPU_PARAM_H #define S390_CPU_PARAM_H -#define TARGET_LONG_BITS 64 #define TARGET_PAGE_BITS 12 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index a30ba992b3..2b6e11dd0a 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -8,7 +8,6 @@ #ifndef SH4_CPU_PARAM_H #define SH4_CPU_PARAM_H -#define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 12 /* 4k */ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #ifdef CONFIG_USER_ONLY diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 14105dc18b..6952ee2b82 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -8,7 +8,6 @@ #define SPARC_CPU_PARAM_H #ifdef TARGET_SPARC64 -# define TARGET_LONG_BITS 64 # define TARGET_PAGE_BITS 13 /* 8k */ # define TARGET_PHYS_ADDR_SPACE_BITS 41 # ifdef TARGET_ABI32 @@ -17,7 +16,6 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 44 # endif #else -# define TARGET_LONG_BITS 32 # define TARGET_PAGE_BITS 12 /* 4k */ # define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index e29d551dd6..790242ef3d 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -8,7 +8,6 @@ #ifndef TRICORE_CPU_PARAM_H #define TRICORE_CPU_PARAM_H -#define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 14 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index 0000725f2f..5e4848ad05 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -8,7 +8,6 @@ #ifndef XTENSA_CPU_PARAM_H #define XTENSA_CPU_PARAM_H -#define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 12 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #ifdef CONFIG_USER_ONLY From patchwork Mon Feb 3 03:18:19 2025 Content-Type: text/plain; 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 12/14] meson: Disallow 64-bit on 32-bit TCG emulation Date: Sun, 2 Feb 2025 19:18:19 -0800 Message-ID: <20250203031821.741477-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For system mode, we can rarely support the amount of RAM that the guest requires. Emulation is restricted to round-robin mode, which solves many of the atomicity issues, but not those associated with virtio. In any case, round-robin does nothing to help the speed of emulation. For user mode, most emulation does not succeed at all. Most of the time we cannot even load 64-bit non-PIE binaries due to lack of a 64-bit address space. Threads are run in parallel, not round-robin, which means that atomicity is not handled. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth --- meson.build | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/meson.build b/meson.build index 5ca3cc3f34..866b8ce477 100644 --- a/meson.build +++ b/meson.build @@ -3176,6 +3176,9 @@ if host_os == 'windows' endif endif +# Detect host pointer size for the target configuration loop. +host_long_bits = cc.sizeof('void *') * 8 + ######################## # Target configuration # ######################## @@ -3268,11 +3271,18 @@ foreach target : target_dirs } endif + config_target += keyval.load('configs/targets' / target + '.mak') + target_kconfig = [] foreach sym: accelerators if sym == 'CONFIG_TCG' + # Disallow 64-bit on 32-bit TCG emulation. + if host_long_bits < config_target['TARGET_LONG_BITS'].to_int() + continue + endif config_target += { 'CONFIG_TCG_TARGET': 'y' } elif target not in accelerator_targets.get(sym, []) + # Other accelerators are handled by accelerator_targets. continue endif config_target += { sym: 'y' } @@ -3286,9 +3296,6 @@ foreach target : target_dirs error('No accelerator available for target @0@'.format(target)) endif - config_target += keyval.load('configs/targets' / target + '.mak') - config_target += { 'TARGET_' + config_target['TARGET_ARCH'].to_upper(): 'y' } - if 'TARGET_NEED_FDT' in config_target and not fdt.found() if default_targets warning('Disabling ' + target + ' due to missing libfdt') @@ -3301,6 +3308,7 @@ foreach target : target_dirs actual_target_dirs += target # Add default keys + config_target += { 'TARGET_' + config_target['TARGET_ARCH'].to_upper(): 'y' } if 'TARGET_BASE_ARCH' not in config_target config_target += {'TARGET_BASE_ARCH': config_target['TARGET_ARCH']} endif From patchwork Mon Feb 3 03:18:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861538 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp1832087wrr; Sun, 2 Feb 2025 19:19:54 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXQL/Dnvr9hPQCIJPCQJR1A4Qnl7eFuJp7sqN8/bpSc13ihFwv0FcNcCnnKVm4XgKolzrvqBA==@linaro.org X-Google-Smtp-Source: AGHT+IGDSzBtlxwZUbkWyspOKwHxcBCinCXI/td/OAX3NmOIGFKnOjZ2Vo2iDDIg6QorI4Vb8CeN X-Received: by 2002:a05:6214:2a8a:b0:6e2:2dd7:1404 with SMTP id 6a1803df08f44-6e243b9848emr289762986d6.3.1738552794398; Sun, 02 Feb 2025 19:19:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738552794; cv=none; d=google.com; s=arc-20240605; b=PlLDH3GosQni++r+rMlHmOzwiAtQdqGZb9HD8GEwAkFRO2o99YoamqIyihG6t+Qvjf eQPcSOmRJL3V82WmCj7Pk2WhCbdP3BTnD7vQTLlR3oz5rXdyh7MqNGHnv7uqc77kOx/g IFTavtMNpgyz3dbIO3EzdL7YVII4lNDfXbCpNBDojf6s0ghMtnd22IHPsOLAnSKyO5a/ Xgn4lvONmkHqcuUZ/kqL/N3Tuw+fOBk236RW4OMQ0j4rak3tC0zuQOzCKEvBIcXjDU6J 0cCeGZEEIsD3fUlfw4XYPVqGkLOyOfrkehs9M69QoOeL4L3yxeQDkwTYu79pb1eywsO5 MDIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2dkBfme6EKCsfk3FvCDsWy/MiBC6SNDbFvZSz+KhyEQ=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=KYkTeFoWpmYnPS/NBPKj7by3ztIfj6D8+9uRhhO69eAtnxiZnGA2jao/zBNv4qlgTi +gBw5Co9rhW4XgD2DPZEdosd18+YumVUTkBjy2stUuqCY62DEQ0On7DUKYJuGRC+iQyq 0vkxWWoPSwBijzh4w5PSESJEd7bBBThfnZHyOHy3X6eHuA9ZyfkxMQrrn8rrLVAKDVeD UWVWhzgArA4K/Qrsm62SLv+SVrDl5HqNP340P0ZXr4mfMOtv1ItfZGB2/g3/Xi3Wqgq8 8UhNWloCFQCG4aAIj3ZPfG2oNi/RtbxLbn/IlYezpulAwWhGXYKJHg3eLlnc9utWcY2g N8/A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BxRwNHkc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 13/14] meson: Deprecate 32-bit host support Date: Sun, 2 Feb 2025 19:18:20 -0800 Message-ID: <20250203031821.741477-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We deprecated i686 system mode support for qemu 8.0. However, to make real cleanups to TCG we need to deprecate all 32-bit hosts. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée --- docs/about/deprecated.rst | 7 +++++++ meson.build | 6 ++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 4a3c302962..7c61d0ba16 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -204,6 +204,13 @@ is going to be so much slower it wouldn't make sense for any serious instrumentation. Due to implementation differences there will also be anomalies in things like memory instrumentation. +32-bit host operating systems (since 10.0) +'''''''''''''''''''''''''''''''''''''''''' + +Keeping 32-bit host support alive is a substantial burden for the +QEMU project. Thus QEMU will in future drop the support for all +32-bit host systems. + System emulator CPUs -------------------- diff --git a/meson.build b/meson.build index 866b8ce477..0dae54da0d 100644 --- a/meson.build +++ b/meson.build @@ -4833,14 +4833,12 @@ if host_arch == 'unknown' message('configure has succeeded and you can continue to build, but') message('QEMU will use a slow interpreter to emulate the target CPU.') endif -elif host_arch == 'mips' +elif host_long_bits < 64 message() warning('DEPRECATED HOST CPU') message() message('Support for CPU host architecture ' + cpu + ' is going to be') - message('dropped as soon as the QEMU project stops supporting Debian 12') - message('("Bookworm"). Going forward, the QEMU project will not guarantee') - message('that QEMU will compile or work on this host CPU.') + message('dropped in a future QEMU release.') endif if not supported_oses.contains(host_os) From patchwork Mon Feb 3 03:18:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861542 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp1832124wrr; Sun, 2 Feb 2025 19:20:04 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXUQtH+6ug5gI9zy6XjdNB+BwrQw+kaneCdk6D+S0OPM63m1N0pWQJgJluJeLOfTJWc/ecDrw==@linaro.org X-Google-Smtp-Source: AGHT+IFIfXhG3cJR4nuTpjX6DtBjZMjAqQghxnRc3COkF4DmePwVqHU5SzHiPp2p2phYVGF7qSVL X-Received: by 2002:a05:6214:dcf:b0:6d9:2f70:2dab with SMTP id 6a1803df08f44-6e25b08a1a9mr155046376d6.16.1738552804214; Sun, 02 Feb 2025 19:20:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738552804; cv=none; d=google.com; s=arc-20240605; b=cziqVn+3BbJ6XmOQc72XJXIrnjvPMRSh73IMLeRT9GfGTBuNwNh7bvQkjplML69BkA W4uHh/GWG2AaLTjoVNd7INOHofmNZefl+18W0+CzZY0WGCuNjkekRSHlOHq1Snkiklt9 crY4PMKP+uxHdOK/3wrw7JT3aJnJV5W57ykyulShyzv9gLxgncM+sCCzWZZkhjYknIk6 /nDeFXwe2mP3iwjCg15xnV/VqRrwQuwtP8EyVvPi10KZVLY9HlEIb+0+xBG6Nfyvc+0W qYH1PWXEhxUf1TqDil3KGS2EFX+lxQHgSjlAVaptTa0loX9S8JLW1bqDZPPhkaU+hr6M 1tTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=p7b0UUGninisR0EI4xpwoVGAOe7defoH91cD8t1dIfI=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=gyegUgTFMF0GPKFAV+nhN9+CzRyZ53O52AaIrgNyI+qPBIUYyPHDvqyuAmgZIKf7zY yNJmHw9L5lBpgvRUNcJYFhBGSruVigQBEzwTsS7/Y4D7/d2KaSqmvWHu6zK3x6jB97K6 Azl6G9ME8OPSHvyCVUvoF8wOq/gMyzdb1QXuqX0nooc8Uzvw9rwv7sY6s8Va0Y/mjSlS t3dvXR88DMJBwjUuRsgk2fV9RzjgBvHHzfX2e/rFE2CRxLoB/LLxaA/fkx7QTIB1stF+ PoHxKqHUzBItXIg5CXpY8lz/AlSNXe18QrCyjrawjPxy+kvsph9Nu9DXkFmxNS++cERx 5ZZg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d3I5XXZZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32eb419sm65698135ad.145.2025.02.02.19.18.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 19:18:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v2 14/14] tcg: Remove TCG_OVERSIZED_GUEST Date: Sun, 2 Feb 2025 19:18:21 -0800 Message-ID: <20250203031821.741477-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203031821.741477-1-richard.henderson@linaro.org> References: <20250203031821.741477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is now prohibited in configuration. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- include/qemu/atomic.h | 18 +++-------------- include/tcg/oversized-guest.h | 23 ---------------------- accel/tcg/cputlb.c | 7 ------- accel/tcg/tcg-all.c | 9 ++++----- target/arm/ptw.c | 34 --------------------------------- target/riscv/cpu_helper.c | 13 +------------ docs/devel/multi-thread-tcg.rst | 1 - 7 files changed, 8 insertions(+), 97 deletions(-) delete mode 100644 include/tcg/oversized-guest.h diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index 7a3f2e6576..f80cba24cf 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -56,25 +56,13 @@ */ #define signal_barrier() __atomic_signal_fence(__ATOMIC_SEQ_CST) -/* Sanity check that the size of an atomic operation isn't "overly large". +/* + * Sanity check that the size of an atomic operation isn't "overly large". * Despite the fact that e.g. i686 has 64-bit atomic operations, we do not * want to use them because we ought not need them, and this lets us do a * bit of sanity checking that other 32-bit hosts might build. - * - * That said, we have a problem on 64-bit ILP32 hosts in that in order to - * sync with TCG_OVERSIZED_GUEST, this must match TCG_TARGET_REG_BITS. - * We'd prefer not want to pull in everything else TCG related, so handle - * those few cases by hand. - * - * Note that x32 is fully detected with __x86_64__ + _ILP32, and that for - * Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) & - * n64 (LP64) ABIs are both detected using __mips64. */ -#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64) -# define ATOMIC_REG_SIZE 8 -#else -# define ATOMIC_REG_SIZE sizeof(void *) -#endif +#define ATOMIC_REG_SIZE sizeof(void *) /* Weak atomic operations prevent the compiler moving other * loads/stores past the atomic operation load/store. However there is diff --git a/include/tcg/oversized-guest.h b/include/tcg/oversized-guest.h deleted file mode 100644 index 641b9749ff..0000000000 --- a/include/tcg/oversized-guest.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define TCG_OVERSIZED_GUEST - * Copyright (c) 2008 Fabrice Bellard - */ - -#ifndef EXEC_TCG_OVERSIZED_GUEST_H -#define EXEC_TCG_OVERSIZED_GUEST_H - -#include "tcg-target-reg-bits.h" -#include "cpu-param.h" - -/* - * Oversized TCG guests make things like MTTCG hard - * as we can't use atomics for cputlb updates. - */ -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -#define TCG_OVERSIZED_GUEST 1 -#else -#define TCG_OVERSIZED_GUEST 0 -#endif - -#endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b4ccf0cdcb..17e2251695 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -47,7 +47,6 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" -#include "tcg/oversized-guest.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -118,12 +117,8 @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry, return qatomic_read(ptr); #else const uint64_t *ptr = &entry->addr_idx[access_type]; -# if TCG_OVERSIZED_GUEST - return *ptr; -# else /* ofs might correspond to .addr_write, so use qatomic_read */ return qatomic_read(ptr); -# endif #endif } @@ -908,8 +903,6 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write; ptr_write += HOST_BIG_ENDIAN; qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY); -#elif TCG_OVERSIZED_GUEST - tlb_entry->addr_write |= TLB_NOTDIRTY; #else qatomic_set(&tlb_entry->addr_write, tlb_entry->addr_write | TLB_NOTDIRTY); diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 95adaacee8..c1a30b0121 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -28,7 +28,6 @@ #include "exec/replay-core.h" #include "system/cpu-timers.h" #include "tcg/startup.h" -#include "tcg/oversized-guest.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/accel.h" @@ -41,6 +40,8 @@ #include "hw/boards.h" #endif #include "internal-common.h" +#include "cpu-param.h" + struct TCGState { AccelState parent_obj; @@ -72,7 +73,7 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, static bool default_mttcg_enabled(void) { - if (icount_enabled() || TCG_OVERSIZED_GUEST) { + if (icount_enabled()) { return false; } #ifdef TARGET_SUPPORTS_MTTCG @@ -145,9 +146,7 @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp) TCGState *s = TCG_STATE(obj); if (strcmp(value, "multi") == 0) { - if (TCG_OVERSIZED_GUEST) { - error_setg(errp, "No MTTCG when guest word size > hosts"); - } else if (icount_enabled()) { + if (icount_enabled()) { error_setg(errp, "No MTTCG when icount is enabled"); } else { #ifndef TARGET_SUPPORTS_MTTCG diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 64bb6878a4..4330900348 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -16,9 +16,6 @@ #include "internals.h" #include "cpu-features.h" #include "idau.h" -#ifdef CONFIG_TCG -# include "tcg/oversized-guest.h" -#endif typedef struct S1Translate { /* @@ -840,7 +837,6 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, ptw->out_rw = true; } -#ifdef CONFIG_ATOMIC64 if (ptw->out_be) { old_val = cpu_to_be64(old_val); new_val = cpu_to_be64(new_val); @@ -852,36 +848,6 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val); cur_val = le64_to_cpu(cur_val); } -#else - /* - * We can't support the full 64-bit atomic cmpxchg on the host. - * Because this is only used for FEAT_HAFDBS, which is only for AA64, - * we know that TCG_OVERSIZED_GUEST is set, which means that we are - * running in round-robin mode and could only race with dma i/o. - */ -#if !TCG_OVERSIZED_GUEST -# error "Unexpected configuration" -#endif - bool locked = bql_locked(); - if (!locked) { - bql_lock(); - } - if (ptw->out_be) { - cur_val = ldq_be_p(host); - if (cur_val == old_val) { - stq_be_p(host, new_val); - } - } else { - cur_val = ldq_le_p(host); - if (cur_val == old_val) { - stq_le_p(host, new_val); - } - } - if (!locked) { - bql_unlock(); - } -#endif - return cur_val; #else /* AArch32 does not have FEAT_HADFS; non-TCG guests only use debug-mode. */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e1dfc4ecbf..8ff6d900f2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -32,7 +32,6 @@ #include "system/cpu-timers.h" #include "cpu_bits.h" #include "debug.h" -#include "tcg/oversized-guest.h" #include "pmp.h" int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) @@ -1167,9 +1166,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, hwaddr pte_addr; int i; -#if !TCG_OVERSIZED_GUEST -restart: -#endif + restart: for (i = 0; i < levels; i++, ptshift -= ptidxbits) { target_ulong idx; if (i == 0) { @@ -1388,13 +1385,6 @@ restart: false, MEMTXATTRS_UNSPECIFIED); if (memory_region_is_ram(mr)) { target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1); -#if TCG_OVERSIZED_GUEST - /* - * MTTCG is not enabled on oversized TCG guests so - * page table updates do not need to be atomic - */ - *pte_pa = pte = updated_pte; -#else target_ulong old_pte; if (riscv_cpu_sxl(env) == MXL_RV32) { old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte); @@ -1405,7 +1395,6 @@ restart: goto restart; } pte = updated_pte; -#endif } else { /* * Misconfigured PTE in ROM (AD bits are not preset) or diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst index 7fd0a07633..b0f473961d 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -37,7 +37,6 @@ if: * forced by --accel tcg,thread=single * enabling --icount mode -* 64 bit guests on 32 bit hosts (TCG_OVERSIZED_GUEST) In the general case of running translated code there should be no inter-vCPU dependencies and all vCPUs should be able to run at full