From patchwork Tue Dec 31 19:39:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 182689 Delivered-To: patch@linaro.org Received: by 2002:a92:815a:0:0:0:0:0 with SMTP id e87csp7934312ild; Tue, 31 Dec 2019 11:39:11 -0800 (PST) X-Google-Smtp-Source: APXvYqxIC8xfbzXXSrOgh/PyZwhxz+vrFLbjbR5n8ycu7Eph30+b0/Cw/0wITuOn0v4danRiCL9D X-Received: by 2002:a17:906:7006:: with SMTP id n6mr51610499ejj.1.1577821151807; Tue, 31 Dec 2019 11:39:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1577821151; cv=none; d=google.com; s=arc-20160816; b=O+hXNCor8CzVRKtmpqS69N5F7ay3ELl0t6ppJyE5iCeThgNGqDHpi2dSY0wiFp+M+i KTlrLbTjAew2x1zfoQD7pVXVmk6G24DXDMdAwTPJ4ybd+e8e7ZyW9i6mICaVr/2gnmcw /BvB2gsrWUv8WkIOR5DFLSat08LYPk4yCN8ShUEiG1UwX8rT3yKnqfgoSuVHuJuoyBhd ZBB5a5FRcHdrv+Ln/gY3zGdlrYBSIQjOHomDBNP0L1L4Rrp6kCEJaXnrQgRvUrtzkE86 lbr6yVX2sbNhpvYC2RMj5q8CdajlfG1qPBfNiIC1HxB6EWzSfB2KlADHgO4fO5wN5vjF 9o3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=iqacRFuypSbp63ZFpYBf+4/J26LILeoQM9atqZZnMj4=; b=Bax5tLLrOCYLsxoCYSQE4f8f3U54dL+32kOD5NBGqFp0dRo4OMVjbADKxVJJzK0oKp un6lmhnXv5okszi+4epfa8z9Iep2KabGj9TNaTPH1tQ3sru8YDrNMxTU1quFm7J5JQUe kD3YPJG+SMl84Xi+NwMz+0XBjz8xG2yLihZPdsHNdrHqkiK+As0uECGgtR7fxoxv9chS SqlZQpQ2+8/Br5KcbeU2D15A3vtSaKrtBzF3K94RZzxyi/NDhYoFWJcR4OSeKoPftYZ3 6EUzIGaufJvVzn/TqmEvbWIJgCChYw4NLM3h3onSWX5Rw1zztA8rHWBHY7FbqTbsxHA3 Appw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l23si33521327edv.243.2019.12.31.11.39.11; Tue, 31 Dec 2019 11:39:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727134AbfLaTjI (ORCPT + 27 others); Tue, 31 Dec 2019 14:39:08 -0500 Received: from mail-il1-f195.google.com ([209.85.166.195]:36874 "EHLO mail-il1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726534AbfLaTjI (ORCPT ); Tue, 31 Dec 2019 14:39:08 -0500 Received: by mail-il1-f195.google.com with SMTP id t8so30844715iln.4; Tue, 31 Dec 2019 11:39:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iqacRFuypSbp63ZFpYBf+4/J26LILeoQM9atqZZnMj4=; b=Dm3z8wXCSAK62yE8DJNLSyBOSFnFuZobkbzxp+NxPbEFswOcF3FOk7RcqES+VSLAfO ncFG26Xnf6pl6kGoS9YKSRhjoIJwIH2+NfHfc598lc1aDjSQtrvKDYUVfEYYeoDxeSJV 9IN+XlSmLby02zeVYoLwr76q2IBMggZon7Qz2M0gWCTO29jweQS893x3WfQLph9Q3G2l ZpVhGf7eMiDAewEs2o6qsGC6EHyGVSesqgCF5Pa+haVk1jkxImD6m/P/CUbKhcCALPgE P7hp4PVNCV0MlU2I04VuRAZ85VHmSbmaZpbhfEAf975GGDNgSezS3QRM3hQZrAI7750p x9eQ== X-Gm-Message-State: APjAAAUbcJyYijGTSkJZngpbuQ481xIgRRJp1kJukCH1nCkCHiKwhz1C TQ4jP3fe13u7VgL41OTTHECsQkc= X-Received: by 2002:a92:3cd4:: with SMTP id j81mr66368596ilf.77.1577821146884; Tue, 31 Dec 2019 11:39:06 -0800 (PST) Received: from xps15.herring.priv ([64.188.179.250]) by smtp.googlemail.com with ESMTPSA id e1sm17860074ill.47.2019.12.31.11.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 11:39:06 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Alan Douglas , Scott Telford , Tom Joseph , Bjorn Helgaas , Lorenzo Pieralisi , Andrew Murray Subject: [PATCH v2 2/3] dt-bindings: PCI: Convert Cadence host to DT schema Date: Tue, 31 Dec 2019 12:39:02 -0700 Message-Id: <20191231193903.15929-2-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191231193903.15929-1-robh@kernel.org> References: <20191231193903.15929-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the Cadence PCIe host binding to DT schema. The 'phy-names' definition is incomplete. 'vendor-id' and 'device-id' aren't listed as those are standard PCI properties. They were incorrectly defined as 16-bit when they should be 32-bits (even though only 16-bits are used). 'cdns,max-outbound-regions' should really be removed. It serves no purpose other than bounds checking 'ranges'. If 'ranges' is wrong for the h/w, what's going to ensure 'cdns,max-outbound-regions' is correct. 'cdns,no-bar-match-nbits' is also suspect. This probably could be determined from 'dma-ranges' using the sizes. Cc: Alan Douglas Cc: Scott Telford Cc: Tom Joseph Cc: Bjorn Helgaas Cc: Lorenzo Pieralisi Cc: Andrew Murray Signed-off-by: Rob Herring --- v2: no change .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ----------- .../bindings/pci/cdns,cdns-pcie-host.yaml | 106 ++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 107 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml -- 2.20.1 diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt deleted file mode 100644 index 91de69c713a9..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt +++ /dev/null @@ -1,66 +0,0 @@ -* Cadence PCIe host controller - -This PCIe controller inherits the base properties defined in -host-generic-pci.txt. - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used. -- reg: Should contain the controller register base address, PCIe configuration - window base address, and AXI interface region base address respectively. -- reg-names: Must be "reg", "cfg" and "mem" respectively. -- #address-cells: Set to <3> -- #size-cells: Set to <2> -- device_type: Set to "pci" -- ranges: Ranges for the PCI memory and I/O regions -- #interrupt-cells: Set to <1> -- interrupt-map-mask and interrupt-map: Standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers. - -Optional properties: -- cdns,max-outbound-regions: Set to maximum number of outbound regions - (default 32) -- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the - number of least significant bits kept during inbound (PCIe -> AXI) address - translations (default 32) -- vendor-id: The PCI vendor ID (16 bits, default is design dependent) -- device-id: The PCI device ID (16 bits, default is design dependent) -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fb000000 { - compatible = "cdns,cdns-pcie-host"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - linux,pci-domain = <0>; - cdns,max-outbound-regions = <16>; - cdns,no-bar-match-nbits = <32>; - vendor-id = /bits/ 16 <0x17cd>; - device-id = /bits/ 16 <0x0200>; - - reg = <0x0 0xfb000000 0x0 0x01000000>, - <0x0 0x41000000 0x0 0x00001000>, - <0x0 0x40000000 0x0 0x04000000>; - reg-names = "reg", "cfg", "mem"; - - ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, - <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; - - #interrupt-cells = <0x1>; - - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; - - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - - msi-parent = <&its_pci>; - - phys = <&pcie_phy0>; - phy-names = "pcie-phy"; -}; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml new file mode 100644 index 000000000000..ada77e267b68 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence PCIe host controller + +maintainers: + - Alan Douglas + - Scott Telford + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: cdns,cdns-pcie-host + + reg: + maxItems: 3 + + reg-names: + items: + - const: reg + - const: cfg + - const: mem + + cdns,max-outbound-regions: + description: maximum number of outbound regions + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 32 + + cdns,no-bar-match-nbits: + description: + Set into the no BAR match register to configure the number of least + significant bits kept during inbound (PCIe -> AXI) address translations + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 32 + default: 32 + + msi-parent: true + + phys: + description: + One per lane if more than one in the list. If only one PHY listed it must + manage all lanes. + minItems: 1 + maxItems: 16 + + phy-names: + items: + - const: pcie-phy + # FIXME: names when more than 1 + +required: + - reg + - reg-names + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@fb000000 { + compatible = "cdns,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <32>; + vendor-id = /bits/ 16 <0x17cd>; + device-id = /bits/ 16 <0x0200>; + + reg = <0x0 0xfb000000 0x0 0x01000000>, + <0x0 0x41000000 0x0 0x00001000>, + <0x0 0x40000000 0x0 0x04000000>; + reg-names = "reg", "cfg", "mem"; + + ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, + <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; + + #interrupt-cells = <0x1>; + + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; + + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + + msi-parent = <&its_pci>; + + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 1072745a8fda..b55f9dd7c47a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12595,7 +12595,7 @@ PCI DRIVER FOR CADENCE PCIE IP M: Tom Joseph L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/cdns,*.txt +F: Documentation/devicetree/bindings/pci/cdns,* F: drivers/pci/controller/pcie-cadence* PCI DRIVER FOR FREESCALE LAYERSCAPE From patchwork Tue Dec 31 19:39:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 182690 Delivered-To: patch@linaro.org Received: by 2002:a92:815a:0:0:0:0:0 with SMTP id e87csp7934323ild; Tue, 31 Dec 2019 11:39:13 -0800 (PST) X-Google-Smtp-Source: APXvYqx01R5+BFv+4fYxLloErsgqH2dTaHNd4AWAX1aqSdNu32Qs1xrsHU/nPg5aoLUdOBcgIIl3 X-Received: by 2002:aa7:c59a:: with SMTP id g26mr77978497edq.109.1577821152904; Tue, 31 Dec 2019 11:39:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1577821152; cv=none; d=google.com; s=arc-20160816; b=ZpWWJUhpM2vTEMtZMtBUK95ZaE7EgVSYVJov5fzJ7dxejN8T8lHPkXoajSpEfPeoGa v2Jm7xRis9q79VOGBbqRGc2XB2UihBblbuJOu3mH3Qq0sC0FGocJBWzYts/iM/h8L7WR DFH/VG3Ed5f1Anbiwwt9hPyjg+iQ1kXVWqI49glgaps0OElRai5lN/tZplWWR23fFxR2 WJnML0Ws3t2x6QVREiJcojLQrxqoFq7MIr+1ZisQ6XYNkbChNuhpR40G+p7PwcDHR03n ukUbk64YaKA/Ta6VV2q2b1O9PdoB0TVO4Nm0sd93ZOlBucD0DeBfPFQxkEnZJXqalyta DHTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Yzg1o+NejcreYIWjvsiNbCW/clv43Gm/h+fsjIitq30=; b=lYMiFKhXDpCf8kPTq/gygQSvtfs5x3A4nQxL+uCIMO2ZSjaxtkMJoszSiHH9vk2jHz X4lpUgdwvf1oLF+6kOJBsNLFBw2rsRNdMv3kZwq8bFl2NU0GWJayhKQGlJxNqwvL4bQJ E2Tdgom0h92v0N1Nk/tEUT/V3ZT6i4qfjVHHIjv7KMhEIFJEtDAxEvxsqrvm9ZUKA2kP l0SiSLCHtPvccS2h2sTMLcJApBnwFg/oMy/7lmtGtsFMsIWuL7sSXK/br3UiLYTr/7FU lV9jW6txGWGyThpirwcx6YonfGalWFfLYlfAY0+erpoWt33hQKTBXYI348uAHVv4bZXb gnzw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l23si33521327edv.243.2019.12.31.11.39.12; Tue, 31 Dec 2019 11:39:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727156AbfLaTjK (ORCPT + 27 others); Tue, 31 Dec 2019 14:39:10 -0500 Received: from mail-il1-f195.google.com ([209.85.166.195]:40911 "EHLO mail-il1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726534AbfLaTjJ (ORCPT ); Tue, 31 Dec 2019 14:39:09 -0500 Received: by mail-il1-f195.google.com with SMTP id c4so30832301ilo.7; Tue, 31 Dec 2019 11:39:09 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yzg1o+NejcreYIWjvsiNbCW/clv43Gm/h+fsjIitq30=; b=OeiZ6mPG+DV5XAGSwbp9ZZiRPuwwEdKHy6MaLR4+QESdlWiBWhsT4AIe9SWrZRJpXF KOizdgxLYQmXkTMHfblRiqFoFHVFQfkUFJeER0RaLwlGNDSYrsSqet7p7PAxSdjccXqA 3rU4OVY+uIg1mwHQGwA1KRysW8E17dEgMwKcvLkbb2YiI3VQ+GPjWl3eAS5otZDNxgPi AwDHnYsHmdfe3rc5twwJDGFrAHYyq7OxBZuujbmt1UPQPXtLGP2mdyzmBaEGcT+TrV0l NArfUWvnervEME7Jj1KN6Tx1G6tCelvkN/RCxriQJ1gActBqRkfTzTSdn9kjgzA3OdBx I/vA== X-Gm-Message-State: APjAAAU9QHX3Kb4F/g8wdCWBuQ7Y0zwFEswBRaeVmnt5Zz8K6kKUWJtm O+YVgqD8UO+nZ+D8Y65vfD4MSXM= X-Received: by 2002:a92:914a:: with SMTP id t71mr65534894ild.293.1577821148339; Tue, 31 Dec 2019 11:39:08 -0800 (PST) Received: from xps15.herring.priv ([64.188.179.250]) by smtp.googlemail.com with ESMTPSA id e1sm17860074ill.47.2019.12.31.11.39.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 11:39:07 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Andrew Murray , Zhou Wang , Will Deacon , David Daney Subject: [PATCH v2 3/3] dt-bindings: PCI: Convert generic host binding to DT schema Date: Tue, 31 Dec 2019 12:39:03 -0700 Message-Id: <20191231193903.15929-3-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191231193903.15929-1-robh@kernel.org> References: <20191231193903.15929-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the generic PCI host binding to DT schema. The derivative Juno, PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in their compatible strings. The simplest way to convert those to schema is just add them into the common generic PCI host schema. The HiSilicon ECAM and Cavium ThunderX PEM bindings have an additional 'reg' entry, but are otherwise the same binding as well. Cc: Bjorn Helgaas Cc: Lorenzo Pieralisi Cc: Andrew Murray Cc: Zhou Wang Cc: Will Deacon Cc: David Daney Signed-off-by: Rob Herring --- v2: - Add in Cavium PEM and HiSilicon ECAM bindings - Drop dma-coherent description - Drop leftover interrupt mapping text - Add description for generic compatibles and drop 'contains' .../bindings/pci/arm,juno-r1-pcie.txt | 10 - .../bindings/pci/designware-pcie-ecam.txt | 42 ----- .../bindings/pci/hisilicon-pcie.txt | 42 ----- .../bindings/pci/host-generic-pci.txt | 101 ---------- .../bindings/pci/host-generic-pci.yaml | 172 ++++++++++++++++++ .../bindings/pci/pci-thunder-ecam.txt | 30 --- .../bindings/pci/pci-thunder-pem.txt | 43 ----- .../bindings/pci/plda,xpressrich3-axi.txt | 12 -- MAINTAINERS | 2 +- 9 files changed, 173 insertions(+), 281 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt delete mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.txt create mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.yaml delete mode 100644 Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt delete mode 100644 Documentation/devicetree/bindings/pci/pci-thunder-pem.txt delete mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt -- 2.20.1 diff --git a/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt b/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt deleted file mode 100644 index f7514c170a32..000000000000 --- a/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt +++ /dev/null @@ -1,10 +0,0 @@ -* ARM Juno R1 PCIe interface - -This PCIe host controller is based on PLDA XpressRICH3-AXI IP -and thus inherits all the common properties defined in plda,xpressrich3-axi.txt -as well as the base properties defined in host-generic-pci.txt. - -Required properties: - - compatible: "arm,juno-r1-pcie" - - dma-coherent: The host controller bridges the AXI transactions into PCIe bus - in a manner that makes the DMA operations to appear coherent to the CPUs. diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted file mode 100644 index 515b2f9542e5..000000000000 --- a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Synopsys DesignWare PCIe root complex in ECAM shift mode - -In some cases, firmware may already have configured the Synopsys DesignWare -PCIe controller in RC mode with static ATU window mappings that cover all -config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion. -In this case, there is no need for the OS to perform any low level setup -of clocks, PHYs or device registers, nor is there any reason for the driver -to reconfigure ATU windows for config and/or IO space accesses at runtime. - -In cases where the IP was synthesized with a minimum ATU window size of -64 KB, it cannot be supported by the generic ECAM driver, because it -requires special config space accessors that filter accesses to device #1 -and beyond on the first bus. - -Required properties: -- compatible: "marvell,armada8k-pcie-ecam" or - "socionext,synquacer-pcie-ecam" or - "snps,dw-pcie-ecam" (must be preceded by a more specific match) - -Please refer to the binding document of "pci-host-ecam-generic" in the -file host-generic-pci.txt for a description of the remaining required -and optional properties. - -Example: - - pcie1: pcie@7f000000 { - compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; - device_type = "pci"; - reg = <0x0 0x7f000000 0x0 0xf00000>; - bus-range = <0x0 0xe>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>, - <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>, - <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; - - #interrupt-cells = <0x1>; - interrupt-map-mask = <0x0 0x0 0x0 0x0>; - interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>; - msi-map = <0x0 &its 0x0 0x10000>; - dma-coherent; - }; diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index 0dcb87d6554f..d6796ef54ea1 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -41,45 +41,3 @@ Hip05 Example (note that Hip06 is the same except compatible): 0x0 0 0 3 &mbigen_pcie 3 12 0x0 0 0 4 &mbigen_pcie 4 13>; }; - -HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description. - -Some BIOSes place the host controller in a mode where it is ECAM -compliant for all devices other than the root complex. In such cases, -the host controller should be described as below. - -The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. - -Properties of the host controller node that differ from -host-generic-pci.txt: - -- compatible : Must be "hisilicon,hip06-pcie-ecam", or - "hisilicon,hip07-pcie-ecam" - -- reg : Two entries: First the ECAM configuration space for any - other bus underneath the root bus. Second, the base - and size of the HiSilicon host bridge registers include - the RC's own config space. - -Example: - pcie0: pcie@a0090000 { - compatible = "hisilicon,hip06-pcie-ecam"; - reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */ - <0 0xa0090000 0 0x10000>; /* host bridge registers */ - bus-range = <0 31>; - msi-map = <0x0000 &its_dsa 0x0000 0x2000>; - msi-map-mask = <0xffff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000 - 0x01000000 0 0 0 0xb7ff0000 0 0x10000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 - 0x0 0 0 2 &mbigen_pcie0 650 4 - 0x0 0 0 3 &mbigen_pcie0 650 4 - 0x0 0 0 4 &mbigen_pcie0 650 4>; - }; diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt b/Documentation/devicetree/bindings/pci/host-generic-pci.txt deleted file mode 100644 index 614b594f4e72..000000000000 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt +++ /dev/null @@ -1,101 +0,0 @@ -* Generic PCI host controller - -Firmware-initialised PCI host controllers and PCI emulations, such as the -virtio-pci implementations found in kvmtool and other para-virtualised -systems, do not require driver support for complexities such as regulator -and clock management. In fact, the controller may not even require the -configuration of a control interface by the operating system, instead -presenting a set of fixed windows describing a subset of IO, Memory and -Configuration Spaces. - -Such a controller can be described purely in terms of the standardized device -tree bindings communicated in pci.txt: - - -Properties of the host controller node: - -- compatible : Must be "pci-host-cam-generic" or "pci-host-ecam-generic" - depending on the layout of configuration space (CAM vs - ECAM respectively). - -- device_type : Must be "pci". - -- ranges : As described in IEEE Std 1275-1994, but must provide - at least a definition of non-prefetchable memory. One - or both of prefetchable Memory and IO Space may also - be provided. - -- bus-range : Optional property (also described in IEEE Std 1275-1994) - to indicate the range of bus numbers for this controller. - If absent, defaults to <0 255> (i.e. all buses). - -- #address-cells : Must be 3. - -- #size-cells : Must be 2. - -- reg : The Configuration Space base address and size, as accessed - from the parent bus. The base address corresponds to - the first bus in the "bus-range" property. If no - "bus-range" is specified, this will be bus 0 (the default). - -Properties of the /chosen node: - -- linux,pci-probe-only - : Optional property which takes a single-cell argument. - If '0', then Linux will assign devices in its usual manner, - otherwise it will not try to assign devices and instead use - them as they are configured already. - -Configuration Space is assumed to be memory-mapped (as opposed to being -accessed via an ioport) and laid out with a direct correspondence to the -geography of a PCI bus address by concatenating the various components to -form an offset. - -For CAM, this 24-bit offset is: - - cfg_offset(bus, device, function, register) = - bus << 16 | device << 11 | function << 8 | register - -While ECAM extends this by 4 bits to accommodate 4k of function space: - - cfg_offset(bus, device, function, register) = - bus << 20 | device << 15 | function << 12 | register - -Interrupt mapping is exactly as described in `Open Firmware Recommended -Practice: Interrupt Mapping' and requires the following properties: - -- #interrupt-cells : Must be 1 - -- interrupt-map : - -- interrupt-map-mask : - - -Example: - -pci { - compatible = "pci-host-cam-generic" - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0x1>; - - // CPU_PHYSICAL(2) SIZE(2) - reg = <0x0 0x40000000 0x0 0x1000000>; - - // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2) - ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>, - <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>; - - - #interrupt-cells = <0x1>; - - // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3) - interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1 - 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1 - 0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1 - 0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>; - - // PCI_DEVICE(3) INT#(1) - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; -} diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml new file mode 100644 index 000000000000..47353d0cd394 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/host-generic-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic PCI host controller + +maintainers: + - Will Deacon + +description: | + Firmware-initialised PCI host controllers and PCI emulations, such as the + virtio-pci implementations found in kvmtool and other para-virtualised + systems, do not require driver support for complexities such as regulator + and clock management. In fact, the controller may not even require the + configuration of a control interface by the operating system, instead + presenting a set of fixed windows describing a subset of IO, Memory and + Configuration Spaces. + + Configuration Space is assumed to be memory-mapped (as opposed to being + accessed via an ioport) and laid out with a direct correspondence to the + geography of a PCI bus address by concatenating the various components to + form an offset. + + For CAM, this 24-bit offset is: + + cfg_offset(bus, device, function, register) = + bus << 16 | device << 11 | function << 8 | register + + While ECAM extends this by 4 bits to accommodate 4k of function space: + + cfg_offset(bus, device, function, register) = + bus << 20 | device << 15 | function << 12 | register + +properties: + compatible: + description: Depends on the layout of configuration space (CAM vs ECAM + respectively). May also have more specific compatibles. + oneOf: + - description: + PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP + items: + - const: arm,juno-r1-pcie + - const: plda,xpressrich3-axi + - const: pci-host-ecam-generic + - description: | + ThunderX PCI host controller for pass-1.x silicon + + Firmware-initialized PCI host controller to on-chip devices found on + some Cavium ThunderX processors. These devices have ECAM-based config + access, but the BARs are all at fixed addresses. We handle the fixed + addresses by synthesizing Enhanced Allocation (EA) capabilities for + these devices. + const: cavium,pci-host-thunder-ecam + - description: + Cavium ThunderX PEM firmware-initialized PCIe host controller + const: cavium,pci-host-thunder-pem + - description: + HiSilicon Hip06/Hip07 PCIe host bridge in almost-ECAM mode. Some + firmware places the host controller in a mode where it is ECAM + compliant for all devices other than the root complex. + enum: + - hisilicon,hip06-pcie-ecam + - hisilicon,hip07-pcie-ecam + - description: | + In some cases, firmware may already have configured the Synopsys + DesignWare PCIe controller in RC mode with static ATU window mappings + that cover all config, MMIO and I/O spaces in a [mostly] ECAM + compatible fashion. In this case, there is no need for the OS to + perform any low level setup of clocks, PHYs or device registers, nor + is there any reason for the driver to reconfigure ATU windows for + config and/or IO space accesses at runtime. + + In cases where the IP was synthesized with a minimum ATU window size + of 64 KB, it cannot be supported by the generic ECAM driver, because + it requires special config space accessors that filter accesses to + device #1 and beyond on the first bus. + items: + - enum: + - marvell,armada8k-pcie-ecam + - socionext,synquacer-pcie-ecam + - const: snps,dw-pcie-ecam + - description: + CAM or ECAM compliant PCI host controllers without any quirks + enum: + - pci-host-cam-generic + - pci-host-ecam-generic + + reg: + description: + The Configuration Space base address and size, as accessed from the parent + bus. The base address corresponds to the first bus in the "bus-range" + property. If no "bus-range" is specified, this will be bus 0 (the + default). Some host controllers have a 2nd non-compliant address range, + so 2 entries are allowed. + minItems: 1 + maxItems: 2 + + ranges: + description: + As described in IEEE Std 1275-1994, but must provide at least a + definition of non-prefetchable memory. One or both of prefetchable Memory + and IO Space may also be provided. + minItems: 1 + maxItems: 3 + + dma-coherent: true + +required: + - compatible + - reg + - ranges + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - if: + properties: + compatible: + contains: + const: arm,juno-r1-pcie + then: + required: + - dma-coherent + + - if: + properties: + compatible: + not: + contains: + enum: + - cavium,pci-host-thunder-pem + - hisilicon,hip06-pcie-ecam + - hisilicon,hip07-pcie-ecam + then: + properties: + reg: + maxItems: 1 + +examples: + - | + + bus { + #address-cells = <2>; + #size-cells = <2>; + pcie@40000000 { + compatible = "pci-host-cam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x1>; + + // CPU_PHYSICAL(2) SIZE(2) + reg = <0x0 0x40000000 0x0 0x1000000>; + + // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2) + ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>, + <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>; + + #interrupt-cells = <0x1>; + + // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3) + interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>, + < 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>, + <0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>, + <0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>; + + // PCI_DEVICE(3) INT#(1) + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt b/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt deleted file mode 100644 index f478874b79ce..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt +++ /dev/null @@ -1,30 +0,0 @@ -* ThunderX PCI host controller for pass-1.x silicon - -Firmware-initialized PCI host controller to on-chip devices found on -some Cavium ThunderX processors. These devices have ECAM-based config -access, but the BARs are all at fixed addresses. We handle the fixed -addresses by synthesizing Enhanced Allocation (EA) capabilities for -these devices. - -The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. - -Properties of the host controller node that differ from -host-generic-pci.txt: - -- compatible : Must be "cavium,pci-host-thunder-ecam" - -Example: - - pcie@84b000000000 { - compatible = "cavium,pci-host-thunder-ecam"; - device_type = "pci"; - msi-parent = <&its>; - msi-map = <0 &its 0x30000 0x10000>; - bus-range = <0 31>; - #size-cells = <2>; - #address-cells = <3>; - #stream-id-cells = <1>; - reg = <0x84b0 0x00000000 0 0x02000000>; /* Configuration space */ - ranges = <0x03000000 0x8180 0x00000000 0x8180 0x00000000 0x80 0x00000000>; /* mem ranges */ - }; diff --git a/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt b/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt deleted file mode 100644 index f131faea3b7c..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt +++ /dev/null @@ -1,43 +0,0 @@ -* ThunderX PEM PCIe host controller - -Firmware-initialized PCI host controller found on some Cavium -ThunderX processors. - -The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. - -Properties of the host controller node that differ from -host-generic-pci.txt: - -- compatible : Must be "cavium,pci-host-thunder-pem" - -- reg : Two entries: First the configuration space for down - stream devices base address and size, as accessed - from the parent bus. Second, the register bank of - the PEM device PCIe bridge. - -Example: - - pci@87e0,c2000000 { - compatible = "cavium,pci-host-thunder-pem"; - device_type = "pci"; - msi-parent = <&its>; - msi-map = <0 &its 0x10000 0x10000>; - bus-range = <0x8f 0xc7>; - #size-cells = <2>; - #address-cells = <3>; - - reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */ - <0x87e0 0xc2000000 0x0 0x00010000>; /* PEM space */ - ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */ - <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */ - <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */ - <0x03000000 0x87e0 0xc2f00000 0x87e0 0xc2000000 0x00 0x00100000>; /* mem64 PEM BAR4 */ - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */ - <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */ - <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */ - <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */ - }; diff --git a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt deleted file mode 100644 index f3f75bfb42bc..000000000000 --- a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt +++ /dev/null @@ -1,12 +0,0 @@ -* PLDA XpressRICH3-AXI host controller - -The PLDA XpressRICH3-AXI host controller can be configured in a manner that -makes it compliant with the SBSA[1] standard published by ARM Ltd. For those -scenarios, the host-generic-pci.txt bindings apply with the following additions -to the compatible property: - -Required properties: - - compatible: should contain "plda,xpressrich3-axi" to identify the IP used. - - -[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0029a/ diff --git a/MAINTAINERS b/MAINTAINERS index b55f9dd7c47a..d13924690259 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12613,7 +12613,7 @@ M: Will Deacon L: linux-pci@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: Documentation/devicetree/bindings/pci/host-generic-pci.txt +F: Documentation/devicetree/bindings/pci/host-generic-pci.yaml F: drivers/pci/controller/pci-host-common.c F: drivers/pci/controller/pci-host-generic.c