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[176.92.167.70]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dcda28cbcesm1107191a12.43.2025.02.04.23.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 23:17:28 -0800 (PST) From: Ilias Apalodimas To: xypron.glpk@gmx.de, trini@konsulko.com Cc: Ilias Apalodimas , Jerome Forissier , Alexey Brodkin , Eugeniy Paltsev , Caleb Connolly , Neil Armstrong , Sumit Garg , Huan Wang , Angelo Dureghello , Thomas Chou , Rick Chen , Leo , Marek Vasut , Nobuhiro Iwamatsu , Max Filippov , Sughosh Ganu , Simon Glass , =?utf-8?q?Pierre-Cl=C3=A9ment_Tosi?= , Sam Protsenko , Peng Fan , Richard Henderson , Sam Edwards , Peter Hoyes , Andre Przywara , Patrick Rudolph , Sam Day , Mayuresh Chitale , Mattijs Korpershoek , Stefan Roese , Jagan Teki , Alex Shumsky , Jiaxun Yang , Joshua Watt , Evgeny Bachinin , Rasmus Villemoes , Michal Simek , Christian Marangi , Jonas Jelonek , uboot-snps-arc@synopsys.com, u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH v1 1/6] meminfo: add memory details for armv8 Date: Wed, 5 Feb 2025 09:16:45 +0200 Message-ID: <20250205071714.635518-2-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250205071714.635518-1-ilias.apalodimas@linaro.org> References: <20250205071714.635518-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 05 Feb 2025 14:15:26 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Upcoming patches are mapping memory with RO, RW^X etc permsissions. Fix the meminfo command to display them properly Acked-by: Jerome Forissier Signed-off-by: Ilias Apalodimas --- arch/arm/cpu/armv8/cache_v8.c | 26 +++++++++++++++++++++++--- arch/arm/include/asm/armv8/mmu.h | 2 ++ cmd/meminfo.c | 5 +++++ 3 files changed, 30 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 5d6953ffedd1..c4b3da4a8da7 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -421,7 +421,7 @@ static int count_ranges(void) return count; } -#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK) +#define ALL_ATTRS (3 << 8 | PMD_ATTRMASK) #define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3) enum walker_state { @@ -568,6 +568,20 @@ static void pretty_print_table_attrs(u64 pte) static void pretty_print_block_attrs(u64 pte) { u64 attrs = pte & PMD_ATTRINDX_MASK; + u64 perm_attrs = pte & PMD_ATTRMASK; + char mem_attrs[16] = { 0 }; + int cnt = 0; + + if (perm_attrs & PTE_BLOCK_PXN) + cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "PXN "); + if (perm_attrs & PTE_BLOCK_UXN) + cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "UXN "); + if (perm_attrs & PTE_BLOCK_RO) + cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "RO"); + if (!mem_attrs[0]) + snprintf(mem_attrs, sizeof(mem_attrs), "RWX "); + + printf(" | %-10s", mem_attrs); switch (attrs) { case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE): @@ -613,6 +627,7 @@ static void print_pte(u64 pte, int level) { if (PTE_IS_TABLE(pte, level)) { printf(" %-5s", "Table"); + printf(" %-12s", "|"); pretty_print_table_attrs(pte); } else { pretty_print_pte_type(pte); @@ -642,9 +657,9 @@ static bool pagetable_print_entry(u64 start_attrs, u64 end, int va_bits, int lev printf("%*s", indent * 2, ""); if (PTE_IS_TABLE(start_attrs, level)) - printf("[%#011llx]%14s", _addr, ""); + printf("[%#016llx]%19s", _addr, ""); else - printf("[%#011llx - %#011llx]", _addr, end); + printf("[%#016llx - %#016llx]", _addr, end); printf("%*s | ", (3 - level) * 2, ""); print_pte(start_attrs, level); @@ -1112,3 +1127,8 @@ void __weak enable_caches(void) icache_enable(); dcache_enable(); } + +void arch_dump_mem_attrs(void) +{ + dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL)); +} diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 0ab681c893d3..6af8cd111a44 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -66,6 +66,7 @@ #define PTE_BLOCK_NG (1 << 11) #define PTE_BLOCK_PXN (UL(1) << 53) #define PTE_BLOCK_UXN (UL(1) << 54) +#define PTE_BLOCK_RO (UL(1) << 7) /* * AttrIndx[2:0] @@ -75,6 +76,7 @@ #define PMD_ATTRMASK (PTE_BLOCK_PXN | \ PTE_BLOCK_UXN | \ PMD_ATTRINDX_MASK | \ + PTE_BLOCK_RO | \ PTE_TYPE_VALID) /* diff --git a/cmd/meminfo.c b/cmd/meminfo.c index 5e83d61c2dd3..3915e2bbb268 100644 --- a/cmd/meminfo.c +++ b/cmd/meminfo.c @@ -15,6 +15,10 @@ DECLARE_GLOBAL_DATA_PTR; +void __weak arch_dump_mem_attrs(void) +{ +} + static void print_region(const char *name, ulong base, ulong size, ulong *uptop) { ulong end = base + size; @@ -54,6 +58,7 @@ static int do_meminfo(struct cmd_tbl *cmdtp, int flag, int argc, puts("DRAM: "); print_size(gd->ram_size, "\n"); + arch_dump_mem_attrs(); if (!IS_ENABLED(CONFIG_CMD_MEMINFO_MAP)) return 0; From patchwork Wed Feb 5 07:16:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 862165 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp800079wrx; Wed, 5 Feb 2025 05:16:14 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUoFQYCdlIGTObbmoGs+naupIRl2ucVPj0+2MGX7GUEM2I1pdziZbjEr/coUHpB/E3Oqqfk9w==@linaro.org X-Google-Smtp-Source: AGHT+IFu1+z9r1znrgyOtC5djGM/A/5KgsA/b7zcISxxwY2ObyPK9e2PulglGuebfEnIx09/ji0n X-Received: by 2002:a17:907:9717:b0:a9a:9df:5580 with SMTP id a640c23a62f3a-ab75e25cb6dmr252563166b.19.1738761373866; Wed, 05 Feb 2025 05:16:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738761373; cv=none; d=google.com; s=arc-20240605; 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[176.92.167.70]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dcda28cbcesm1107191a12.43.2025.02.04.23.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 23:17:34 -0800 (PST) From: Ilias Apalodimas To: xypron.glpk@gmx.de, trini@konsulko.com Cc: Ilias Apalodimas , Alexey Brodkin , Eugeniy Paltsev , Caleb Connolly , Neil Armstrong , Sumit Garg , Huan Wang , Angelo Dureghello , Thomas Chou , Rick Chen , Leo , Marek Vasut , Nobuhiro Iwamatsu , Max Filippov , Sughosh Ganu , Simon Glass , Sam Protsenko , Jerome Forissier , Peng Fan , Richard Henderson , Sam Edwards , Andre Przywara , Peter Hoyes , Patrick Rudolph , Sam Day , Mayuresh Chitale , Mattijs Korpershoek , Stefan Roese , Jiaxun Yang , Alex Shumsky , Jagan Teki , Joshua Watt , Evgeny Bachinin , Peter Robinson , Christian Marangi , Michal Simek , Jonas Jelonek , uboot-snps-arc@synopsys.com, u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH v1 2/6] doc: update meminfo with arch specific information Date: Wed, 5 Feb 2025 09:16:46 +0200 Message-ID: <20250205071714.635518-3-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250205071714.635518-1-ilias.apalodimas@linaro.org> References: <20250205071714.635518-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 05 Feb 2025 14:15:26 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Since we added support in meminfo to dump live page tables, describe the only working architecture for now (aarch64) and add links to public documentation for further reading. Signed-off-by: Ilias Apalodimas --- doc/usage/cmd/meminfo.rst | 71 +++++++++++++++++++++++++++++---------- 1 file changed, 53 insertions(+), 18 deletions(-) diff --git a/doc/usage/cmd/meminfo.rst b/doc/usage/cmd/meminfo.rst index 6c94493cccc6..cf123f653059 100644 --- a/doc/usage/cmd/meminfo.rst +++ b/doc/usage/cmd/meminfo.rst @@ -18,7 +18,8 @@ Description The meminfo command shows the amount of memory. If ``CONFIG_CMD_MEMINFO_MAP`` is enabled, then it also shows the layout of memory used by U-Boot and the region -which is free for use by images. +which is free for use by images. In architectures that support it, it also prints +the mapped pages and their permissions. The latter is architecture specific. The layout of memory is set up before relocation, within the init sequence in ``board_init_f()``, specifically the various ``reserve_...()`` functions. This @@ -26,8 +27,9 @@ The layout of memory is set up before relocation, within the init sequence in ending with the stack. This results in the maximum possible amount of memory being left free for image-loading. -The meminfo command writes the DRAM size, then the rest of its outputs in 5 -columns: +The meminfo command writes the DRAM size. If the architecture supports it +(currently only aarch64) dumps the page table entries and then the rest of +its outputs in 5 columns: Region Name of the region @@ -99,28 +101,61 @@ free Free memory, which is available for loading images. The base address of this is ``gd->ram_base`` which is generally set by ``CFG_SYS_SDRAM_BASE``. +Aarch64 specific flags +---------------------- + +More information on the output can be found +Chapter D8 - The AArch64 Virtual Memory System Architecture at +https://developer.arm.com/documentation/ddi0487/latest/ + +In short, for a stage 1 translation regime the following apply: + +* RWX: Pages mapped with Read, Write and Execute permissions +* RO: Pages mapped with Read-Only permissions +* PXN: PXN (Privileged Execute Never) applies to execution at EL1 and above +* UXN: UXN (Unprivileged Execute Never) applies to EL0 + Example ------- This example shows output with both ``CONFIG_CMD_MEMINFO`` and -``CONFIG_CMD_MEMINFO_MAP`` enabled:: - - => meminfo - DRAM: 256 MiB +``CONFIG_CMD_MEMINFO_MAP`` enabled for aarch64 qemu:: + + DRAM: 8 GiB + Walking pagetable at 000000023ffe0000, va_bits: 40. Using 4 levels + [0x0000023ffe1000] | Table | | | + [0x0000023ffe2000] | Table | | | + [0x00000000000000 - 0x00000008000000] | Block | RWX | Normal | Inner-shareable + [0x00000008000000 - 0x00000040000000] | Block | PXN UXN | Device-nGnRnE | Non-shareable + [0x00000040000000 - 0x00000200000000] | Block | RWX | Normal | Inner-shareable + [0x0000023ffea000] | Table | | | + [0x00000200000000 - 0x0000023f600000] | Block | RWX | Normal | Inner-shareable + [0x0000023ffeb000] | Table | | | + [0x0000023f600000 - 0x0000023f68c000] | Pages | RWX | Normal | Inner-shareable + [0x0000023f68c000 - 0x0000023f74f000] | Pages | RO | Normal | Inner-shareable + [0x0000023f74f000 - 0x0000023f794000] | Pages | PXN UXN RO | Normal | Inner-shareable + [0x0000023f794000 - 0x0000023f79d000] | Pages | PXN UXN | Normal | Inner-shareable + [0x0000023f79d000 - 0x0000023f800000] | Pages | RWX | Normal | Inner-shareable + [0x0000023f800000 - 0x00000240000000] | Block | RWX | Normal | Inner-shareable + [0x00000240000000 - 0x00004000000000] | Block | RWX | Normal | Inner-shareable + [0x0000023ffe3000] | Table | | | + [0x00004010000000 - 0x00004020000000] | Block | PXN UXN | Device-nGnRnE | Non-shareable + [0x0000023ffe4000] | Table | | | + [0x00008000000000 - 0x00010000000000] | Block | PXN UXN | Device-nGnRnE | Non-shareable Region Base Size End Gap ------------------------------------------------ - video f000000 1000000 10000000 - code ec3a000 3c5d28 efffd28 2d8 - malloc 8c38000 6002000 ec3a000 0 - board_info 8c37f90 68 8c37ff8 8 - global_data 8c37d80 208 8c37f88 8 - devicetree 8c33000 4d7d 8c37d7d 3 - bootstage 8c32c20 3c8 8c32fe8 18 - bloblist 8c32000 400 8c32400 820 - stack 7c31ff0 1000000 8c31ff0 10 - free 0 7c31ff0 7c31ff0 0 - + video 23f7e0000 800000 23ffe0000 + code 23f68a000 156000 23f7e0000 0 + malloc 23e64a000 1040000 23f68a000 0 + board_info 23e649f80 78 23e649ff8 8 + global_data 23e649df0 188 23e649f78 8 + devicetree 23e549df0 100000 23e649df0 0 + bloblist 23e547000 2000 23e549000 df0 + stack 23d546ff0 1000000 23e546ff0 10 + lmb 23d546ff0 0 23d546ff0 0 + lmb 23d543000 3ff0 23d546ff0 0 + free 40000000 23d543000 27d543000 ffffffffc0000000 Return value ------------ From patchwork Wed Feb 5 07:16:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 862166 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp800134wrx; Wed, 5 Feb 2025 05:16:23 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW2k7aElL8Va5lEVB1yrNfpTUJ6wi/ZjYstBUUlUpTfCKUrciiHlPrk5ZXGPX5Gx+Abp+7Xiw==@linaro.org X-Google-Smtp-Source: AGHT+IEMZB3SK/tscZzBb6oQjUqc978JNkfgU73FJvpC0Y8vHbEpeKoP03U3a1mIZKmuNJMpA17D X-Received: by 2002:a17:907:94c7:b0:ab6:f4e0:320a with SMTP id a640c23a62f3a-ab75e265100mr263719166b.21.1738761382942; Wed, 05 Feb 2025 05:16:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738761382; cv=none; d=google.com; s=arc-20240605; b=igrQ6UUf+8jommcHbWvBOuA2dZXhSVs58zp+InVquUQuG4sZIs9KqgcGQ3HL0jG1S3 bAB7Nge9D+rlFWHL6h1Qny+hwbJjaTNPEfsC6+IFOcr/IJNygOqDB3K/DXI+lwv1GALV Styn+FkgzBTRCwXOmf4/fUjmWMjT2XPn+mCvv7gzd2wxRw2dm8qL/2Rta9lKKaHJ3T49 g5OFs/cAlTL2Ck+Ky13EQ/IFnBi5TsTG3IIGyH+Wu4oKaOto/69Z5ocjBaABb0QjfLp+ /qjQiteoo61GszefiiFyrcRkmNd8VDl7pQZcyXBpC1yB6Ib/GrQI2JbpPIjvyXhssO7z xR+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=VUGPK86DWi9+WCYvLPgrYc5wTB8ycSj3VW2D0BfVeDA=; fh=5VI7fLN8pcuuzyzNF8Z0obiI6F8I7YIaqhS+91Jv8PU=; b=k+r87rMVZpZoY6atrJ+0TiJ2R6UouEL95AJMQUkiprA7hVZdMco5VthLBx/v71x0iy PptqfaW0Dezdlbh/BqvH2XvQOILdKw92TqXoFbWd91OzK1K7JvRIIVUgkJKSxqVcmbiu YYKgcwkW/dRzwvpTP1HJXD0WQZ92nunvm1cAyHC9cW6xp12HsgSdQqbIlHT8kXMUX7aV lfHTYamh760igYs0GLGyT29AYNW4YCOA5+ESe0AVMxBh8ppTk2NRCtcODNdmeGseMQby DG7OjjIyLRh4/x6V0H3ri9+pamvgSmr2+n+9tq1SnuWwSHLLO5ZLF8XW2TlmiS8M+g00 qDcQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="khl/pd3i"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[176.92.167.70]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dcda28cbcesm1107191a12.43.2025.02.04.23.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 23:17:42 -0800 (PST) From: Ilias Apalodimas To: xypron.glpk@gmx.de, trini@konsulko.com Cc: Ilias Apalodimas , Jerome Forissier , Alexey Brodkin , Eugeniy Paltsev , Caleb Connolly , Neil Armstrong , Sumit Garg , Huan Wang , Angelo Dureghello , Thomas Chou , Rick Chen , Leo , Marek Vasut , Nobuhiro Iwamatsu , Max Filippov , Simon Glass , Sughosh Ganu , Marc Zyngier , Sam Protsenko , =?utf-8?q?Pierre-Cl=C3=A9ment_Tosi?= , Peng Fan , Richard Henderson , Sam Edwards , Andre Przywara , Peter Hoyes , Patrick Rudolph , Sam Day , Mayuresh Chitale , Mattijs Korpershoek , Stefan Roese , Joshua Watt , Jiaxun Yang , Alex Shumsky , Jagan Teki , Evgeny Bachinin , Rasmus Villemoes , Christian Marangi , Michal Simek , Jonas Jelonek , uboot-snps-arc@synopsys.com, u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH v1 3/6] arm: Prepare linker scripts for memory permissions Date: Wed, 5 Feb 2025 09:16:47 +0200 Message-ID: <20250205071714.635518-4-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250205071714.635518-1-ilias.apalodimas@linaro.org> References: <20250205071714.635518-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 05 Feb 2025 14:15:26 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Upcoming patches are switching the memory mappings to RW, RO, RX after the U-Boot binary and its data are relocated. Add annotations in the linker scripts to and mark text, data, rodata sections and align them to a page boundary. It's worth noting that efi_runtime relocations are left untouched for now. The efi runtime regions can be relocated by the OS when the latter is calling SetVirtualAddressMap. Which means we have to configure the pages as RX for U-Boot but convert them to RWX just before ExitBootServices. It also needs extra code in efi_tuntime relocation code since R_AARCH64_NONE are emitted as well if we page align the section. Keep it out for now and we can fix it in future patches. Acked-by: Jerome Forissier Signed-off-by: Ilias Apalodimas --- arch/arm/cpu/armv8/u-boot.lds | 29 +++++++++++++++++------------ include/asm-generic/sections.h | 2 ++ 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index 857f44412e07..35afc3cbe7ec 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -22,7 +22,7 @@ SECTIONS . = ALIGN(8); __image_copy_start = ADDR(.text); - .text : + .text ALIGN(4096): { CPUDIR/start.o (.text*) } @@ -36,9 +36,12 @@ SECTIONS __efi_runtime_stop = .; } - .text_rest : + .text_rest ALIGN(4096) : { + __text_start = .; *(.text*) + . = ALIGN(4096); + __text_end = .; } #ifdef CONFIG_ARMV8_PSCI @@ -98,18 +101,20 @@ SECTIONS } #endif - . = ALIGN(8); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + .rodata ALIGN(4096): { + __start_rodata = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4096); + __end_rodata = .; + } - . = ALIGN(8); - .data : { + .data ALIGN(4096) : { + __start_data = .; *(.data*) + . = ALIGN(4096); + __end_data = .; } - . = ALIGN(8); - - . = .; - . = ALIGN(8); __u_boot_list : { KEEP(*(SORT(__u_boot_list*))); @@ -136,10 +141,10 @@ SECTIONS /* * arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0 */ - .bss ALIGN(8) : { + .bss ALIGN(4096) : { __bss_start = .; *(.bss*) - . = ALIGN(8); + . = ALIGN(4096); __bss_end = .; } diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 3fd5c772a1af..024b1adde270 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -23,6 +23,7 @@ extern char __kprobes_text_start[], __kprobes_text_end[]; extern char __entry_text_start[], __entry_text_end[]; extern char __initdata_begin[], __initdata_end[]; extern char __start_rodata[], __end_rodata[]; +extern char __start_data[], __end_data[]; extern char __efi_helloworld_begin[]; extern char __efi_helloworld_end[]; extern char __efi_var_file_begin[]; @@ -63,6 +64,7 @@ static inline int arch_is_kernel_data(unsigned long addr) /* Start of U-Boot text region */ extern char __text_start[]; +extern char __text_end[]; /* This marks the text region which must be relocated */ extern char __image_copy_start[], __image_copy_end[]; From patchwork Wed Feb 5 07:16:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 862167 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp800195wrx; Wed, 5 Feb 2025 05:16:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVDkXIadlkTO+2/o9oetkG8pNve+tUAgwDtZkRlVvVOczk8FHAmB2B6qL37f9jG+huSh9vOoA==@linaro.org X-Google-Smtp-Source: AGHT+IGybGvX6qRb2k9I4tQ+S4XCGFYFhJbyzPh90Exu1ErLIgZVaXdQMnDG7qOmdc8IIVobmvN1 X-Received: by 2002:a05:6402:1d49:b0:5d0:d9e6:fea1 with SMTP id 4fb4d7f45d1cf-5dcdb756dbfmr3869087a12.19.1738761391955; Wed, 05 Feb 2025 05:16:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738761391; cv=none; d=google.com; s=arc-20240605; b=Tm+1u7GgVuC2lxWuBqKdLkpve99w3Iu/Inr1zLY8z+sWceIwMvCxQy+ZC3htWaR2gp j5tLNpMxMaf6h9G1u2HMOuWcXRPVOkCVj7N5nKv8R48r4uwbcK0vMY6kj40OmQ0nQori 11hwKKLz85E21yDwR7LUsVqG449AqGfyxAPXOQp/aeQgIxj0UCiImO15WScrFXqBiLjk hkjCiTzR1m6KXNyfBCMTmOlc7Dofjlgr/uwitct/O7kEqzpLY/XiMRw3wwC21YP3AXIV gdFQcLq1XT9Zy/lyakKGH7+p4MP2REjsDO+zQbf5URCE1d+uXL2RFssLK8woT91bjbg+ 0hYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5vMO6iN3NnCiRZ5O772lxPg+OODwikPNOb2/pBTuVKo=; fh=2o9IzM8p6Mwctt73DVWd6I6ACu7L/PB9OXeB+1CCS9g=; b=hxiVFHmDojWR8Jpi/CVBSVTFTCLX0Oa/I9/STtQPSa3K8tgN+l4Q4T2odqe5zhy6Rv BEj8hC4KMevIEjD1uTaRL8zTKP6inxn7WreV8ApeZZan9Dwa7g0z2US0uTRqXKYwVnOI L+IBC0yWhXegF40F2B4syJtmjuguoasR1UuhanueHG3yEsNYyfpLLMoCYZLpTiTFMd14 0/7MNfpo68UE9YwXlOdfINTMjvM4dbGgjOdTFjYFzfrADHWqYlytke0w6kFggmCGe4r5 kGNVoYaA1gKXlxh6WqqXwhai6Pwj8I0IlDwhTKowyXgifro5aShO/3VRz5wouz0BhVOs ONSw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x9K0qMH2; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[176.92.167.70]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dcda28cbcesm1107191a12.43.2025.02.04.23.17.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 23:17:48 -0800 (PST) From: Ilias Apalodimas To: xypron.glpk@gmx.de, trini@konsulko.com Cc: Ilias Apalodimas , Alexey Brodkin , Eugeniy Paltsev , Caleb Connolly , Neil Armstrong , Sumit Garg , Huan Wang , Angelo Dureghello , Thomas Chou , Rick Chen , Leo , Marek Vasut , Nobuhiro Iwamatsu , Max Filippov , Sughosh Ganu , Simon Glass , Sam Protsenko , =?utf-8?q?Pierre-Cl=C3=A9ment_T?= =?utf-8?q?osi?= , Marc Zyngier , Peng Fan , Richard Henderson , Sam Edwards , Jerome Forissier , Peter Hoyes , Andre Przywara , Patrick Rudolph , Sam Day , Mayuresh Chitale , Mattijs Korpershoek , Stefan Roese , Jiaxun Yang , Alex Shumsky , Jagan Teki , Joshua Watt , Evgeny Bachinin , Rasmus Villemoes , Christian Marangi , Michal Simek , Jonas Jelonek , uboot-snps-arc@synopsys.com, u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH v1 4/6] arm64: mmu_change_region_attr() add an option not to break PTEs Date: Wed, 5 Feb 2025 09:16:48 +0200 Message-ID: <20250205071714.635518-5-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250205071714.635518-1-ilias.apalodimas@linaro.org> References: <20250205071714.635518-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 05 Feb 2025 14:15:26 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The ARM ARM on section 8.17.1 describes the cases where break-before-make is required when changing live page tables. Since we can use this function to tweak block and page permssions, where BBM is not required add an extra argument to the function. While at it add a function description. Signed-off-by: Ilias Apalodimas --- arch/arm/cpu/armv8/cache_v8.c | 6 +++++- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 10 +++++----- arch/arm/include/asm/system.h | 11 ++++++++++- arch/arm/mach-snapdragon/board.c | 2 +- 4 files changed, 21 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c4b3da4a8da7..670379e17b7a 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -972,11 +972,14 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, * The procecess is break-before-make. The target region will be marked as * invalid during the process of changing. */ -void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) +void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs, bool bbm) { int level; u64 r, size, start; + if (!bbm) + goto skip_break; + start = addr; size = siz; /* @@ -1001,6 +1004,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) gd->arch.tlb_addr + gd->arch.tlb_size); __asm_invalidate_tlb_all(); +skip_break: /* * Loop through the address range until we find a page granule that fits * our alignment constraints, then set it to the new cache attributes diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d2d3e346a36f..caf1dab05936 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1573,7 +1573,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); } else { mmu_change_region_attr( CFG_SYS_SDRAM_BASE, @@ -1581,7 +1581,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); #ifdef CONFIG_SYS_DDR_BLOCK3_BASE #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" @@ -1594,7 +1594,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); mmu_change_region_attr( CONFIG_SYS_DDR_BLOCK3_BASE, gd->ram_size - @@ -1603,7 +1603,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); } else #endif { @@ -1614,7 +1614,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); } } } diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index dbf9ab43e280..f84bffe9d4fb 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -287,7 +287,16 @@ void flush_l3_cache(void); * @emerg: Also map the region in the emergency table */ void mmu_map_region(phys_addr_t start, u64 size, bool emerg); -void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); + +/** + * mmu_change_region_attr() - change a mapped region attributes + * + * @start: Start address of the region + * @size: Size of the region + * @aatrs: New attributes + * @bbm: Perform a break-before-make on the page tables entries + */ +void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs, bool bbm); /* * smc_call() - issue a secure monitor call diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 2ef936aab757..13f4e8e640ef 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -577,7 +577,7 @@ static void carve_out_reserved_memory(void) if (i == count || start + size < res[i].start - SZ_2M) { debug(" 0x%016llx - 0x%016llx: reserved\n", start, start + size); - mmu_change_region_attr(start, size, PTE_TYPE_FAULT); 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[176.92.167.70]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dcda28cbcesm1107191a12.43.2025.02.04.23.17.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 23:17:55 -0800 (PST) From: Ilias Apalodimas To: xypron.glpk@gmx.de, trini@konsulko.com Cc: Ilias Apalodimas , Alexey Brodkin , Eugeniy Paltsev , Caleb Connolly , Neil Armstrong , Sumit Garg , Huan Wang , Angelo Dureghello , Thomas Chou , Rick Chen , Leo , Marek Vasut , Nobuhiro Iwamatsu , Max Filippov , Simon Glass , Sughosh Ganu , Sam Protsenko , =?utf-8?q?Pierre-Cl=C3=A9ment_T?= =?utf-8?q?osi?= , Peng Fan , Richard Henderson , Sam Edwards , Jerome Forissier , Andre Przywara , Peter Hoyes , Patrick Rudolph , Sam Day , Mayuresh Chitale , Mattijs Korpershoek , Stefan Roese , Alex Shumsky , Jiaxun Yang , Joshua Watt , Jagan Teki , Evgeny Bachinin , Peter Robinson , Christian Marangi , Michal Simek , Jonas Jelonek , uboot-snps-arc@synopsys.com, u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH v1 5/6] treewide: Add a function to change page permissions Date: Wed, 5 Feb 2025 09:16:49 +0200 Message-ID: <20250205071714.635518-6-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250205071714.635518-1-ilias.apalodimas@linaro.org> References: <20250205071714.635518-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 05 Feb 2025 14:15:26 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean For armv8 we are adding proper page permissions for the relocated U-Boot binary. Add a weak function that can be used across architectures to change the page permissions Signed-off-by: Ilias Apalodimas --- arch/arc/lib/cache.c | 2 ++ arch/arm/cpu/arm926ejs/cache.c | 2 ++ arch/arm/cpu/armv7/cache_v7.c | 1 + arch/arm/cpu/armv7m/cache.c | 2 ++ arch/arm/cpu/armv8/cache_v8.c | 22 ++++++++++++++++++++++ arch/arm/lib/cache.c | 2 ++ arch/m68k/lib/cache.c | 2 ++ arch/nios2/lib/cache.c | 2 ++ arch/powerpc/lib/cache.c | 2 ++ arch/riscv/lib/cache.c | 2 ++ arch/sh/cpu/sh4/cache.c | 2 ++ arch/xtensa/lib/cache.c | 2 ++ include/cpu_func.h | 16 ++++++++++++++++ 13 files changed, 59 insertions(+) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 5169fc627fa5..5c79243d7223 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -819,3 +819,5 @@ void sync_n_cleanup_cache_all(void) __ic_entire_invalidate(); } + +void __weak pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) {} diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 5b87a3af91b2..857311b3dfad 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -88,3 +88,5 @@ void enable_caches(void) dcache_enable(); #endif } + +void __weak pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) {} diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index d11420d2fdd0..14c9be77db8d 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -209,3 +209,4 @@ __weak void v7_outer_cache_flush_all(void) {} __weak void v7_outer_cache_inval_all(void) {} __weak void v7_outer_cache_flush_range(u32 start, u32 end) {} __weak void v7_outer_cache_inval_range(u32 start, u32 end) {} +__weak void pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) {} diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c index b6d08b7aad73..458a214e9577 100644 --- a/arch/arm/cpu/armv7m/cache.c +++ b/arch/arm/cpu/armv7m/cache.c @@ -370,3 +370,5 @@ void enable_caches(void) dcache_enable(); #endif } + +void __weak pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) {} diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 670379e17b7a..1cf3870177ee 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -1028,6 +1028,28 @@ skip_break: __asm_invalidate_tlb_all(); } +void pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) +{ + u64 attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE | PTE_TYPE_VALID; + + switch (perm) { + case MMU_ATTR_RO: + attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_RO; + break; + case MMU_ATTR_RX: + attrs |= PTE_BLOCK_RO; + break; + case MMU_ATTR_RW: + attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN; + break; + default: + log_err("Unknown attribute %llx\n", perm); + return; + } + + mmu_change_region_attr(addr, size, attrs, false); +} + #else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ /* diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 516754caeaf9..c7704d8ee354 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -170,3 +170,5 @@ __weak int arm_reserve_mmu(void) return 0; } + +void __weak pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) {} diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c index 370ad40f1423..b275646384a5 100644 --- a/arch/m68k/lib/cache.c +++ b/arch/m68k/lib/cache.c @@ -151,3 +151,5 @@ __weak void flush_dcache_range(unsigned long start, unsigned long stop) { /* An empty stub, real implementation should be in platform code */ } + +void __weak pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) {} diff --git a/arch/nios2/lib/cache.c b/arch/nios2/lib/cache.c index 8f543f2a2f26..7a93a8fcc6a7 100644 --- a/arch/nios2/lib/cache.c +++ b/arch/nios2/lib/cache.c @@ -127,3 +127,5 @@ void dcache_disable(void) { flush_dcache_all(); } + +void __weak pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) {} diff --git a/arch/powerpc/lib/cache.c b/arch/powerpc/lib/cache.c index a9cd7b8d30ac..3d0536caccde 100644 --- a/arch/powerpc/lib/cache.c +++ b/arch/powerpc/lib/cache.c @@ -58,3 +58,5 @@ void invalidate_icache_all(void) { puts("No arch specific invalidate_icache_all available!\n"); } + +void __weak pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) {} diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 71e4937ab542..1c751e562157 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -151,3 +151,5 @@ __weak void enable_caches(void) if (!zicbom_block_size) log_debug("Zicbom not initialized.\n"); } + +void __weak pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) {} diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index 99acc5999652..22e0f1484a33 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -126,3 +126,5 @@ int dcache_status(void) { return 0; } + +void __weak pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) {} diff --git a/arch/xtensa/lib/cache.c b/arch/xtensa/lib/cache.c index e6a7f6827fc2..aacc2d2627d6 100644 --- a/arch/xtensa/lib/cache.c +++ b/arch/xtensa/lib/cache.c @@ -57,3 +57,5 @@ void invalidate_icache_all(void) { __invalidate_icache_all(); } + +void __weak pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm) {} diff --git a/include/cpu_func.h b/include/cpu_func.h index 7e81c4364a73..17b6d199302a 100644 --- a/include/cpu_func.h +++ b/include/cpu_func.h @@ -69,6 +69,22 @@ void flush_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_all(void); void invalidate_icache_all(void); + +enum pgprot_attrs { + MMU_ATTR_RO, + MMU_ATTR_RX, + MMU_ATTR_RW, +}; + +/** pgprot_set_attrs() - Set page table permissions + * + * @addr: Physical address start + * @size: size of memory to change + * @perm: New permissions + * + **/ +void pgprot_set_attrs(phys_addr_t addr, size_t size, u64 perm); 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[176.92.167.70]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dcda28cbcesm1107191a12.43.2025.02.04.23.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 23:18:02 -0800 (PST) From: Ilias Apalodimas To: xypron.glpk@gmx.de, trini@konsulko.com Cc: Ilias Apalodimas , Alexey Brodkin , Eugeniy Paltsev , Caleb Connolly , Neil Armstrong , Sumit Garg , Huan Wang , Angelo Dureghello , Thomas Chou , Rick Chen , Leo , Marek Vasut , Nobuhiro Iwamatsu , Max Filippov , Sughosh Ganu , Simon Glass , =?utf-8?q?Pierre-Cl=C3=A9ment_Tosi?= , Sam Protsenko , Peng Fan , Richard Henderson , Sam Edwards , Jerome Forissier , Andre Przywara , Peter Hoyes , Patrick Rudolph , Sam Day , Mayuresh Chitale , Mattijs Korpershoek , Stefan Roese , Jiaxun Yang , Joshua Watt , Alex Shumsky , Jagan Teki , Evgeny Bachinin , Christian Marangi , Peter Robinson , Michal Simek , Jonas Jelonek , uboot-snps-arc@synopsys.com, u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH v1 6/6] arm64: Enable RW, RX and RO mappings for the relocated binary Date: Wed, 5 Feb 2025 09:16:50 +0200 Message-ID: <20250205071714.635518-7-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250205071714.635518-1-ilias.apalodimas@linaro.org> References: <20250205071714.635518-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 05 Feb 2025 14:15:26 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Now that we have everything in place switch the page permissions for .rodata, .text and .data just after we relocate everything in top of the RAM. Unfortunately we can't enable this by default, since we have examples of U-Boot crashing due to invalid access. This usually happens because code defines const variables that it later writes. So hide it behind a Kconfig option until we sort it out. It's worth noting that EFI runtime services are not covered by this patch on purpose. Since the OS can call SetVirtualAddressMap which can relocate runtime services, we need to set them to RX initially but remap them as RWX right before ExitBootServices. Link: https://lore.kernel.org/u-boot/20250129-rockchip-pinctrl-const-v1-0-450ccdadfa7e@cherry.de/ Link: https://lore.kernel.org/u-boot/20250130133646.2177194-1-andre.przywara@arm.com/ Signed-off-by: Ilias Apalodimas Reviewed-by: Jerome Forissier --- common/Kconfig | 13 +++++++++++++ common/board_r.c | 20 ++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/common/Kconfig b/common/Kconfig index 7685914fa6fd..dbae7e062b0a 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -914,6 +914,19 @@ config STACKPROTECTOR Enable stack smash detection through compiler's stack-protector canary logic +config MMU_PGPROT + bool "Enable RO, RW and RX mappings" + help + U-Boot maps all pages as RWX. If selected pages will + be marked as RO(.rodata), RX(.text), RW(.data) right after + we relocate. Since code sections needs to be page aligned + the final binary size will increase. + The mapping can be dumped using the 'meminfo' command. + We should make this default 'y' in the future, but currently + we have code defining const variables that are later written. + Enabling this will crash U-Boot if that code path runs, so keep + it off by default until we fix invalid accesses. + config SPL_STACKPROTECTOR bool "Stack Protector buffer overflow detection for SPL" depends on STACKPROTECTOR && SPL diff --git a/common/board_r.c b/common/board_r.c index 179259b00de8..c1e9aa46e3fa 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -170,7 +170,27 @@ static int initr_reloc_global_data(void) efi_save_gd(); efi_runtime_relocate(gd->relocaddr, NULL); + #endif + /* + * We are done with all relocations change the permissions of the binary + * NOTE: __start_rodata etc are defined in arm64 linker scripts and + * sections.h. If you want to add support for your platform you need to + * add the symbols on your linker script, otherwise they will point to + * random addresses. + * + */ + if (IS_ENABLED(CONFIG_MMU_PGPROT)) { + pgprot_set_attrs((phys_addr_t)(uintptr_t)(__start_rodata), + (phys_addr_t)(uintptr_t)(__end_rodata - __start_rodata), + MMU_ATTR_RO); + pgprot_set_attrs((phys_addr_t)(uintptr_t)(__start_data), + (phys_addr_t)(uintptr_t)(__end_data - __start_data), + MMU_ATTR_RW); + pgprot_set_attrs((phys_addr_t)(uintptr_t)(__text_start), + (phys_addr_t)(uintptr_t)(__text_end - __text_start), + MMU_ATTR_RX); + } return 0; }