From patchwork Fri Feb 7 10:27:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 862975 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp245150wrt; Fri, 7 Feb 2025 02:29:41 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXJ8syYgScWflM+8chKnELt2GQRZJ5//cMtk36XMgYVXTQV3LyLMSwyfojOdR+P+IxnBNRiZg==@linaro.org X-Google-Smtp-Source: AGHT+IHVDArg1vJPiq/7kTge0SocAUSbiL9Q+Eegi0t6Guk00h2RJtX2S3TDdbtvZifpgfNXHBCb X-Received: by 2002:a05:620a:298e:b0:7b1:1180:a455 with SMTP id af79cd13be357-7c047bbab72mr309404285a.22.1738924180828; Fri, 07 Feb 2025 02:29:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738924180; cv=none; d=google.com; s=arc-20240605; b=W/piZtR+dS12YJ9UgMB3fHGaxrQ7tg4G0eUxdj/NJY3DYm/VDbPrmRl3Z5Z2qdyhK8 RuCotREcoTgZ24yl5jWjgJUKEN0IVC5oB2m2VP3JNdAiKYNE4m9dQZtvzdXwRAUjlsMl tQt1VXIxRfmfYyg9ZeEiV1/U+PsErqlD4H7MrhvgIaXoqZCPeYfZG2O3RqeGinaVLqV5 sYYkb7csXfEDyidJx0b7CtTEfe3ZV7m11o3TeOg4TQAR5A96czZWpmZA/9+DUxyb11m5 NplVOIh5SSukGI8b07+EYthEzaRwaBjm/wFhjO6Na2753sroFaIxWQwkfunOYQ0Cc+5e cFuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=33vv0LTRkoa8007dZV9o44ZqrRUf3Wofq/Zn2BVSNwk=; fh=uPW6WSpdOYSnzV7QidTRWeV51Hb4eOtHu9B8J/jMDd4=; b=WjrTnzU0zJDtv6CAJ0Xm/YTYrLmgIrdAn+U8d8XgDW9WbOJpbzhXPRF6YkmEfgK0qe 1hS+jOy0G/SEQK0M2ddiAVuD0/41UiHvOEX5b/wMnEMvFsOd65hU0KfAcsqkzyHEIJon 65eB2FQ68r3mkQINh6GgQOal+iCXYABqCfhmNepWXHwMVar5ItAcyjFQ//8g6jvNgv+/ YhzsYNu/0CfMXpjukJkhnVOa+eyzESc886vM2gfhn/3pe82sb0QTZpr9WK1tCHSgFH97 QWEoFxW2Jvz2uxU+dabARHfNZVsePttRp6dqvyl4oijgEvPwW8gwZLip7sk1xXvjYqOH b/aw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=K1p1Yf2A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7c041e94d3asi294589185a.248.2025.02.07.02.29.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Feb 2025 02:29:40 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=K1p1Yf2A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tgLbA-0005tf-QZ; Fri, 07 Feb 2025 05:28:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tgLb3-0005rP-WC for qemu-devel@nongnu.org; Fri, 07 Feb 2025 05:28:30 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tgLb2-0008Ej-Af for qemu-devel@nongnu.org; Fri, 07 Feb 2025 05:28:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1738924107; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=33vv0LTRkoa8007dZV9o44ZqrRUf3Wofq/Zn2BVSNwk=; b=K1p1Yf2AZ8HvKw7qh22QJwuDmL8ukW8pMq86OTwphKMy+6fLpVpx0MHm5NKDuctIHPW5G5 fMteeaxlqYQRW4gNp+94Hm5m1eh+uHRmQfFyL1J1ApcQXhfvQk0uDp+aR6bhtOtQZjj/oT g8MTaTheOQ/SVSx0Tjt09mAlFjf7nLI= Received: from mail-ej1-f69.google.com (mail-ej1-f69.google.com [209.85.218.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-138-N9G2cArxM1mFlsXwjlM7QA-1; Fri, 07 Feb 2025 05:28:26 -0500 X-MC-Unique: N9G2cArxM1mFlsXwjlM7QA-1 X-Mimecast-MFC-AGG-ID: N9G2cArxM1mFlsXwjlM7QA Received: by mail-ej1-f69.google.com with SMTP id a640c23a62f3a-aa689b88293so210736066b.3 for ; Fri, 07 Feb 2025 02:28:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738924104; x=1739528904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=33vv0LTRkoa8007dZV9o44ZqrRUf3Wofq/Zn2BVSNwk=; b=TCtTj0s1aOSXrYiYegyktbcuHo8+HWly7nOzVwwe4ixp2jePrgqB5XckP8ZXerlRff wqy46WnjGkxUhZNPCVFftI+Snj1MbeFMKGdNfvo+gYLKpeVzJFBcEkUuMSefHS3qi4Tc 1fUE6YclDMwOfc3p0K+FYXKm7PiYtlNVMhMIrMazMpYs/+L0nv/4IQLKAtH9AQfRIbC9 olAvjL+WB8KYxTbnLn1n6DKvPCJB8fZTd25s2p9TQsKO7UpytZ7+KkF3eqNZyR76ZBgV Hqqnl5Bf3BzqzJFOgTMs//KaRZMPdQj+elVh4O2PfToTCoyNx9+YwKsmhQbfi1GMSZl4 ga/A== X-Gm-Message-State: AOJu0YzgDLPEi6Y6p5qKqaHHxmCq5oNKYktNVx/zss6zf2jKqC1eJa7E blxlOCmBADPhUx/UkXT1LUAKRM0NT1W96gNC8yL4D17KD04qDMkoxf52PFZPAPdEjFMy+WZ0YWX XZd6ha03795gPlzMf5rUQ1b/1jxeBGXwOH8speZotQivlz8RKbgFU01OPg+HuebcCIXw/V0ZXbG ajw1jOhMRM0qAeJZKrwY+mhUQ7yA7V4pAP3pi0NeM= X-Gm-Gg: ASbGncubPjh3bqfOdWe5/jKcLdi2GE1qj/niPkSD3T1YdG8lQngawuGrJDQcxch1QCs zaXG6LuZ6SofAIhSr0gua70eWJwNWgYZuPElGrQAG8tf4JLe1RPI6gaGhujd02CuN4NfUx6Hws+ yVUf9MSt+qnh1SazDGZY7wAPhKac4ZvE8pX2hHzB4UszuqUOP2oVIyNCUSENja441oXIWJu1OpD gqXZCRPCYJ93uqS15752xn5F4kgV7XeodgtaImTZQg4XTK9FVmqpWaAMxeqgkQ3r1OJ2TtRy/4M zOvvJA== X-Received: by 2002:a17:907:7b06:b0:ab6:eec6:7cab with SMTP id a640c23a62f3a-ab789c3ac8amr290121666b.38.1738924103577; Fri, 07 Feb 2025 02:28:23 -0800 (PST) X-Received: by 2002:a17:907:7b06:b0:ab6:eec6:7cab with SMTP id a640c23a62f3a-ab789c3ac8amr290118366b.38.1738924103085; Fri, 07 Feb 2025 02:28:23 -0800 (PST) Received: from [192.168.10.3] ([151.62.97.55]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab79298641asm19003166b.90.2025.02.07.02.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 02:28:18 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-stable@nongnu.org, Richard Henderson Subject: [PULL 5/7] target/i386: Do not raise Invalid for 0 * Inf + QNaN Date: Fri, 7 Feb 2025 11:27:59 +0100 Message-ID: <20250207102802.2445596-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250207102802.2445596-1-pbonzini@redhat.com> References: <20250207102802.2445596-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell In commit 8adcff4ae7 ("fpu: handle raising Invalid for infzero in pick_nan_muladd") we changed the handling of 0 * Inf + QNaN to always raise the Invalid exception regardless of target architecture. (This was a change affecting hppa, i386, sh4 and tricore.) However, this was incorrect for i386, which documents in the SDM section 14.5.2 that for the 0 * Inf + NaN case that it will only raise the Invalid exception when the input is an SNaN. (This is permitted by the IEEE 754-2008 specification, which documents that whether we raise Invalid for 0 * Inf + QNaN is implementation defined.) Adjust the softfloat pick_nan_muladd code to allow the target to suppress the raising of Invalid for the inf * zero + NaN case (as an extra flag orthogonal to its choice for when to use the default NaN), and enable that for x86. We do not revert here the behaviour change for hppa, sh4 or tricore: * The sh4 manual is clear that it should signal Invalid * The tricore manual is a bit vague but doesn't say it shouldn't * The hppa manual doesn't talk about fused multiply-add corner cases at all Cc: qemu-stable@nongnu.org Fixes: 8adcff4ae7 (""fpu: handle raising Invalid for infzero in pick_nan_muladd") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Link: https://lore.kernel.org/r/20250116112536.4117889-2-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini --- include/fpu/softfloat-types.h | 16 +++++++++++++--- target/i386/tcg/fpu_helper.c | 5 ++++- fpu/softfloat-parts.c.inc | 5 +++-- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 616c290145f..2e43d1dd9e6 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -280,11 +280,21 @@ typedef enum __attribute__((__packed__)) { /* No propagation rule specified */ float_infzeronan_none = 0, /* Result is never the default NaN (so always the input NaN) */ - float_infzeronan_dnan_never, + float_infzeronan_dnan_never = 1, /* Result is always the default NaN */ - float_infzeronan_dnan_always, + float_infzeronan_dnan_always = 2, /* Result is the default NaN if the input NaN is quiet */ - float_infzeronan_dnan_if_qnan, + float_infzeronan_dnan_if_qnan = 3, + /* + * Don't raise Invalid for 0 * Inf + NaN. Default is to raise. + * IEEE 754-2008 section 7.2 makes it implementation defined whether + * 0 * Inf + QNaN raises Invalid or not. Note that 0 * Inf + SNaN will + * raise the Invalid flag for the SNaN anyway. + * + * This is a flag which can be ORed in with any of the above + * DNaN behaviour options. + */ + float_infzeronan_suppress_invalid = (1 << 7), } FloatInfZeroNaNRule; /* diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 3d764bc138d..de6d0b252ec 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -178,8 +178,11 @@ void cpu_init_fp_statuses(CPUX86State *env) * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is * specified -- for 0 * inf + NaN the input NaN is selected, and if * there are multiple input NaNs they are selected in the order a, b, c. + * We also do not raise Invalid for the 0 * inf + (Q)NaN case. */ - set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); + set_float_infzeronan_rule(float_infzeronan_dnan_never | + float_infzeronan_suppress_invalid, + &env->sse_status); set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); /* Default NaN: sign bit set, most significant frac bit set */ set_float_default_nan_pattern(0b11000000, &env->fp_status); diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index fee05d0a863..73621f4a970 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -126,7 +126,8 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, float_raise(float_flag_invalid | float_flag_invalid_snan, s); } - if (infzero) { + if (infzero && + !(s->float_infzeronan_rule & float_infzeronan_suppress_invalid)) { /* This is (0 * inf) + NaN or (inf * 0) + NaN */ float_raise(float_flag_invalid | float_flag_invalid_imz, s); } @@ -144,7 +145,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, * Inf * 0 + NaN -- some implementations return the * default NaN here, and some return the input NaN. */ - switch (s->float_infzeronan_rule) { + switch (s->float_infzeronan_rule & ~float_infzeronan_suppress_invalid) { case float_infzeronan_dnan_never: break; case float_infzeronan_dnan_always: From patchwork Fri Feb 7 10:28:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 862976 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp245170wrt; Fri, 7 Feb 2025 02:29:42 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU74bkwKhS64ZpAL7Eel9hFT7K/+DqHN/KIRLKy43P0ikOWT/qrDcrILhkNYFYKdjsA99VXYQ==@linaro.org X-Google-Smtp-Source: AGHT+IGIBYJ8DX8EESi+koaTp+a8pDJGXy1zLj1+xJ+VER7QdMJH8dAznZPACoIUColyvpSH48pp X-Received: by 2002:a05:620a:6011:b0:7a9:ad65:f4a1 with SMTP id af79cd13be357-7c047bc6ffdmr374624385a.26.1738924182070; Fri, 07 Feb 2025 02:29:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738924182; cv=none; d=google.com; s=arc-20240605; b=GYftTRKu2B60tLhcp/pe+q7ISa+Hm5YDPv/dr/qjM2C1qSLVKIHZPNbFwJ60HV8XcE HD3DjdG7K1+yGIy7kaaVOPZxWJCF1CZpEka3KvXVslOG2EWxXLvLZHFXjbBqyqw4qyu8 fLzNO/ojOQRgLA2kJ/zA7k4GrV1biDo7vNLqIYE9VrEARf1lP1cLHPBdvTOLWrpsP3fW 3v03M7zlN85xowggaDYToaG8xXogsNeCHHoyZLZuLwxmasvsZH5+fkgvhoIRenKU5Zi7 AQSAzxqB787E+egc3sU+S7M0t5KXkRfZstQeut+/ruC412J6+pjwe2Nm0vi9fPjbVFq8 Uvag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dGTMV/JVOhgwSD7zfFhjmY9o50J6ILSLJjCbihcs1Oc=; fh=mAkTJkmys9sHI/rBpbMW0gFFmA1+Q6Xmaym6a9hMRlo=; b=CBSIr0gFedAYBgIz9gySnsRawFeHP+sQ8Hxem1rBw+BuVuxpEQJ9j8Gt6t/bnJWDVA gOmEs+IwRLas9NJ59Gsr/+jRXYJck2oVx02QXjmX0L8UXABQR7h437m81bV/G4pzRmTl +7CPNPB4NiviAw+W1SRBESIvyoPjFOLXk48BbzlsoTdStXWLPqrcixFhyL1X9Fs/EsEp 1L6JIhUage/N+5IOntOWtJjJtJ43FJuqcmUbigfDgL3enD7x5ZHgdq1zyAofKVGgOqoG 1D2Z5lGfpvDFY/mYBFxcKwZdaZzOW2Ku4zYXRvb7pQhC4Eqr5Td2i5VjbZ94EOi/4I3q ddog==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=EF5nqKhX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7c041df5d3fsi298972385a.70.2025.02.07.02.29.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Feb 2025 02:29:42 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=EF5nqKhX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tgLbH-0005w0-NX; Fri, 07 Feb 2025 05:28:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tgLb8-0005t7-Lm for qemu-devel@nongnu.org; Fri, 07 Feb 2025 05:28:35 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tgLb6-0008KG-TB for qemu-devel@nongnu.org; Fri, 07 Feb 2025 05:28:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1738924112; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dGTMV/JVOhgwSD7zfFhjmY9o50J6ILSLJjCbihcs1Oc=; b=EF5nqKhXRwhZXCtwCWBYU0IgDXrYCuwFiw8atvhrpbtIJcbf/TsKGtHoWBwQRlksBkgVsl 9PwKDHz832yhjfniGmNIcbVTAIxMQ4bdvWO2ly/IjGqDekX6l/lH/Oxd5RLd6anbcgyyBV xLp5WTSVE4vkvsTRh/HnlBpmLsZ+UNg= Received: from mail-ej1-f70.google.com (mail-ej1-f70.google.com [209.85.218.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-493-3KzueV56MA2BRjcXDlq-2Q-1; Fri, 07 Feb 2025 05:28:30 -0500 X-MC-Unique: 3KzueV56MA2BRjcXDlq-2Q-1 X-Mimecast-MFC-AGG-ID: 3KzueV56MA2BRjcXDlq-2Q Received: by mail-ej1-f70.google.com with SMTP id a640c23a62f3a-ab78afc6390so66870866b.3 for ; Fri, 07 Feb 2025 02:28:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738924108; x=1739528908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dGTMV/JVOhgwSD7zfFhjmY9o50J6ILSLJjCbihcs1Oc=; b=I6WiJwxKwWxKtDgbIgO/z57fkmWV3aGsk2lb71clpT2W8t2/zD0kLQTz64Y17A8V+e 4Y8IgkgsAFvDfyT1uhM8JV/H3ECoWLUeR0WPeVz3G9uzRxCDEf+SBHG68mwLN8V4ziZz LtR3leE0wlKvr45fEj+HXKm3TIyCtqtBd+HAc8qOPamh3yYBI6rEupWe2RHvhQiKHWE2 N2yafspnqKzKx7TlykS0Po5ttMckRQZM/OF8sjMLMQrij6OpHXzSiV1IYJWPhvx5ZjfE mV7q5Q2v3sL9pibnIv7nFqrB7G5c92ljwHqggqhQ6F6hZoi3T5f4cKBojz5mnh3rgLij 57Ng== X-Gm-Message-State: AOJu0YyQnZ3wyVtsQQpwFp1TCHj5yBNPEjiRpHqHnNz3BwU4Ydwpdc4e gbkRvoCtV1qWFv6IzqNUn0jKHfa1YPY4qYXyWQ9NWv4+s/XfG4+ZGpSbkC7dAJ2/lHlEX1c6h9R nUE6DNjNER1qei4M4KrysP5gMaVBb9uuihM2R5ZhW0sgmFeq/aJOw2rxt/rV0RykWrw9uQpXRnr psrdNOmbqcZsXz/fdiryw0677mAIRaSxXNvCHt+k0= X-Gm-Gg: ASbGncs0yDT0XIqK+GpTiIIo3aS1NY84KCNBAnopDy1LLqpoHObFK+bwe6t7ZBva53K vZvUqJg0PBR7yjmrp6oGJl6IeZfelx7IJ8gPuQkAFz5n+RjT7ZSiXMe5a7sO7q3bUAmZqRZE4Xp 4A3haUgMu+98x1XfZIMoGieIcgog+PdpeGiLqZja9ToK6s1WamKocX7xpfuh9jpBhKt9+2Y+Ir0 0cUIoGjQ5YEdzCL+XD8AgxMeoPbn9DfwY7oWfu8XbK8qTDizkQ3JV4IdEChaWtojuBIFMDyG1S/ xIH35Q== X-Received: by 2002:a17:907:2d2c:b0:ab7:93a9:2ba6 with SMTP id a640c23a62f3a-ab793a92c49mr36776966b.5.1738924108464; Fri, 07 Feb 2025 02:28:28 -0800 (PST) X-Received: by 2002:a17:907:2d2c:b0:ab7:93a9:2ba6 with SMTP id a640c23a62f3a-ab793a92c49mr36773366b.5.1738924108004; Fri, 07 Feb 2025 02:28:28 -0800 (PST) Received: from [192.168.10.3] ([151.62.97.55]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab7732e71e3sm240031566b.112.2025.02.07.02.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 02:28:24 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Peter Maydell , Richard Henderson Subject: [PULL 6/7] tests/tcg/x86_64/fma: Test some x86 fused-multiply-add cases Date: Fri, 7 Feb 2025 11:28:00 +0100 Message-ID: <20250207102802.2445596-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250207102802.2445596-1-pbonzini@redhat.com> References: <20250207102802.2445596-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell Add a test case which tests some corner case behaviour of fused-multiply-add on x86: * 0 * Inf + SNaN should raise Invalid * 0 * Inf + QNaN shouldh not raise Invalid * tininess should be detected after rounding There is also one currently-disabled test case: * flush-to-zero should be done after rounding This is disabled because QEMU's emulation currently does this incorrectly (and so would fail the test). The test case is kept in but disabled, as the justification for why the test running harness has support for testing both with and without FTZ set. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Link: https://lore.kernel.org/r/20250116112536.4117889-3-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini --- tests/tcg/x86_64/fma.c | 109 +++++++++++++++++++++++++++++++ tests/tcg/x86_64/Makefile.target | 1 + 2 files changed, 110 insertions(+) create mode 100644 tests/tcg/x86_64/fma.c diff --git a/tests/tcg/x86_64/fma.c b/tests/tcg/x86_64/fma.c new file mode 100644 index 00000000000..09c622ebc00 --- /dev/null +++ b/tests/tcg/x86_64/fma.c @@ -0,0 +1,109 @@ +/* + * Test some fused multiply add corner cases. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include +#include +#include +#include + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/* + * Perform one "n * m + a" operation using the vfmadd insn and return + * the result; on return *mxcsr_p is set to the bottom 6 bits of MXCSR + * (the Flag bits). If ftz is true then we set MXCSR.FTZ while doing + * the operation. + * We print the operation and its results to stdout. + */ +static uint64_t do_fmadd(uint64_t n, uint64_t m, uint64_t a, + bool ftz, uint32_t *mxcsr_p) +{ + uint64_t r; + uint32_t mxcsr = 0; + uint32_t ftz_bit = ftz ? (1 << 15) : 0; + uint32_t saved_mxcsr = 0; + + asm volatile("stmxcsr %[saved_mxcsr]\n" + "stmxcsr %[mxcsr]\n" + "andl $0xffff7fc0, %[mxcsr]\n" + "orl %[ftz_bit], %[mxcsr]\n" + "ldmxcsr %[mxcsr]\n" + "movq %[a], %%xmm0\n" + "movq %[m], %%xmm1\n" + "movq %[n], %%xmm2\n" + /* xmm0 = xmm0 + xmm2 * xmm1 */ + "vfmadd231sd %%xmm1, %%xmm2, %%xmm0\n" + "movq %%xmm0, %[r]\n" + "stmxcsr %[mxcsr]\n" + "ldmxcsr %[saved_mxcsr]\n" + : [r] "=r" (r), [mxcsr] "=m" (mxcsr), + [saved_mxcsr] "=m" (saved_mxcsr) + : [n] "r" (n), [m] "r" (m), [a] "r" (a), + [ftz_bit] "r" (ftz_bit) + : "xmm0", "xmm1", "xmm2"); + *mxcsr_p = mxcsr & 0x3f; + printf("vfmadd132sd 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 + " = 0x%" PRIx64 " MXCSR flags 0x%" PRIx32 "\n", + n, m, a, r, *mxcsr_p); + return r; +} + +typedef struct testdata { + /* Input n, m, a */ + uint64_t n; + uint64_t m; + uint64_t a; + bool ftz; + /* Expected result */ + uint64_t expected_r; + /* Expected low 6 bits of MXCSR (the Flag bits) */ + uint32_t expected_mxcsr; +} testdata; + +static testdata tests[] = { + { 0, 0x7ff0000000000000, 0x7ff000000000aaaa, false, /* 0 * Inf + SNaN */ + 0x7ff800000000aaaa, 1 }, /* Should be QNaN and does raise Invalid */ + { 0, 0x7ff0000000000000, 0x7ff800000000aaaa, false, /* 0 * Inf + QNaN */ + 0x7ff800000000aaaa, 0 }, /* Should be QNaN and does *not* raise Invalid */ + /* + * These inputs give a result which is tiny before rounding but which + * becomes non-tiny after rounding. x86 is a "detect tininess after + * rounding" architecture, so it should give a non-denormal result and + * not set the Underflow flag (only the Precision flag for an inexact + * result). + */ + { 0x3fdfffffffffffff, 0x001fffffffffffff, 0x801fffffffffffff, false, + 0x8010000000000000, 0x20 }, + /* + * Flushing of denormal outputs to zero should also happen after + * rounding, so setting FTZ should not affect the result or the flags. + * QEMU currently does not emulate this correctly because we do the + * flush-to-zero check before rounding, so we incorrectly produce a + * zero result and set Underflow as well as Precision. + */ +#ifdef ENABLE_FAILING_TESTS + { 0x3fdfffffffffffff, 0x001fffffffffffff, 0x801fffffffffffff, true, + 0x8010000000000000, 0x20 }, /* Enabling FTZ shouldn't change flags */ +#endif +}; + +int main(void) +{ + bool passed = true; + for (int i = 0; i < ARRAY_SIZE(tests); i++) { + uint32_t mxcsr; + uint64_t r = do_fmadd(tests[i].n, tests[i].m, tests[i].a, + tests[i].ftz, &mxcsr); + if (r != tests[i].expected_r) { + printf("expected result 0x%" PRIx64 "\n", tests[i].expected_r); + passed = false; + } + if (mxcsr != tests[i].expected_mxcsr) { + printf("expected MXCSR flags 0x%x\n", tests[i].expected_mxcsr); + passed = false; + } + } + return passed ? 0 : 1; +} diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.target index d6dff559c7d..be20fc64e88 100644 --- a/tests/tcg/x86_64/Makefile.target +++ b/tests/tcg/x86_64/Makefile.target @@ -18,6 +18,7 @@ X86_64_TESTS += adox X86_64_TESTS += test-1648 X86_64_TESTS += test-2175 X86_64_TESTS += cross-modifying-code +X86_64_TESTS += fma TESTS=$(MULTIARCH_TESTS) $(X86_64_TESTS) test-x86_64 else TESTS=$(MULTIARCH_TESTS)