From patchwork Fri Feb 7 06:42:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 863080 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F4F9198A06; Fri, 7 Feb 2025 06:43:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910601; cv=none; b=VGtBmTtSxXEF0jpfOBXKEgL03KNZruus4njY+CJ7sfuWQO8AirGIs1a0vv6vlbY5O2NTU/frcsDZ5a9LNRWTBzAZbh+kj0In9S3XpDeBbB7XctUCONvUlxTb9pubUvY6jq/nCe8UpwkSGP3WOe3TbfYH2pW+qSIne1xweD4mc1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910601; c=relaxed/simple; bh=avuDxrX+bDgNvLafMJuvmb3oYf4uTe94mdHy6Nw7USo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fPOmGljL3Dn8eMtQEukRXB6CP/mMepnFZ7UakJM8nWyg3amEb2uOurtxOUoYRiUTRc2hDrTJmXyBj5BPOIft61EcMDdgCaP4j8psWEEuMsXF9GK/PLsw+O9+S6YsScVKc7zBqk8wA3SB109vC6Y90/d1gy8vxXeMwZF9N3lSF+0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=kUyjJGR9; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="kUyjJGR9" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5171PCdD028298; Fri, 7 Feb 2025 06:42:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= qQMOQZffzsMfKn3CfdTJ9UbXMyLWAPH3pYBo3aDkzCI=; b=kUyjJGR9A2SDd9DX goDkkXqWt0Jbu6cFpZdPrmeOCUpP2U3CG22SAOyewBkwHpRvWhh8m6kVNhLOWwlf V0siUx+zSCkmEvw18+0Y/68laY7Z4d68H6ANz2VfT5o4pO/hsb2b7WqC7rF9/aCN G4Y65FKO3hFc1Oh5XCg0582MpfalZNjiHnK0hqXjIuLs4jo2uUpxyi8kSF0vr9xY uJZCpkLwsIw8GpjmsWTIOoOFc7Q2Zz087jj9RwS2oaVkAlvzG2sA6lAT5KH+F++k Oj/ohBt7eoEWYRN9Fph0H0jqOaNNVKq1naZ31efASO83xXQJHrlHi21HDDYuqCOR 90mFRQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44n7p7rrjm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 06:42:48 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5176glYr002052 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 06:42:47 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 22:42:42 -0800 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Tingwei Zhang , Jinlong Mao , , , , , , Subject: [PATCH v10 1/7] Coresight: Add support for new APB clock name Date: Fri, 7 Feb 2025 14:42:07 +0800 Message-ID: <20250207064213.2314482-2-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250207064213.2314482-1-quic_jiegan@quicinc.com> References: <20250207064213.2314482-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: u6xLoVi71VegeVr_NRxhqfq8laLAcE9p X-Proofpoint-ORIG-GUID: u6xLoVi71VegeVr_NRxhqfq8laLAcE9p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_03,2025-02-07_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=858 impostorscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1015 mlxscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070051 Add support for new APB clock-name. If the function fails to obtain the clock with the name "apb_pclk", it will attempt to acquire the clock with the name "apb". Reviewed-by: James Clark Signed-off-by: Jie Gan --- include/linux/coresight.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 17276965ff1d..157c4bd009a1 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -459,8 +459,11 @@ static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev) int ret; pclk = clk_get(dev, "apb_pclk"); - if (IS_ERR(pclk)) - return NULL; + if (IS_ERR(pclk)) { + pclk = clk_get(dev, "apb"); + if (IS_ERR(pclk)) + return NULL; + } ret = clk_prepare_enable(pclk); if (ret) { From patchwork Fri Feb 7 06:42:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 863081 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AD9815199C; Fri, 7 Feb 2025 06:43:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910596; cv=none; b=bkJLeRz9yxZ/4YyTvoVbAsliRyYeOO1ue0uMxvexMh46kNbVP9JxWyk1xfWVhS3p/2FZH38YopYjrgwgnS0yI/er1UAVz3iiQdgkUFwgcWn419+mhQQKP5bgVF2v8mZWA85C4d6H46Yx1sJGkI2pAOag2vHwvUNBEZbj3OVfdcQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910596; c=relaxed/simple; bh=Yf7kyqWdOoKCiD+rt4o3E6TpJM7o3QxSY83IupDlzrI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VROYG5c4OAF/ikEtHBH0GaqBtT39CuJDnuh3J3olVW9HsDFcGs+2g6W2fyxc/0i8ypYtpWXWxDyEpFsin9CO1QuTpLVlMdsFh/atlTczOgETMbLft7h5BtYV3TSpJaKeNXU5Olp8p1nvafuJNgyiV6pq9WVJVK5DvXe6edHXv/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=W0e7RNn2; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="W0e7RNn2" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5175H5VL021447; Fri, 7 Feb 2025 06:42:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= NX5v8nJ2puhYj5wXMtsaWBp0DSoGX4fWn2lmiYpQN9c=; b=W0e7RNn2/CQSxI8F A/YnnG+ejINoeaDT+x5oXSsp6lVoJn8qppXB+IChaR8uTkO4CG6Fi3PqaIb0sZSE 4E3Mhplnu5dbSc93ArOyFJoZKaqQAd2SfcayPardZzr7Lgwgx9aGor+xfsi/HID5 dL5SXff9Yftf/V6PXH6QXw9ktL8YbGI1sLkQTljlNf2/EshPBl426rAH+h5Zshlz BxqQ78J8ZOCtARjsB/PzvEekf5hDBJwGx4pf+kEUG4WhOdxWdY47nEtDZjaL4j3w bN5dOj1YU3WHMANhS72sgJKJsmo3y2TpVfCBo0GofI98yIqmlHYP8VjT57oYtd2P KFTV3Q== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44nbvur5sc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 06:42:54 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5176grZ6004438 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 06:42:53 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 22:42:48 -0800 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Tingwei Zhang , Jinlong Mao , , , , , , Subject: [PATCH v10 2/7] Coresight: Add trace_id function to retrieving the trace ID Date: Fri, 7 Feb 2025 14:42:08 +0800 Message-ID: <20250207064213.2314482-3-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250207064213.2314482-1-quic_jiegan@quicinc.com> References: <20250207064213.2314482-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Z8HLDujoaAOOGCMRKrbQYBql3ggZP06G X-Proofpoint-ORIG-GUID: Z8HLDujoaAOOGCMRKrbQYBql3ggZP06G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_03,2025-02-07_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 spamscore=0 impostorscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070051 Add 'trace_id' function pointer in ops. It's responsible for retrieving the device's trace ID. Co-developed-by: James Clark Signed-off-by: James Clark Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 27 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-dummy.c | 11 ++++++++ .../coresight/coresight-etm3x-core.c | 1 + .../coresight/coresight-etm4x-core.c | 1 + drivers/hwtracing/coresight/coresight-stm.c | 11 ++++++++ drivers/hwtracing/coresight/coresight-tpda.c | 11 ++++++++ include/linux/coresight.h | 8 ++++++ 7 files changed, 70 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 0a9380350fb5..6cad777757f3 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -23,6 +23,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" /* * Mutex used to lock all sysfs enable and disable actions and loading and @@ -1515,6 +1516,32 @@ void coresight_remove_driver(struct amba_driver *amba_drv, } EXPORT_SYMBOL_GPL(coresight_remove_driver); +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, + struct coresight_device *sink) +{ + int trace_id; + int cpu = source_ops(csdev)->cpu_id(csdev); + + switch (mode) { + case CS_MODE_SYSFS: + trace_id = coresight_trace_id_get_cpu_id(cpu); + break; + case CS_MODE_PERF: + trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map); + break; + default: + trace_id = -EINVAL; + break; + } + + if (!IS_VALID_CS_TRACE_ID(trace_id)) + dev_err(&csdev->dev, + "Failed to allocate trace ID on CPU%d\n", cpu); + + return trace_id; +} +EXPORT_SYMBOL_GPL(coresight_etm_get_trace_id); + MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Pratik Patel "); MODULE_AUTHOR("Mathieu Poirier "); diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c index 9be53be8964b..c47f0382b943 100644 --- a/drivers/hwtracing/coresight/coresight-dummy.c +++ b/drivers/hwtracing/coresight/coresight-dummy.c @@ -41,6 +41,16 @@ static void dummy_source_disable(struct coresight_device *csdev, dev_dbg(csdev->dev.parent, "Dummy source disabled\n"); } +static int dummy_source_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, + __maybe_unused struct coresight_device *sink) +{ + struct dummy_drvdata *drvdata; + + drvdata = dev_get_drvdata(csdev->dev.parent); + + return drvdata->traceid; +} + static int dummy_sink_enable(struct coresight_device *csdev, enum cs_mode mode, void *data) { @@ -59,6 +69,7 @@ static int dummy_sink_disable(struct coresight_device *csdev) static const struct coresight_ops_source dummy_source_ops = { .enable = dummy_source_enable, .disable = dummy_source_disable, + .trace_id = dummy_source_trace_id, }; static const struct coresight_ops dummy_source_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index c103f4c70f5d..a38e72ef8e79 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -701,6 +701,7 @@ static const struct coresight_ops_source etm_source_ops = { .cpu_id = etm_cpu_id, .enable = etm_enable, .disable = etm_disable, + .trace_id = coresight_etm_get_trace_id, }; static const struct coresight_ops etm_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 2c1a60577728..1a993d5380e7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1064,6 +1064,7 @@ static const struct coresight_ops_source etm4_source_ops = { .cpu_id = etm4_cpu_id, .enable = etm4_enable, .disable = etm4_disable, + .trace_id = coresight_etm_get_trace_id, }; static const struct coresight_ops etm4_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index b581a30a1cd9..64fcfa916562 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -281,9 +281,20 @@ static void stm_disable(struct coresight_device *csdev, } } +static int stm_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, + __maybe_unused struct coresight_device *sink) +{ + struct stm_drvdata *drvdata; + + drvdata = dev_get_drvdata(csdev->dev.parent); + + return drvdata->traceid; +} + static const struct coresight_ops_source stm_source_ops = { .enable = stm_enable, .disable = stm_disable, + .trace_id = stm_trace_id, }; static const struct coresight_ops stm_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 189a4abc2561..d80b6427e5a6 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -241,9 +241,20 @@ static void tpda_disable(struct coresight_device *csdev, dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port); } +static int tpda_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, + __maybe_unused struct coresight_device *sink) +{ + struct tpda_drvdata *drvdata; + + drvdata = dev_get_drvdata(csdev->dev.parent); + + return drvdata->atid; +} + static const struct coresight_ops_link tpda_link_ops = { .enable = tpda_enable, .disable = tpda_disable, + .trace_id = tpda_trace_id, }; static const struct coresight_ops tpda_cs_ops = { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 157c4bd009a1..70407d61262e 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -368,6 +368,7 @@ struct coresight_ops_sink { * Operations available for links. * @enable: enables flow between iport and oport. * @disable: disables flow between iport and oport. + * @trace_id: alloc or read the traceid. */ struct coresight_ops_link { int (*enable)(struct coresight_device *csdev, @@ -376,6 +377,8 @@ struct coresight_ops_link { void (*disable)(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out); + int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode, + struct coresight_device *sink); }; /** @@ -385,6 +388,7 @@ struct coresight_ops_link { * is associated to. * @enable: enables tracing for a source. * @disable: disables tracing for a source. + * @trace_id: alloc or read the traceid. */ struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); @@ -392,6 +396,8 @@ struct coresight_ops_source { enum cs_mode mode, struct coresight_trace_id_map *id_map); void (*disable)(struct coresight_device *csdev, struct perf_event *event); + int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode, + struct coresight_device *sink); }; /** @@ -697,4 +703,6 @@ int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, void coresight_remove_driver(struct amba_driver *amba_drv, struct platform_driver *pdev_drv); +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, + struct coresight_device *sink); #endif /* _LINUX_COREISGHT_H */ From patchwork Fri Feb 7 06:42:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 863375 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B50C118FC7B; Fri, 7 Feb 2025 06:43:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910599; cv=none; b=ftTZMetGbkNbJz1PbdBKLx7fZeVDbRrapldrVD0QXDk53euWfQkkCfGhRYN2rR3fvF9r9+2joHZsNOffd4TtH9TsyFjfYajTP7YJ2vi6BsmfJrHiJdpy20j+kZa4gu6dxIBS9pLWzbBeQNMX7OL5U5DFE0UQAoTEzp5rbRsrU/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910599; c=relaxed/simple; bh=2hbBuhR12HCknxy3ZpWFC8nk41wqAjEyvCv4koA/gaw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=I+xNBBgDl9QQ5oq2Y3rRxeLpjOLgJHXaxV3sKoFCKj36VtbHmA3lCbOi17PDSd9CBjHJBl5WbX0UVA+TBjFbC2468A/BWfXAx7oaEns79jMpml9oHacLznBo/YzjtCy9lRYp8YEwkPlRFMADmLM6nC57+AamgqwuRC+SeDcv7YM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=nB7WcRnY; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="nB7WcRnY" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5172Ie3m003486; Fri, 7 Feb 2025 06:43:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= n5s+flF43R133QAlfIXrz56WnUrn/DbnTJQG3zWrhNo=; b=nB7WcRnYWpcrmP7P zh9DfyK/8KwfQyFNhubwZX8pVBgAQjA8VdHlyiXwjno5YDEWC+Kfks6qHh1JYrpv wOqim2iZjrii4kt0QsouFAg51d6fuviDcUAo5Lzm+7zI1PaGgIZhqZhjbqycZvMX mpuhsBMOuL3PGcskkTkkjTf5Kw+jG8wIQuqogNIobJkMTlgIHr/jufKqnMhIO7yd iLw3/CUt9hdFzsrBec3sIZNqh6sHASeHEYLtYZixNTgY9uhs92q0ffXavKeJXSdW C5SRtXbmHvJrlCurQBD5540areHtGOipRpSJ+HH/tZqxBe4bncZxRM+4oUfgN3ev W7duCw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44n99e8hg4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 06:43:00 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5176gxRo004517 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 06:42:59 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 22:42:53 -0800 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Tingwei Zhang , Jinlong Mao , , , , , , Subject: [PATCH v10 3/7] Coresight: Use coresight_etm_get_trace_id() in traceid_show() Date: Fri, 7 Feb 2025 14:42:09 +0800 Message-ID: <20250207064213.2314482-4-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250207064213.2314482-1-quic_jiegan@quicinc.com> References: <20250207064213.2314482-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: K5T6A5KkFKDIeBiHXAoytKCJlsBe9sr0 X-Proofpoint-GUID: K5T6A5KkFKDIeBiHXAoytKCJlsBe9sr0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_03,2025-02-07_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 phishscore=0 adultscore=0 mlxlogscore=735 malwarescore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070051 From: James Clark Use the new API, coresight_etm_get_trace_id, to read the traceid of the ETM device when call traceid_show via sysfs node. Signed-off-by: James Clark Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 3 +-- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index 68c644be9813..b9006451f515 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -1190,10 +1190,9 @@ static DEVICE_ATTR_RO(cpu); static ssize_t traceid_show(struct device *dev, struct device_attribute *attr, char *buf) { - int trace_id; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); + int trace_id = coresight_etm_get_trace_id(drvdata->csdev, CS_MODE_SYSFS, NULL); - trace_id = etm_read_alloc_trace_id(drvdata); if (trace_id < 0) return trace_id; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index c767f8ae4cf1..e5216c0f60da 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -4,6 +4,7 @@ * Author: Mathieu Poirier */ +#include #include #include #include @@ -2402,10 +2403,9 @@ static ssize_t trctraceid_show(struct device *dev, struct device_attribute *attr, char *buf) { - int trace_id; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + int trace_id = coresight_etm_get_trace_id(drvdata->csdev, CS_MODE_SYSFS, NULL); - trace_id = etm4_read_alloc_trace_id(drvdata); if (trace_id < 0) return trace_id; From patchwork Fri Feb 7 06:42:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 863079 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37B902343A1; Fri, 7 Feb 2025 06:43:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910605; cv=none; b=dxYAgY99Hw+uexAGo3rJR2jo1yjN+Eu5RD2R9YhMJ9/wZj9YZ+9CGwOb4RqIVMUPx9LlhuLJ8vRleBZl/W4M4yxKBYaej5T6PIVA2wjt+LDEQy+/X0rbpNyxHrzfcqPytaDtYQPmrb+PfnP8JkikWMQSx3zAX2U8vZPF4aMyyYM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910605; c=relaxed/simple; bh=wV58oJcWp1zdkUOBayRAdv8Es8iIyE50E4bKxV8xkpc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mPwGPo8uZUkX6NRROGWhwugdEcutqsFe31GiwKCsr1hMmW6neQuq/f+mV6fv0mZ1hGd84Y/pOqc1uKZ3TrLOMcHvcfc+1LNLEteRGKxd1oZS5vxfsLgGiTZ2GREfyD87UN8oCrU2sZYVwbUYz2mcCNk8JUIRb0A62v5/vbpzJlY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=HNwItMVe; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="HNwItMVe" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51756vMu024488; Fri, 7 Feb 2025 06:43:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= tV6TwpVsHYj3buv5NnBevXC8TvjqVz0WF3VmeQZCPHk=; b=HNwItMVejaaKFpG9 F7jUAcvSJPMXezxcQKLv5dz1Pg66T+gSaMNT/VNXWpxryrrjac4N6fI/xrZWcRdm ed1GFKGjU9D8S2y8rBvTWxQ9biF0H3azouTArOMQY7MRMFeGCyCV8l2mEK/j2kXS 4WBnz3p3iV6iXIJIQwDkHRsqwdIpk8wBx29WwjQzYqdHR94rzP3uyanhhy2EtOF9 yn4B2eSYPp/6BkphOE4Uz5FWHRx16rz/VBGJ/cYPjoxNy86vUv124TCb6SOQ1cNI VLBpoVJ2eRm2lF/FOSIYLawjg5KOiUrzNf6y/+KYs19gir2aQOzOFJ0mv+S8wRWN Bikzgg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44nbr406ye-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 06:43:07 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5176h6ep015090 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 06:43:06 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 22:42:59 -0800 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Tingwei Zhang , Jinlong Mao , , , , , , Subject: [PATCH v10 4/7] Coresight: Introduce a new struct coresight_path Date: Fri, 7 Feb 2025 14:42:10 +0800 Message-ID: <20250207064213.2314482-5-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250207064213.2314482-1-quic_jiegan@quicinc.com> References: <20250207064213.2314482-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: l-FZC0ONdoghIIqMPWE71i1WMcGbiKte X-Proofpoint-ORIG-GUID: l-FZC0ONdoghIIqMPWE71i1WMcGbiKte X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_03,2025-02-07_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 mlxscore=0 adultscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070051 Add 'struct coresight_path' to store the data that is needed by coresight_enable_path/coresight_disable_path. The structure will be transmitted to any required devices to enable related funcationalities. The trace_id will be allocated after the path is built. Consequently, The ETM3x and ETM4x devices will directly read the trace_id from path which result in etm_read_alloc_trace_id and etm4_read_alloc_trace_id being deleted. Co-developed-by: James Clark Signed-off-by: James Clark Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 106 +++++++++++++----- drivers/hwtracing/coresight/coresight-dummy.c | 5 +- .../hwtracing/coresight/coresight-etm-perf.c | 30 +++-- .../hwtracing/coresight/coresight-etm-perf.h | 2 +- drivers/hwtracing/coresight/coresight-etm.h | 1 - .../coresight/coresight-etm3x-core.c | 54 ++------- .../coresight/coresight-etm4x-core.c | 54 ++------- drivers/hwtracing/coresight/coresight-etm4x.h | 1 - drivers/hwtracing/coresight/coresight-priv.h | 12 +- drivers/hwtracing/coresight/coresight-stm.c | 3 +- drivers/hwtracing/coresight/coresight-sysfs.c | 17 ++- drivers/hwtracing/coresight/coresight-tpdm.c | 3 +- include/linux/coresight.h | 12 +- 13 files changed, 143 insertions(+), 157 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 6cad777757f3..3bdd6ebd4b6e 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -76,14 +76,14 @@ struct coresight_device *coresight_get_percpu_sink(int cpu) } EXPORT_SYMBOL_GPL(coresight_get_percpu_sink); -static struct coresight_device *coresight_get_source(struct list_head *path) +static struct coresight_device *coresight_get_source(struct coresight_path *path) { struct coresight_device *csdev; if (!path) return NULL; - csdev = list_first_entry(path, struct coresight_node, link)->csdev; + csdev = list_first_entry(path->path_list, struct coresight_node, link)->csdev; if (!coresight_is_device_source(csdev)) return NULL; @@ -332,12 +332,12 @@ static int coresight_enable_helper(struct coresight_device *csdev, return helper_ops(csdev)->enable(csdev, mode, data); } -static void coresight_disable_helper(struct coresight_device *csdev) +static void coresight_disable_helper(struct coresight_device *csdev, void *data) { - helper_ops(csdev)->disable(csdev, NULL); + helper_ops(csdev)->disable(csdev, data); } -static void coresight_disable_helpers(struct coresight_device *csdev) +static void coresight_disable_helpers(struct coresight_device *csdev, void *data) { int i; struct coresight_device *helper; @@ -345,7 +345,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev) for (i = 0; i < csdev->pdata->nr_outconns; ++i) { helper = csdev->pdata->out_conns[i]->dest_dev; if (helper && coresight_is_helper(helper)) - coresight_disable_helper(helper); + coresight_disable_helper(helper, data); } } @@ -362,7 +362,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev) void coresight_disable_source(struct coresight_device *csdev, void *data) { source_ops(csdev)->disable(csdev, data); - coresight_disable_helpers(csdev); + coresight_disable_helpers(csdev, NULL); } EXPORT_SYMBOL_GPL(coresight_disable_source); @@ -371,16 +371,16 @@ EXPORT_SYMBOL_GPL(coresight_disable_source); * @nd in the list. If @nd is NULL, all the components, except the SOURCE are * disabled. */ -static void coresight_disable_path_from(struct list_head *path, +static void coresight_disable_path_from(struct coresight_path *path, struct coresight_node *nd) { u32 type; struct coresight_device *csdev, *parent, *child; if (!nd) - nd = list_first_entry(path, struct coresight_node, link); + nd = list_first_entry(path->path_list, struct coresight_node, link); - list_for_each_entry_continue(nd, path, link) { + list_for_each_entry_continue(nd, path->path_list, link) { csdev = nd->csdev; type = csdev->type; @@ -418,11 +418,11 @@ static void coresight_disable_path_from(struct list_head *path, } /* Disable all helpers adjacent along the path last */ - coresight_disable_helpers(csdev); + coresight_disable_helpers(csdev, path); } } -void coresight_disable_path(struct list_head *path) +void coresight_disable_path(struct coresight_path *path) { coresight_disable_path_from(path, NULL); } @@ -447,7 +447,7 @@ static int coresight_enable_helpers(struct coresight_device *csdev, return 0; } -int coresight_enable_path(struct list_head *path, enum cs_mode mode, +int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, void *sink_data) { int ret = 0; @@ -457,12 +457,12 @@ int coresight_enable_path(struct list_head *path, enum cs_mode mode, struct coresight_device *source; source = coresight_get_source(path); - list_for_each_entry_reverse(nd, path, link) { + list_for_each_entry_reverse(nd, path->path_list, link) { csdev = nd->csdev; type = csdev->type; /* Enable all helpers adjacent to the path first */ - ret = coresight_enable_helpers(csdev, mode, sink_data); + ret = coresight_enable_helpers(csdev, mode, path); if (ret) goto err; /* @@ -510,20 +510,21 @@ int coresight_enable_path(struct list_head *path, enum cs_mode mode, goto out; } -struct coresight_device *coresight_get_sink(struct list_head *path) +struct coresight_device *coresight_get_sink(struct coresight_path *path) { struct coresight_device *csdev; if (!path) return NULL; - csdev = list_last_entry(path, struct coresight_node, link)->csdev; + csdev = list_last_entry(path->path_list, struct coresight_node, link)->csdev; if (csdev->type != CORESIGHT_DEV_TYPE_SINK && csdev->type != CORESIGHT_DEV_TYPE_LINKSINK) return NULL; return csdev; } +EXPORT_SYMBOL_GPL(coresight_get_sink); u32 coresight_get_sink_id(struct coresight_device *csdev) { @@ -654,6 +655,51 @@ static void coresight_drop_device(struct coresight_device *csdev) } } +/** + * Links or sources will read their existing or alloc a trace ID, if their ID + * callback is set. + */ +static int coresight_get_trace_id(struct coresight_device *csdev, + enum cs_mode mode, + struct coresight_device *sink) +{ + if (csdev->type == CORESIGHT_DEV_TYPE_LINK && link_ops(csdev)->trace_id) + return link_ops(csdev)->trace_id(csdev, mode, sink); + + if (csdev->type == CORESIGHT_DEV_TYPE_SOURCE && source_ops(csdev)->trace_id) + return source_ops(csdev)->trace_id(csdev, mode, sink); + + return 0; +} + +/** + * Call this after creating the path and before enabling it. This leaves + * the trace ID set on the path and returns the ID, or an error if it + * couldn't be assigned. + */ +int coresight_path_assign_trace_id(struct coresight_path *path, + enum cs_mode mode) +{ + struct coresight_device *sink = coresight_get_sink(path); + struct coresight_node *nd; + int ret; + + list_for_each_entry(nd, path->path_list, link) { + /* Assign a trace ID to the path for the first device that wants to do it */ + ret = coresight_get_trace_id(nd->csdev, mode, sink); + + /* + * 0 in this context is that it didn't want to assign so keep searching. + * Non 0 is either success or fail, return it either way. + */ + if (ret != 0) { + path->trace_id = ret; + return ret; + } + } + return 0; +} + /** * _coresight_build_path - recursively build a path from a @csdev to a sink. * @csdev: The device to start from. @@ -669,7 +715,7 @@ static void coresight_drop_device(struct coresight_device *csdev) static int _coresight_build_path(struct coresight_device *csdev, struct coresight_device *source, struct coresight_device *sink, - struct list_head *path) + struct coresight_path *path) { int i, ret; bool found = false; @@ -722,28 +768,37 @@ static int _coresight_build_path(struct coresight_device *csdev, return -ENOMEM; node->csdev = csdev; - list_add(&node->link, path); + list_add(&node->link, path->path_list); return 0; } -struct list_head *coresight_build_path(struct coresight_device *source, +struct coresight_path *coresight_build_path(struct coresight_device *source, struct coresight_device *sink) { - struct list_head *path; + struct coresight_path *path; + struct list_head *path_list; int rc; if (!sink) return ERR_PTR(-EINVAL); - path = kzalloc(sizeof(struct list_head), GFP_KERNEL); + path = kzalloc(sizeof(struct coresight_path), GFP_KERNEL); if (!path) return ERR_PTR(-ENOMEM); - INIT_LIST_HEAD(path); + path_list = kzalloc(sizeof(struct list_head), GFP_KERNEL); + if (!path_list) { + kfree(path); + return ERR_PTR(-ENOMEM); + } + + INIT_LIST_HEAD(path_list); + path->path_list = path_list; rc = _coresight_build_path(source, source, sink, path); if (rc) { + kfree(path_list); kfree(path); return ERR_PTR(rc); } @@ -758,12 +813,12 @@ struct list_head *coresight_build_path(struct coresight_device *source, * Go through all the elements of a path and 1) removed it from the list and * 2) free the memory allocated for each node. */ -void coresight_release_path(struct list_head *path) +void coresight_release_path(struct coresight_path *path) { struct coresight_device *csdev; struct coresight_node *nd, *next; - list_for_each_entry_safe(nd, next, path, link) { + list_for_each_entry_safe(nd, next, path->path_list, link) { csdev = nd->csdev; coresight_drop_device(csdev); @@ -771,6 +826,7 @@ void coresight_release_path(struct list_head *path) kfree(nd); } + kfree(path->path_list); kfree(path); } diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c index c47f0382b943..d9a811d44885 100644 --- a/drivers/hwtracing/coresight/coresight-dummy.c +++ b/drivers/hwtracing/coresight/coresight-dummy.c @@ -22,9 +22,8 @@ struct dummy_drvdata { DEFINE_CORESIGHT_DEVLIST(source_devs, "dummy_source"); DEFINE_CORESIGHT_DEVLIST(sink_devs, "dummy_sink"); -static int dummy_source_enable(struct coresight_device *csdev, - struct perf_event *event, enum cs_mode mode, - __maybe_unused struct coresight_trace_id_map *id_map) +static int dummy_source_enable(struct coresight_device *csdev, struct perf_event *event, + enum cs_mode mode, struct coresight_path *path) { if (!coresight_take_mode(csdev, mode)) return -EBUSY; diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index ad6a8f4b70b6..0a09a9961197 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -136,13 +136,13 @@ static const struct attribute_group *etm_pmu_attr_groups[] = { NULL, }; -static inline struct list_head ** +static inline struct coresight_path ** etm_event_cpu_path_ptr(struct etm_event_data *data, int cpu) { return per_cpu_ptr(data->path, cpu); } -static inline struct list_head * +static inline struct coresight_path * etm_event_cpu_path(struct etm_event_data *data, int cpu) { return *etm_event_cpu_path_ptr(data, cpu); @@ -226,7 +226,7 @@ static void free_event_data(struct work_struct *work) cscfg_deactivate_config(event_data->cfg_hash); for_each_cpu(cpu, mask) { - struct list_head **ppath; + struct coresight_path **ppath; ppath = etm_event_cpu_path_ptr(event_data, cpu); if (!(IS_ERR_OR_NULL(*ppath))) { @@ -276,7 +276,7 @@ static void *alloc_event_data(int cpu) * unused memory when dealing with single CPU trace scenarios is small * compared to the cost of searching through an optimized array. */ - event_data->path = alloc_percpu(struct list_head *); + event_data->path = alloc_percpu(struct coresight_path *); if (!event_data->path) { kfree(event_data); @@ -352,7 +352,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, * CPUs, we can handle it and fail the session. */ for_each_cpu(cpu, mask) { - struct list_head *path; + struct coresight_path *path; struct coresight_device *csdev; csdev = per_cpu(csdev_src, cpu); @@ -405,15 +405,15 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, cpumask_clear_cpu(cpu, mask); continue; } - /* ensure we can allocate a trace ID for this CPU */ - trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map); - if (!IS_VALID_CS_TRACE_ID(trace_id)) { + trace_id = coresight_path_assign_trace_id(path, CS_MODE_PERF); + + /* Can be 0 and valid, ETE doesn't need an ID */ + if (trace_id < 0) { cpumask_clear_cpu(cpu, mask); coresight_release_path(path); continue; } - coresight_trace_id_perf_start(&sink->perf_sink_id_map); *etm_event_cpu_path_ptr(event_data, cpu) = path; } @@ -458,9 +458,8 @@ static void etm_event_start(struct perf_event *event, int flags) struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt); struct perf_output_handle *handle = &ctxt->handle; struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu); - struct list_head *path; + struct coresight_path *path; u64 hw_id; - u8 trace_id; if (!csdev) goto fail; @@ -503,8 +502,7 @@ static void etm_event_start(struct perf_event *event, int flags) goto fail_end_stop; /* Finally enable the tracer */ - if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF, - &sink->perf_sink_id_map)) + if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF, path)) goto fail_disable_path; /* @@ -514,13 +512,11 @@ static void etm_event_start(struct perf_event *event, int flags) if (!cpumask_test_cpu(cpu, &event_data->aux_hwid_done)) { cpumask_set_cpu(cpu, &event_data->aux_hwid_done); - trace_id = coresight_trace_id_read_cpu_id_map(cpu, &sink->perf_sink_id_map); - hw_id = FIELD_PREP(CS_AUX_HW_ID_MAJOR_VERSION_MASK, CS_AUX_HW_ID_MAJOR_VERSION); hw_id |= FIELD_PREP(CS_AUX_HW_ID_MINOR_VERSION_MASK, CS_AUX_HW_ID_MINOR_VERSION); - hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, trace_id); + hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, path->trace_id); hw_id |= FIELD_PREP(CS_AUX_HW_ID_SINK_ID_MASK, coresight_get_sink_id(sink)); perf_report_aux_output_id(event, hw_id); @@ -558,7 +554,7 @@ static void etm_event_stop(struct perf_event *event, int mode) struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt); struct perf_output_handle *handle = &ctxt->handle; struct etm_event_data *event_data; - struct list_head *path; + struct coresight_path *path; /* * If we still have access to the event_data via handle, diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index 744531158d6b..5febbcdb8696 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -59,7 +59,7 @@ struct etm_event_data { cpumask_t aux_hwid_done; void *snk_config; u32 cfg_hash; - struct list_head * __percpu *path; + struct coresight_path * __percpu *path; }; int etm_perf_symlink(struct coresight_device *csdev, bool link); diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index e02c3ea972c9..171f1384f7c0 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -284,6 +284,5 @@ extern const struct attribute_group *coresight_etm_groups[]; void etm_set_default(struct etm_config *config); void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); -int etm_read_alloc_trace_id(struct etm_drvdata *drvdata); void etm_release_trace_id(struct etm_drvdata *drvdata); #endif diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index a38e72ef8e79..cb8a30a3b48e 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -455,26 +455,6 @@ static int etm_cpu_id(struct coresight_device *csdev) return drvdata->cpu; } -int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) -{ - int trace_id; - - /* - * This will allocate a trace ID to the cpu, - * or return the one currently allocated. - * - * trace id function has its own lock - */ - trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); - if (IS_VALID_CS_TRACE_ID(trace_id)) - drvdata->traceid = (u8)trace_id; - else - dev_err(&drvdata->csdev->dev, - "Failed to allocate trace ID for %s on CPU%d\n", - dev_name(&drvdata->csdev->dev), drvdata->cpu); - return trace_id; -} - void etm_release_trace_id(struct etm_drvdata *drvdata) { coresight_trace_id_put_cpu_id(drvdata->cpu); @@ -482,38 +462,22 @@ void etm_release_trace_id(struct etm_drvdata *drvdata) static int etm_enable_perf(struct coresight_device *csdev, struct perf_event *event, - struct coresight_trace_id_map *id_map) + struct coresight_path *path) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - int trace_id; if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) return -EINVAL; /* Configure the tracer based on the session's specifics */ etm_parse_event_config(drvdata, event); - - /* - * perf allocates cpu ids as part of _setup_aux() - device needs to use - * the allocated ID. This reads the current version without allocation. - * - * This does not use the trace id lock to prevent lock_dep issues - * with perf locks - we know the ID cannot change until perf shuts down - * the session - */ - trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map); - if (!IS_VALID_CS_TRACE_ID(trace_id)) { - dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", - dev_name(&drvdata->csdev->dev), drvdata->cpu); - return -EINVAL; - } - drvdata->traceid = (u8)trace_id; + drvdata->traceid = path->trace_id; /* And enable it */ return etm_enable_hw(drvdata); } -static int etm_enable_sysfs(struct coresight_device *csdev) +static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct etm_enable_arg arg = { }; @@ -521,10 +485,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev) spin_lock(&drvdata->spinlock); - /* sysfs needs to allocate and set a trace ID */ - ret = etm_read_alloc_trace_id(drvdata); - if (ret < 0) - goto unlock_enable_sysfs; + drvdata->traceid = path->trace_id; /* * Configure the ETM only if the CPU is online. If it isn't online @@ -545,7 +506,6 @@ static int etm_enable_sysfs(struct coresight_device *csdev) if (ret) etm_release_trace_id(drvdata); -unlock_enable_sysfs: spin_unlock(&drvdata->spinlock); if (!ret) @@ -554,7 +514,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev) } static int etm_enable(struct coresight_device *csdev, struct perf_event *event, - enum cs_mode mode, struct coresight_trace_id_map *id_map) + enum cs_mode mode, struct coresight_path *path) { int ret; struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -566,10 +526,10 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event, switch (mode) { case CS_MODE_SYSFS: - ret = etm_enable_sysfs(csdev); + ret = etm_enable_sysfs(csdev, path); break; case CS_MODE_PERF: - ret = etm_enable_perf(csdev, event, id_map); + ret = etm_enable_perf(csdev, event, path); break; default: ret = -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 1a993d5380e7..3d0fc25085ea 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -233,25 +233,6 @@ static int etm4_cpu_id(struct coresight_device *csdev) return drvdata->cpu; } -int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) -{ - int trace_id; - - /* - * This will allocate a trace ID to the cpu, - * or return the one currently allocated. - * The trace id function has its own lock - */ - trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); - if (IS_VALID_CS_TRACE_ID(trace_id)) - drvdata->trcid = (u8)trace_id; - else - dev_err(&drvdata->csdev->dev, - "Failed to allocate trace ID for %s on CPU%d\n", - dev_name(&drvdata->csdev->dev), drvdata->cpu); - return trace_id; -} - void etm4_release_trace_id(struct etmv4_drvdata *drvdata) { coresight_trace_id_put_cpu_id(drvdata->cpu); @@ -788,9 +769,9 @@ static int etm4_parse_event_config(struct coresight_device *csdev, static int etm4_enable_perf(struct coresight_device *csdev, struct perf_event *event, - struct coresight_trace_id_map *id_map) + struct coresight_path *path) { - int ret = 0, trace_id; + int ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) { @@ -803,22 +784,7 @@ static int etm4_enable_perf(struct coresight_device *csdev, if (ret) goto out; - /* - * perf allocates cpu ids as part of _setup_aux() - device needs to use - * the allocated ID. This reads the current version without allocation. - * - * This does not use the trace id lock to prevent lock_dep issues - * with perf locks - we know the ID cannot change until perf shuts down - * the session - */ - trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map); - if (!IS_VALID_CS_TRACE_ID(trace_id)) { - dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", - dev_name(&drvdata->csdev->dev), drvdata->cpu); - ret = -EINVAL; - goto out; - } - drvdata->trcid = (u8)trace_id; + drvdata->trcid = path->trace_id; /* And enable it */ ret = etm4_enable_hw(drvdata); @@ -827,7 +793,7 @@ static int etm4_enable_perf(struct coresight_device *csdev, return ret; } -static int etm4_enable_sysfs(struct coresight_device *csdev) +static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct etm4_enable_arg arg = { }; @@ -844,10 +810,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) spin_lock(&drvdata->spinlock); - /* sysfs needs to read and allocate a trace ID */ - ret = etm4_read_alloc_trace_id(drvdata); - if (ret < 0) - goto unlock_sysfs_enable; + drvdata->trcid = path->trace_id; /* * Executing etm4_enable_hw on the cpu whose ETM is being enabled @@ -864,7 +827,6 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) if (ret) etm4_release_trace_id(drvdata); -unlock_sysfs_enable: spin_unlock(&drvdata->spinlock); if (!ret) @@ -873,7 +835,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) } static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, - enum cs_mode mode, struct coresight_trace_id_map *id_map) + enum cs_mode mode, struct coresight_path *path) { int ret; @@ -884,10 +846,10 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, switch (mode) { case CS_MODE_SYSFS: - ret = etm4_enable_sysfs(csdev); + ret = etm4_enable_sysfs(csdev, path); break; case CS_MODE_PERF: - ret = etm4_enable_perf(csdev, event, id_map); + ret = etm4_enable_perf(csdev, event, path); break; default: ret = -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 1119762b5cec..2b92de17b5a2 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1066,6 +1066,5 @@ static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) return drvdata->arch >= ETM_ARCH_ETE; } -int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata); void etm4_release_trace_id(struct etmv4_drvdata *drvdata); #endif diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 76403530f33e..c10dd3643854 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -132,16 +132,16 @@ static inline void CS_UNLOCK(void __iomem *addr) } while (0); } -void coresight_disable_path(struct list_head *path); -int coresight_enable_path(struct list_head *path, enum cs_mode mode, +void coresight_disable_path(struct coresight_path *path); +int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, void *sink_data); -struct coresight_device *coresight_get_sink(struct list_head *path); +struct coresight_device *coresight_get_sink(struct coresight_path *path); struct coresight_device *coresight_get_sink_by_id(u32 id); struct coresight_device * coresight_find_default_sink(struct coresight_device *csdev); -struct list_head *coresight_build_path(struct coresight_device *csdev, +struct coresight_path *coresight_build_path(struct coresight_device *csdev, struct coresight_device *sink); -void coresight_release_path(struct list_head *path); +void coresight_release_path(struct coresight_path *path); int coresight_add_sysfs_link(struct coresight_sysfs_link *info); void coresight_remove_sysfs_link(struct coresight_sysfs_link *info); int coresight_create_conns_sysfs_group(struct coresight_device *csdev); @@ -152,6 +152,8 @@ int coresight_make_links(struct coresight_device *orig, void coresight_remove_links(struct coresight_device *orig, struct coresight_connection *conn); u32 coresight_get_sink_id(struct coresight_device *csdev); +int coresight_path_assign_trace_id(struct coresight_path *path, + enum cs_mode mode); #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) extern int etm_readl_cp14(u32 off, unsigned int *val); diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 64fcfa916562..0d4a9d325df4 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -194,8 +194,7 @@ static void stm_enable_hw(struct stm_drvdata *drvdata) } static int stm_enable(struct coresight_device *csdev, struct perf_event *event, - enum cs_mode mode, - __maybe_unused struct coresight_trace_id_map *trace_id) + enum cs_mode mode, struct coresight_path *path) { struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c index a01c9e54e2ed..c2b0a1f59d1a 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -22,7 +22,7 @@ static DEFINE_IDR(path_idr); * When operating Coresight drivers from the sysFS interface, only a single * path can exist from a tracer (associated to a CPU) to a sink. */ -static DEFINE_PER_CPU(struct list_head *, tracer_path); +static DEFINE_PER_CPU(struct coresight_path *, tracer_path); ssize_t coresight_simple_show_pair(struct device *_dev, struct device_attribute *attr, char *buf) @@ -53,7 +53,8 @@ ssize_t coresight_simple_show32(struct device *_dev, EXPORT_SYMBOL_GPL(coresight_simple_show32); static int coresight_enable_source_sysfs(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { int ret; @@ -64,7 +65,7 @@ static int coresight_enable_source_sysfs(struct coresight_device *csdev, */ lockdep_assert_held(&coresight_mutex); if (coresight_get_mode(csdev) != CS_MODE_SYSFS) { - ret = source_ops(csdev)->enable(csdev, data, mode, NULL); + ret = source_ops(csdev)->enable(csdev, NULL, mode, path); if (ret) return ret; } @@ -167,7 +168,7 @@ int coresight_enable_sysfs(struct coresight_device *csdev) { int cpu, ret = 0; struct coresight_device *sink; - struct list_head *path; + struct coresight_path *path; enum coresight_dev_subtype_source subtype; u32 hash; @@ -209,11 +210,15 @@ int coresight_enable_sysfs(struct coresight_device *csdev) goto out; } + ret = coresight_path_assign_trace_id(path, CS_MODE_SYSFS); + if (ret < 0) + goto err_path; + ret = coresight_enable_path(path, CS_MODE_SYSFS, NULL); if (ret) goto err_path; - ret = coresight_enable_source_sysfs(csdev, CS_MODE_SYSFS, NULL); + ret = coresight_enable_source_sysfs(csdev, CS_MODE_SYSFS, path); if (ret) goto err_source; @@ -262,7 +267,7 @@ EXPORT_SYMBOL_GPL(coresight_enable_sysfs); void coresight_disable_sysfs(struct coresight_device *csdev) { int cpu, ret; - struct list_head *path = NULL; + struct coresight_path *path = NULL; u32 hash; mutex_lock(&coresight_mutex); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index c38f9701665e..f0880a62028f 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -439,8 +439,7 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata) } static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, - enum cs_mode mode, - __maybe_unused struct coresight_trace_id_map *id_map) + enum cs_mode mode, struct coresight_path *path) { struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 70407d61262e..03d833a15726 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -329,6 +329,16 @@ static struct coresight_dev_list (var) = { \ #define to_coresight_device(d) container_of(d, struct coresight_device, dev) +/** + * struct coresight_path - data needed by enable/disable path + * @path: path from source to sink. + * @trace_id: trace_id of the whole path. + */ +struct coresight_path { + struct list_head *path_list; + u8 trace_id; +}; + enum cs_mode { CS_MODE_DISABLED, CS_MODE_SYSFS, @@ -393,7 +403,7 @@ struct coresight_ops_link { struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); int (*enable)(struct coresight_device *csdev, struct perf_event *event, - enum cs_mode mode, struct coresight_trace_id_map *id_map); + enum cs_mode mode, struct coresight_path *path); void (*disable)(struct coresight_device *csdev, struct perf_event *event); int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode, From patchwork Fri Feb 7 06:42:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 863373 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A2BB234986; Fri, 7 Feb 2025 06:43:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910608; cv=none; b=gw851WSI0n/7ZXqqsRko+0AkFUV5rLpJDtmyQ9Yij6t1kUMerMkgyzZQjH/XYyCuPEqcTqBphkSNbW6kUt7uDH33USlgkjkxdAUgVqDEApBXkpsFsBFw1yXvBgjUO/RmFCi9LF22Nf+xG51vbX3zJQ/jng6IYR+G4a5T/6ZnnF8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910608; c=relaxed/simple; bh=HEEcfnOq54LR0U51mqX/+LvcTri4c03Xzg8uUxcuZx0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uqlYZCzp3+t4W9UEBzAWKCTBV/KvoVAylbtBwfLwh2RC9eaeErAXVckAU8zcqO6Pg5Hw/YZbiH/eIiOgMJtcKArSY3TjI7haQxexVa3ijUCbLFMnTRvw5ySJJw4JctczTGZqFMUTsh8I+vLkVR95RFZr0ickjpbNYG/4W6CB3gI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ihrCrKS1; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ihrCrKS1" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5171Q5fD030930; Fri, 7 Feb 2025 06:43:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 9T6vDCQgh1gIYQoLsdnmEUZ+H4oulTkXaYpu8/f4F1Q=; b=ihrCrKS11bJ2gLjF L6IpE6h/IurQfSDp5m+iQte9MhG8iq2t6z1UG49fN5Cm4KkLt6nQbEdPWf09s0e8 +ZYL2z8eBmOHbbFdpbyGUHOh7HpWJaedyYKzqyzR6takUoB+5DK9MEFK1lPPqqF2 E7BinriJs1BUtuoX3ZuDkaPT0d8JlJaTSRiEJctLfJlwiQMa14UBxVnAstOWoem2 ad3qqy/4s79rFlprxkONQTvPeY548m6mgsPyxw5PL/XHRy5mnGE26aI6nY9J8+IF nMmrEpn1KOVeoQ3LvXJcRkYcvDoMdNWkdcyPDH6RO9GRlxZ2l/BejjANZhYXUxhL bsQEPg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44n2rt9d8w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 06:43:12 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5176hCjp002581 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 06:43:12 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 22:43:06 -0800 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Tingwei Zhang , Jinlong Mao , , , , , , Subject: [PATCH v10 5/7] dt-bindings: arm: Add Coresight TMC Control Unit hardware Date: Fri, 7 Feb 2025 14:42:11 +0800 Message-ID: <20250207064213.2314482-6-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250207064213.2314482-1-quic_jiegan@quicinc.com> References: <20250207064213.2314482-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: j3V40-ew2uHQvhKT9b_Gcy7-cW0Jt1vE X-Proofpoint-GUID: j3V40-ew2uHQvhKT9b_Gcy7-cW0Jt1vE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_03,2025-02-07_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 adultscore=2 bulkscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070050 Add binding file to specify how to define a Coresight TMC Control Unit device in device tree. It is responsible for controlling the data filter function based on the source device's Trace ID for TMC ETR device. The trace data with that Trace id can get into ETR's buffer while other trace data gets ignored. Reviewed-by: Rob Herring (Arm) Signed-off-by: Jie Gan --- .../bindings/arm/qcom,coresight-ctcu.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml new file mode 100644 index 000000000000..843b52eaf872 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight TMC Control Unit + +maintainers: + - Yuanfang Zhang + - Mao Jinlong + - Jie Gan + +description: | + The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB), + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations. + The configuration mode (ETB, ETF, ETR) is discovered at boot time when + the device is probed. + + The Coresight TMC Control unit controls various Coresight behaviors. + It works as a helper device when connected to TMC ETR device. + It is responsible for controlling the data filter function based on + the source device's Trace ID for TMC ETR device. The trace data with + that Trace id can get into ETR's buffer while other trace data gets + ignored. + +properties: + compatible: + enum: + - qcom,sa8775p-ctcu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-1])?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - in-ports + +additionalProperties: false + +examples: + - | + ctcu@1001000 { + compatible = "qcom,sa8775p-ctcu"; + reg = <0x1001000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ctcu_in_port0: endpoint { + remote-endpoint = <&etr0_out_port>; + }; + }; + + port@1 { + reg = <1>; + ctcu_in_port1: endpoint { + remote-endpoint = <&etr1_out_port>; + }; + }; + }; + }; From patchwork Fri Feb 7 06:42:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 863078 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 290BC198823; Fri, 7 Feb 2025 06:43:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910616; cv=none; b=N6FLWPevLUG1Z4tZ/gCJp6l0QrWTt1zfGemuxQQsIrNfteqT0oncqoU1dM3koB8x3cQrLiD9AzFIjocn91n3dODIpFTbsj95vbsyYrvlhFwA4vXob0OdSLbtcHv1cNRcEU9cg6+IPZJiCKCjB1judJtICitBMpcjD/V7FuGouR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910616; c=relaxed/simple; bh=F6M4HxWzO9jD/PTmMqQNUe4y5QhsoTOm8DxEGk7SpQQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bC5n04qc14E8gdGNl7+KETaBT6By43+6ksie4TgOBrsyfIE17u2O4PheVQLnv2e/LpDMOZOXimyWpauw4/Vbl9E5UcShGFjujAAQyQBW3PxSgJ8oP/Ok4j4WXO/CYeIhEB9iWdVK6ZRHYJQdCG3YQnaEEBTdXwYm/Bbo6COSuk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=D37OhRgL; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="D37OhRgL" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5175GkZp021200; Fri, 7 Feb 2025 06:43:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= PgS/JF5vYAYtclpRjmuYOE3IltrT4IQpDBT+7U19T00=; b=D37OhRgLWi+2MMu/ f/jj6zg5A3s92mQ6rKlkW9/15Y1Nt+17GCJCysdtmc++RNfPzTyECKqsFJmtL8g5 4PB2CfNh+MYSerMJ139w3PCDDNkteYVS/aOZSDrWqUZ1lIuO64QE6xzSHhd3RiVp mgMGCOCyBQGaExbTyi3tXzjfntxVde9w1AqGMhsZjjNTOju2CIE9T/PdpaiANims NyFp0Z4ff1ModqkUhVmYNGp3TW8Lbtw6IDJ0X4AeKhWTinQmA7Eutsg3RrIziFxv faAw/DIsGMbZplPeCLxWwqtsp1VkbOp804Igbtsf7p55JaEhsoz86ymFaQ2ByBoe YYhoUg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44nbvur5tc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 06:43:19 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5176hIpb002673 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 06:43:18 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 22:43:12 -0800 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Tingwei Zhang , Jinlong Mao , , , , , , Subject: [PATCH v10 6/7] Coresight: Add Coresight TMC Control Unit driver Date: Fri, 7 Feb 2025 14:42:12 +0800 Message-ID: <20250207064213.2314482-7-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250207064213.2314482-1-quic_jiegan@quicinc.com> References: <20250207064213.2314482-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Wkz9Yuy6Cx6Z6TAn231w8mulS3gY6FpF X-Proofpoint-ORIG-GUID: Wkz9Yuy6Cx6Z6TAn231w8mulS3gY6FpF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_03,2025-02-07_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 spamscore=0 impostorscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070051 The Coresight TMC Control Unit hosts miscellaneous configuration registers which control various features related to TMC ETR sink. Based on the trace ID, which is programmed in the related CTCU ATID register of a specific ETR, trace data with that trace ID gets into the ETR buffer, while other trace data gets dropped. Enabling source device sets one bit of the ATID register based on source device's trace ID. Disabling source device resets the bit according to the source device's trace ID. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/Kconfig | 12 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-ctcu.c | 268 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++ include/linux/coresight.h | 3 +- 5 files changed, 307 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 06f0a7594169..ecd7086a5b83 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -133,6 +133,18 @@ config CORESIGHT_STM To compile this driver as a module, choose M here: the module will be called coresight-stm. +config CORESIGHT_CTCU + tristate "CoreSight TMC Control Unit driver" + depends on CORESIGHT_LINK_AND_SINK_TMC + help + This driver provides support for CoreSight TMC Control Unit + that hosts miscellaneous configuration registers. This is + primarily used for controlling the behaviors of the TMC + ETR device. + + To compile this driver as a module, choose M here: the + module will be called coresight-ctcu. + config CORESIGHT_CPU_DEBUG tristate "CoreSight CPU Debug driver" depends on ARM || ARM64 diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 4ba478211b31..1b7869910a12 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/hwtracing/coresight/coresight-ctcu.c new file mode 100644 index 000000000000..e1460a627c4d --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-ctcu.h" +#include "coresight-priv.h" + +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); + +#define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->base + offset) +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset) + +/* + * The TMC Coresight Control Unit uses four ATID registers to control the data + * filter function based on the trace ID for each TMC ETR sink. The length of + * each ATID register is 32 bits. Therefore, the ETR has a related field in + * CTCU that is 128 bits long. Each trace ID is represented by one bit in that + * filed. + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5 + * bit5 + * ------------------------------------------------------ + * | |28| |24| |20| |16| |12| |8| 1|4| |0| + * ------------------------------------------------------ + * + * e.g. ETR0: + * 127 0 from ATID_offset for ETR0ATID0 + * ------------------------- + * |ATID3|ATID2|ATID1|ATID0| + */ +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \ + ((traceid / 32) * 4 + atid_offset) + +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32) +#define CTCU_ATID_REG_SIZE 0x10 + +struct ctcu_atid_config { + const u32 atid_offset; + const u32 port_num; +}; + +struct ctcu_config { + const struct ctcu_atid_config *atid_config; + int num_atid_config; +}; + +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = { + {0xf8, 0}, + {0x108, 1}, +}; + +static const struct ctcu_config sa8775p_cfgs = { + .atid_config = sa8775p_atid_cfgs, + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs), +}; + +static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset, + u8 bit, bool enable) +{ + u32 val; + + CS_UNLOCK(drvdata->base); + val = ctcu_readl(drvdata, reg_offset); + val = enable? (val | BIT(bit)) : (val & ~BIT(bit)); + ctcu_writel(drvdata, val, reg_offset); + CS_LOCK(drvdata->base); +} + +/* + * __ctcu_set_etr_traceid: Set bit in the ATID register based on trace ID when enable is true. + * Reset the bit of the ATID register based on trace ID when enable is false. + * + * @csdev: coresight_device struct related to the device + * @traceid: trace ID of the source tracer. + * @port_num: port number from TMC ETR sink. + * @enable: True for set bit and false for reset bit. + * + * Returns 0 indicates success. Non-zero result means failure. + */ +static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8 traceid, int port_num, + bool enable) +{ + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + u32 atid_offset, reg_offset; + u8 refcnt, bit; + + atid_offset = drvdata->atid_offset[port_num]; + if (atid_offset == 0) + return -EINVAL; + + bit = CTCU_ATID_REG_BIT(traceid); + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset); + if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE) + return -EINVAL; + + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); + refcnt = drvdata->traceid_refcnt[port_num][traceid]; + /* Only program the atid register when the refcnt value is 0 or 1 */ + if (enable && (++refcnt == 1)) + ctcu_program_atid_register(drvdata, reg_offset, bit, enable); + else if (!enable && (--refcnt == 0)) + ctcu_program_atid_register(drvdata, reg_offset, bit, enable); + + drvdata->traceid_refcnt[port_num][traceid] = refcnt; + + return 0; +} + +static int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper) +{ + int i; + + for (i = 0; i < sink->pdata->nr_outconns; ++i) { + if (sink->pdata->out_conns[i]->dest_dev) + return sink->pdata->out_conns[i]->dest_port; + } + + return -EINVAL; +} + +static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight_path *path, + bool enable) +{ + struct coresight_device *sink = coresight_get_sink(path); + u8 traceid = path->trace_id; + int port_num; + + if ((sink == NULL) || !IS_VALID_CS_TRACE_ID(traceid)) { + dev_err(&csdev->dev, "Invalid parameters\n"); + return -EINVAL; + } + + port_num = ctcu_get_active_port(sink, csdev); + if (port_num < 0) + return -EINVAL; + + dev_dbg(&csdev->dev, "traceid is %d\n", traceid); + + return __ctcu_set_etr_traceid(csdev, traceid, port_num, enable); +} + +static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, + void *data) +{ + struct coresight_path *path = (struct coresight_path *)data; + + return ctcu_set_etr_traceid(csdev, path, true); +} + +static int ctcu_disable(struct coresight_device *csdev, void *data) +{ + struct coresight_path *path = (struct coresight_path *)data; + + return ctcu_set_etr_traceid(csdev, path, false); +} + +static const struct coresight_ops_helper ctcu_helper_ops = { + .enable = ctcu_enable, + .disable = ctcu_disable, +}; + +static const struct coresight_ops ctcu_ops = { + .helper_ops = &ctcu_helper_ops, +}; + +static int ctcu_probe(struct platform_device *pdev) +{ + int i; + void __iomem *base; + struct device *dev = &pdev->dev; + struct coresight_platform_data *pdata; + struct ctcu_drvdata *drvdata; + struct coresight_desc desc = { 0 }; + const struct ctcu_config *cfgs; + const struct ctcu_atid_config *atid_cfg; + + desc.name = coresight_alloc_device_name(&ctcu_devs, dev); + if (!desc.name) + return -ENOMEM; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + pdata = coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + dev->platform_data = pdata; + + base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (!base) + return -ENOMEM; + + drvdata->apb_clk = coresight_get_enable_apb_pclk(dev); + if (IS_ERR(drvdata->apb_clk)) + return -ENODEV; + + cfgs = of_device_get_match_data(dev); + if (cfgs) { + if (cfgs->num_atid_config <= ATID_MAX_NUM) { + for (i = 0; i < cfgs->num_atid_config; i++) { + atid_cfg = &cfgs->atid_config[i]; + drvdata->atid_offset[i] = atid_cfg->atid_offset; + } + } + } + + drvdata->base = base; + drvdata->dev = dev; + platform_set_drvdata(pdev, drvdata); + + desc.type = CORESIGHT_DEV_TYPE_HELPER; + desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; + desc.pdata = pdata; + desc.dev = dev; + desc.ops = &ctcu_ops; + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) { + if (!IS_ERR_OR_NULL(drvdata->apb_clk)) + clk_put(drvdata->apb_clk); + + return PTR_ERR(drvdata->csdev); + } + + return 0; +} + +static void ctcu_remove(struct platform_device *pdev) +{ + struct ctcu_drvdata *drvdata = platform_get_drvdata(pdev); + + coresight_unregister(drvdata->csdev); + if (!IS_ERR_OR_NULL(drvdata->apb_clk)) + clk_put(drvdata->apb_clk); +} + +static const struct of_device_id ctcu_match[] = { + {.compatible = "qcom,sa8775p-ctcu", .data = &sa8775p_cfgs}, + {} +}; + +static struct platform_driver ctcu_driver = { + .probe = ctcu_probe, + .remove = ctcu_remove, + .driver = { + .name = "coresight-ctcu", + .of_match_table = ctcu_match, + .suppress_bind_attrs = true, + }, +}; +module_platform_driver(ctcu_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("CoreSight TMC Control Unit driver"); diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtracing/coresight/coresight-ctcu.h new file mode 100644 index 000000000000..9890c3da5ec8 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CORESIGHT_CTCU_H +#define _CORESIGHT_CTCU_H +#include "coresight-trace-id.h" + +/* Maximum number of supported sink devices for a single CTCU in current projects. */ +#define ATID_MAX_NUM 2 + +struct ctcu_drvdata { + void __iomem *base; + struct clk *apb_clk; + phys_addr_t pbase; + struct device *dev; + struct coresight_device *csdev; + raw_spinlock_t spin_lock; + u32 atid_offset[ATID_MAX_NUM]; + /* refcnt for each traceid of each sink */ + u8 traceid_refcnt[ATID_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; +}; +#endif diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 03d833a15726..55bb825d509e 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -71,7 +71,8 @@ enum coresight_dev_subtype_source { enum coresight_dev_subtype_helper { CORESIGHT_DEV_SUBTYPE_HELPER_CATU, - CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI + CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI, + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU, }; /** From patchwork Fri Feb 7 06:42:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 863372 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C01A71991CF; Fri, 7 Feb 2025 06:43:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910620; cv=none; b=M28cLh0yqKFjpqr54g9uMYdmQ0cqGYB10amwDCcjfSc0rPwCHLVi8BP2gIaY11x1SCzR3TeY854+fNoOqCcO0JjGbnvVnFuIPyRlU1ykEt0eCHtrS/Lq7O1SHsNnSA4lWKIevKP+OBYCnc13koaQtX6ZCRDCb2K0ZjA12P7CieY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738910620; c=relaxed/simple; bh=tYFvJAC+E6lq1I465BOU8f0pSMGntQzDYaPmWQtwSuc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tJdrF7M1gajOnZ2iUokrTeMXghBCZmvI4Ciwq0qC+CaLUaBvWOwvYW4vxn58nS7SU4dv39X2uPErwyHADlL9RS5NAJhBNNhwuvHfkgBvNMg0o93abGDH4WllpznUtBEzJSgVfFW1hnLETMi7XjFhpfm9ML3uNzEwDL1Tw7zDmHk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Zp/NzhxE; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Zp/NzhxE" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5171PXai029939; Fri, 7 Feb 2025 06:43:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= FrWpXWtpt+ZULEbiR2Up6sVFlN84+mzhnBc7WKp2O/Q=; b=Zp/NzhxE7qzl2Tj1 D+l8iuuWY1/LI85ZnLKykQiD3wcYgipaeUjyJLAPOyXxq5MSC7wZK7KX36OdK0xq 25zooswxVwp6jNLWIRhn+EFBj7lc7dqyO1rACp7MV/z6svFvfIy4mMcm+m4VVLAu s8uBS9BfSIdnNu5piVA9wgV7cJ+1ltcoIGPFpvJDNOiJRBo0tKwGxQANqD1Pqi9S YIDDxkpJxtmQIzSbha3LspVetHlDl15V2pe44SbZM9Kfhw660NynOt4RcWwH7jCH fS3RlfPnjkbXq7S+RFDIQAQ78KwsWmw5EU4uJF46ZceRzObfGfC9Lrj8WRc+hQhi Yea/4A== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44n2rt9d9g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 06:43:25 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5176hO5f002778 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 06:43:24 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 22:43:18 -0800 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Tingwei Zhang , Jinlong Mao , , , , , , , Konrad Dybcio Subject: [PATCH v10 7/7] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes Date: Fri, 7 Feb 2025 14:42:13 +0800 Message-ID: <20250207064213.2314482-8-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250207064213.2314482-1-quic_jiegan@quicinc.com> References: <20250207064213.2314482-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fkU6W8CiK_QDSDrOT9g65MHIA69xApnY X-Proofpoint-GUID: fkU6W8CiK_QDSDrOT9g65MHIA69xApnY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_03,2025-02-07_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 adultscore=0 bulkscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070050 Add CTCU and ETR nodes in DT to enable related functionalities. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 153 ++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 3394ae2d1300..31aa94d2a043 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2429,6 +2429,35 @@ crypto: crypto@1dfa000 { interconnect-names = "memory"; }; + ctcu@4001000 { + compatible = "qcom,sa8775p-ctcu"; + reg = <0x0 0x04001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&etr1_out>; + }; + }; + }; + }; + stm: stm@4002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x4002000 0x0 0x1000>, @@ -2633,6 +2662,122 @@ qdss_funnel_in1: endpoint { }; }; + replicator@4046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x04046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = <&etr_rep_in>; + }; + }; + }; + }; + + tmc_etr: tmc@4048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x04048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04c0 0x00>; + + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@404e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x0404e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + etr_rep_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + etr_rep_out1: endpoint { + remote-endpoint = <&etr1_in>; + }; + }; + }; + }; + + tmc_etr1: tmc@404f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x0404f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04a0 0x40>; + + arm,scatter-gather; + arm,buffer-size = <0x400000>; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + funnel@4b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x4b04000 0x0 0x1000>; @@ -2708,6 +2853,14 @@ out-ports { #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; swao_rep_out1: endpoint {