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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/12] target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation Date: Mon, 10 Feb 2025 15:49:31 +0000 Message-Id: <20250210154942.3634878-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The pxa2xx CPUs are now only useful with user-mode emulation, because we dropped all the machine types that used them in 9.2. (Technically you could alse use "-cpu pxa270" with a board model like versatilepb which doesn't sanity-check the CPU type, but that has never been a supported config.) To use them (or iwMMXt emulation) with QEMU user-mode you would need to explicitly select them with the -cpu option or the QEMU_CPU environment variable. A google search finds no examples of anybody doing this in the last decade; I don't believe the GCC folks are using QEMU to test their iwMMXt codegen either. In fact, GCC is in the process of dropping support for iwMMXT entirely. The iwMMXt emulation is thousands of lines of code in QEMU, and is now the only bit of Arm insn decode which doesn't use decodetree. We have no way to test or validate changes to it. This code is just dead weight that is almost certainly not being used by anybody. Mark it as deprecated. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250127112715.2936555-2-peter.maydell@linaro.org --- docs/about/deprecated.rst | 21 +++++++++++++++++++++ target/arm/cpu.h | 1 + target/arm/cpu.c | 3 +++ target/arm/tcg/cpu32.c | 36 ++++++++++++++++++++++++------------ 4 files changed, 49 insertions(+), 12 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 4a3c302962a..29de49351d1 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -204,6 +204,27 @@ is going to be so much slower it wouldn't make sense for any serious instrumentation. Due to implementation differences there will also be anomalies in things like memory instrumentation. +linux-user mode CPUs +-------------------- + +iwMMXt emulation and the ``pxa`` CPUs (since 10.0) +'''''''''''''''''''''''''''''''''''''''''''''''''' + +The ``pxa`` CPU family (``pxa250``, ``pxa255``, ``pxa260``, +``pxa261``, ``pxa262``, ``pxa270-a0``, ``pxa270-a1``, ``pxa270``, +``pxa270-b0``, ``pxa270-b1``, ``pxa270-c0``, ``pxa270-c5``) are no +longer used in system emulation, because all the machine types which +used these CPUs were removed in the QEMU 9.2 release. These CPUs can +now only be used in linux-user mode, and to do that you would have to +explicitly select one of these CPUs with the ``-cpu`` command line +option or the ``QEMU_CPU`` environment variable. + +We don't believe that anybody is using the iwMMXt emulation, and we do +not have any tests to validate it or any real hardware or similar +known-good implementation to test against. GCC is in the process of +dropping their support for iwMMXt codegen. These CPU types are +therefore deprecated in QEMU, and will be removed in a future release. + System emulator CPUs -------------------- diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2213c277348..c2d2d99b462 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1118,6 +1118,7 @@ struct ArchCPU { typedef struct ARMCPUInfo { const char *name; + const char *deprecation_note; void (*initfn)(Object *obj); void (*class_init)(ObjectClass *oc, void *data); } ARMCPUInfo; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a83b9ee34f..32dc7c1e692 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2758,6 +2758,9 @@ static void cpu_register_class_init(ObjectClass *oc, void *data) acc->info = data; cc->gdb_core_xml_file = "arm-core.xml"; + if (acc->info->deprecation_note) { + cc->deprecation_note = acc->info->deprecation_note; + } } void arm_cpu_register(const ARMCPUInfo *info) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 2ad21825255..0f1c5bc87e8 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -1026,19 +1026,31 @@ static const ARMCPUInfo arm_tcg_cpus[] = { { .name = "ti925t", .initfn = ti925t_initfn }, { .name = "sa1100", .initfn = sa1100_initfn }, { .name = "sa1110", .initfn = sa1110_initfn }, - { .name = "pxa250", .initfn = pxa250_initfn }, - { .name = "pxa255", .initfn = pxa255_initfn }, - { .name = "pxa260", .initfn = pxa260_initfn }, - { .name = "pxa261", .initfn = pxa261_initfn }, - { .name = "pxa262", .initfn = pxa262_initfn }, + { .name = "pxa250", .initfn = pxa250_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, + { .name = "pxa255", .initfn = pxa255_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, + { .name = "pxa260", .initfn = pxa260_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, + { .name = "pxa261", .initfn = pxa261_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, + { .name = "pxa262", .initfn = pxa262_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, /* "pxa270" is an alias for "pxa270-a0" */ - { .name = "pxa270", .initfn = pxa270a0_initfn }, - { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, - { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, - { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, - { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, - { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, - { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, + { .name = "pxa270", .initfn = pxa270a0_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, + { .name = "pxa270-a0", .initfn = pxa270a0_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, + { .name = "pxa270-a1", .initfn = pxa270a1_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, + { .name = "pxa270-b0", .initfn = pxa270b0_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, + { .name = "pxa270-b1", .initfn = pxa270b1_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, + { .name = "pxa270-c0", .initfn = pxa270c0_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, + { .name = "pxa270-c5", .initfn = pxa270c5_initfn, + .deprecation_note = "iwMMXt CPUs are no longer supported", }, #ifndef TARGET_AARCH64 { .name = "max", .initfn = arm_max_initfn }, #endif From patchwork Mon Feb 10 15:49:32 2025 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/12] tests/tcg/arm: Remove test-arm-iwmmxt test Date: Mon, 10 Feb 2025 15:49:32 +0000 Message-Id: <20250210154942.3634878-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The test-arm-iwmmmxt test isn't testing what it thinks it's testing. If you run it with a CPU type that supports iwMMXt then it will crash immediately with a SIGILL, because (even with -marm) GCC will link it against startup code that is in Thumb mode, and no iwMMXt CPU has Thumb: 00010338 <_start>: 10338: f04f 0b00 mov.w fp, #0 1033c: f04f 0e00 mov.w lr, #0 If you run it with a CPU type which does *not* support iwMMXt, which is what 'make check-tcg' does, then QEMU will not try to handle the insns as iwMMXt. Instead the translator turns them into illegal instructions. Then in the linux-user cpu_loop() code we identify them as FPA11 instructions inside emulate_arm_fpa11(), because the FPA11 happened to use the same coprocessor number as these iwMMXt insns. So we execute a completely different set of FPA11 insns, which means we don't crash, but we will print garbage to stdout. Then the test binary always exits with a 0 return code, so 'make check-tcg' thinks the test passes. Modern gnueabihf toolchains assume in their startup code that the CPU is not so old as to not support Thumb, so there's no way to get them to generate a binary that actually does what the test wants. Since we're deprecating iwMMXt emulation anyway, it's not worth trying to salvage the test case to get it to really test the iwMMXt insns. Delete the test entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250127112715.2936555-3-peter.maydell@linaro.org --- tests/tcg/arm/Makefile.target | 7 ----- tests/tcg/arm/README | 5 ---- tests/tcg/arm/test-arm-iwmmxt.S | 49 --------------------------------- 3 files changed, 61 deletions(-) delete mode 100644 tests/tcg/arm/test-arm-iwmmxt.S diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 06ddf3e04fc..99a953b6671 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -20,13 +20,6 @@ ARM_TESTS = hello-arm hello-arm: CFLAGS+=-marm -ffreestanding -fno-stack-protector hello-arm: LDFLAGS+=-nostdlib -# IWMXT floating point extensions -ARM_TESTS += test-arm-iwmmxt -# Clang assembler does not support IWMXT, so use the external assembler. -test-arm-iwmmxt: CFLAGS += -marm -march=iwmmxt -mabi=aapcs -mfpu=fpv4-sp-d16 $(CROSS_CC_HAS_FNIA) -test-arm-iwmmxt: test-arm-iwmmxt.S - $(CC) $(CFLAGS) -Wa,--noexecstack $< -o $@ $(LDFLAGS) - # Float-convert Tests ARM_TESTS += fcvt fcvt: LDFLAGS += -lm diff --git a/tests/tcg/arm/README b/tests/tcg/arm/README index e6307116e23..aceccc127f7 100644 --- a/tests/tcg/arm/README +++ b/tests/tcg/arm/README @@ -4,8 +4,3 @@ hello-arm --------- A very simple inline assembly, write syscall based hello world - -test-arm-iwmmxt ---------------- - -A simple test case for older iwmmxt extended ARMs diff --git a/tests/tcg/arm/test-arm-iwmmxt.S b/tests/tcg/arm/test-arm-iwmmxt.S deleted file mode 100644 index d647f9404ae..00000000000 --- a/tests/tcg/arm/test-arm-iwmmxt.S +++ /dev/null @@ -1,49 +0,0 @@ -@ Checks whether iwMMXt is functional. -.code 32 -.globl main - -main: -ldr r0, =data0 -ldr r1, =data1 -ldr r2, =data2 -#ifndef FPA -wldrd wr0, [r0, #0] -wldrd wr1, [r0, #8] -wldrd wr2, [r1, #0] -wldrd wr3, [r1, #8] -wsubb wr2, wr2, wr0 -wsubb wr3, wr3, wr1 -wldrd wr0, [r2, #0] -wldrd wr1, [r2, #8] -waddb wr0, wr0, wr2 -waddb wr1, wr1, wr3 -wstrd wr0, [r2, #0] -wstrd wr1, [r2, #8] -#else -ldfe f0, [r0, #0] -ldfe f1, [r0, #8] -ldfe f2, [r1, #0] -ldfe f3, [r1, #8] -adfdp f2, f2, f0 -adfdp f3, f3, f1 -ldfe f0, [r2, #0] -ldfe f1, [r2, #8] -adfd f0, f0, f2 -adfd f1, f1, f3 -stfe f0, [r2, #0] -stfe f1, [r2, #8] -#endif -mov r0, #1 -mov r1, r2 -mov r2, #0x11 -swi #0x900004 -mov r0, #0 -swi #0x900001 - -.data -data0: -.string "aaaabbbbccccdddd" -data1: -.string "bbbbccccddddeeee" -data2: -.string "hvLLWs\x1fsdrs9\x1fNJ-\n" From patchwork Mon Feb 10 15:49:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 863778 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp1661392wrt; Mon, 10 Feb 2025 07:51:12 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWaP3EZSTMVuqipP+l/sB7ZyDHAuenyNA3uFC4+jBGfhVXWZGN5+iCg1FdOrw3uFgtCkxmY9w==@linaro.org X-Google-Smtp-Source: AGHT+IHcguAlCxlUCdRCaMy74Yu9Z7rcBJstwsXgHR2OqtEzZoS7eMpGQJ+GYqHVoXSJcCTmBdwW X-Received: by 2002:a05:622a:180a:b0:467:5d5d:fabf with SMTP id d75a77b69052e-47167a24a29mr213166211cf.25.1739202672279; Mon, 10 Feb 2025 07:51:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739202672; cv=none; d=google.com; s=arc-20240605; b=PDQRXEifkIxmNWxIQufZVaSiWpSfSM8HkNK2vj8BV71Ge7ylLsszbKI3sMXoaB/1I8 fa2nNIHmZ0iJ5okmSvWLVCs1wKHx4DHjQmOWjlquAz4P2bC3I9KNIbbPiCdkadEwoyZT W2yjlaJ+KuG38KqHCxO2LdjxcHbSKpaIL9R+EnzwNp4FP5cooTrl8PP9khTCmQllho+4 nYRhWH/nLRbzGwfqoO7MDIYOyaSibLZHCEcrSEieA2obug8sg01bhv9ljm6vl8etuWaj BSdVd8/jTvJut4i3czEf1UeJpD+vTurmiDx5KofwzTuWXYe6lyEqdZJJIaXUvYGPKZn0 jngA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FO85tXvs/pUPFn5N5WJ2viYG9RIRLbfEX4UNIOcXTy8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=WLApwUZD8FYuSIwaF2HfrS8Lv4TtUP5rVlNtmGyV0U0c5fJZtd9xbb0IqKL0ppVuuv m/tDMm6bPC/lR7op1XqrNYN0t4kFQjhIUgJ7WEz16+SfASGhKX1htObp4RxRzEkeKx7Z exvZpzRzJY36q2uX7tgJLviA50r0gen8su5QWghEZsjnAHl2KcjtbPKdk3b/Ezz/wIlT CrY+Yr7MjtVixs9i+xjSYIJowkukuBM0vFirxkWM8G8uMs8DsNi9g05ChoblABv2BU8M 7Ac/H0JkU6Zt1SfO3ScVOW6/03YJWsagpce9Q0PXe2n7hJXNHDHpHEsoaHdBgoXV8Qrm KfBA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hbsu1lHU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/12] target/arm: Drop unused AArch64DecodeTable typedefs Date: Mon, 10 Feb 2025 15:49:33 +0000 Message-Id: <20250210154942.3634878-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We removed the old table-based decoder in favour of decodetree, but we left a couple of typedefs that are now unused; delete them. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20250128135046.4108775-1-peter.maydell@linaro.org --- target/arm/tcg/translate-a64.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 0b76a2cdb78..d6ac2ed418a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -75,17 +75,6 @@ static int scale_by_log2_tag_granule(DisasContext *s, int x) #include "decode-sme-fa64.c.inc" #include "decode-a64.c.inc" -/* Table based decoder typedefs - used when the relevant bits for decode - * are too awkwardly scattered across the instruction (eg SIMD). - */ -typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn); - -typedef struct AArch64DecodeTable { - uint32_t pattern; - uint32_t mask; - AArch64DecodeFn *disas_fn; -} AArch64DecodeTable; - /* initialize TCG globals. */ void a64_translate_init(void) { From patchwork Mon Feb 10 15:49:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 863776 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp1661057wrt; Mon, 10 Feb 2025 07:50:29 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUEaH7fbRZw/K/BVLTBJ6MeCmXnyOSHs7b7iH7zMs9Oo6YRWokuSl+7EAl7KdHTtxvyq7BV4Q==@linaro.org X-Google-Smtp-Source: AGHT+IHJiqUrdt8xhKWm3E5lab0PosYS6avxXF8RybwXGnqJeCZIEsRvEEXJH5BFLiWZkP6BXrWp X-Received: by 2002:ac8:5ac4:0:b0:466:8819:6fa5 with SMTP id d75a77b69052e-47167a0c88fmr189619891cf.15.1739202629322; Mon, 10 Feb 2025 07:50:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739202629; cv=none; d=google.com; s=arc-20240605; b=Svflm50PggAW+GX7uDxy8Dp/R0OhYhursVZpyYBCvKKQT7Vnap2VTBXkz5pL9yQFUJ 0PQqDxILujAPj8MLdEbH7veLiZVjOdJOBrrSQBY+CYKW3nEJDES64zRUybVGCVH/fjDm 2wXieZKpyHreGlwU840Z0Hu+9WZczVLoKtx7VB3fL6DeC4gejcaZVwX19/MfeaAjLaQp xMtw95VeW4Kp4kfmusFWB7Nw3Sas6zwushOJ6LmSgitbGe7JTiJhRjsMxibeWfr/0mz/ oIbfVfih1RCE9mY+gNcgyFlMTj56LC/mkkK1ChUyyH9Ma4PO4kJQ5a2lrle445g8MLoZ JFqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hQ//IdqEgE6/omsnCXSjledOx7ZAm6kjJCgkts3JmS8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=EsVVGcbGPv4tG0mmfxpRx6vHdsysD+6sffn5QGVoEn9EU4vAbqt4BGRlrGrQYGEEfG CzLemTBCrdkZYHZlfN/n93jDOsjfxUwTH9yQnelelKavK36O5B/yzgdW54FlKWQdg4mp RcNTHdda43FYWmlsMbtXaFGS9M+PJVC0vU2N2ZhEFSRXQ+jMng3QBTmZej/9r6bL4dL/ XqqXcpW52doxFQal9imHtU/W1aUtPbgNsDSwm9q/W/xf7VxOmbUz8ohOP4ymFVtsVZBK q3EgDeSVVfEN7jv4UDtVzZGknRKFC2SYO5F6MZuwSGYsR8kW3I9MtHyixF+k41zsWtsA E8og==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y9XY6+OE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/12] hw/arm/boot: Propagate vCPU to arm_load_dtb() Date: Mon, 10 Feb 2025 15:49:34 +0000 Message-Id: <20250210154942.3634878-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé In heterogeneous setup the first vCPU might not be the one expected, better pass it explicitly. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Message-id: 20250130112615.3219-2-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/boot.h | 4 +++- hw/arm/boot.c | 11 ++++++----- hw/arm/virt.c | 2 +- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index 80c492d7421..b12bf61ca81 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -160,6 +160,7 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu, * @binfo: struct describing the boot environment * @addr_limit: upper limit of the available memory area at @addr * @as: address space to load image to + * @cpu: ARM CPU object * * Load a device tree supplied by the machine or by the user with the * '-dtb' command line option, and put it at offset @addr in target @@ -176,7 +177,8 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu, * Note: Must not be called unless have_dtb(binfo) is true. */ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, - hwaddr addr_limit, AddressSpace *as, MachineState *ms); + hwaddr addr_limit, AddressSpace *as, MachineState *ms, + ARMCPU *cpu); /* Write a secure board setup routine with a dummy handler for SMCs */ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, diff --git a/hw/arm/boot.c b/hw/arm/boot.c index cbc24356fc1..42c18355e85 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -432,13 +432,12 @@ out: return ret; } -static void fdt_add_psci_node(void *fdt) +static void fdt_add_psci_node(void *fdt, ARMCPU *armcpu) { uint32_t cpu_suspend_fn; uint32_t cpu_off_fn; uint32_t cpu_on_fn; uint32_t migrate_fn; - ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); const char *psci_method; int64_t psci_conduit; int rc; @@ -512,7 +511,8 @@ static void fdt_add_psci_node(void *fdt) } int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, - hwaddr addr_limit, AddressSpace *as, MachineState *ms) + hwaddr addr_limit, AddressSpace *as, MachineState *ms, + ARMCPU *cpu) { void *fdt = NULL; int size, rc, n = 0; @@ -655,7 +655,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, } } - fdt_add_psci_node(fdt); + fdt_add_psci_node(fdt, cpu); if (binfo->modify_dtb) { binfo->modify_dtb(binfo, fdt); @@ -1327,7 +1327,8 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) * decided whether to enable PSCI and set the psci-conduit CPU properties. */ if (!info->skip_dtb_autoload && have_dtb(info)) { - if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { + if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, + as, ms, cpu) < 0) { exit(1); } } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99e0a68b6c5..d23b14718af 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1746,7 +1746,7 @@ void virt_machine_done(Notifier *notifier, void *data) vms->memmap[VIRT_PLATFORM_BUS].size, vms->irqmap[VIRT_PLATFORM_BUS]); } - if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { + if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) { exit(1); } From patchwork Mon Feb 10 15:49:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 863777 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp1661314wrt; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/12] hw/arm/fsl-imx6: Add local 'mpcore/gic' variables Date: Mon, 10 Feb 2025 15:49:35 +0000 Message-Id: <20250210154942.3634878-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The A9MPCore forward the IRQs from its internal GIC. To make the code clearer, add the 'mpcore' and 'gic' variables. Reviewed-by: Cédric Le Goater Signed-off-by: Philippe Mathieu-Daudé Message-id: 20250130112615.3219-3-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/fsl-imx6.c | 52 +++++++++++++++++++---------------------------- 1 file changed, 21 insertions(+), 31 deletions(-) diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 88b9ccff493..dc86338b3a5 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -117,6 +117,8 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) uint16_t i; qemu_irq irq; unsigned int smp_cpus = ms->smp.cpus; + DeviceState *mpcore = DEVICE(&s->a9mpcore); + DeviceState *gic; if (smp_cpus > FSL_IMX6_NUM_CPUS) { error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", @@ -143,21 +145,21 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) } } - object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus, - &error_abort); + object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort); - object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", + object_property_set_int(OBJECT(mpcore), "num-irq", FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) { + if (!sysbus_realize(SYS_BUS_DEVICE(mpcore), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); + gic = mpcore; for (i = 0; i < smp_cpus; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, + sysbus_connect_irq(SYS_BUS_DEVICE(gic), i, qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, + sysbus_connect_irq(SYS_BUS_DEVICE(gic), i + smp_cpus, qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); } @@ -195,8 +197,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - serial_table[i].irq)); + qdev_get_gpio_in(gic, serial_table[i].irq)); } s->gpt.ccm = IMX_CCM(&s->ccm); @@ -207,8 +208,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - FSL_IMX6_GPT_IRQ)); + qdev_get_gpio_in(gic, FSL_IMX6_GPT_IRQ)); /* Initialize all EPIT timers */ for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { @@ -228,8 +228,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - epit_table[i].irq)); + qdev_get_gpio_in(gic, epit_table[i].irq)); } /* Initialize all I2C */ @@ -249,8 +248,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - i2c_table[i].irq)); + qdev_get_gpio_in(gic, i2c_table[i].irq)); } /* Initialize all GPIOs */ @@ -307,11 +305,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - gpio_table[i].irq_low)); + qdev_get_gpio_in(gic, gpio_table[i].irq_low)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - gpio_table[i].irq_high)); + qdev_get_gpio_in(gic, gpio_table[i].irq_high)); } /* Initialize all SDHC */ @@ -338,8 +334,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - esdhc_table[i].irq)); + qdev_get_gpio_in(gic, esdhc_table[i].irq)); } /* USB */ @@ -360,8 +355,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, FSL_IMX6_USBOH3_USB_ADDR + i * 0x200); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - FSL_IMX6_USBn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6_USBn_IRQ[i])); } /* Initialize all ECSPI */ @@ -384,8 +378,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - spi_table[i].irq)); + qdev_get_gpio_in(gic, spi_table[i].irq)); } object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, @@ -396,11 +389,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - FSL_IMX6_ENET_MAC_IRQ)); + qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - FSL_IMX6_ENET_MAC_1588_IRQ)); + qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_1588_IRQ)); /* * SNVS @@ -427,8 +418,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a9mpcore), - FSL_IMX6_WDOGn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6_WDOGn_IRQ[i])); } /* From patchwork Mon Feb 10 15:49:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 863783 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp1661951wrt; Mon, 10 Feb 2025 07:52:31 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXxFDlqNtVBUGk2Sf9enPBR/n7oEyV6CEnvwKLAlcz8HWWhNEaDN4KPjTluDQK8LyzHoG3w0Q==@linaro.org X-Google-Smtp-Source: AGHT+IHStv2rMOUsA84B40CgpT4bQJfcIqw3hK162EbIJqNaL+JstHaNegN11EOpuHCqqD/gPL9j X-Received: by 2002:a05:620a:2726:b0:7ad:832a:4063 with SMTP id af79cd13be357-7c047c1f58fmr2553233585a.7.1739202750868; Mon, 10 Feb 2025 07:52:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739202750; cv=none; d=google.com; s=arc-20240605; b=hJ/KeN074wV1rVUcifUqY+OA31RuuMXJhtz1k41zo48Qy2hh5bXaHkS9tMY3jIJFUz zLTIGQhmKhL+gPq9RgtckuRGlfkBbqpTeAD3f1tmYyVixlM9A2nvQrgFPAshV9xMEPq3 LaubwAK6xbxdNG7wlVTVDh6BHpPfTc/n4+hJpgaOSAvs7m+4pTKrnThUT9WONneDS8sf JA0ZcaBhyjyCzP0yFd86kzdYvTsBkgLjgaArOsqC0z3aF/p7c4wrfoRKtGy6+8DybaUL zATXm5EBXWK7puMmWtQJKTmZjgx6D0bcmc/IstIqCQPJauU0vGeyh0Uk6M0p2owhzpEh ByQQ== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/12] hw/arm/fsl-imx6ul: Add local 'mpcore/gic' variables Date: Mon, 10 Feb 2025 15:49:36 +0000 Message-Id: <20250210154942.3634878-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The A7MPCore forward the IRQs from its internal GIC. To make the code clearer, add the 'mpcore' and 'gic' variables. Rename 'd' variable as 'cpu'. Reviewed-by: Cédric Le Goater Signed-off-by: Philippe Mathieu-Daudé Message-id: 20250130112615.3219-4-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/fsl-imx6ul.c | 64 +++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 37 deletions(-) diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 79e4847953a..34c4aa15cd0 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -157,10 +157,12 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) { MachineState *ms = MACHINE(qdev_get_machine()); FslIMX6ULState *s = FSL_IMX6UL(dev); + DeviceState *mpcore = DEVICE(&s->a7mpcore); int i; char name[NAME_SIZE]; - SysBusDevice *sbd; - DeviceState *d; + DeviceState *gic; + SysBusDevice *gicsbd; + DeviceState *cpu; if (ms->smp.cpus > 1) { error_setg(errp, "%s: Only a single CPU is supported (%d requested)", @@ -173,19 +175,19 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) /* * A7MPCORE */ - object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", 1, &error_abort); - object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", + object_property_set_int(OBJECT(mpcore), "num-cpu", 1, &error_abort); + object_property_set_int(OBJECT(mpcore), "num-irq", FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); + sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); - sbd = SYS_BUS_DEVICE(&s->a7mpcore); - d = DEVICE(&s->cpu); - - sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ)); - sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ)); - sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ)); - sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ)); + gic = mpcore; + gicsbd = SYS_BUS_DEVICE(gic); + cpu = DEVICE(&s->cpu); + sysbus_connect_irq(gicsbd, 0, qdev_get_gpio_in(cpu, ARM_CPU_IRQ)); + sysbus_connect_irq(gicsbd, 1, qdev_get_gpio_in(cpu, ARM_CPU_FIQ)); + sysbus_connect_irq(gicsbd, 2, qdev_get_gpio_in(cpu, ARM_CPU_VIRQ)); + sysbus_connect_irq(gicsbd, 3, qdev_get_gpio_in(cpu, ARM_CPU_VFIQ)); /* * A7MPCORE DAP @@ -244,8 +246,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_GPTn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_GPTn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_GPTn_IRQ[i])); } /* @@ -269,8 +270,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_EPITn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_EPITn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_EPITn_IRQ[i])); } /* @@ -307,12 +307,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_GPIOn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_GPIOn_LOW_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_LOW_IRQ[i])); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_GPIOn_HIGH_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_HIGH_IRQ[i])); } /* @@ -366,8 +364,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_SPIn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_SPIn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_SPIn_IRQ[i])); } /* @@ -392,8 +389,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_I2Cn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_I2Cn_IRQ[i])); } /* @@ -430,8 +426,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_UARTn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_UARTn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_UARTn_IRQ[i])); } /* @@ -480,12 +475,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_ENETn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_ENETn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_ENETn_IRQ[i])); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_ENETn_TIMER_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_ENETn_TIMER_IRQ[i])); } /* @@ -521,8 +514,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, FSL_IMX6UL_USB02_USBn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_USBn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_USBn_IRQ[i])); } /* @@ -547,8 +539,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_USDHCn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_USDHCn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_USDHCn_IRQ[i])); } /* @@ -580,8 +571,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6UL_WDOGn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX6UL_WDOGn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX6UL_WDOGn_IRQ[i])); } /* From patchwork Mon Feb 10 15:49:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 863786 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp1662376wrt; Mon, 10 Feb 2025 07:53:28 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXePifxK/MwWx+FvXXuDnRey20LGz9KGLE5MphO6bK3Taopun9n0ymF/Kbig9xzkpqnYZ8jPQ==@linaro.org X-Google-Smtp-Source: AGHT+IFCrf71ElCol2DpbwsCZeniN7aNfSnLEVA7tBbjANL3URxiPYBFD57vTTHDwUgD70qSaWuC X-Received: by 2002:a05:622a:8e02:b0:471:8c1b:7e33 with SMTP id d75a77b69052e-4718c1b81cbmr47100321cf.33.1739202807874; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/12] hw/arm/fsl-imx7: Add local 'mpcore/gic' variables Date: Mon, 10 Feb 2025 15:49:37 +0000 Message-Id: <20250210154942.3634878-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The A7MPCore forward the IRQs from its internal GIC. To make the code clearer, add the 'mpcore' and 'gic' variables. Reviewed-by: Cédric Le Goater Signed-off-by: Philippe Mathieu-Daudé Message-id: 20250130112615.3219-5-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/fsl-imx7.c | 52 +++++++++++++++++++++-------------------------- 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 004bf499376..3374018cde0 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -166,7 +166,8 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) { MachineState *ms = MACHINE(qdev_get_machine()); FslIMX7State *s = FSL_IMX7(dev); - Object *o; + DeviceState *mpcore = DEVICE(&s->a7mpcore); + DeviceState *gic; int i; qemu_irq irq; char name[NAME_SIZE]; @@ -182,7 +183,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) * CPUs */ for (i = 0; i < smp_cpus; i++) { - o = OBJECT(&s->cpu[i]); + Object *o = OBJECT(&s->cpu[i]); /* On uniprocessor, the CBAR is set to 0 */ if (smp_cpus > 1) { @@ -205,16 +206,15 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) /* * A7MPCORE */ - object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", smp_cpus, - &error_abort); - object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", + object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort); + object_property_set_int(OBJECT(mpcore), "num-irq", FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort); + sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX7_A7MPCORE_ADDR); - sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR); - + gic = mpcore; for (i = 0; i < smp_cpus; i++) { - SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); + SysBusDevice *sbd = SYS_BUS_DEVICE(gic); DeviceState *d = DEVICE(qemu_get_cpu(i)); irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); @@ -255,8 +255,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_GPTn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_GPTn_IRQ[i])); } /* @@ -298,12 +297,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) FSL_IMX7_GPIOn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_GPIOn_LOW_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_LOW_IRQ[i])); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_GPIOn_HIGH_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_HIGH_IRQ[i])); } /* @@ -355,8 +352,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, FSL_IMX7_SPIn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_SPIn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_SPIn_IRQ[i])); } /* @@ -381,8 +377,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_I2Cn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_I2Cn_IRQ[i])); } /* @@ -416,7 +411,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]); + irq = qdev_get_gpio_in(gic, FSL_IMX7_UARTn_IRQ[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq); } @@ -454,9 +449,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0)); + irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3)); + irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 3)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq); } @@ -483,7 +478,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, FSL_IMX7_USDHCn_ADDR[i]); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]); + irq = qdev_get_gpio_in(gic, FSL_IMX7_USDHCn_IRQ[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq); } @@ -522,8 +517,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_WDOGn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_WDOGn_IRQ[i])); } /* @@ -606,11 +600,11 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_MSI_IRQ); qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ); + irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTA_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ); + irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTB_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ); + irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTC_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); @@ -643,7 +637,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, FSL_IMX7_USBn_ADDR[i]); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]); + irq = qdev_get_gpio_in(gic, FSL_IMX7_USBn_IRQ[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq); snprintf(name, NAME_SIZE, "usbmisc%d", i); From patchwork Mon Feb 10 15:49:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 863779 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp1661572wrt; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/12] hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE Date: Mon, 10 Feb 2025 15:49:38 +0000 Message-Id: <20250210154942.3634878-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé No need to duplicate and forward the 'num-cpu' property from TYPE_ARM11MPCORE_PRIV to TYPE_REALVIEW_MPCORE, alias it with QOM object_property_add_alias(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Message-id: 20250130112615.3219-6-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/cpu/realview_mpcore.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/hw/cpu/realview_mpcore.c b/hw/cpu/realview_mpcore.c index 4268735e3a5..7480b38d1ab 100644 --- a/hw/cpu/realview_mpcore.c +++ b/hw/cpu/realview_mpcore.c @@ -14,7 +14,6 @@ #include "hw/cpu/arm11mpcore.h" #include "hw/intc/realview_gic.h" #include "hw/irq.h" -#include "hw/qdev-properties.h" #include "qom/object.h" #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" @@ -68,7 +67,6 @@ static void realview_mpcore_realize(DeviceState *dev, Error **errp) int n; int i; - qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); if (!sysbus_realize(SYS_BUS_DEVICE(&s->priv), errp)) { return; } @@ -100,6 +98,7 @@ static void mpcore_rirq_init(Object *obj) int i; object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV); + object_property_add_alias(obj, "num-cpu", OBJECT(&s->priv), "num-cpu"); privbusdev = SYS_BUS_DEVICE(&s->priv); sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0)); @@ -108,16 +107,11 @@ static void mpcore_rirq_init(Object *obj) } } -static const Property mpcore_rirq_properties[] = { - DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), -}; - static void mpcore_rirq_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = realview_mpcore_realize; - device_class_set_props(dc, mpcore_rirq_properties); } static const TypeInfo mpcore_rirq_info = { From patchwork Mon Feb 10 15:49:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 863781 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp1661924wrt; Mon, 10 Feb 2025 07:52:28 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVYgFX5ekroBHQMBBuipw6IYpNoD4K53BQN1BzDM+CEp2hTVQBqAOK4M4ZPTdZB2t12wMASuA==@linaro.org X-Google-Smtp-Source: AGHT+IEz/QghUAZPDRBHgdKPslaEYRSHvzeBiwAq405UHI4JRIYIxnXosNat3brBu/PDea17obYt X-Received: by 2002:ac8:5993:0:b0:471:97ef:28d5 with SMTP id d75a77b69052e-47197ef2928mr52013611cf.46.1739202747801; Mon, 10 Feb 2025 07:52:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739202747; cv=none; d=google.com; s=arc-20240605; b=dB/XoVLKb31hftlUMcxlHWBHUre69BkDjNXEUnbgPYdqCVa1ypPu2xM/TJ1FhPAd48 4mXGCiLA4MUMutX3W1eqqQS7XYTivr9rTzBcKamZV2PF29ITR31GbZpfsdrQZrayWWdn 88BpvpygwyLSDF5Z8zS7aLDBehOcZf0Tt6ZOafI5fmwEialNpcef1G01McHReYPh8eJg bw6gRWV0eb/WvIfPyR14PSyp2N5qTFoRE7AtpWN1n49x8EEaU3fRbdMr2AobYDZsYRL/ ZFa9vn5vr4QiJ03AznjJikZRIzAtZmPAd5K9K7j2uUAiJGqcA71h896fdddNJqYP2NIS zDUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mZ4KLCN5rTxCDwJzmAh6VIQu5Td0a43voxEJaqli8sk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=B6zlHsGqB+zfp4DxcXOhM4FXINBEur1KtHNfMURYluguGZhq0bG79ZLiQO4bi06y58 6L9iuq4wwuPxRnVj7WvXa5guAl7vGcZOTgE6W6b0Gj5Eys4Gb3Se1axgzEyCM5HARGxU 0OrlOcSj8Oatr/IMR7z3GVulstNL4DtWhtcNjQOxvifJXw6qxD06D592/ITuxokaa+DY VEpt6REoPzW/my90ySneq7ap5HMovUA0Y7nhn7pXySQKIRc+2R8Io8P3FJ9AFNFSRq+I EIdIAbQFqNntWvNAwUUSS/kHNmYsrZ5i+8y0JSUH32q5tg+tXi6wSQ+sE4l1lyP7Yqhr MnVg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gCMCHnDp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/12] hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro Date: Mon, 10 Feb 2025 15:49:39 +0000 Message-Id: <20250210154942.3634878-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Message-id: 20250130112615.3219-7-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/cpu/a15mpcore.c | 21 +++++++++------------ hw/cpu/a9mpcore.c | 21 +++++++++------------ hw/cpu/arm11mpcore.c | 21 +++++++++------------ hw/cpu/realview_mpcore.c | 21 +++++++++------------ 4 files changed, 36 insertions(+), 48 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 3b0897e54ee..d24ab0a6ab2 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -164,17 +164,14 @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data) /* We currently have no saveable state */ } -static const TypeInfo a15mp_priv_info = { - .name = TYPE_A15MPCORE_PRIV, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(A15MPPrivState), - .instance_init = a15mp_priv_initfn, - .class_init = a15mp_priv_class_init, +static const TypeInfo a15mp_types[] = { + { + .name = TYPE_A15MPCORE_PRIV, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(A15MPPrivState), + .instance_init = a15mp_priv_initfn, + .class_init = a15mp_priv_class_init, + }, }; -static void a15mp_register_types(void) -{ - type_register_static(&a15mp_priv_info); -} - -type_init(a15mp_register_types) +DEFINE_TYPES(a15mp_types) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 9671585b5f9..25416c5032b 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -177,17 +177,14 @@ static void a9mp_priv_class_init(ObjectClass *klass, void *data) device_class_set_props(dc, a9mp_priv_properties); } -static const TypeInfo a9mp_priv_info = { - .name = TYPE_A9MPCORE_PRIV, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(A9MPPrivState), - .instance_init = a9mp_priv_initfn, - .class_init = a9mp_priv_class_init, +static const TypeInfo a9mp_types[] = { + { + .name = TYPE_A9MPCORE_PRIV, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(A9MPPrivState), + .instance_init = a9mp_priv_initfn, + .class_init = a9mp_priv_class_init, + }, }; -static void a9mp_register_types(void) -{ - type_register_static(&a9mp_priv_info); -} - -type_init(a9mp_register_types) +DEFINE_TYPES(a9mp_types) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 94861a06d94..b56bee6d543 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -152,17 +152,14 @@ static void mpcore_priv_class_init(ObjectClass *klass, void *data) device_class_set_props(dc, mpcore_priv_properties); } -static const TypeInfo mpcore_priv_info = { - .name = TYPE_ARM11MPCORE_PRIV, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(ARM11MPCorePriveState), - .instance_init = mpcore_priv_initfn, - .class_init = mpcore_priv_class_init, +static const TypeInfo arm11mp_types[] = { + { + .name = TYPE_ARM11MPCORE_PRIV, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(ARM11MPCorePriveState), + .instance_init = mpcore_priv_initfn, + .class_init = mpcore_priv_class_init, + }, }; -static void arm11mpcore_register_types(void) -{ - type_register_static(&mpcore_priv_info); -} - -type_init(arm11mpcore_register_types) +DEFINE_TYPES(arm11mp_types) diff --git a/hw/cpu/realview_mpcore.c b/hw/cpu/realview_mpcore.c index 7480b38d1ab..b1408886184 100644 --- a/hw/cpu/realview_mpcore.c +++ b/hw/cpu/realview_mpcore.c @@ -114,17 +114,14 @@ static void mpcore_rirq_class_init(ObjectClass *klass, void *data) dc->realize = realview_mpcore_realize; } -static const TypeInfo mpcore_rirq_info = { - .name = TYPE_REALVIEW_MPCORE_RIRQ, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(mpcore_rirq_state), - .instance_init = mpcore_rirq_init, - .class_init = mpcore_rirq_class_init, +static const TypeInfo realview_mpcore_types[] = { + { + .name = TYPE_REALVIEW_MPCORE_RIRQ, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(mpcore_rirq_state), + .instance_init = mpcore_rirq_init, + .class_init = mpcore_rirq_class_init, + }, }; -static void realview_mpcore_register_types(void) -{ - type_register_static(&mpcore_rirq_info); -} - -type_init(realview_mpcore_register_types) +DEFINE_TYPES(realview_mpcore_types) From patchwork Mon Feb 10 15:49:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 863780 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp1661633wrt; Mon, 10 Feb 2025 07:51:50 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXmAeIOzNDmgVTbPcGh1sBLbcxESdkzNwQud+Jga5EZVSR7Vr8t6x/tIY1432QTwk74YhkCNQ==@linaro.org X-Google-Smtp-Source: AGHT+IHGnGLN5Fw9xycWG+OJcCIesgcqM5b1gbqA7CqgPX0Y2iZCSkBv+DQ836qHKdSpDA9gnCDk X-Received: by 2002:ac8:5a56:0:b0:471:9774:5f39 with SMTP id d75a77b69052e-47197746971mr41087661cf.3.1739202709877; Mon, 10 Feb 2025 07:51:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739202709; cv=none; d=google.com; s=arc-20240605; b=lcsCqIy6cuju/M3QQ4PiTjES8b1x9wMhSW142f7HLqXD47ImEyVK/pGWd0dKhfLArq wtAIyvvS4S+VkDjVp0MJocha3rMvw1HliUrO8OcYCgklc+W6QUyGSEZC3ZcsQemEOjty DLkNhiBmZS/fVfoeOh9Ze05jncVFk3SbOI33bLXEV4JsTLtxeNQpMpdYN914iSx3nfc7 lo/HjlXgt/MnFjztXsy3c6awO2LEX2LUBcXgjnvrquUB1pyiFasj7davpm0CR0qjqj8R zUyWicTCRwELHv1rf+V8Gm42Hk5cr4G68alMNixqLg5E6mN5wLE0hC+sehXk7rlyUbW7 t8Pg== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/12] hw/net/cadence_gem: Fix the mask/compare/disable-mask logic Date: Mon, 10 Feb 2025 15:49:40 +0000 Message-Id: <20250210154942.3634878-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Andrew Yuan Our current handling of the mask/compare logic in the Cadence GEM ethernet device is wrong: (1) we load the same byte twice from rx_buf when creating the compare value (2) we ignore the DISABLE_MASK flag The "Cadence IP for Gigabit Ethernet MAC Part Number: IP7014 IP Rev: R1p12 - Doc Rev: 1.3 User Guide" states that if the DISABLE_MASK bit in type2_compare_x_word_1 is set, the mask_value field in type2_compare_x_word_0 is used as an additional 2 byte Compare Value. Correct these bugs: * in the !disable_mask codepath, use lduw_le_p() so we correctly load a 16-bit value for comparison * in the disable_mask codepath, we load a full 4-byte value from rx_buf for the comparison, set the compare value to the whole of the cr0 register (i.e. the concatenation of the mask and compare fields), and set mask to 0xffffffff to force a 32-bit comparison Signed-off-by: Andrew Yuan Message-id: 20241219061658.805-1-andrew.yuan@jaguarmicro.com Suggested-by: Philippe Mathieu-Daudé [PMM: Expand commit message and comment] Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index f744054a6d8..80fbbacc1e7 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -909,8 +909,8 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, /* Compare A, B, C */ for (j = 0; j < 3; j++) { - uint32_t cr0, cr1, mask, compare; - uint16_t rx_cmp; + uint32_t cr0, cr1, mask, compare, disable_mask; + uint32_t rx_cmp; int offset; int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6, R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH); @@ -946,9 +946,25 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, break; } - rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; - mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); - compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); + disable_mask = + FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, DISABLE_MASK); + if (disable_mask) { + /* + * If disable_mask is set, mask_value is used as an + * additional 2 byte Compare Value; that is equivalent + * to using the whole cr0 register as the comparison value. + * Load 32 bits of data from rx_buf, and set mask to + * all-ones so we compare all 32 bits. + */ + rx_cmp = ldl_le_p(rxbuf_ptr + offset); + mask = 0xFFFFFFFF; + compare = cr0; + } else { + rx_cmp = lduw_le_p(rxbuf_ptr + offset); + mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); + compare = + FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); + } if ((rx_cmp & mask) == (compare & mask)) { matched = true; From patchwork Mon Feb 10 15:49:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 863782 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp1661942wrt; Mon, 10 Feb 2025 07:52:30 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXGuEf2D2yi4JT5KsYSZpOntYrhO51d6CNEqNeSR52zmdWTj08LlUKXdwjyzdqHWGEm8tc6cA==@linaro.org X-Google-Smtp-Source: AGHT+IHDN1zOX82YfOn3JvXKGaqY5+y0GJ1pJyDTH6rm/ipwPbFfttXnWjCewli4AFX+49S8bxO2 X-Received: by 2002:a05:620a:2b4d:b0:7c0:5bf2:815 with SMTP id af79cd13be357-7c05bf209f8mr786895885a.14.1739202750347; Mon, 10 Feb 2025 07:52:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739202750; cv=none; d=google.com; s=arc-20240605; b=IIRLocQ/WhvcKW00p4XSDQzdaS2ze/w5mP3TdwLEuvEpTn7ZtsROceNSHiH98XvH67 aPq4lg+Avfn0ckSU+MCngOPRkOky8TCe4bKma4wLpk+3/h4O+5g6mWFCH5SPLmHFDMmE t5FhwbSDz5VLUp6PNhS5isZyMbaOunC4bbmbw6IsFVrwl51aUcm0BwdY+bQREFmcJz2d mjNB3jP1TsYl1PnCBcdQQALWBw1bznpbHa6uS6RDfLZLMpcj8YDrkEni4Yi/iK1ZdAN6 eBZmaarsmMfC5ciLAwTcknq18OPEM/GJCZ/uj8fRGL7pUU0RBrxqS7EnyQp3+ryjkAXN tEQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ach7bnbaT/M/a9OUubHchNVXpLnBww1JCB9bAXJ6NA4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=l2GVYcqWiC4JQyEW7po4sQySCdN6NGw639AjzDnrvU94V6CXNlOHO2XnEil2sDiM9j mO6dINEVGNBPFvhF++G+ximgRDFfgZzO9ccSSAHEI1S7cqZW6u5gQO4ufI46NoQBKc0w aJbqn37qg+Rpcr+8Z1WU6HhuEdZQAZjHt08AWvM8p655jYBtQ2cDlU33hBYWLwwhD0Jn xORwHl+cJw8IlR6JfKREBiWgjrxZv0D3nZq1V34pYi297o1QgZVXrKkfok++dHXtYdw7 NVGS6L5bMOvBElHv+Ip1ohW1SfYEVgrMzTsNo4V/bnh8vBQB7E339JIL3IukgFww1o0b QjJA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=phrMCiuc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/12] qemu-options: Deprecate -old-param command line option Date: Mon, 10 Feb 2025 15:49:41 +0000 Message-Id: <20250210154942.3634878-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The '-old-param' command line option is specific to Arm targets; it is very briefly documented as "old param mode". What this option actually does is change the behaviour when directly booting a guest kernel, so that command line arguments are passed to the kernel using the extremely old "param_struct" ABI, rather than the newer ATAGS or even newer DTB mechanisms. This support was added back in 2007 to support an old vendor kernel on the akita/terrier board types: https://mail.gnu.org/archive/html/qemu-devel/2007-07/msg00344.html Even then, it was an out-of-date mechanism from the kernel's point of view -- the kernel has had a comment since 2001 marking it as deprecated. As of mid-2024, the kernel only retained param_struct support for the RiscPC and Footbridge platforms: https://lore.kernel.org/linux-arm-kernel/2831c5a6-cfbf-4fe0-b51c-0396e5b0aeb7@app.fastmail.com/ None of the board types QEMU supports need param_struct support; mark this option as deprecated. Signed-off-by: Peter Maydell Reviewed-by: Daniel P. Berrangé Message-id: 20250127123113.2947620-1-peter.maydell@linaro.org --- docs/about/deprecated.rst | 13 +++++++++++++ system/vl.c | 1 + 2 files changed, 14 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 29de49351d1..a4c7d642236 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -68,6 +68,19 @@ configurations (e.g. -smp drawers=1,books=1,clusters=1 for x86 PC machine) is marked deprecated since 9.0, users have to ensure that all the topology members described with -smp are supported by the target machine. +``-old-param`` option for booting Arm kernels via param_struct (since 10.0) +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The ``-old-param`` command line option is specific to Arm targets: +it is used when directly booting a guest kernel to pass it the +command line and other information via the old ``param_struct`` ABI, +rather than the newer ATAGS or DTB mechanisms. This option was only +ever needed to support ancient kernels on some old board types +like the ``akita`` or ``terrier``; it has been deprecated in the +kernel since 2001. None of the board types QEMU supports need +``param_struct`` support, so this option has been deprecated and will +be removed in a future QEMU version. + User-mode emulator command line arguments ----------------------------------------- diff --git a/system/vl.c b/system/vl.c index db8e604ebab..aa91047c480 100644 --- a/system/vl.c +++ b/system/vl.c @@ -3469,6 +3469,7 @@ void qemu_init(int argc, char **argv) nb_prom_envs++; break; case QEMU_OPTION_old_param: + warn_report("-old-param is deprecated"); old_param = 1; break; case QEMU_OPTION_rtc: From patchwork Mon Feb 10 15:49:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 863785 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp1662065wrt; Mon, 10 Feb 2025 07:52:42 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUMyAG7yTBT/Z/VKQmQZh/xEIxqRM4NKcbP10+UziMTP6hx1lyVQWTz4JzXMhj6d8nbEh9dGQ==@linaro.org X-Google-Smtp-Source: AGHT+IFFce1MRk41sdj0MvyOoZVF5jUvpRURiUkiKtHiKKVDEyVNhTBuv4c1XAjvJqmS2OvMBio/ X-Received: by 2002:a05:620a:17a6:b0:7c0:6865:ad86 with SMTP id af79cd13be357-7c068824196mr24058885a.35.1739202762630; Mon, 10 Feb 2025 07:52:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739202762; cv=none; d=google.com; s=arc-20240605; b=NX+8Y9/xH3cSoAtS563wY4YVsQ1MHitohtpSziQH4k6nneLfGLRquF0DTx3wO++a4h TVy/Ijc5iGLmzE8ne99WkSUNJTeLyb+rBPf6t4bXvizqFuZ+NCSeWxwjq8EBt8fZqlG0 Zt1y5USLR3bPLaorhIuBACr7pRtBTvrqTh4KyyMvN3W7Q7P3Y2hm0vVmv4nmL/3KDUOr 36jMSOlK9AvXPyOCh+4zKicNTnGY1VYMETyIc2GX1Bc1uOJPPHZBXJzjNcAJliBoyLEF OO/PPu9veUOzeXXp2EKGJJpPQelOynChNyUUKjZw+SBsYvS2Nevvmovnsy5TGQPLJduH ha1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yUBcHpc5OCe44EFqf9E+CLvvwsZEvaTZC3OB4U4wEFU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=UYz0anUCI4gi98rVvHWdqpP8G3+MBeTIUwm6an7NNTLYrGmJour93Mn6aCMxmB+Jfd v0f8rgBvr5UvP95tqqIUGnFpvLn1TruGRalzo8RoeOe4yVmtFOgw+tyoBFJ2ajPGCfwG G18N2supzVvmPKbIZ9QwLRUYR7pcSZHhqc32JE3KnjSsdt3zp2TC5gYXeN2hYWGfWMyk j1GH6WoJPUrcOk7H2ERtm3KG2FY5U2jcN1p8FKCtnotrQH50alX7OhdBG4wKS9FUhzem s/2ylsUeVfAgBU0DnbbXTFBHLXmKfXaEJwVVA30q8Qf1EHXerhrrXlpIZUjtU8kX4ESe c/2Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iz72c136; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/12] linux-user: Do not define struct sched_attr if libc headers do Date: Mon, 10 Feb 2025 15:49:42 +0000 Message-Id: <20250210154942.3634878-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Khem Raj glibc 2.41+ has added [1] definitions for sched_setattr and sched_getattr functions and struct sched_attr. Therefore, it needs to be checked for here as well before defining sched_attr, to avoid a compilation failure. Define sched_attr conditionally only when SCHED_ATTR_SIZE_VER0 is not defined. [1] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=21571ca0d70302909cf72707b2a7736cf12190a0;hp=298bc488fdc047da37482f4003023cb9adef78f8 Signed-off-by: Khem Raj Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2799 Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- linux-user/syscall.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 6ee02383daf..df5ed18062c 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -360,7 +360,8 @@ _syscall3(int, sys_sched_getaffinity, pid_t, pid, unsigned int, len, #define __NR_sys_sched_setaffinity __NR_sched_setaffinity _syscall3(int, sys_sched_setaffinity, pid_t, pid, unsigned int, len, unsigned long *, user_mask_ptr); -/* sched_attr is not defined in glibc */ +/* sched_attr is not defined in glibc < 2.41 */ +#ifndef SCHED_ATTR_SIZE_VER0 struct sched_attr { uint32_t size; uint32_t sched_policy; @@ -373,6 +374,7 @@ struct sched_attr { uint32_t sched_util_min; uint32_t sched_util_max; }; +#endif #define __NR_sys_sched_getattr __NR_sched_getattr _syscall4(int, sys_sched_getattr, pid_t, pid, struct sched_attr *, attr, unsigned int, size, unsigned int, flags);