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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dc9ce31e8sm10652676f8f.5.2025.02.10.14.18.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Feb 2025 14:18:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 01/10] target: Set disassemble_info::endian value for little-endian targets Date: Mon, 10 Feb 2025 23:18:21 +0100 Message-ID: <20250210221830.69129-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250210221830.69129-1-philmd@linaro.org> References: <20250210221830.69129-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field for little-endian targets. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson --- target/alpha/cpu.c | 1 + target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/i386/cpu.c | 1 + target/loongarch/cpu.c | 1 + target/rx/cpu.c | 1 + 6 files changed, 6 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index da21f99a6ac..acf81fda371 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -85,6 +85,7 @@ static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch) static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { + info->endian = BFD_ENDIAN_LITTLE; info->mach = bfd_mach_alpha_ev6; info->print_insn = print_insn_alpha; } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5a0e21465e5..2871d30540a 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -102,6 +102,7 @@ static void avr_cpu_reset_hold(Object *obj, ResetType type) static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { + info->endian = BFD_ENDIAN_LITTLE; info->mach = bfd_arch_avr; info->print_insn = avr_print_insn; } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 238e63bcea4..a9beb9a1757 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -293,6 +293,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) { info->print_insn = print_insn_hexagon; + info->endian = BFD_ENDIAN_LITTLE; } static void hexagon_cpu_realize(DeviceState *dev, Error **errp) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b5dd60d2812..85815c0805d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8497,6 +8497,7 @@ static void x86_disas_set_info(CPUState *cs, disassemble_info *info) X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; + info->endian = BFD_ENDIAN_LITTLE; info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 : bfd_mach_i386_i8086); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 227870e2856..cb9b9f909f3 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -617,6 +617,7 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type) static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) { + info->endian = BFD_ENDIAN_LITTLE; info->print_insn = print_insn_loongarch; } diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 154906ef5f4..acd5a6e12da 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -160,6 +160,7 @@ static void rx_cpu_set_irq(void *opaque, int no, int request) static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { + info->endian = BFD_ENDIAN_LITTLE; info->mach = bfd_mach_rx; info->print_insn = print_insn_rx; } From patchwork Mon Feb 10 22:18:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 863872 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d4c:0:b0:385:e875:8a9e with SMTP id a12csp14482wru; Mon, 10 Feb 2025 14:20:04 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWGQNeePbTXNJx26CM44KYI2ODP3tu0CfyAit0cYdZ/DBlDCzsztVPX5kLQmpZDrRmbC3pDWw==@linaro.org X-Google-Smtp-Source: AGHT+IEalxhw2QnNtxZ2S/J+UUabTEVyZoBCdH1gtOYcHAHCQobtGEQndrSB0UEGOQxJp5Cvaov4 X-Received: by 2002:a05:620a:254b:b0:7bd:bafc:32b0 with SMTP id af79cd13be357-7c047c94929mr2731108785a.47.1739226004030; Mon, 10 Feb 2025 14:20:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739226004; cv=none; d=google.com; s=arc-20240605; b=MvhF/cnBuzCQ4hu5T4XhVIb7yLYOuR1cawjbDRGUxNQn6zu1Bp8TNfOeVibmlIObFn Y10W9nKjhMS4ghhSrl79JeUcl9OtCVi+pMj3IDlTASSRXKNTe9e4kdF7o0Ls+HQJJbIe yEvWhkCGASiufh86Viz3SwEQ+edttRhhgnkFwD9ts+HW0tXF5fEV/wzwp7EklZwN/Zks xl2xnVfQfm7inPLUTH5I4EKHo2av99SBMrhCP06NSZAlqV8RK7G5AWEwSoevFoKvVSmx 5MoFV8fLKoPv/vwIiXr8yiC9pv1u84aVYluYw74+DowOh5Si1IICSQn6RDkBFJoALbk4 J4Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wvSW0yNHAxQVpap9+gIBQOievXbQcesYepvpw1E/5Ok=; fh=gTloOz3hcaaNOIl6Yk1/UbfPcJyg7bUZlwmawbBQn5U=; b=iy+na4+Mr2o9xlrVo+cy2qpryrsZpxDyiFt2mKpC7odd9n549e3IS/AHcJubgEaF3n CSg7HciBPW0wdOk5K/JrpJ+7zZFnGf1VyMGqlj/dMNtTg3IgUROmH3b8fdQEpFpD3kG9 1/B2keQuztK8gSFYNIsyxD4GkXm5FC48W0f7XNWzHgvpDimIGoWEP/GGOMb58DpWD2Wu U7UqSlR1yI0amK0Foj0D8/fOI0SHqW0+AMG2QOiyEyEY0bLzrnezeLH2isNRrSYf0j9b ihRcOOHXVwkzRH/tifINXhTc9xY9enYScPXI0irXiQlmB3JRM19g3fEtpuCOnrthpHh9 QvEg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zitY9Z4v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439463d17a1sm35990265e9.21.2025.02.10.14.18.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Feb 2025 14:18:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 02/10] target: Set disassemble_info::endian value for big-endian targets Date: Mon, 10 Feb 2025 23:18:22 +0100 Message-ID: <20250210221830.69129-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250210221830.69129-1-philmd@linaro.org> References: <20250210221830.69129-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field for big-endian targets. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson --- target/hppa/cpu.c | 1 + target/m68k/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sparc/cpu.c | 1 + 5 files changed, 5 insertions(+) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4bb5cff624e..d15f8c9c217 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -150,6 +150,7 @@ static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) { info->mach = bfd_mach_hppa20; + info->endian = BFD_ENDIAN_BIG; info->print_insn = print_insn_hppa; } diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5eac4a38c62..ff167aaea71 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -122,6 +122,7 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) static void m68k_cpu_disas_set_info(CPUState *s, disassemble_info *info) { info->print_insn = print_insn_m68k; + info->endian = BFD_ENDIAN_BIG; info->mach = 0; } diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index a74fab43a91..33c81928370 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -83,6 +83,7 @@ static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) { + info->endian = BFD_ENDIAN_BIG; info->print_insn = print_insn_or1k; } diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 3bea014f9ee..972d265478d 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -243,6 +243,7 @@ static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { info->mach = bfd_mach_s390_64; info->cap_arch = CS_ARCH_SYSZ; + info->endian = BFD_ENDIAN_BIG; info->cap_insn_unit = 2; info->cap_insn_split = 6; } diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index e3b46137178..9fd222e4c82 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -106,6 +106,7 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) { info->print_insn = print_insn_sparc; + info->endian = BFD_ENDIAN_BIG; #ifdef TARGET_SPARC64 info->mach = bfd_mach_sparc_v9b; #endif From patchwork Mon Feb 10 22:18:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 863871 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d4c:0:b0:385:e875:8a9e with SMTP id a12csp14403wru; Mon, 10 Feb 2025 14:19:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUFBj2CEltkicET6nOmnxoaeoaHtvdSSVkWbSJaRlImG7A6Zoyj4G1COvhjupSnNukHebxv8g==@linaro.org X-Google-Smtp-Source: AGHT+IGqaRmvctU6LLPmMLCJaUyoTBG0GXiZsGZsuDfo7v4kENJ7g8rIMb3pIdhAx5Zsl2deJ62E X-Received: by 2002:a05:622a:13c9:b0:471:9bec:e1ee with SMTP id d75a77b69052e-471a070e639mr25183681cf.34.1739225992921; Mon, 10 Feb 2025 14:19:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739225992; cv=none; d=google.com; s=arc-20240605; b=enz1UuNtwn40qQQueyhrp9QEHlP91avrnXddHBU07oum6fGzC6AQb3LSnDc6gACKxR 9m+rePwmyw8PpYxyIsGAkuJcJAYz7uhHQOfQ3fbzCaA0UI7OnKoozVd2EuKx0Q72eJFp 0EzEfhNnTEHohmWdJ6Y3oupmTSxvO7bpfEVyoQNPTlFiT91tu8TaUD5gQWOr5ea4Sq7b cHEdtQKqcTLabeZHkY2JzJP7qNVRa7Rp/C7xmO9t91HqIfpKdBSpjXuKmeNTjJktFyTa cHyNwoy1AmvWZnthTKeZ1Fh0Y/s7s3dHgFedx2PbvpcpGJVVlz6Iyt7C0HOvWEak72pQ 8+cA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=verx53GTrTT7sD7mWRhDwPgxK/V6+ka4Dj5r4zGv8rc=; fh=gTloOz3hcaaNOIl6Yk1/UbfPcJyg7bUZlwmawbBQn5U=; b=Y3JO3MjYi6GunQ/IgIOj+JrOOq45B9l169ccivdGm5UkFhBiYYrLfz/5vwBT06cuXC OEwuGIbJHkk4juWBPdkqnSRw7BsGOuKcgeBnigC84xDxaFgxJPKBBD3pJAPHPQDrGR5A rlkZhCErmLo1I0AVJUDb0S4n3MCCEmVJcKDyiZanKEHVIqiRqTypVbmYnXGIXh6itiF5 6XasoDbB2Ga2q4eb8OFuoeKmEjuTQr37zwuDovvgrLDVGYDPHqyqKEGMszcOAx4UvKmN aCljPdSpguqe2t6IZs7xQN+2rDr/W5PQY1GGPnha+hiUc8TnbmmB/9wppwKZmgGb1dtm DdnQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FD45hCCC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dc17e278bsm12408209f8f.48.2025.02.10.14.18.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Feb 2025 14:18:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 03/10] target/arm: Set disassemble_info::endian value in disas_set_info() Date: Mon, 10 Feb 2025 23:18:23 +0100 Message-ID: <20250210221830.69129-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250210221830.69129-1-philmd@linaro.org> References: <20250210221830.69129-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 94f1c55622b..68b3a9d3ab0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1188,7 +1188,7 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) { ARMCPU *ac = ARM_CPU(cpu); CPUARMState *env = &ac->env; - bool sctlr_b; + bool sctlr_b = arm_sctlr_b(env); if (is_a64(env)) { info->cap_arch = CS_ARCH_ARM64; @@ -1215,13 +1215,9 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) info->cap_mode = cap_mode; } - sctlr_b = arm_sctlr_b(env); + info->endian = BFD_ENDIAN_LITTLE; if (bswap_code(sctlr_b)) { -#if TARGET_BIG_ENDIAN - info->endian = BFD_ENDIAN_LITTLE; -#else - info->endian = BFD_ENDIAN_BIG; -#endif + info->endian = TARGET_BIG_ENDIAN ? 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd295200asm8134874f8f.44.2025.02.10.14.18.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Feb 2025 14:18:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 04/10] target/microblaze: Set disassemble_info::endian value in disas_set_info Date: Mon, 10 Feb 2025 23:18:24 +0100 Message-ID: <20250210221830.69129-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250210221830.69129-1-philmd@linaro.org> References: <20250210221830.69129-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 13d194cef88..d5ee1244cad 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -224,6 +224,8 @@ static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) { info->mach = bfd_arch_microblaze; info->print_insn = print_insn_microblaze; + info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG + : BFD_ENDIAN_LITTLE; } static void mb_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Mon Feb 10 22:18:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 863874 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d4c:0:b0:385:e875:8a9e with SMTP id a12csp14590wru; Mon, 10 Feb 2025 14:20:26 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWMg84LNVDRyYsto4RGzodCB7MI7a/Ov6+mvVHj83MPKjE0qJzKX4xnz+Q+ibWsLkijoCNODg==@linaro.org X-Google-Smtp-Source: AGHT+IHAWb1Qk9jp97Hg3lzeNtGKZ7of5T+OsMuY59JehjJ0B0KZ70kYBFueOHS128iCRQEyjhwL X-Received: by 2002:a05:622a:6a90:b0:471:826e:3efa with SMTP id d75a77b69052e-471826e6777mr116965791cf.49.1739226026033; Mon, 10 Feb 2025 14:20:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739226026; cv=none; d=google.com; s=arc-20240605; b=EkglYclxA3UzbtTXTL82yREXVPlweh8UNdg5g/STKE/XBFsGkxoXdzMYheGI8fEJXO snvXPojJh+wu+OmXPxvVo12wE+HyONAk9/7PdoSMwKb1xSKUOQyFG/YDWEW5Z0chFouv t5rObwCp5/kGoygoWJY44Z508iuCxcUeNkUsmvSU3PrhaZOEJr7XVahgrv3dz7Iw5MhS lBSznKfAkGji6rO8LdMAyOVf8cjbd6A1vErb1Hk0pZqgf36JrwFM/kDpDak9HfqduvxX zVgL1mtg1lreNti06I6e0PVbSPZHf/xXx/nPnRgsBhDrQQMMl4RDotvc0v4IY8PlmICh 6qDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PUkz5f9MQ2pvcvCLkym9eiE0tZLYKK08nDn81l1HJFM=; fh=gTloOz3hcaaNOIl6Yk1/UbfPcJyg7bUZlwmawbBQn5U=; b=bwItIthOgig5rMbCWtO+PemJWuvuUsRxMBGmPYyXLIuMDxsYrbSmhNFHms9waaj9HY c2nV74RAaTAn4oyseoxfLWn6jX5uHlxP84JokwObfqqM442cLGbmgknzeVa1iXOlT1PO vWm6VCZlrjCByy7OfXi9aGhJ2dBqeMrNftxDzoHDUIq7Nr+UwSgv9WzjGszZpIseNOnf //mw9g/bPG4pDfoqyYH4KS92ozvSkKlFhBqH2pJsKBYDQPlm9POdQuNmnm8iwQYwWnP6 V6dDpKmhOY9FshCyUqSsFLXMtYiUIlUnnJDP3eLWwlC5hvGnTfhy5/IFJHGXDb+gCfqT 5ktA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=btk1CvvP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dc9ef8ac6sm10675362f8f.27.2025.02.10.14.18.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Feb 2025 14:18:57 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 05/10] target/mips: Set disassemble_info::endian value in disas_set_info() Date: Mon, 10 Feb 2025 23:18:25 +0100 Message-ID: <20250210221830.69129-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250210221830.69129-1-philmd@linaro.org> References: <20250210221830.69129-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson --- target/mips/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 0b267d2e507..e76298699ab 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -428,13 +428,13 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type) static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) { if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) { -#if TARGET_BIG_ENDIAN - info->print_insn = print_insn_big_mips; -#else - info->print_insn = print_insn_little_mips; -#endif + info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG + : BFD_ENDIAN_LITTLE; + info->print_insn = TARGET_BIG_ENDIAN ? print_insn_big_mips + : print_insn_little_mips; } else { info->print_insn = print_insn_nanomips; + info->endian = BFD_ENDIAN_LITTLE; } } From patchwork Mon Feb 10 22:18:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 863867 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d4c:0:b0:385:e875:8a9e with SMTP id a12csp14267wru; Mon, 10 Feb 2025 14:19:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUtdz6TUF16vrI+gjf/eAGnEeqV4G9wvKiTvekK87BocAjUcocYSH0uDEdvWad37rYkC49rGQ==@linaro.org X-Google-Smtp-Source: AGHT+IEmX6y/yBW9sYD0CCm8ZNZnFthaV9KiUsDhHSR2e8aDgHFxM6NP2FCi6qw32pE4+tSmkBOY X-Received: by 2002:a05:622a:13c9:b0:471:9bec:e1ee with SMTP id d75a77b69052e-471a070e639mr25153261cf.34.1739225959181; Mon, 10 Feb 2025 14:19:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739225959; cv=none; d=google.com; s=arc-20240605; b=fx/AesI7LnNQ47qNby5K5wR047XfPV9oKYoSBGB5dXyzIemfN43IlpPK2xghA1mGAN wxKZPAxbrn2Sld3dd1VsH9F7yhsYZwcXMIwDH55o2nl4Kw0e6OoIq1ChvJAdvy2l/ux5 rvSTV0vHeItl5+6wHN761oVfdf/mFbDoTTxCENifBgQk3QtDSBPLHhe2IrLfF0OPG/X4 UvKa3UfQyzAx8SbqcbGPWCedE6oMXvi+bc6eOXojDQKNMtjz0kPDHCykC/jxtAZAM5PK 8WnZXeBf8Q2ApbHRb1PjsyYJbZHpBh8xTWSqbTaOAC3pdFeqp3NgDDdSAjxFSO4fjdhy EAYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=na4NIhR7KjWn9JvA007jmUlM2ztPp6QYgo9rPBZi7l8=; fh=gTloOz3hcaaNOIl6Yk1/UbfPcJyg7bUZlwmawbBQn5U=; b=DYZ4e8jwwv0Idm11dOCopjpaDkHrjoejHqqY9Al85m9kH+uJ4BIQ7wNpEKWWSOA39h Ai1qobXdk4znAwsr4klwsLRqM3ceWljzWqzUoh9VpwlJE72dy3Mulpezbksk1MT/v/RD eZDbqUU1cd6J997vMy5bW6D1ICDwg4yWwW/KPkvsnkWC6G6bDhDrug5GZFngn2D7I8lX 5wb7dvj1eeJTf3QIxfd5s9K3wOSf/V9Kc0iCbbtH74gh0RW2yo+k/NP4ihJ7+8NkcX/0 bpZ0XfZB/o8MIinT9c6dKY+x0opcMlatKl3RG4X0EAkTPt6AwXCQoSLGhQCLSRQjxP6b R4tw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AzS3onox; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390daf4438sm197149585e9.25.2025.02.10.14.19.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Feb 2025 14:19:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 06/10] target/ppc: Set disassemble_info::endian value in disas_set_info() Date: Mon, 10 Feb 2025 23:18:26 +0100 Message-ID: <20250210221830.69129-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250210221830.69129-1-philmd@linaro.org> References: <20250210221830.69129-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback always set\ the disassemble_info::endian field. Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 25e835d65e7..e816d30114b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7398,6 +7398,8 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) if ((env->hflags >> MSR_LE) & 1) { info->endian = BFD_ENDIAN_LITTLE; + } else { + info->endian = BFD_ENDIAN_BIG; } info->mach = env->bfd_mach; if (!env->bfd_mach) { From patchwork Mon Feb 10 22:18:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 863876 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d4c:0:b0:385:e875:8a9e with SMTP id a12csp14814wru; Mon, 10 Feb 2025 14:21:09 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVyq3g+LPZSd7fRY0QesRy0As+6Do+RSDhPmke/UHaTIhXKdPlbOqWyacV2ClI8/49CnImWJA==@linaro.org X-Google-Smtp-Source: AGHT+IH/7cjC7lHKBH7sjlAaN0CoWsJ88uATQWigHSGAKiMX770IonzcM269+JLLzkDmrAWzezaR X-Received: by 2002:ad4:5dea:0:b0:6df:9771:978e with SMTP id 6a1803df08f44-6e4456d9b15mr279617936d6.34.1739226069658; Mon, 10 Feb 2025 14:21:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739226069; cv=none; d=google.com; s=arc-20240605; b=PucTRU7PDmvzBkWCi9TGpt1paefc453Vnb2XLij9+f/3r9lj0A4EYQeOCazLNA4pWz 04wEkPLULAeCUTCCv+Wg5bqsYtx24ikaqI5zKwtOiUpLjEj5FaAVRNGdngCbqiHXKf+Z Uiih96qI2AlUEV7j+U+qtQppwKEJrj2dmm3miDdyxeiUXgSn8fleDPfFAMYssJR/Gw3E 4TYoyNv7wC8pk+HcanyEljl4HyGEdSl81u7BS+Go9QOkXnUrIKXYAsXPLM0g6g5afrTn /oFi17mETGfJzohVEi45ewr+Qzdwfn6ePqa9KKo5avC2tJptF75eibU0+1YrLuGKJ2V4 3a6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Bm3IwAVfo/Moh0xAEaNpxkkhaYnZBCTmolWG6ZgnfJI=; fh=gTloOz3hcaaNOIl6Yk1/UbfPcJyg7bUZlwmawbBQn5U=; b=ZtcpRnHkB+1IVpFAY1sCBnvdfbF5qM7v2MG34AdMPFRVMLp9jYNQjL6t4R9CuVU2Rd D7Iz5SZrdUuYyANmd4ZhmdWEFbgeMpeN3WmoV3Trj6Lb+/cQ2WB8nRLowgkUoIw60P1M l31sEfuchjTa7dL3slIw6ofwSOt8SdlInBt/IeCoLnyB6hOomH93eNFU+9w84wulgain FDtUneCrOMxB6Z+4UVcxocUekgqA5wG6pyxilNmgduHIwTB2i+Kh/n5Zp2QT/HHD0d7E DlHycCI2gsAVF7MXZh+SKZzl6X8JCbp1yPodPYyrU7MAzN4aUx5wlMpAEW3x2Y9KV19c lswg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NQY8n0fA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd5930aabsm7579434f8f.56.2025.02.10.14.19.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Feb 2025 14:19:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 07/10] target/riscv: Set disassemble_info::endian value in disas_set_info() Date: Mon, 10 Feb 2025 23:18:27 +0100 Message-ID: <20250210221830.69129-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250210221830.69129-1-philmd@linaro.org> References: <20250210221830.69129-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d4bd157d2c..b39a701d751 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1156,6 +1156,15 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) CPURISCVState *env = &cpu->env; info->target_info = &cpu->cfg; + /* + * A couple of bits in MSTATUS set the endianness: + * - MSTATUS_UBE (User-mode), + * - MSTATUS_SBE (Supervisor-mode), + * - MSTATUS_MBE (Machine-mode) + * but we don't implement that yet. + */ + info->endian = BFD_ENDIAN_LITTLE; + switch (env->xl) { case MXL_RV32: info->print_insn = print_insn_riscv32; From patchwork Mon Feb 10 22:18:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 863868 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d4c:0:b0:385:e875:8a9e with SMTP id a12csp14287wru; Mon, 10 Feb 2025 14:19:22 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXjgRftxZaLDI70n24cStCYalHAiBiNAbpTnb3hKqSBMROeA5SLIfUzIBiP+J4GWgc6Xa1JXg==@linaro.org X-Google-Smtp-Source: AGHT+IEiXageI495nh/LpaGSQFr3NMgFldHYCyG7jAUICwlBU+k8vbvdlmENirsEPwZQBGoMS2pM X-Received: by 2002:a05:622a:2304:b0:467:603d:1cd5 with SMTP id d75a77b69052e-471a13eea54mr18498961cf.26.1739225962197; Mon, 10 Feb 2025 14:19:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739225962; cv=none; d=google.com; s=arc-20240605; b=jYiJjN2KzIQeXvA8kNJApEArj299zX7wL32Y+52Rf2PUH7PBMttxr9hyLcgZ/hrxMf fSgPu4DEer0EZeHzYL0GqypPNs0/ST3pWvEqWoS9iUSEXBWPnC3EqV6ZtNKhxYfhr4bG F2J6Q4HyLSliLDZuxzA6+zWOEBJDbdoAU4ZJdkNESjO4l7MHkWW6dQ4/qAZ6k/Bb2U6Y Ttyu9nVmyilwrbUzULHCkVaZr/pWEoEE1Vk5ju2EZAqCe4hoiWNofcgrT+t7MWMgRpAT rwRRKu6H2/01tByLamAXGBpAblbroQhUEdtV1fWj7etwocfylXtmrDnlfFEepUq8yXm6 UNig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=00i7CvZqld+dgS2CaEcbjOiQuiuQI6ulPrtY/Q/ykxw=; fh=gTloOz3hcaaNOIl6Yk1/UbfPcJyg7bUZlwmawbBQn5U=; b=NkkMDENYctQiOX/QLwX9gD8d4K2/Oxoz7V73Mx8v9pNOjEsoTKOp+icTxHNjivbM+H wDbXVyCaCa3gtX1uRHORFxHRo96Axjy0utnTnfHvkxIx4EP/Nm7Idr7YY0mJy9PK+dWB SUdmHf3se9q90WRqS+aXQTXCeAbBaKZw7Klr14BZ74Dcp7PGqMNUrNHOTjMGQBby2IlJ KfJvhAxCkgkjx53IpoYpbN5kZ/zRyUBWFJAKFZAJ4Xf+ULWfGA4Bs+eRgUAlH55A0kKl C/9WNXOC2/OSFxtnq+9WUcGdKCA4sJXr7pLeQm3NNImRlsSSvSOEX96Ha1IcQOcmfhKF zJSg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hq8sMejr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439427b48f8sm50529075e9.30.2025.02.10.14.19.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Feb 2025 14:19:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 08/10] target/sh4: Set disassemble_info::endian value in disas_set_info() Date: Mon, 10 Feb 2025 23:18:28 +0100 Message-ID: <20250210221830.69129-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250210221830.69129-1-philmd@linaro.org> References: <20250210221830.69129-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson --- target/sh4/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index e3c2aea1a64..4a50f2746ab 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -134,6 +134,8 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { + info->endian = TARGET_BIG_ENDIAN ? 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d94d685sm191800815e9.13.2025.02.10.14.19.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Feb 2025 14:19:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 09/10] target/xtensa: Set disassemble_info::endian value in disas_set_info() Date: Mon, 10 Feb 2025 23:18:29 +0100 Message-ID: <20250210221830.69129-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250210221830.69129-1-philmd@linaro.org> References: <20250210221830.69129-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson --- target/xtensa/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index efbfe73fcfb..f9e298ace45 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -159,6 +159,8 @@ static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) info->private_data = cpu->env.config->isa; info->print_insn = print_insn_xtensa; + info->endian = TARGET_BIG_ENDIAN ? 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd5e3cddasm7271481f8f.22.2025.02.10.14.19.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Feb 2025 14:19:22 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 10/10] disas: Remove target_words_bigendian() call in initialize_debug_target() Date: Mon, 10 Feb 2025 23:18:30 +0100 Message-ID: <20250210221830.69129-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250210221830.69129-1-philmd@linaro.org> References: <20250210221830.69129-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All CPUClass implementating disas_set_info() must set the disassemble_info::endian value. Ensure that by setting %endian to BFD_ENDIAN_UNKNOWN before calling the CPUClass::disas_set_info() handler, then asserting %endian is not BFD_ENDIAN_UNKNOWN after the call. This allows removing the target_words_bigendian() call in disas/. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- disas/disas-common.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/disas/disas-common.c b/disas/disas-common.c index 57505823cb7..21c2f03430b 100644 --- a/disas/disas-common.c +++ b/disas/disas-common.c @@ -7,7 +7,6 @@ #include "disas/disas.h" #include "disas/capstone.h" #include "hw/core/cpu.h" -#include "exec/tswap.h" #include "disas-internal.h" @@ -61,14 +60,11 @@ void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu) s->cpu = cpu; s->info.print_address_func = print_address; - if (target_words_bigendian()) { - s->info.endian = BFD_ENDIAN_BIG; - } else { - s->info.endian = BFD_ENDIAN_LITTLE; - } + s->info.endian = BFD_ENDIAN_UNKNOWN; if (cpu->cc->disas_set_info) { cpu->cc->disas_set_info(cpu, &s->info); + g_assert(s->info.endian != BFD_ENDIAN_UNKNOWN); } }