From patchwork Tue Feb 11 19:43:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 864142 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5D5A1E5B7F; Tue, 11 Feb 2025 19:46:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303193; cv=none; b=FcgmzW/1J737AWZoEk0PsbQeLG4ha09hLFf37OkkbPxdWzGPWrq+ecC2MaCffSA6VmdSbvASnbnbHM9lPdQQoTgTgwDqfy3WbogxqxPqIUQXKr6mTqLjmuVLBVsRzmZKP/sZYinqnAbR6AgaYkN2fkJO78oWyxThbI7mZI4eqbw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303193; c=relaxed/simple; bh=mdpfH17o5dkDM3WpmrEspA/mb9FHGuKgj/Hbbefju8Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J+Ntm5IIGnOHp21eeMbTMI0ArR66TtSzo0IaGHynvvQhRbj/NMflWIPUU/ge5+sEW8kEwnpiSWRRC0RABI6TCa5Jb/qmTwUN1ekucJxxQ3WYhwldLzU4SY1vuD2uTxXofrgYH2Oksb8CXk//DKyghSn9xuOYdHj9jMlKaU2LLBU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Te5r9zT5; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Te5r9zT5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739303192; x=1770839192; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mdpfH17o5dkDM3WpmrEspA/mb9FHGuKgj/Hbbefju8Y=; b=Te5r9zT5Bt7pSjYMzzYbWkcpGFiRxQiz7NPqqqDg3NMBgiNmzEb/BHtm aqPiTUaQF/1imp+jGBEv+J6ytVYSKO5IJzmdcnfF7Pucb+GGIxZr461mL TilMK7TNT1HysImtrPakIXvIAdYAovpvbF/KTV92pUndARHsTy9pKfBEt QvvourrwWPFv6zX9sA9TOR0m1ArRlZMbfDkYt3EUeeZlx9MElRaiTp8oS VGbpNzZky8eH5kpG/oT0ehHU82+pq0hgcppIXNZLp4MSOo7Win0x7xJKK uNEqvzoZgH9xJVtaonjpmkhgbPNEhgaU9JTUNSE9Cfbp031sqkt6sKddi w==; X-CSE-ConnectionGUID: GeyYWcLuSx6NptSe085pAQ== X-CSE-MsgGUID: qcI1d0HnTCCmNsDd4JYP8A== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="39854802" X-IronPort-AV: E=Sophos;i="6.13,278,1732608000"; d="scan'208";a="39854802" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 11:46:29 -0800 X-CSE-ConnectionGUID: z1UQie1tT/uhlJlaQkVHDg== X-CSE-MsgGUID: VYDIrfl/QTqUmE5+1I+tsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143519258" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa001.fm.intel.com with ESMTP; 11 Feb 2025 11:46:29 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [PATCH v2 02/17] x86/smpboot: Fix INIT delay optimization for extended Intel Families Date: Tue, 11 Feb 2025 19:43:52 +0000 Message-ID: <20250211194407.2577252-3-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250211194407.2577252-1-sohil.mehta@intel.com> References: <20250211194407.2577252-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently only Family 6 is considered as modern and avoids the 10 msec INIT delay. The optimization doesn't extend to the upcoming Family 18/19 models. Also, the omission of Family 15 (Pentium 4s) seems like an oversight and should probably be included in the modern check as well. Choose a simpler check and extend the optimization to all Intel processors Family 6 and beyond. Signed-off-by: Sohil Mehta --- v2: Make the changelog more precise --- arch/x86/kernel/smpboot.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index eb91ed0f2a06..871c61df4edb 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -675,9 +675,9 @@ static void __init smp_set_init_udelay(void) return; /* if modern processor, use no delay */ - if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || - ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || - ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { + if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86_vfm >= INTEL_PENTIUM_PRO) || + (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON && boot_cpu_data.x86 >= 0x18) || + (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && boot_cpu_data.x86 >= 0xF)) { init_udelay = 0; return; } From patchwork Tue Feb 11 19:43:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 864141 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A48D262D0D; Tue, 11 Feb 2025 19:46:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303194; cv=none; b=S5+PokEmt0h+/7jdeMRHhjviqJierlCu+T2sx/ih76G9lTDLzAepGX9Ef2PZbgH1Ej7ZYmdhOQxwcUjmIr5ytA2AuU8UQqMr3uX8R+W9ETH05Iz/ASLoC4Zjss9jXwUyt7BnKzI3xpcwXFyJiPy2GKMx7ECx2fjjRMQ2777uHLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303194; c=relaxed/simple; bh=ePwF89ZyGeQ88u1VMJmUdubzH3tE/n8QmTHiT5e0Tw8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mPae8zKGxTnU0ReMkiB+RbLxtwU4dEThZ3KHzU42GByhMCTj0woWQN8YZGIU1apKa1ZjUzryPb2ibbGGKy9Bc6SjL/eRO2acJNphkovzQ8ghrDMNN7IxWAT9lBcDfGbH6UGeWgjnHTIcqadQdceVydm+GeVIYDEEeX53MxYkK1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VOHlEdJy; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VOHlEdJy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739303193; x=1770839193; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ePwF89ZyGeQ88u1VMJmUdubzH3tE/n8QmTHiT5e0Tw8=; b=VOHlEdJyxWtZzWf9syCerBYhTxGvm7IHEiup1j3jq35KlngC8EsIS490 omS/M6IyC8AeBoXlBaRdfWcgJQVh+ZtXH2/Zm8m4AjwLKtfAMCoRrM9Lz rHLt7+b0x6Quupxw7l4eHNsdIFd/t5sPrfpa6Apcv9qzVKJkKGG2vBVFV 7A6jtR+XCfrr+f/tbLeBNNcadFFjBwITv9zVWX+5bkDRLZQS6WuRdiHIX sFoSnhU299gS3Mt22JtSfd5/dWMhLx17OrFCO1Ga1r3gGRbPCygOvwAGG nVKDB4UpJ75+p+QLvNPAbTNXKvYpdheH3hQFtRoNhDNTg/JdpqriRGLTa g==; X-CSE-ConnectionGUID: m6JpGQMOQa+6P7Kx6qWB2w== X-CSE-MsgGUID: ljaZSWbdQKay9TB9eSUTOw== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="39854839" X-IronPort-AV: E=Sophos;i="6.13,278,1732608000"; d="scan'208";a="39854839" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 11:46:31 -0800 X-CSE-ConnectionGUID: YyreT7gCTA+apRxuwOe1IQ== X-CSE-MsgGUID: JrlHJLAtSaCQhcBTGPb/NQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143519266" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa001.fm.intel.com with ESMTP; 11 Feb 2025 11:46:30 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [PATCH v2 04/17] x86/cpu/intel: Fix the movsl alignment preference for extended Families Date: Tue, 11 Feb 2025 19:43:54 +0000 Message-ID: <20250211194407.2577252-5-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250211194407.2577252-1-sohil.mehta@intel.com> References: <20250211194407.2577252-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The alignment preference for 32-bit movsl based bulk memory move has been 8-byte for a long time. However this preference is only set for Family 6 and 15 processors. Extend the preference to upcoming Family numbers 18 and 19 to maintain legacy behavior. Also, use a VFM based check instead of switching based on Family numbers. Refresh the comment to reflect the new check. Signed-off-by: Sohil Mehta --- v2: Split the patch into two parts. Update commit message. --- arch/x86/kernel/cpu/intel.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 3dce22f00dc3..e5f34a90963e 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -449,23 +449,16 @@ static void intel_workarounds(struct cpuinfo_x86 *c) (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) set_cpu_bug(c, X86_BUG_11AP); - #ifdef CONFIG_X86_INTEL_USERCOPY /* - * Set up the preferred alignment for movsl bulk memory moves + * movsl bulk memory moves can be slow when source and dest are not + * both 8-byte aligned. PII/PIII only like movsl with 8-byte alignment. + * + * Set the preferred alignment for Pentium Pro and newer processors, as + * it has only been tested on these. */ - switch (c->x86) { - case 4: /* 486: untested */ - break; - case 5: /* Old Pentia: untested */ - break; - case 6: /* PII/PIII only like movsl with 8-byte alignment */ + if (c->x86_vfm >= INTEL_PENTIUM_PRO) movsl_mask.mask = 7; - break; - case 15: /* P4 is OK down to 8-byte alignment */ - movsl_mask.mask = 7; - break; - } #endif intel_smp_check(c); From patchwork Tue Feb 11 19:43:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 864140 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 000CF2638AC; Tue, 11 Feb 2025 19:46:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303195; cv=none; b=q3iHAT8plM+ZT9ll6B6Ebw8Q2H6wSoRiN/22AV4xl58KbKeaNIcFNhbLXIOZjLE/7vZWaXpLliiz88UrOwb8kJRYYdUiLWQGk2Ie3eU3RqJuWODqX4P0Ix2zLJDO8faGoLmbmynzeH6fjHyoW44g9FE9Pic+cRgI6uJiYNCiEhU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303195; c=relaxed/simple; bh=UJAvG1jigca5lIA6pwMy0uKJY5UsaQ/LXhbyxsZnADc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fMg4EvS6ng7DalcvYkhAQEiefXtxZIbE+nQE5wv/mTW7PdzjNEBX4h786dJtsJDwGmcdN8tX04UiJRXhuvsbcCO2tBo14GOcnk5ftma59NRks0DsY5BB1aw4f+urBFeGTsvQNF0ARaIXKiWGygszNcLjx/+Gkv+qk7Pzgux1YdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PRUuzCrv; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PRUuzCrv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739303194; x=1770839194; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UJAvG1jigca5lIA6pwMy0uKJY5UsaQ/LXhbyxsZnADc=; b=PRUuzCrvqGA2glGK6EX68rnOfPY1Q0SLvU22trChBpzGL/wZ504ZmMnh ziidvZmbQk/UeWz1Np5sU+U3FGBWdHJZBmnJeuRupy1EMynS8QXetKLoR mbdW7qBY+xfLVCw9MAFOMcD4izOvzCwRw0PFRGmvPCQn0bRUGqhOkInPl DIzf00A/QS1+6s7dqQzusHH13fYX2YxDowGMxGgHiyXvWMJOLACVzD4gU 9pAFJBvfn0PG0uuGDUzAPWyTiFW/a5RWwCpaq+5R3YEkm0UWTYTYTVVjt KyHogWlN1j0vl2IlPidj29luret0i/Z2oBY/3eftC3thqlGQQ8LgBGq4R A==; X-CSE-ConnectionGUID: GsNPeIyaSnW1UkaDbWegQg== X-CSE-MsgGUID: qoStRDC0RsydDUr6SHkrMg== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="39854880" X-IronPort-AV: E=Sophos;i="6.13,278,1732608000"; d="scan'208";a="39854880" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 11:46:32 -0800 X-CSE-ConnectionGUID: iJJLIjOWRQat8XwnT7y0zA== X-CSE-MsgGUID: Y5QTbKMKQUSKPWqutvaibg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143519276" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa001.fm.intel.com with ESMTP; 11 Feb 2025 11:46:31 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [PATCH v2 06/17] cpufreq: Fix the efficient idle check for Intel extended Families Date: Tue, 11 Feb 2025 19:43:56 +0000 Message-ID: <20250211194407.2577252-7-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250211194407.2577252-1-sohil.mehta@intel.com> References: <20250211194407.2577252-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 IO time is considered as busy by default for modern Intel processors. However the check doesn't include the upcoming Family 18 and 19 processors. Also, Arjan van de Ven says the current nature of the check was mainly due to lack of testing on old systems. He suggests considering all Intel processors as having efficient idle. Extend the IO busy classification to all Intel processors starting with Family 6. Signed-off-by: Sohil Mehta --- v2: Improve commit message and code comments. --- drivers/cpufreq/cpufreq_ondemand.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/cpufreq_ondemand.c b/drivers/cpufreq/cpufreq_ondemand.c index a7c38b8b3e78..b13f197707f4 100644 --- a/drivers/cpufreq/cpufreq_ondemand.c +++ b/drivers/cpufreq/cpufreq_ondemand.c @@ -15,6 +15,10 @@ #include #include +#ifdef CONFIG_X86 +#include +#endif + #include "cpufreq_ondemand.h" /* On-demand governor macros */ @@ -32,21 +36,20 @@ static unsigned int default_powersave_bias; /* * Not all CPUs want IO time to be accounted as busy; this depends on how * efficient idling at a higher frequency/voltage is. - * Pavel Machek says this is not so for various generations of AMD and old - * Intel systems. + * Pavel Machek says this is not so for various generations of AMD. * Mike Chan (android.com) claims this is also not true for ARM. - * Because of this, whitelist specific known (series) of CPUs by default, and + * Because of this, select known series of CPUs by default, and * leave all others up to the user. */ static int should_io_be_busy(void) { #if defined(CONFIG_X86) /* - * For Intel, Core 2 (model 15) and later have an efficient idle. + * Starting with Family 6 consider all Intel CPUs to have an + * efficient idle. */ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && - boot_cpu_data.x86 == 6 && - boot_cpu_data.x86_model >= 15) + boot_cpu_data.x86_vfm >= INTEL_PENTIUM_PRO) return 1; #endif return 0; From patchwork Tue Feb 11 19:43:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 864139 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CE13264621; Tue, 11 Feb 2025 19:46:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303197; cv=none; b=LMSGr/TSqlMkzOITTu1LO0IvIOkkivLSnM8VbfvDXLhgf152ml/kcFePBeMndKR1za3N83eC451bLtm2zfv5zzMcJC57yWYclLSHsLs8iZW7ZPzQI4HjTEcX07unYm0VezzU2zj+Ilso4UJ0Twy6UmkCmnYoYAtSnv7KpnlUAAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303197; c=relaxed/simple; bh=nzUCrs1+DTXuNre3max01ArGpANP9d9Vy4S2KxVyNPg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jg080a5sQtP0TEJiJclHAHmXWrMfQM2EY6DeGmrbPOI5Z4F6ruzj2KuDthwNFJNcM5CCKrO425i93uybYrI/paPkKrjBff02F/HxTdp9fpzzHEBMxAmSaDcMxUplrhDXHTdzSaRbjeomRVPgoQmjDrs8Rr/csKCoKp4R5OGhwwY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DbMS2vCG; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DbMS2vCG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739303196; x=1770839196; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nzUCrs1+DTXuNre3max01ArGpANP9d9Vy4S2KxVyNPg=; b=DbMS2vCG7CApEu354OFasqhtdEx6ZZhWPmTx9BN3EktxV1ahDuzXoT74 uq6PJnapscu2rEGs+T0ovri4TtpVwl5eubOlu7LckNllHLBZ0/EjNJFbE sKaQXbSbVMkk2zetqgkF3vXB/nl6mzbA/HwxZxzgfslY5OESMTFn9Lpxf mIjlMdOPapG3QXxAasCTP3a8Z5P47VIGkDST1oqm6D/g+F0l5NZhlp1MD RWS6kQfPFHImlruCjKnw5ZjcrUqpL6LgEXiQUrHP/rsL/yLdzwAQFtGQt kHGl3+1WoeXSQ8Mxd8jJI2QPT7lQrQDSbpD1WgFSfCE6UAY/swINGWoS4 w==; X-CSE-ConnectionGUID: lw6r7UAPSRSUSEuSCZncIw== X-CSE-MsgGUID: NPr08YlPTqaT/zm+R4qJJQ== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="39854913" X-IronPort-AV: E=Sophos;i="6.13,278,1732608000"; d="scan'208";a="39854913" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 11:46:33 -0800 X-CSE-ConnectionGUID: fwJaGHBtQI6D7LhuuIK/xQ== X-CSE-MsgGUID: NPAaN3yLShqbZTeGCxww8g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143519283" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa001.fm.intel.com with ESMTP; 11 Feb 2025 11:46:33 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [PATCH v2 08/17] x86/microcode: Update the Intel processor flag scan check Date: Tue, 11 Feb 2025 19:43:58 +0000 Message-ID: <20250211194407.2577252-9-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250211194407.2577252-1-sohil.mehta@intel.com> References: <20250211194407.2577252-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Family model check to read the processor flag MSR is misleading and potentially incorrect. It doesn't consider Family while comparing the model number. The original check did have a Family number but it got lost/moved during refactoring. intel_collect_cpu_info() is called through multiple paths such as early initialization, CPU hotplug as well as IFS image load. Some of these flows would be error prone due to the ambiguous check. Correct the processor flag scan check to use a Family number and update it to a VFM based one to make it more readable. Signed-off-by: Sohil Mehta --- v2: Use a VFM check instead of hardcoded numbers. I evaluted whether CPUID can be avoided in intel_collect_cpu_info(). But the answer seems a bit more complex than I expected. * On the BSP, intel_collect_cpu_info() can be called very early via load_ucode_bsp() even before cpu_data[] has been populated. * In the hotplug path, based on section II.c. of Documentation/power/suspend-and-cpuhotplug.rst rescanning of FMS during ucode load might be intentional. Maybe this can be resolved by updating the Intel ucode load flows to pass the CPU information or the cpuid_eax information around. But it is beyond the scope of this series. Also, I am not sure whether the effort/risk would be worth saving a single cpuid() call in an uncommon path. If this is desired, I can work on it in a seperate patch. --- arch/x86/include/asm/intel-family.h | 1 + arch/x86/kernel/cpu/microcode/intel.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 6d7b04ffc5fd..cccc932d761e 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -46,6 +46,7 @@ #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) #define INTEL_PENTIUM_PRO IFM(6, 0x01) +#define INTEL_PENTIUM_III_DESCHUTES IFM(6, 0x05) #define INTEL_CORE_YONAH IFM(6, 0x0E) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index f3d534807d91..819199bc0119 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -74,7 +74,7 @@ void intel_collect_cpu_info(struct cpu_signature *sig) sig->pf = 0; sig->rev = intel_get_microcode_revision(); - if (x86_model(sig->sig) >= 5 || x86_family(sig->sig) > 6) { + if (IFM(x86_family(sig->sig), x86_model(sig->sig)) >= INTEL_PENTIUM_III_DESCHUTES) { unsigned int val[2]; /* get processor flags from MSR 0x17 */ From patchwork Tue Feb 11 19:44:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 864138 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1E5F265CA5; Tue, 11 Feb 2025 19:46:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303198; cv=none; b=DG7+OrgsFLfmHL+UobMY1wu5C0wsMyu9mWy1o+rk1fP/zl/luBxsjSDK5/Bg26WjYDyMMYsFh6f1nsBjK3cEPQARyk4y5UCuqrhKBnghmr3ZDHhLGzA+Khpdm90cCC+sMt4sfx0uqPBDaQDKRF5AdYdkajc4v9cOStT6YhisOAc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303198; c=relaxed/simple; bh=RW1ny/tYzrCYc8zeQqvO3ayjEhUrOOQFk5fWlGTpPRI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m1ym/S3LwsX55yDAiQ0yfqP2JEruO8yGLVvyYcG/jfrX9VnVEKsYvCWt3tcraPMbEfx1oKoJoXJiHAQz7eQeRfQXpQyMfcybUEGcjp229Yg9cEH3S23eurtvTwgbf1RmBvEfIdCM4Va/amNLt8kM2qY6ZpNcfVXhv3Ajp+mtdRE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lDScgHHc; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lDScgHHc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739303197; x=1770839197; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RW1ny/tYzrCYc8zeQqvO3ayjEhUrOOQFk5fWlGTpPRI=; b=lDScgHHc4MtPEVjEj0BU8DlgiCfNPrs53UdLCcdR5xmXbzCFaD6HzyOl rsXHpQ55pTNdeIbrTqlgVQOJ2NYyu8gdCZIMgx7GxuodD9td2Zd5QNzJ/ vHoy+CQ8n7qn23W/3w6djx905tpG4MSPDCT+W+4EW00/+faWuQg4oPWEI fr/W1xDDu3EyzOKa8NW8owvTjk5/WpNiIEXR3vpP7EohXrro8moy17H8+ UdGNgxnikg9fWTvY6njbkf9ZXUfEykp3Mk1qgIeN0C7eejWSidSHLryOy /oM5iQ3BO4CmxLC8s8sYpdf0l9/YdbFH0XF0NcznnSpqh3Gql8qa85Qcm g==; X-CSE-ConnectionGUID: vuV/8ReCR3uMN6MzDd0yaw== X-CSE-MsgGUID: BY4JY2TiQouMZh1HSOf6KA== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="39854944" X-IronPort-AV: E=Sophos;i="6.13,278,1732608000"; d="scan'208";a="39854944" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 11:46:34 -0800 X-CSE-ConnectionGUID: 6QzRga5jTEGQhiDKHYAbug== X-CSE-MsgGUID: l2jWCZXDRUK5uVe/JIIVpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143519292" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa001.fm.intel.com with ESMTP; 11 Feb 2025 11:46:34 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [PATCH v2 10/17] x86/cpu/intel: Replace early Family 6 checks with VFM ones Date: Tue, 11 Feb 2025 19:44:00 +0000 Message-ID: <20250211194407.2577252-11-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250211194407.2577252-1-sohil.mehta@intel.com> References: <20250211194407.2577252-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce names for some old pentium models and replace the x86_model checks with VFM ones. Signed-off-by: Sohil Mehta --- v2: No change --- arch/x86/include/asm/intel-family.h | 4 ++++ arch/x86/kernel/cpu/intel.c | 13 ++++++------- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index cccc932d761e..c1a081585fcb 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -45,8 +45,12 @@ /* Wildcard match so X86_MATCH_VFM(ANY) works */ #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) +/* Family 6 */ #define INTEL_PENTIUM_PRO IFM(6, 0x01) +#define INTEL_PENTIUM_II_KLAMATH IFM(6, 0x03) #define INTEL_PENTIUM_III_DESCHUTES IFM(6, 0x05) +#define INTEL_PENTIUM_III_TUALATIN IFM(6, 0x0B) +#define INTEL_PENTIUM_M_DOTHAN IFM(6, 0x0D) #define INTEL_CORE_YONAH IFM(6, 0x0E) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 4f8b02cbe8c5..1b6e077a037a 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -195,7 +195,7 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return; - if (c->x86 < 6 || (c->x86 == 6 && c->x86_model < 0xd)) + if (c->x86_vfm < INTEL_PENTIUM_M_DOTHAN) return; /* @@ -309,7 +309,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) * If fast string is not enabled in IA32_MISC_ENABLE for any reason, * clear the fast string and enhanced fast string CPU capabilities. */ - if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { + if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) { rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { pr_info("Disabled fast string operations\n"); @@ -358,9 +358,7 @@ static void bsp_init_intel(struct cpuinfo_x86 *c) int ppro_with_ram_bug(void) { /* Uses data from early_cpu_detect now */ - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && - boot_cpu_data.x86 == 6 && - boot_cpu_data.x86_model == 1 && + if (boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO && boot_cpu_data.x86_stepping < 8) { pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); return 1; @@ -421,7 +419,8 @@ static void intel_workarounds(struct cpuinfo_x86 *c) * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until * model 3 mask 3 */ - if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) + if ((c->x86_vfm == INTEL_PENTIUM_II_KLAMATH && c->x86_stepping < 3) || + c->x86_vfm < INTEL_PENTIUM_II_KLAMATH) clear_cpu_cap(c, X86_FEATURE_SEP); /* @@ -621,7 +620,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) * to determine which, so we use a boottime override * for the 512kb model, and assume 256 otherwise. */ - if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) + if (c->x86_vfm == INTEL_PENTIUM_III_TUALATIN && size == 0) size = 256; /* From patchwork Tue Feb 11 19:44:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 864137 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90C97267B84; Tue, 11 Feb 2025 19:46:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303200; cv=none; b=ZT2QZctDq8fZPnT6EkC+w8IkljOQzh4fzzauehi3cO0u/q9JWan/N6GF1tJyvbzlgBl6w42W61bVXun36iolGWdWSG3IGhGCjHr5BaMpyjbDVgLwcxVO+qMuekMNfzbremvCYqwD3ItvRSdhosR6xiqrhRMadovvdRT7aAWc7A0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303200; c=relaxed/simple; bh=ovSvGTD2eoxGo/w6M7zOZJrTYNbTQnNqk+N7Hm0U4M4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WpR5gJD2ycU9GnNta4MO/G6UPesGmv8c/mQKBjkK32G1+fhVQ4Qtkt35EXn4Ns11ojR+5YL4zW0V05ahubLvH3gemj+TBk8dVHNtkP7KyizJzcVhpvtMNuDZBmT3hTz7NUfarq4I0lq1lLLdz4yqOFdVQGdQzk2/jAY86YQr6ac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GsQA4DVY; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GsQA4DVY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739303199; x=1770839199; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ovSvGTD2eoxGo/w6M7zOZJrTYNbTQnNqk+N7Hm0U4M4=; b=GsQA4DVYnivsMaTmPatta0kDNgLc5Kk8hoPAzUR9gPtq19H7Gu5eJLmu 8p7CbRgACldVeaGLOXjjlnjqK8ua986CeDWo5Vvj63k5YsZpY/O3CqfHg YCBa5uBGQ2UWHS0apX0MFJgWkZEUMIgmlFbZnI5W/7yZWIX9Asb2RYfbK Fb1Rct8bbIe3o1rvIHqOxk3fbzkt692iHbclopWK80Jxlrjw3BVBvJk1v ds6QpNHJi7lBoaM1XG6DpRHdyIzldjI9fkrCLwg8E8ca0ibDkyYKKpZ8L yB25wH0uTaianqJL/aARIbmyPWhnd2wY5j+6UpgxybFSCa1b8uKbdMx76 Q==; X-CSE-ConnectionGUID: PdUxOQFsT2KQkRZJJnjPFA== X-CSE-MsgGUID: UITlqjPgQxeLWB6SnEIOpw== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="39854973" X-IronPort-AV: E=Sophos;i="6.13,278,1732608000"; d="scan'208";a="39854973" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 11:46:35 -0800 X-CSE-ConnectionGUID: mOkwpg8cRJmcQtKP9JbZsw== X-CSE-MsgGUID: uU2Bpy/mRyO4VQQoMIuYRQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143519301" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa001.fm.intel.com with ESMTP; 11 Feb 2025 11:46:35 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [PATCH v2 12/17] x86/cpu/intel: Replace Family 5 model checks with VFM ones Date: Tue, 11 Feb 2025 19:44:02 +0000 Message-ID: <20250211194407.2577252-13-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250211194407.2577252-1-sohil.mehta@intel.com> References: <20250211194407.2577252-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce names for some Family 5 models and convert some of the checks to be VFM based. Also, to keep the file sorted by family, move Family 5 to the top of the header file. Signed-off-by: Sohil Mehta --- v2: Reorder the Family 5 models to be at the top of the file. --- arch/x86/include/asm/intel-family.h | 9 ++++++--- arch/x86/kernel/cpu/intel.c | 11 +++++------ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index f509061b8c7e..9e6a13f03f0e 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -45,6 +45,12 @@ /* Wildcard match so X86_MATCH_VFM(ANY) works */ #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) +/* Family 5 */ +#define INTEL_FAM5_START IFM(5, 0x00) /* Notational marker, also P5 A-step */ +#define INTEL_PENTIUM_75 IFM(5, 0x02) /* P54C */ +#define INTEL_PENTIUM_MMX IFM(5, 0x04) /* P55C */ +#define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */ + /* Family 6 */ #define INTEL_PENTIUM_PRO IFM(6, 0x01) #define INTEL_PENTIUM_II_KLAMATH IFM(6, 0x03) @@ -181,9 +187,6 @@ #define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */ #define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */ -/* Family 5 */ -#define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */ - /* Family 15 - NetBurst */ #define INTEL_P4_WILLAMETTE IFM(15, 0x01) /* Also Xeon Foster */ #define INTEL_P4_PRESCOTT IFM(15, 0x03) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 507cb4c6d587..1b01ef4dfda2 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -375,9 +375,8 @@ static void intel_smp_check(struct cpuinfo_x86 *c) /* * Mask B, Pentium, but not Pentium MMX */ - if (c->x86 == 5 && - c->x86_stepping >= 1 && c->x86_stepping <= 4 && - c->x86_model <= 3) { + if (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_PENTIUM_MMX && + c->x86_stepping >= 1 && c->x86_stepping <= 4) { /* * Remember we have B step Pentia with bugs */ @@ -404,7 +403,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c) * The Quark is also family 5, but does not have the same bug. */ clear_cpu_bug(c, X86_BUG_F00F); - if (c->x86 == 5 && c->x86_model < 9) { + if (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_QUARK_X1000) { static int f00f_workaround_enabled; set_cpu_bug(c, X86_BUG_F00F); @@ -452,7 +451,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c) * integrated APIC (see 11AP erratum in "Pentium Processor * Specification Update"). */ - if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && + if (boot_cpu_has(X86_FEATURE_APIC) && c->x86_vfm == INTEL_PENTIUM_75 && (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) set_cpu_bug(c, X86_BUG_11AP); @@ -627,7 +626,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) * Intel Quark SoC X1000 contains a 4-way set associative * 16K cache with a 16 byte cache line and 256 lines per tag */ - if ((c->x86 == 5) && (c->x86_model == 9)) + if (c->x86_vfm == INTEL_QUARK_X1000) size = 16; return size; } From patchwork Tue Feb 11 19:44:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 864136 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FEFA269CF0; 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a="39855015" X-IronPort-AV: E=Sophos;i="6.13,278,1732608000"; d="scan'208";a="39855015" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 11:46:37 -0800 X-CSE-ConnectionGUID: FA+WwvtKRBays9aeg2PjtA== X-CSE-MsgGUID: mjez5CfLQ+iOcRlUF7vkVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143519312" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa001.fm.intel.com with ESMTP; 11 Feb 2025 11:46:36 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [PATCH v2 15/17] x86/cpu/intel: Bound the non-architectural constant_tsc model checks Date: Tue, 11 Feb 2025 19:44:05 +0000 Message-ID: <20250211194407.2577252-16-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250211194407.2577252-1-sohil.mehta@intel.com> References: <20250211194407.2577252-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Constant TSC has been architectural on Intel CPUs for a while. Supported CPUs use the architectural Invariant TSC bit in CPUID.80000007. A Family-model check is not required for these CPUs. Prevent unnecessary confusion but restricting the model specific checks to CPUs that need it and moving it closer to the architectural check. Invariant TSC was likely introduced around the Nehalam timeframe on the Xeon side and Saltwell timeframe on the Atom side. Due to interspersed model numbers extend the non-architectural capability setting until Ivybridge to be safe. Signed-off-by: Sohil Mehta --- v2: No change. --- arch/x86/kernel/cpu/intel.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 1b01ef4dfda2..ab195dcea50b 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -210,10 +210,6 @@ static void early_init_intel(struct cpuinfo_x86 *c) { u64 misc_enable; - if ((c->x86 == 0xf && c->x86_model >= 0x03) || - (c->x86 == 0x6 && c->x86_model >= 0x0e)) - set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); - if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) c->microcode = intel_get_microcode_revision(); @@ -272,6 +268,11 @@ static void early_init_intel(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); } + /* Some older CPUs have invariant TSC but may not report it architecturally via 8000_0007 */ + if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_WILLAMETTE) || + (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); + /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ switch (c->x86_vfm) { case INTEL_ATOM_SALTWELL_MID: From patchwork Tue Feb 11 19:44:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 864135 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FE6F269CEF; Tue, 11 Feb 2025 19:46:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303204; cv=none; b=SAZf5LTdpEJVTjp047p4PWzXJqCDcnRBwH/imuk9MsuOx0p28FsUDYj2XMG8UrxLuhk34xKwNiEN/ykIlYr6+LpF2bYiflSpqWXeAtpud7u1+G4PcuiMjzhpqKnqoavyPu9gKWtGBRx/ZOtkrJgl7zDoQ6EZ5Xi+nYDPCH61XJI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739303204; c=relaxed/simple; bh=zc8rXlTX5Ht3PzLU/txMXtYoBxP3G1MDHe0W5dQiEsg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sIWaurO3zonN8T7p5BLgOeU38vcgsnITxqKG5/kN4z66EoiHVIHc5Btse8rXSLIw3c6RSjd8yZDcB2NiRXTAGbxn1OmUi/5wNoCq95F8OP6DAsPawvl4JwWcKMNLhokW/C5nDn2Gibe7xpm29q2EkFKoKw0hFrAKov0AW/PtnJk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=f9BKt5Mp; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="f9BKt5Mp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739303202; x=1770839202; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zc8rXlTX5Ht3PzLU/txMXtYoBxP3G1MDHe0W5dQiEsg=; b=f9BKt5Mp46RfFkyv2Lrywt259WKoyU3NDz7rxjgNeK2OP+swf7NHm9AK 5Fib8cAYImPbD1IMUScSEEvDxhSuErWUnrqkMSEMgA8MJ1YgqlCPQPoFa G9ySfLW6bxa2YHHbdmcb8G/sXIcyIyRVd4DWWX3RUNwQ2hSvjcgdNXB/o IOyp9MsBY2MsxujfnV/AmgrN3ZYz189u++1gJGWN3Ln1KSFq2rdHVUruY 2qSaKB8J4qorlNXUZnzQ8SqyDUHG7WXJZzKa0n60LA9hOBz9x0u/o8nCM CWXHNVPvSYVUiyI953YhKOtF146ewD7ABAtycqHJltMFPKlUwKgIhRKb+ Q==; X-CSE-ConnectionGUID: EV36C4P2Q1uzAXpK//Y2EA== X-CSE-MsgGUID: +5Iv4kQaSeSnK5z4iAzhFw== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="39855029" X-IronPort-AV: E=Sophos;i="6.13,278,1732608000"; d="scan'208";a="39855029" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 11:46:37 -0800 X-CSE-ConnectionGUID: CA9spOHLT1i+GCi+S+jTKg== X-CSE-MsgGUID: 0/OfcbVdQaa1ala7LvkDpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143519315" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa001.fm.intel.com with ESMTP; 11 Feb 2025 11:46:36 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [PATCH v2 16/17] perf/x86: Simplify P6 PMU initialization Date: Tue, 11 Feb 2025 19:44:06 +0000 Message-ID: <20250211194407.2577252-17-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250211194407.2577252-1-sohil.mehta@intel.com> References: <20250211194407.2577252-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 A switch case is unnecessary when only a single case matters. Also, the gaps in the case numbers are due to no CPU with those model numbers being released. Avoid the switch case and combine the cases into simpler VFM checks. Also, this gets rid of one last few Intel x86_model comparisons. No functional change intended. Signed-off-by: Sohil Mehta --- v2: No change. --- arch/x86/events/intel/p6.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c index a6cffb4f4ef5..37e3beb6d633 100644 --- a/arch/x86/events/intel/p6.c +++ b/arch/x86/events/intel/p6.c @@ -2,6 +2,8 @@ #include #include +#include + #include "../perf_event.h" /* @@ -244,35 +246,19 @@ static __init void p6_pmu_rdpmc_quirk(void) } } +/* Only called for Family 6 CPUs without X86_FEATURE_ARCH_PERFMON */ __init int p6_pmu_init(void) { x86_pmu = p6_pmu; - switch (boot_cpu_data.x86_model) { - case 1: /* Pentium Pro */ - x86_add_quirk(p6_pmu_rdpmc_quirk); - break; - - case 3: /* Pentium II - Klamath */ - case 5: /* Pentium II - Deschutes */ - case 6: /* Pentium II - Mendocino */ - break; - - case 7: /* Pentium III - Katmai */ - case 8: /* Pentium III - Coppermine */ - case 10: /* Pentium III Xeon */ - case 11: /* Pentium III - Tualatin */ - break; - - case 9: /* Pentium M - Banias */ - case 13: /* Pentium M - Dothan */ - break; - - default: + if (boot_cpu_data.x86_vfm >= INTEL_CORE_YONAH) { pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model); return -ENODEV; } + if (boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO) + x86_add_quirk(p6_pmu_rdpmc_quirk); + memcpy(hw_cache_event_ids, p6_hw_cache_event_ids, sizeof(hw_cache_event_ids));