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Tue, 11 Feb 2025 02:37:47 -0800 From: Sumit Gupta To: , , , , , , , , , CC: , , , , , , , , Subject: [Patch 1/5] ACPI: CPPC: add read perf ctrls api and rename few existing Date: Tue, 11 Feb 2025 16:07:33 +0530 Message-ID: <20250211103737.447704-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250211103737.447704-1-sumitg@nvidia.com> References: <20250211103737.447704-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB51:EE_|MN0PR12MB5786:EE_ X-MS-Office365-Filtering-Correlation-Id: e2280d21-b61a-4749-9810-08dd4a882b85 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|7416014|376014|36860700013|82310400026|1800799024|921020; X-Microsoft-Antispam-Message-Info: q1BYjg1P9u7EbDK4bw3s9TsB6zI8GPho4Sq/miRaIpM2IxfZUuiPTbZudKhbTrybTHxwd8JPX8V3e8I5Zb5wQTDG1a1UVwovd2EyCNJMiOpT9U4VnhCRFaW55IG4Y+V1TBNbcwBLQ/x9rOSbZNubS3H7Z+Yj4D5NyOwNOryV1auliVM4LyWpno6zH1hiUP0lmioIDPK+qee3T8Lzon7010YzeiQAOVwLATJzA/IbwcFeFYAe1T2bJRm4PeWHCz1fGQPivNo6eg4xpSvHvah9DXTPm4b6OhwrDEKhEh/Ir6bIa/PMQ5zLqCdoOpTZfRko5Zs6BuVSPgcHJt8LmXPZif3Jj7GwBEWGbgpKk7alpIE1cXcTWXD97SQoH/0vDCNpdzfLjwcIzvHKSNn+THjm8K5UTbEId98jEnxFRe/9VGUPlYhOvaKjsNDYMDVGovQcoc1kDc6tBvfBS8mdOk1X6foaSz3C75GNibNeafCtTP8cv9fss7Gygc/IRWWejnq+9iv1is8ohrOTCIOeJWjR/+gzG5Nf6YobSrkgMrsfxvBSm+KZO9CzOR2aFUS54/LSl+zJLPtYK0JgVqnedZuS44X3aVW40oyUMsu+KmBP59kmvmXQ3oiDDCQ6CeHf9pD7BZ08RHPEDiVisIhMdzMZHRkRZdRDPt39dIr4sRVeG3RsppjUq3J556cn3VEFzxc1AHVqQi5GwD4UAUX4Ig3dMiK2Cq8u9zB+P/Daac5yZtaSu8HTWfd9k7AnXxZJmLNp2Mqe2y0OEfUZprmvqNLmEnvn4lxBnId4YQpYh5E0Uc90e0UtpPUBvtPr38bFeRnkisYbzePUHRLwjzmg1IH75s+tyWrsPfx9XrXpjkaKpirz9RHI2cWlNGuFZKZBng+0e748E5Ekmnq8krGJ0i5KLLCq8AXq7JGVlxbDvjYVa42PVXlmTgP2/hVGSRWp54sUtu/u5IoZWzKfKKabA/npnmVqa9kydiu6TEwiD/ETIhXjXyrUKDINY+H20eLPxc4VNYmxwvofSRKDFsmYFth4djaAXFNixzu/OhV+66/pqyrsVGSTvGrda+rFxlf9+N8hjrP3AhVjtEJWHou9EG9JnvvFi3Hvmr1TRMctWjDVh2rdPOvjLADFqJGKYNNYWgI8cMAugjcujedX4hT5yFXIFXrtzQ1gv/DRojoYEw7zcBGCgQNV++CEWkQ5da7o0tNnBMLYe6lqohpufw4Cg2XMNUmo1AlF8Y56S2/vry680k9pz3qSFo+r3AY0iHVT+wKdUOuulup4QH1oyqrg9DMtQlfFBAK5V/vbKEwZJycAtdGQq2eRLlHhCCp9iJMt6MbTE46GvgnKbUMZCfPrT1XoSg4KpzHJqK7W/SHiGXmRvEktQn4bWE7bFyhARbpFD3zKubFEHYc9IusthBTIRLHSpYvdWUynyQOPtuCpTZgqXJDkEvYBsPP6Qs3t8S8jXB1iYkjid8MlJzFBGTNY5UCDb55yNg/mQ+kzZJF5luSucSoZ8gLzcMZ1nRah0V5xVjxf X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 10:38:06.0630 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2280d21-b61a-4749-9810-08dd4a882b85 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB51.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5786 Add new API cppc_get_perf_ctrls() to read the performance controls. Rename the following existing API's for more clarity. - cppc_set_perf() to cppc_set_perf_ctrls(). - cppc_get_perf_ctrs() to cppc_get_perf_fb_ctrs(). - cppc_get_perf_ctrs_sample() to cppc_get_perf_fb_ctrs_sample(). Also, remove redundant energy_perf field from 'struct cppc_perf_caps'. It is also present in 'struct cppc_perf_ctrls' which is being used. Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 91 +++++++++++++++++++++++++++++----- drivers/cpufreq/cppc_cpufreq.c | 26 +++++----- include/acpi/cppc_acpi.h | 14 ++++-- 3 files changed, 101 insertions(+), 30 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index f193e713825a..297e689f8214 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -59,7 +59,7 @@ struct cppc_pcc_data { /* * Lock to provide controlled access to the PCC channel. * - * For performance critical usecases(currently cppc_set_perf) + * For performance critical usecases(currently cppc_set_perf_ctrls) * We need to take read_lock and check if channel belongs to OSPM * before reading or writing to PCC subspace * We need to take write_lock before transferring the channel @@ -169,8 +169,8 @@ show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, guaranteed_perf); show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); -show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); -show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); +show_cppc_data(cppc_get_perf_fb_ctrs, cppc_perf_fb_ctrs, reference_perf); +show_cppc_data(cppc_get_perf_fb_ctrs, cppc_perf_fb_ctrs, wraparound_time); /* Check for valid access_width, otherwise, fallback to using bit_width */ #define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width) @@ -189,7 +189,7 @@ static ssize_t show_feedback_ctrs(struct kobject *kobj, struct cppc_perf_fb_ctrs fb_ctrs = {0}; int ret; - ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); + ret = cppc_get_perf_fb_ctrs(cpc_ptr->cpu_id, &fb_ctrs); if (ret) return ret; @@ -1360,7 +1360,7 @@ EXPORT_SYMBOL_GPL(cppc_get_perf_caps); * * CPPC has flexibility about how CPU performance counters are accessed. * One of the choices is PCC regions, which can have a high access latency. This - * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time. + * routine allows callers of cppc_get_perf_fb_ctrs() to know this ahead of time. * * Return: true if any of the counters are in PCC regions, false otherwise */ @@ -1398,13 +1398,13 @@ bool cppc_perf_ctrs_in_pcc(void) EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc); /** - * cppc_get_perf_ctrs - Read a CPU's performance feedback counters. + * cppc_get_perf_fb_ctrs - Read a CPU's performance feedback counters. * @cpunum: CPU from which to read counters. * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h * * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. */ -int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) +int cppc_get_perf_fb_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); struct cpc_register_resource *delivered_reg, *reference_reg, @@ -1475,7 +1475,7 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) up_write(&pcc_ss_data->pcc_lock); return ret; } -EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); +EXPORT_SYMBOL_GPL(cppc_get_perf_fb_ctrs); /* * Set Energy Performance Preference Register value through @@ -1674,15 +1674,82 @@ int cppc_set_enable(int cpu, bool enable) return cpc_write(cpu, enable_reg, enable); } EXPORT_SYMBOL_GPL(cppc_set_enable); +/** + * cppc_get_perf - Get a CPU's performance controls. + * @cpu: CPU for which to get performance controls. + * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * + * Return: 0 for success with perf_ctrls, -ERRNO otherwise. + */ +int cppc_get_perf_ctrls(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *desired_perf_reg, *min_perf_reg, *max_perf_reg, + *energy_perf_reg; + u64 max, min, desired_perf, energy_perf; + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0, regs_in_pcc = 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + desired_perf_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; + min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF]; + max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF]; + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + /* Are any of the regs PCC ?*/ + if (CPC_IN_PCC(desired_perf_reg) || CPC_IN_PCC(min_perf_reg) || + CPC_IN_PCC(max_perf_reg) || CPC_IN_PCC(energy_perf_reg)) { + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id\n"); + return -ENODEV; + } + pcc_ss_data = pcc_data[pcc_ss_id]; + regs_in_pcc = 1; + down_write(&pcc_ss_data->pcc_lock); + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { + ret = -EIO; + goto out_err; + } + } + + /* Read optional elements if present */ + if (CPC_SUPPORTED(max_perf_reg)) + cpc_read(cpu, max_perf_reg, &max); + perf_ctrls->max_perf = max; + + if (CPC_SUPPORTED(min_perf_reg)) + cpc_read(cpu, min_perf_reg, &min); + perf_ctrls->min_perf = min; + + if (CPC_SUPPORTED(desired_perf_reg)) + cpc_read(cpu, desired_perf_reg, &desired_perf); + perf_ctrls->desired_perf = desired_perf; + + if (CPC_SUPPORTED(energy_perf_reg)) + cpc_read(cpu, energy_perf_reg, &energy_perf); + perf_ctrls->energy_perf = energy_perf; + +out_err: + if (regs_in_pcc) + up_write(&pcc_ss_data->pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf_ctrls); /** - * cppc_set_perf - Set a CPU's performance controls. + * cppc_set_perf_ctrls - Set a CPU's performance controls. * @cpu: CPU for which to set performance controls. * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h * * Return: 0 for success, -ERRNO otherwise. */ -int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +int cppc_set_perf_ctrls(int cpu, struct cppc_perf_ctrls *perf_ctrls) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg; @@ -1746,7 +1813,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) /* * This is Phase-II where we transfer the ownership of PCC to Platform * - * Short Summary: Basically if we think of a group of cppc_set_perf + * Short Summary: Basically if we think of a group of cppc_set_perf_ctrls * requests that happened in short overlapping interval. The last CPU to * come out of Phase-I will enter Phase-II and ring the doorbell. * @@ -1805,7 +1872,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) } return ret; } -EXPORT_SYMBOL_GPL(cppc_set_perf); +EXPORT_SYMBOL_GPL(cppc_set_perf_ctrls); /** * cppc_get_transition_latency - returns frequency transition latency in ns diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index b3d74f9adcf0..17c49653a3c4 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -90,7 +90,7 @@ static void cppc_scale_freq_workfn(struct kthread_work *work) cppc_fi = container_of(work, struct cppc_freq_invariance, work); cpu_data = cppc_fi->cpu_data; - if (cppc_get_perf_ctrs(cppc_fi->cpu, &fb_ctrs)) { + if (cppc_get_perf_fb_ctrs(cppc_fi->cpu, &fb_ctrs)) { pr_warn("%s: failed to read perf counters\n", __func__); return; } @@ -125,7 +125,7 @@ static void cppc_scale_freq_tick(void) struct cppc_freq_invariance *cppc_fi = &per_cpu(cppc_freq_inv, smp_processor_id()); /* - * cppc_get_perf_ctrs() can potentially sleep, call that from the right + * cppc_get_perf_fb_ctrs() can potentially sleep, call that from the right * context. */ irq_work_queue(&cppc_fi->irq_work); @@ -151,7 +151,7 @@ static void cppc_cpufreq_cpu_fie_init(struct cpufreq_policy *policy) kthread_init_work(&cppc_fi->work, cppc_scale_freq_workfn); init_irq_work(&cppc_fi->irq_work, cppc_irq_work); - ret = cppc_get_perf_ctrs(cpu, &cppc_fi->prev_perf_fb_ctrs); + ret = cppc_get_perf_fb_ctrs(cpu, &cppc_fi->prev_perf_fb_ctrs); if (ret) { pr_warn("%s: failed to read perf counters for cpu:%d: %d\n", __func__, cpu, ret); @@ -281,7 +281,7 @@ static int cppc_cpufreq_set_target(struct cpufreq_policy *policy, freqs.new = target_freq; cpufreq_freq_transition_begin(policy, &freqs); - ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls); + ret = cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); cpufreq_freq_transition_end(policy, &freqs, ret != 0); if (ret) @@ -301,7 +301,7 @@ static unsigned int cppc_cpufreq_fast_switch(struct cpufreq_policy *policy, desired_perf = cppc_khz_to_perf(&cpu_data->perf_caps, target_freq); cpu_data->perf_ctrls.desired_perf = desired_perf; - ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls); + ret = cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); if (ret) { pr_debug("Failed to set target on CPU:%d. ret:%d\n", @@ -657,7 +657,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) policy->cur = cppc_perf_to_khz(caps, caps->highest_perf); cpu_data->perf_ctrls.desired_perf = caps->highest_perf; - ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls); + ret = cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); if (ret) { pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", caps->highest_perf, cpu, ret); @@ -683,7 +683,7 @@ static void cppc_cpufreq_cpu_exit(struct cpufreq_policy *policy) cpu_data->perf_ctrls.desired_perf = caps->lowest_perf; - ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls); + ret = cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); if (ret) pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", caps->lowest_perf, cpu, ret); @@ -723,19 +723,19 @@ static int cppc_perf_from_fbctrs(struct cppc_cpudata *cpu_data, return (reference_perf * delta_delivered) / delta_reference; } -static int cppc_get_perf_ctrs_sample(int cpu, - struct cppc_perf_fb_ctrs *fb_ctrs_t0, - struct cppc_perf_fb_ctrs *fb_ctrs_t1) +static int cppc_get_perf_fb_ctrs_sample(int cpu, + struct cppc_perf_fb_ctrs *fb_ctrs_t0, + struct cppc_perf_fb_ctrs *fb_ctrs_t1) { int ret; - ret = cppc_get_perf_ctrs(cpu, fb_ctrs_t0); + ret = cppc_get_perf_fb_ctrs(cpu, fb_ctrs_t0); if (ret) return ret; udelay(2); /* 2usec delay between sampling */ - return cppc_get_perf_ctrs(cpu, fb_ctrs_t1); + return cppc_get_perf_fb_ctrs(cpu, fb_ctrs_t1); } static unsigned int cppc_cpufreq_get_rate(unsigned int cpu) @@ -753,7 +753,7 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int cpu) cpufreq_cpu_put(policy); - ret = cppc_get_perf_ctrs_sample(cpu, &fb_ctrs_t0, &fb_ctrs_t1); + ret = cppc_get_perf_fb_ctrs_sample(cpu, &fb_ctrs_t0, &fb_ctrs_t1); if (ret) { if (ret == -EFAULT) /* Any of the associated CPPC regs is 0. */ diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 62d368bcd9ec..31f4fd288b65 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -110,7 +110,6 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; - u32 energy_perf; bool auto_sel; }; @@ -142,8 +141,9 @@ struct cppc_cpudata { extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf); -extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); -extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_get_perf_fb_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); +extern int cppc_get_perf_ctrls(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_set_perf_ctrls(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_enable(int cpu, bool enable); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern bool cppc_perf_ctrs_in_pcc(void); @@ -177,11 +177,15 @@ static inline int cppc_get_highest_perf(int cpunum, u64 *highest_perf) { return -EOPNOTSUPP; } -static inline int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs) +static inline int cppc_get_perf_fb_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs) +{ + return -EOPNOTSUPP; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 10:38:09.8737 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 09a95590-d5c9-44c4-e8b4-08dd4a882dc3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001509.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7739 Rename show_cppc_data() macro to sysfs_cppc_data() and expand it to enable creating the acpi_cppc sysfs store node. Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 297e689f8214..cc2bf958e84f 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -139,12 +139,21 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); #define OVER_16BTS_MASK ~0xFFFFULL #define define_one_cppc_ro(_name) \ -static struct kobj_attribute _name = \ + static struct kobj_attribute _name = \ __ATTR(_name, 0444, show_##_name, NULL) +#define define_one_cppc_rw(_name) \ + static struct kobj_attribute _name = \ +__ATTR(_name, 0644, show_##_name, store_##_name) + #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) -#define show_cppc_data(access_fn, struct_name, member_name) \ +#define define_one_cppc(member_name, mode) define_one_cppc_attr(mode, member_name) +#define define_one_cppc_attr(mode, member_name) define_one_cppc_attr_##mode(member_name) +#define define_one_cppc_attr_ro(member_name) define_one_cppc_ro(member_name) +#define define_one_cppc_attr_rw(member_name) define_one_cppc_rw(member_name) + +#define sysfs_cppc_data(access_fn, struct_name, member_name, mode) \ static ssize_t show_##member_name(struct kobject *kobj, \ struct kobj_attribute *attr, char *buf) \ { \ @@ -159,18 +168,18 @@ __ATTR(_name, 0444, show_##_name, NULL) return sysfs_emit(buf, "%llu\n", \ (u64)st_name.member_name); \ } \ - define_one_cppc_ro(member_name) - -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, guaranteed_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); - -show_cppc_data(cppc_get_perf_fb_ctrs, cppc_perf_fb_ctrs, reference_perf); -show_cppc_data(cppc_get_perf_fb_ctrs, cppc_perf_fb_ctrs, wraparound_time); + define_one_cppc(member_name, mode) + +sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf, ro); +sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf, ro); +sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf, ro); +sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf, ro); +sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, guaranteed_perf, ro); +sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq, ro); +sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq, ro); + +sysfs_cppc_data(cppc_get_perf_fb_ctrs, cppc_perf_fb_ctrs, reference_perf, ro); +sysfs_cppc_data(cppc_get_perf_fb_ctrs, cppc_perf_fb_ctrs, wraparound_time, ro); /* Check for valid access_width, otherwise, fallback to using bit_width */ #define GET_BIT_WIDTH(reg) ((reg)->access_width ? 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026)(7416014)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 10:38:18.4899 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a3d0a05-8541-4c76-a4cd-08dd4a8832e6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7223 Add support to update the CPC registers used for Autonomous Performance Level Selection from acpi_cppc sysfs store nodes. Registers supported for updation are: - Engergy Performance Preference (EPP): energy_perf - Autonomous Selection: auto_sel - Maximum Performance: max_perf - Minimum Performance: min_perf Also, enable show nodes to read of the following CPC registers: - Performance Limited: perf_limited - Autonomous Activity Window: auto_activity_window Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 191 ++++++++++++++++++++++++++++++++++++--- include/acpi/cppc_acpi.h | 5 + 2 files changed, 183 insertions(+), 13 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index cc2bf958e84f..c60ad66ece85 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -170,6 +170,133 @@ __ATTR(_name, 0644, show_##_name, store_##_name) } \ define_one_cppc(member_name, mode) +static ssize_t store_min_perf(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); + struct cpufreq_policy *policy; + struct cppc_cpudata *cpu_data; + u32 min_perf, input; + int ret; + + policy = cpufreq_cpu_get(cpc_ptr->cpu_id); + cpu_data = policy->driver_data; + + if (kstrtouint(buf, 10, &input)) + return -EINVAL; + + if (input > cpu_data->perf_ctrls.max_perf) + return -EINVAL; + + input = clamp(input, cpu_data->perf_caps.lowest_perf, cpu_data->perf_caps.highest_perf); + + min_perf = cpu_data->perf_ctrls.min_perf; + cpu_data->perf_ctrls.min_perf = input; + + ret = cppc_set_perf_ctrls(cpc_ptr->cpu_id, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err writing CPU%d perf ctrls: ret:%d\n", cpc_ptr->cpu_id, ret); + cpu_data->perf_ctrls.min_perf = min_perf; + return ret; + } + cpufreq_cpu_put(policy); + + return count; +} + +static ssize_t store_max_perf(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); + struct cpufreq_policy *policy; + struct cppc_cpudata *cpu_data; + u32 max_perf, input; + int ret; + + policy = cpufreq_cpu_get(cpc_ptr->cpu_id); + cpu_data = policy->driver_data; + + if (kstrtouint(buf, 10, &input)) + return -EINVAL; + + if (input < cpu_data->perf_ctrls.min_perf) + return -EINVAL; + + input = clamp(input, cpu_data->perf_caps.lowest_perf, cpu_data->perf_caps.highest_perf); + + max_perf = cpu_data->perf_ctrls.max_perf; + cpu_data->perf_ctrls.max_perf = input; + + ret = cppc_set_perf_ctrls(cpc_ptr->cpu_id, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err writing CPU%d perf ctrls: ret:%d\n", cpc_ptr->cpu_id, ret); + cpu_data->perf_ctrls.max_perf = max_perf; + return ret; + } + cpufreq_cpu_put(policy); + + return count; +} + +static ssize_t store_energy_perf(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); + struct cpufreq_policy *policy; + struct cppc_cpudata *cpu_data; + u64 epp, input; + int ret; + + policy = cpufreq_cpu_get(cpc_ptr->cpu_id); + cpu_data = policy->driver_data; + + if (kstrtou64(buf, 10, &input)) + return -EINVAL; + + input = clamp(input, CPPC_EPP_PERFORMANCE_PREF, CPPC_EPP_ENERGY_EFFICIENCY_PREF); + + epp = cpu_data->perf_ctrls.energy_perf; + cpu_data->perf_ctrls.energy_perf = input; + + ret = cppc_set_epp_perf(cpc_ptr->cpu_id, &cpu_data->perf_ctrls, + cpu_data->perf_caps.auto_sel); + if (ret) { + pr_debug("failed to set energy perf value (%d)\n", ret); + cpu_data->perf_ctrls.energy_perf = epp; + return ret; + } + cpufreq_cpu_put(policy); + + return count; +} + +static ssize_t store_auto_sel(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); + struct cpufreq_policy *policy; + struct cppc_cpudata *cpu_data; + bool input = false; + int ret; + + policy = cpufreq_cpu_get(cpc_ptr->cpu_id); + cpu_data = policy->driver_data; + + if (kstrtobool(buf, &input)) + return -EINVAL; + + ret = cppc_set_auto_sel(cpc_ptr->cpu_id, input); + if (ret) { + pr_info("failed to set autonomous selection (%d)\n", ret); + return ret; + } + cpu_data->perf_caps.auto_sel = input; + + cpufreq_cpu_put(policy); + + return count; +} + sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf, ro); sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf, ro); sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf, ro); @@ -177,9 +304,16 @@ sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf, ro); sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, guaranteed_perf, ro); sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq, ro); sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq, ro); +sysfs_cppc_data(cppc_get_perf_caps, cppc_perf_caps, auto_sel, rw); sysfs_cppc_data(cppc_get_perf_fb_ctrs, cppc_perf_fb_ctrs, reference_perf, ro); sysfs_cppc_data(cppc_get_perf_fb_ctrs, cppc_perf_fb_ctrs, wraparound_time, ro); +sysfs_cppc_data(cppc_get_perf_fb_ctrs, cppc_perf_fb_ctrs, perf_limited, ro); + +sysfs_cppc_data(cppc_get_perf_ctrls, cppc_perf_ctrls, min_perf, rw); +sysfs_cppc_data(cppc_get_perf_ctrls, cppc_perf_ctrls, max_perf, rw); +sysfs_cppc_data(cppc_get_perf_ctrls, cppc_perf_ctrls, energy_perf, rw); +sysfs_cppc_data(cppc_get_perf_ctrls, cppc_perf_ctrls, auto_activity_window, ro); /* Check for valid access_width, otherwise, fallback to using bit_width */ #define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width) @@ -218,6 +352,12 @@ static struct attribute *cppc_attrs[] = { &nominal_perf.attr, &nominal_freq.attr, &lowest_freq.attr, + &auto_sel.attr, + &max_perf.attr, + &min_perf.attr, + &perf_limited.attr, + &auto_activity_window.attr, + &energy_perf.attr, NULL }; ATTRIBUTE_GROUPS(cppc); @@ -1286,8 +1426,8 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); struct cpc_register_resource *highest_reg, *lowest_reg, *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg, - *low_freq_reg = NULL, *nom_freq_reg = NULL; - u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0; + *low_freq_reg = NULL, *nom_freq_reg = NULL, *auto_sel_reg = NULL; + u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0, auto_sel = 0; int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); struct cppc_pcc_data *pcc_ss_data = NULL; int ret = 0, regs_in_pcc = 0; @@ -1304,11 +1444,12 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ]; nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ]; guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF]; + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; /* Are any of the regs PCC ?*/ if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) || - CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) { + CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg) || CPC_IN_PCC(auto_sel_reg)) { if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id\n"); return -ENODEV; @@ -1356,6 +1497,9 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) perf_caps->lowest_freq = low_f; perf_caps->nominal_freq = nom_f; + if (CPC_SUPPORTED(auto_sel_reg)) + cpc_read(cpunum, auto_sel_reg, &auto_sel); + perf_caps->auto_sel = (bool)auto_sel; out_err: if (regs_in_pcc) @@ -1535,8 +1679,22 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) CPC_SUPPORTED(epp_set_reg) && CPC_IN_FFH(epp_set_reg)) { ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); } else { - ret = -ENOTSUPP; - pr_debug("_CPC in PCC and _CPC in FFH are not supported\n"); + if (CPC_SUPPORTED(auto_sel_reg) && CPC_SUPPORTED(epp_set_reg)) { + ret = cpc_write(cpu, auto_sel_reg, enable); + if (ret) { + pr_debug("Error in writing auto_sel for CPU:%d\n", cpu); + return ret; + } + + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + if (ret) { + pr_debug("Error in writing energy_perf for CPU:%d\n", cpu); + return ret; + } + } else { + ret = -EOPNOTSUPP; + pr_debug("_CPC in PCC and _CPC in FFH are not supported\n"); + } } return ret; @@ -1553,6 +1711,7 @@ int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps) struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); struct cpc_register_resource *auto_sel_reg; u64 auto_sel; + int ret = 0; if (!cpc_desc) { pr_debug("No CPC descriptor for CPU:%d\n", cpunum); @@ -1561,13 +1720,9 @@ int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps) auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; - if (!CPC_SUPPORTED(auto_sel_reg)) - pr_warn_once("Autonomous mode is not unsupported!\n"); - if (CPC_IN_PCC(auto_sel_reg)) { int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); struct cppc_pcc_data *pcc_ss_data = NULL; - int ret = 0; if (pcc_ss_id < 0) return -ENODEV; @@ -1588,7 +1743,15 @@ int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps) return ret; } - return 0; + if (CPC_SUPPORTED(auto_sel_reg)) { + cpc_read(cpunum, auto_sel_reg, &auto_sel); + } else { + pr_debug("Autonomous mode is not unsupported!\n"); + ret = -EOPNOTSUPP; + } + perf_caps->auto_sel = (bool)auto_sel; + + return ret; } EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps); @@ -1630,11 +1793,13 @@ int cppc_set_auto_sel(int cpu, bool enable) /* after writing CPC, transfer the ownership of PCC to platform */ ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); up_write(&pcc_ss_data->pcc_lock); - } else { - ret = -ENOTSUPP; - pr_debug("_CPC in PCC is not supported\n"); + + return ret; } + if (CPC_SUPPORTED(auto_sel_reg)) + ret = cpc_write(cpu, auto_sel_reg, enable); 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Also, add information about other regsiters like Guaranteed performance and Performance limited. Signed-off-by: Sumit Gupta --- Documentation/admin-guide/acpi/cppc_sysfs.rst | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/admin-guide/acpi/cppc_sysfs.rst b/Documentation/admin-guide/acpi/cppc_sysfs.rst index 36981c667823..ff3f48d95bb7 100644 --- a/Documentation/admin-guide/acpi/cppc_sysfs.rst +++ b/Documentation/admin-guide/acpi/cppc_sysfs.rst @@ -27,22 +27,33 @@ for each cpu X:: $ ls -lR /sys/devices/system/cpu/cpu0/acpi_cppc/ /sys/devices/system/cpu/cpu0/acpi_cppc/: total 0 + -r--r--r-- 1 root root 65536 Mar 5 19:38 auto_activity_window + -rw-r--r-- 1 root root 65536 Mar 5 19:38 auto_sel + -rw-r--r-- 1 root root 65536 Mar 5 19:38 energy_perf -r--r--r-- 1 root root 65536 Mar 5 19:38 feedback_ctrs + -r--r--r-- 1 root root 65536 Mar 5 19:38 guaranteed_perf -r--r--r-- 1 root root 65536 Mar 5 19:38 highest_perf -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_freq -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_nonlinear_perf -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_perf + -rw-r--r-- 1 root root 65536 Mar 5 19:38 max_perf + -rw-r--r-- 1 root root 65536 Mar 5 19:38 min_perf -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_freq -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_perf + -r--r--r-- 1 root root 65536 Mar 5 19:38 per_limited -r--r--r-- 1 root root 65536 Mar 5 19:38 reference_perf -r--r--r-- 1 root root 65536 Mar 5 19:38 wraparound_time +Performance Capabilities / Thresholds: * highest_perf : Highest performance of this processor (abstract scale). * nominal_perf : Highest sustained performance of this processor (abstract scale). * lowest_nonlinear_perf : Lowest performance of this processor with nonlinear power savings (abstract scale). * lowest_perf : Lowest performance of this processor (abstract scale). +* guaranteed_perf : Current maximum sustained performance level of a processor, + taking into account all known external constraints. All processors are expected + to be able to sustain their guaranteed performance levels simultaneously. * lowest_freq : CPU frequency corresponding to lowest_perf (in MHz). * nominal_freq : CPU frequency corresponding to nominal_perf (in MHz). @@ -50,6 +61,7 @@ for each cpu X:: frequency instead of abstract scale. These values should not be used for any functional decisions. +Performance Feedback: * feedback_ctrs : Includes both Reference and delivered performance counter. Reference counter ticks up proportional to processor's reference performance. Delivered counter ticks up proportional to processor's delivered performance. @@ -57,6 +69,22 @@ for each cpu X:: (seconds). * reference_perf : Performance level at which reference performance counter accumulates (abstract scale). +* perf_limited : Set when Delivered Performance has been constrained due to an + unpredictable event. It is not utilized when Autonomous Selection is enabled. + +Performance Controls: +* max_perf : Maximum performance level at which the platform may run in the + range [Lowest Performance, Highest Performance], inclusive. +* min_perf : Minimum performance level at which the platform may run in the + range [Lowest Performance, Highest Performance], inclusive but must be set + to a value that is less than or equal to that specified by the max_perf. +* auto_sel : Enable Autonomous Performance Level Selection on this processor. +* auto_activity_window : Indicates a moving utilization sensitivity window to + the platform’s autonomous selection policy. +* energy_perf: Provides a value ranging from 0 (performance preference) to + 0xFF (energy efficiency preference) that influences the rate of performance + increase /decrease and the result of the hardware's energy efficiency and + performance optimization policies. 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(82310400026)(36860700013)(1800799024)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 10:38:36.5735 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4bf04b6-3274-438c-bf71-08dd4a883db2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7429 Add new 'cppc_cpufreq_epp' instance of the 'cppc_cpufreq' driver for supporting the Autonomous Performance Level Selection and Engergy Performance Preference (EPP) as per the ACPI specification. Autonomous selection will get enabled during boot if 'cppc_auto_sel' bootarg is present or the 'Autonomous Selection Enable' register is set before kernel boot. When Autonomous selection capability is enabled, then the hardware is allowed to autonomously select the CPU frequency within the min and max perf boundaries according to EPP hints. EPP values range from '0x0'(performance preference) to '0xFF'(energy efficiency preference). It influences the rate of performance increase/decrease and the result of the hardware's energy efficiency and performance optimization policies. Signed-off-by: Sumit Gupta --- .../admin-guide/kernel-parameters.txt | 11 + drivers/cpufreq/cppc_cpufreq.c | 234 +++++++++++++++++- 2 files changed, 241 insertions(+), 4 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index aa7447f8837c..8777970e6e35 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -904,6 +904,17 @@ Format: ,,,[,] + cppc_auto_sel= [CPU_FREQ] Autonomous Performance Level Selection. + When Autonomous selection is enabled, then the hardware is + allowed to autonomously select the CPU frequency. + In Autonomous mode, Engergy Performance Preference(EPP) + provides input to the hardware to favour performance (0x0) + or energy efficiency (0xff). + Format: + Default: disabled. + 0: force disabled + 1: force enabled + cpuidle.off=1 [CPU_IDLE] disable the cpuidle sub-system diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 17c49653a3c4..a4fa46cc2a6f 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -34,7 +34,10 @@ */ static LIST_HEAD(cpu_data_list); -static struct cpufreq_driver cppc_cpufreq_driver; +/* Autonomous Selection */ +static bool auto_sel_mode; + +static struct cpufreq_driver *current_cppc_cpufreq_driver; #ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE static enum { @@ -519,7 +522,7 @@ static int populate_efficiency_class(void) } index++; } - cppc_cpufreq_driver.register_em = cppc_cpufreq_register_em; + current_cppc_cpufreq_driver->register_em = cppc_cpufreq_register_em; return 0; } @@ -567,6 +570,12 @@ static struct cppc_cpudata *cppc_cpufreq_get_cpu_data(unsigned int cpu) goto free_mask; } + ret = cppc_get_perf_ctrls(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err reading CPU%d perf ctrls: ret:%d\n", cpu, ret); + goto free_mask; + } + list_add(&cpu_data->node, &cpu_data_list); return cpu_data; @@ -672,6 +681,171 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) return ret; } +static int cppc_cpufreq_epp_cpu_init(struct cpufreq_policy *policy) +{ + unsigned int cpu = policy->cpu; + struct cppc_cpudata *cpu_data; + struct cppc_perf_ctrls *ctrls; + struct cppc_perf_caps *caps; + int ret; + + cpu_data = cppc_cpufreq_get_cpu_data(cpu); + if (!cpu_data) { + pr_err("Error in acquiring _CPC/_PSD data for CPU%d.\n", cpu); + return -ENODEV; + } + caps = &cpu_data->perf_caps; + ctrls = &cpu_data->perf_ctrls; + policy->driver_data = cpu_data; + + policy->min = cppc_perf_to_khz(caps, ctrls->min_perf); + policy->max = cppc_perf_to_khz(caps, ctrls->max_perf); + + /* + * Set cpuinfo.min_freq to Lowest to make the full range of performance + * available if userspace wants to use any perf between lowest & minimum perf + */ + policy->cpuinfo.min_freq = cppc_perf_to_khz(caps, caps->lowest_perf); + policy->cpuinfo.max_freq = cppc_perf_to_khz(caps, caps->highest_perf); + + policy->transition_delay_us = cppc_cpufreq_get_transition_delay_us(cpu); + policy->shared_type = cpu_data->shared_type; + + switch (policy->shared_type) { + case CPUFREQ_SHARED_TYPE_HW: + case CPUFREQ_SHARED_TYPE_NONE: + /* Nothing to be done - we'll have a policy for each CPU */ + break; + case CPUFREQ_SHARED_TYPE_ANY: + /* + * All CPUs in the domain will share a policy and all cpufreq + * operations will use a single cppc_cpudata structure stored + * in policy->driver_data. + */ + cpumask_copy(policy->cpus, cpu_data->shared_cpu_map); + break; + default: + pr_debug("Unsupported CPU co-ord type: %d\n", + policy->shared_type); + ret = -EFAULT; + goto out; + } + + /* Set policy->cur to max now. The governors will adjust later. */ + policy->cur = cppc_perf_to_khz(caps, caps->highest_perf); + + ret = cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", + caps->highest_perf, cpu, ret); + goto out; + } + + cppc_cpufreq_cpu_fie_init(policy); + return 0; + +out: + cppc_cpufreq_put_cpu_data(policy); + return ret; +} + +static int cppc_cpufreq_epp_update_perf_ctrls(struct cpufreq_policy *policy, + u32 highest_perf, u32 lowest_perf) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + int ret; + + pr_debug("cpu%d, curr max_perf:%u, curr min_perf:%u, highest_perf:%u, lowest_perf:%u\n", + policy->cpu, cpu_data->perf_ctrls.max_perf, cpu_data->perf_ctrls.min_perf, + highest_perf, lowest_perf); + + cpu_data->perf_ctrls.max_perf = highest_perf; + cpu_data->perf_ctrls.min_perf = lowest_perf; + + ret = cppc_set_perf_ctrls(policy->cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Failed to set perf_ctrls on CPU:%d. ret:%d\n", policy->cpu, ret); + return ret; + } + + return ret; +} + +static int cppc_cpufreq_epp_update_auto_mode(struct cpufreq_policy *policy, int auto_sel, u32 epp) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + int ret, curr_epp; + + curr_epp = cpu_data->perf_ctrls.energy_perf; + pr_debug("cpu%d, curr epp:%u, new epp:%u, curr mode:%u, new mode:%u\n", + curr_epp, epp, cpu_data->perf_caps.auto_sel, auto_sel); + + /* set Performance preference as default */ + cpu_data->perf_ctrls.energy_perf = epp; + ret = cppc_set_epp_perf(policy->cpu, &cpu_data->perf_ctrls, auto_sel); + if (ret < 0) { + pr_err("failed to set energy perf value (%d)\n", ret); + cpu_data->perf_ctrls.energy_perf = curr_epp; + return ret; + } + cpu_data->perf_caps.auto_sel = auto_sel; + + return ret; +} + +static int cppc_cpufreq_epp_update_perf(struct cpufreq_policy *policy, int auto_sel, u32 epp, + u32 highest_perf, u32 lowest_perf) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + int ret; + + ret = cppc_cpufreq_epp_update_perf_ctrls(policy, highest_perf, lowest_perf); + if (ret) + return ret; + + ret = cppc_cpufreq_epp_update_auto_mode(policy, auto_sel, epp); + if (ret) + return ret; + + return ret; +} + +static int cppc_cpufreq_epp_set_policy(struct cpufreq_policy *policy) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + int ret; + + if (!cpu_data) + return -ENODEV; + + ret = cppc_cpufreq_epp_update_perf(policy, true, CPPC_EPP_PERFORMANCE_PREF, + cpu_data->perf_caps.highest_perf, + cpu_data->perf_caps.lowest_perf); + if (ret) + return ret; + + return ret; +} + +static void cppc_cpufreq_epp_cpu_exit(struct cpufreq_policy *policy) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + int ret; + + cppc_cpufreq_cpu_fie_exit(policy); + + cpu_data->perf_ctrls.desired_perf = cpu_data->perf_caps.lowest_perf; + + cppc_cpufreq_epp_update_perf_ctrls(policy, cpu_data->perf_caps.highest_perf, + cpu_data->perf_caps.lowest_perf); + + ret = cppc_set_auto_sel(policy->cpu, false); + if (ret) + pr_debug("failed to disable autonomous selection (%d)\n", ret); + + cppc_cpufreq_put_cpu_data(policy); +} + static void cppc_cpufreq_cpu_exit(struct cpufreq_policy *policy) { struct cppc_cpudata *cpu_data = policy->driver_data; @@ -828,17 +1002,57 @@ static struct cpufreq_driver cppc_cpufreq_driver = { .name = "cppc_cpufreq", }; +static struct cpufreq_driver cppc_cpufreq_epp_driver = { + .flags = CPUFREQ_CONST_LOOPS, + .verify = cppc_verify_policy, + .setpolicy = cppc_cpufreq_epp_set_policy, + .get = cppc_cpufreq_get_rate, + .init = cppc_cpufreq_epp_cpu_init, + .exit = cppc_cpufreq_epp_cpu_exit, + .attr = cppc_cpufreq_attr, + .name = "cppc_cpufreq_epp", +}; + +static int cppc_cpufreq_auto_sel_enable(bool auto_sel_mode) +{ + struct cppc_cpudata *cpu_data; + int cpu, pref, ret = 0; + + if (auto_sel_mode) { + for_each_present_cpu(cpu) { + /* Enable autonomous mode */ + ret = cppc_set_auto_sel(cpu, true); + if (ret) + pr_debug("failed to enable autonomous selection (%d)\n", ret); + } + } + + return ret; +} + static int __init cppc_cpufreq_init(void) { + struct cppc_perf_caps caps; int ret; if (!acpi_cpc_valid()) return -ENODEV; + cppc_get_auto_sel_caps(0, &caps); + if (auto_sel_mode || caps.auto_sel) { + ret = cppc_cpufreq_auto_sel_enable(true); + if (ret) + return ret; + + current_cppc_cpufreq_driver = &cppc_cpufreq_epp_driver; + } else { + current_cppc_cpufreq_driver = &cppc_cpufreq_driver; + } + cppc_freq_invariance_init(); populate_efficiency_class(); - ret = cpufreq_register_driver(&cppc_cpufreq_driver); + ret = cpufreq_register_driver(current_cppc_cpufreq_driver); if (ret) cppc_freq_invariance_exit(); @@ -859,12 +1073,24 @@ static inline void free_cpu_data(void) static void __exit cppc_cpufreq_exit(void) { - cpufreq_unregister_driver(&cppc_cpufreq_driver); + cpufreq_unregister_driver(current_cppc_cpufreq_driver); cppc_freq_invariance_exit(); free_cpu_data(); } +static int __init cppc_auto_sel_setup(char *buf) +{ + int ret = 0; + + ret = kstrtobool(buf, &auto_sel_mode); + if (!ret) + pr_err("Wrong autonomous selection param\n"); + + return ret; +} +__setup("cppc_auto_sel=", cppc_auto_sel_setup); + module_exit(cppc_cpufreq_exit); MODULE_AUTHOR("Ashwin Chaugule"); MODULE_DESCRIPTION("CPUFreq driver based on the ACPI CPPC v5.0+ spec");