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Mon, 10 Feb 2025 14:13:45 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 01/15] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy Date: Mon, 10 Feb 2025 14:13:01 -0700 Message-ID: <7e2c590467171cb3a942692aef5a679f127e567e.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 DDR3phy compatible to DT bindings documentation Signed-off-by: Ryan Wanner --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index b414de4fa779b..51d896c88dafa 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -90,6 +90,7 @@ select: - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr + - microchip,sama7d65-ddr3phy - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon - mstar,msc313-pmsleep @@ -188,6 +189,7 @@ properties: - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr + - microchip,sama7d65-ddr3phy - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon - mstar,msc313-pmsleep From patchwork Mon Feb 10 21:13:02 2025 Content-Type: text/plain; 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Mon, 10 Feb 2025 14:13:45 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu Date: Mon, 10 Feb 2025 14:13:02 -0700 Message-ID: <4cac19e32295c708d72b9fc6ba342b5c961fb6c3.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 SFRBU compatible string to DT bindings documentation Signed-off-by: Ryan Wanner --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 51d896c88dafa..727292ffe092e 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -91,6 +91,7 @@ select: - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7d65-ddr3phy + - microchip,sama7d65-sfrbu - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon - mstar,msc313-pmsleep From patchwork Mon Feb 10 21:13:03 2025 Content-Type: text/plain; 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Mon, 10 Feb 2025 14:13:45 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 03/15] dt-bindings: sram: Add microchip,sama7d65-sram Date: Mon, 10 Feb 2025 14:13:03 -0700 Message-ID: <384759dc826f9e37b43a69a1f2f6b79f56b99d38.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add microchip,sama7d65-sram compatibility to DT binding documentation. Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/sram/sram.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 7c1337e159f23..3071c5075ee48 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -31,6 +31,7 @@ properties: - amlogic,meson-gxbb-sram - arm,juno-sram-ns - atmel,sama5d2-securam + - microchip,sama7d65-securam - nvidia,tegra186-sysram - nvidia,tegra194-sysram - nvidia,tegra234-sysram From patchwork Mon Feb 10 21:13:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 865747 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3542024CEEF; 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Mon, 10 Feb 2025 14:13:46 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 05/15] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Date: Mon, 10 Feb 2025 14:13:05 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 RSTC compatible to DT bindings documentation. The sama7d65-rstc is compatible with the sama7g5-rstc. Signed-off-by: Ryan Wanner Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 98465d26949ee..a1c21c3880f9d 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -23,6 +23,11 @@ properties: - atmel,sama5d3-rstc - microchip,sam9x60-rstc - microchip,sama7g5-rstc + + - items: + - const: microchip,sama7d65-rstc + - const: microchip,sama7g5-rstc + - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc From patchwork Mon Feb 10 21:13:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 865746 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56A8424FBF8; Mon, 10 Feb 2025 21:14:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222057; cv=none; b=nBbBzICsrO8QsIlUgtdeZ3nC3JUiTa0I9QIUSCxfGabUmgvuyXNrfGBfheIpp/7f7UDf/BygLpYsmoGnBFzmzUbn6B1SsiKe1gz8XgC1QcZbV19FIN2O1SFHCctA1BdpicoT6KinfKqTkE+RPx7XEWwJ519/bntYAWwjB5js3fI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222057; c=relaxed/simple; bh=knmHj9Bcj4Yvp/EQxNnRvlMYu2rnMigY+aERKel7pvk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CPs1iE6fbgwjvIS9VXZ5/5OZVmE9PYUVqTOwpir1QHy7UGUi3wWt9OTB6ubJ5fbd/QwISUop8bK/u/7ibMfbggNR65PKbQjqGn3VRN6nOoZjxXQjT6ZolSWzP3igm02tQbzWoc9lEYLtUEevvRW2MkE+Hb8TNhwUYshVQvuHlgw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=uFROxsAG; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="uFROxsAG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222055; x=1770758055; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=knmHj9Bcj4Yvp/EQxNnRvlMYu2rnMigY+aERKel7pvk=; b=uFROxsAGArMDWitzbLFQGL6UD4NFrMkR05cAzmInGjwrr8YwjECVmeDw Atlk5QpK7g5sm6VPt9bqN5a7c19R97gkCJKZwLMd/qhuOKCtCNMjj1RyR eiiJcLgw89cpfmiRNTvnNP6U2ZMOs4eu1zN/w4pIClCtyCiAAqmCxo37U otjeVVb4vVp/PkVklx0Oo+39QPSx5O7T2TJ5yl6Pf5uHyCk9qOEWRaGMV 09Ld85ephjV1YWGq8TcJ6XwVSSdsJliCnemY7+Ocj8D3dvH0XM3GvsWEA udlxxkX3gyKghZLWYfmiDVBvV1lnzDwU61BSReXGPnrEfW+E7FC/mEgeK Q==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: bXPPyR86SfKUyhxlHyNVLg== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027974" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:05 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:46 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:46 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 06/15] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Date: Mon, 10 Feb 2025 14:13:06 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 RTC compatible to DT bindings documentation. Signed-off-by: Ryan Wanner --- .../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml index c8bb2eef442dd..0c878331170b4 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml @@ -25,6 +25,9 @@ properties: - items: - const: microchip,sam9x7-rtc - const: microchip,sam9x60-rtc + - items: + - const: microchip,sama7d65-rtc + - const: microchip,sam9x60-rtc reg: maxItems: 1 From patchwork Mon Feb 10 21:13:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 864326 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2B892505C5; Mon, 10 Feb 2025 21:14:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222057; cv=none; b=GaT1GPRl78rc9cXcz9ygEYvgSUx1xRUvxop3NK80P4nveii/vqHZmJc7aJI6XEkRBOGpyzy2LO47TaOt39I9pQSOAvk+jd8O9NQIlLdLbmvm+YBD34vJzKDZHBmheUueKMLWkYgV8brp/aHfyLMDvEpKY7TdSnuLmsZvftqhxms= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222057; c=relaxed/simple; bh=vVcwZO42JPNUOdcIsOkBSUgYQfQ7lZG5absw3HX57CE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gu/AVTPCP03ZnCU2tsGBQbcVK6HRuAtgmoezY0vJ7JkA+2EuFB5OBtNFtRQvMrHqgc7Ll0V3rYlbZZNSFq18XbypO+UZA8FFtMj1KCdC35r3ouMrRbZorw+AYsJKkoFkvvpu7SyooYFGKZ4f9/YddTTNf2tl/4+S/zt5v0cA9rQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=i5+O+11F; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="i5+O+11F" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222056; x=1770758056; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vVcwZO42JPNUOdcIsOkBSUgYQfQ7lZG5absw3HX57CE=; b=i5+O+11FdDiGDgz8/JLHizzQ0Uqdx0R/t0KXgCAXFwzfwz1bkGd/fPiL ocxjffT+pb7nNb5GI8TtTiijTshrr9zbEbiuZtSn8l40SiDeCADaIMbMq 12qxZKxF1ogjvNuIpw0uz5vIj2CZb6cURCev8I76ME7GY+FqhsuxM1FNX hkDEtxc9kzXcxDZJapoo7wRidKc29xJIJ2UodqBLhuxn8mLuOidXK3n19 H2VNPgQmp4f/mS3K+wfBJFQp3KxHJe2xFYs6qQrbNjpyssEKT2OnxQZEx lbk0/qOLwvN8O88KpFD4nukB1iZB1J+pHbL9PSkSHYap9Ye+eouTLNoNV Q==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: wAxkISw7RgW1cXiYsTRZ6A== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027978" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:05 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:46 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:46 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Date: Mon, 10 Feb 2025 14:13:07 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 RTT compatible to DT bindings documentation. Signed-off-by: Ryan Wanner --- .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml index a7f6c1d1a08ab..48a2e013a6b24 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -23,6 +23,9 @@ properties: - microchip,sam9x60-rtt - microchip,sam9x7-rtt - const: atmel,at91sam9260-rtt + - items: + - const: microchip,sama7d65-rtt + - const: atmel,at91sam9260-rtt - items: - const: microchip,sama7g5-rtt - const: microchip,sam9x60-rtt From patchwork Mon Feb 10 21:13:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 865745 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C2522505DF; Mon, 10 Feb 2025 21:14:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222057; cv=none; b=UMy6Eu2nbEuaaswrbpj9g8vHpYddSIyuRlU7gehbWKjCJsc8C9mf8o6yYY03Nfu0NwI2PYDQvcY6R7P8aiOrDvMKqasQ8//x3WPAr6FAdj47KuThQ53PisDVHEeMtnAhwlrwPeTq4VkrOLsbNZfzPjorioxPb6Cv9wI3l2DkoM4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222057; c=relaxed/simple; bh=tr+5ctybWd1qXbabAXHiNSfhGJo/z7RoiOi9HQGyK+g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eK4BoxdhYZtz0X6Z10hF9GMt21mzDEe8HRo1VYg70KTwpR7K7HZ+/x1WLXtYrqot1ZzrLMaaKfsD531GTSL3mHkXJHKy6ApOxh4qDxfd4UOGhf9YBj9LY5kSRo6NzedrM4Oh7bwgaU/cGEnsqRJBlTc7LEA5B1tTUKBusCUANZk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Ex+mAjaA; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Ex+mAjaA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222056; x=1770758056; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tr+5ctybWd1qXbabAXHiNSfhGJo/z7RoiOi9HQGyK+g=; b=Ex+mAjaALjWKR3lPikS2fgPxRsh3wjUKFqEAk+yEewrHmfsQfq78BV0c VQMActTDa9V0zAxRaGaIJmDpvf1EJDuQPUDNL8UHlSy3Qf6Yuo8zuBR/u 6+3/J5nByTmNKiklfaF+nLcp6+vviARy7ObDHRsAC98fVdasoD03y0eQa XLOs2C3dFT+N2PUJSN1LH0IpWAKDuipdS1Ve7fPts9P8gwdfyVNyKAaBn dseflt4cpBlN+AWn5mc6mjIWUbjwSdunknVdNJXWD76obWMTTyTPb6WUS gzFwC2DeV2c0xvedBEbv2RdiSnoFHQNI3Kmp/9rj4zd1kdAPpL4Dd4aT5 g==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: 3/XXqYBWQPeiFfEj3UQroQ== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027980" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:05 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:46 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:46 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 08/15] ARM: at91: Add PM support to sama7d65 Date: Mon, 10 Feb 2025 14:13:08 -0700 Message-ID: <2bb7550c7f7bd573abcbaf6060ea3a0b59117e4c.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add PM support to SAMA7D65 SoC. Signed-off-by: Ryan Wanner --- arch/arm/mach-at91/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 04bd91c72521c..f3ff1220c0fb0 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -65,6 +65,7 @@ config SOC_SAMA7D65 select HAVE_AT91_SAM9X60_PLL select HAVE_AT91_USB_CLK select HAVE_AT91_UTMI + select PM_OPP select SOC_SAMA7 help Select this if you are using one of Microchip's SAMA7D65 family SoC. From patchwork Mon Feb 10 21:13:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 864325 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35E1624C667; Mon, 10 Feb 2025 21:14:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222059; cv=none; b=He7ZrJ+IJywMWxuW8aui1F8tbuKZKwBc1Hyzwaj3Wg/k+Q988ozl+KdOh1qhuEUIOjeIzZ9coMwIh6Q1IBsphydO18GaQIhS0iyNjNgxI5e7FKsjVt2rqrOGzHAXZXLDlKGyiQYZfavKMePyGAx1jK6pgeAlb0OcinqzC435PoY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222059; c=relaxed/simple; bh=EC1+VWxeTyKipOmsfV+ugr3Ogr25ipgQiLkDdijoRG8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hk/WNpPQYgIAzUnz6hBe6gHM7ZKRVl7MuvhOhOfPjz/lRPnYFyqgrensxz2BK8MGipIE9Jcx1nNEc9WTEoT6iJa/uTsrPWWyoSW5xOOYIi6nd9NpenT8T3QIBryjo5FGyKWE3wmaF3HLBFW1+Hu+v8uUJ0JtIIlHN49nbYhYgzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=pNo0CyUI; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="pNo0CyUI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222057; x=1770758057; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EC1+VWxeTyKipOmsfV+ugr3Ogr25ipgQiLkDdijoRG8=; b=pNo0CyUIGpry6AtIuS+DDwY9qR/LfWnxHaLGLx/ebx9YavdVDuJbODc6 QJcDKuR8oruPQB59XtPF1nbX1aGbGKwhYoONsZUNiuv3Vxdjt1vP7ZV9A mIR+vZ8DTACtsYt6TuQD+ScI9tGzupTr1lIU1d7v4ZqLuJPyySaZGIPhH PdU/ZAnlpWEK4gHthFxTOCUQorkTx/xczhhx7TsC0zInJNj66hwSqx4VU AI1VWko+yzW1mD8ACt1CChGPD82RUGAlf1eurJ2y33d35diowwvQg67RP /xIgXtDLT4jNM706O4F7nBw0go58Fk0DB8qnEmqi7bBo1xL5cvI1r4jAG w==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: 1dErltO1Rla3Z/Bsv54o7g== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027983" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:06 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:46 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:46 -0700 From: To: , , , , , , , , CC: , , , , , , Li Bin , Ryan Wanner , "Durai Manickam KR" , Andrei Simion Subject: [PATCH v2 09/15] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration Date: Mon, 10 Feb 2025 14:13:09 -0700 Message-ID: <4e685b1f1828b006cb60aa6b66239f2c0966501a.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Li Bin For sama7g5 and sama7d65 backup mode, we encountered a "ZQ calibrate error" during recalibrating the impedance in BootStrap. We found that the impedance value saved in at91_suspend_finish() before the DDR entered self-refresh mode did not match the resistor values. The ZDATA field in the DDR3PHY_ZQ0CR0 register uses a modified gray code to select the different impedance setting. But these gray code are incorrect, a workaournd from design team fixed the bug in the calibration logic. The ZDATA contains four independent impedance elements, but the algorithm combined the four elements into one. The elements were fixed using properly shifted offsets. Signed-off-by: Li Bin [nicolas.ferre@microchip.com: fix indentation and combine 2 patches] Signed-off-by: Nicolas Ferre Tested-by: Ryan Wanner Tested-by: Durai Manickam KR Tested-by: Andrei Simion --- arch/arm/mach-at91/pm.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 05a1547642b60..6c3e6aa22606f 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -545,11 +545,12 @@ extern u32 at91_pm_suspend_in_sram_sz; static int at91_suspend_finish(unsigned long val) { - unsigned char modified_gray_code[] = { - 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d, - 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b, - 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, - 0x10, 0x11, + /* SYNOPSYS workaround to fix a bug in the calibration logic */ + unsigned char modified_fix_code[] = { + 0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18, + 0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13, + 0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14, + 0x1e, 0x1f, }; unsigned int tmp, index; int i; @@ -560,25 +561,25 @@ static int at91_suspend_finish(unsigned long val) * restore the ZQ0SR0 with the value saved here. But the * calibration is buggy and restoring some values from ZQ0SR0 * is forbidden and risky thus we need to provide processed - * values for these (modified gray code values). + * values for these. */ tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0); /* Store pull-down output impedance select. */ index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] = modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDO_OFF; /* Store pull-up output impedance select. */ index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PUO_OFF; /* Store pull-down on-die termination impedance select. */ index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDODT_OFF; /* Store pull-up on-die termination impedance select. */ index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SRO_PUODT_OFF; /* * The 1st 8 words of memory might get corrupted in the process From patchwork Mon Feb 10 21:13:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 865744 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06D212512DF; Mon, 10 Feb 2025 21:14:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222060; cv=none; b=aBKlhSRxExsdct9+j8G0RABIOvk/6VIxhIGMjal0jZTtIzw3QHsW1sTMXRPosp3GsFYIcWRbJrkfryjB/AumobTw0axSnzadNCuQCws6L0aeWn5XkHxf6T+BlQlCcwhUgsrcGRVMWfJh3ZpSnJqcJtTd5xoMP/NCTU+WNp3WabE= ARC-Message-Signature: i=1; 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Mon, 10 Feb 2025 14:13:46 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:46 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 10/15] ARM: at91: pm: add DT compatible support for sama7d65 Date: Mon, 10 Feb 2025 14:13:10 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add support for SAMA7D65 new compatible strings in pm.c file for wakeup source IDs and PMC. This is the first bits of PM for this new SoC. PM depends on other patches. Signed-off-by: Ryan Wanner [nicolas.ferre@microchip.com: split patch and address only the pm.c changes] Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/pm.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 6c3e6aa22606f..1eec68e92f8d8 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -222,13 +222,16 @@ static const struct of_device_id sam9x60_ws_ids[] = { { /* sentinel */ } }; -static const struct of_device_id sama7g5_ws_ids[] = { - { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] }, +static const struct of_device_id sama7_ws_ids[] = { + { .compatible = "microchip,sama7d65-rtc", .data = &ws_info[1] }, + { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] }, { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, { .compatible = "usb-ohci", .data = &ws_info[2] }, { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, { .compatible = "usb-ehci", .data = &ws_info[2] }, + { .compatible = "microchip,sama7d65-sdhci", .data = &ws_info[3] }, { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, + { .compatible = "microchip,sama7d65-rtt", .data = &ws_info[4] }, { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] }, { /* sentinel */ } }; @@ -1379,6 +1382,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = { { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] }, + { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] }, { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, { /* sentinel */ }, }; @@ -1672,7 +1676,7 @@ void __init sama7_pm_init(void) at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); at91_pm_init(NULL); - soc_pm.ws_ids = sama7g5_ws_ids; + soc_pm.ws_ids = sama7_ws_ids; soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); From patchwork Mon Feb 10 21:13:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 864324 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A2D72512E7; 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Add SHDWC_SR read to clear the status bits once finished exiting low power modes. This is only for SAMA7D65 SoCs. Signed-off-by: Ryan Wanner --- arch/arm/mach-at91/pm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 1eec68e92f8d8..55cab31ce1ecb 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -707,6 +707,9 @@ static int at91_pm_enter(suspend_state_t state) static void at91_pm_end(void) { at91_pm_config_ws(soc_pm.data.mode, false); + + if (IS_ENABLED(CONFIG_SOC_SAMA7D65)) + readl(soc_pm.data.shdwc + 0x08); } @@ -1065,7 +1068,8 @@ static int __init at91_pm_backup_init(void) int ret = -ENODEV, located = 0; if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && - !IS_ENABLED(CONFIG_SOC_SAMA7G5)) + !IS_ENABLED(CONFIG_SOC_SAMA7G5) && + !IS_ENABLED(CONFIG_SOC_SAMA7D65)) return -EPERM; if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) From patchwork Mon Feb 10 21:13:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 865743 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51F3F253342; Mon, 10 Feb 2025 21:14:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222061; cv=none; b=j2+IPem4d9aHDknUDO8sevcS67p7yonbaEfUPk8rLThn8u2mMSREuEWqT+10PPvvW6OCiAaFThqImNryL0F3gHYL/jdJdAMTaSnVU3WCslgmVIlsfiK0koVylBimP5Vfp7v7wr/eZ6IEFSHox5n6YKuguCMB95LbSzQ+N+PLSV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222061; c=relaxed/simple; bh=B6aS897YVfVNdZ35OyKx+E3aJaDtsqvem9ciXmWUbd8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bhC+nCkJJPhV57WcehgzQuc20lSAR1ScOxKQWnG54z5OQNF2fFyWAFISNylNVmAUmI7xF2Wattam9awUbVF2Tb/9NDhl3LGXRaRwsxJixS6oY4JrVerYQfOdcMH38E1B7Fo5SkBoV9HJSVxA7oYc7Nv2CpcykqMctmvcZdD1gA0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=bKQ1hXCT; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="bKQ1hXCT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222059; x=1770758059; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B6aS897YVfVNdZ35OyKx+E3aJaDtsqvem9ciXmWUbd8=; b=bKQ1hXCTKQ2UGF7wAgfcq9dd1CJzh9OiPoa9uSw0p24fe1BL01I6V0/2 SPb9mg4DFReb79cZvkeSjn/JZc1MefPd2gK4PqON81N3Q5nebAMjbHa+H NlwnSPEcyM+mBp8a562Ez0MoTkavewKHd9xsnw1YpVYKCApouo9Ybf0BP Fz68S5YXuB36jguG7lZWHCPfIzK6MZO1cyGZjo6tqL3dQ9MIJa9hlqOrQ ZH7bSXB+7oesGr8F83LKgdUXRjyC3K4okRQcFcP4T8W/hXu6qyeRAIQLP SCCsrR/c4RevxvtS/qwcyCCS3OiXJz+Pz8bqslnjNmpQrAZkS5STdpVLF g==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: XUu9bLimSAOqG4pa9ESZ3g== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027990" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:06 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:47 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:47 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 for SAMA7D65 Date: Mon, 10 Feb 2025 14:13:12 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a total of 10 main clocks that need to be saved for ULP0 mode. Add mck_count member to at91_pm_data, this will be used to determine how many mcks need to be saved. In the mck_count member will also make sure that no unnecessary clock settings are written during mck_ps_restore. Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low power modes. Signed-off-by: Ryan Wanner Acked-by: Nicolas Ferre --- arch/arm/mach-at91/pm.c | 19 +++++- arch/arm/mach-at91/pm.h | 1 + arch/arm/mach-at91/pm_data-offsets.c | 2 + arch/arm/mach-at91/pm_suspend.S | 97 ++++++++++++++++++++++++++-- 4 files changed, 110 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 55cab31ce1ecb..50bada544eede 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -1337,6 +1337,7 @@ struct pmc_info { unsigned long uhp_udp_mask; unsigned long mckr; unsigned long version; + unsigned long mck_count; }; static const struct pmc_info pmc_infos[] __initconst = { @@ -1344,30 +1345,42 @@ static const struct pmc_info pmc_infos[] __initconst = { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP, .mckr = 0x30, .version = AT91_PMC_V1, + .mck_count = 1, }, { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, .mckr = 0x30, .version = AT91_PMC_V1, + .mck_count = 1, }, { .uhp_udp_mask = AT91SAM926x_PMC_UHP, .mckr = 0x30, .version = AT91_PMC_V1, + .mck_count = 1, }, { .uhp_udp_mask = 0, .mckr = 0x30, .version = AT91_PMC_V1, + .mck_count = 1, }, { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, .mckr = 0x28, .version = AT91_PMC_V2, + .mck_count = 1, }, { .mckr = 0x28, .version = AT91_PMC_V2, + .mck_count = 5, + }, + { + .uhp_udp_mask = AT91SAM926x_PMC_UHP, + .mckr = 0x28, + .version = AT91_PMC_V2, + .mck_count = 10, }, }; @@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = { { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] }, - { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] }, + { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] }, { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, { /* sentinel */ }, }; @@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void)) soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask; soc_pm.data.pmc_mckr_offset = pmc->mckr; soc_pm.data.pmc_version = pmc->version; + soc_pm.data.pmc_mck_count = pmc->mck_count; if (pm_idle) arm_pm_idle = pm_idle; @@ -1659,7 +1673,8 @@ void __init sama7_pm_init(void) AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, }; static const u32 iomaps[] __initconst = { - [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU), + [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU) | + AT91_PM_IOMAP(SHDWC), [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) | AT91_PM_IOMAP(SHDWC) | AT91_PM_IOMAP(ETHC), diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 53bdc9000e447..ccde9c8728c27 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -39,6 +39,7 @@ struct at91_pm_data { unsigned int suspend_mode; unsigned int pmc_mckr_offset; unsigned int pmc_version; + unsigned int pmc_mck_count; }; #endif diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c index 40bd4e8fe40a5..59a4838038381 100644 --- a/arch/arm/mach-at91/pm_data-offsets.c +++ b/arch/arm/mach-at91/pm_data-offsets.c @@ -18,6 +18,8 @@ int main(void) pmc_mckr_offset)); DEFINE(PM_DATA_PMC_VERSION, offsetof(struct at91_pm_data, pmc_version)); + DEFINE(PM_DATA_PMC_MCK_COUNT, offsetof(struct at91_pm_data, + pmc_mck_count)); return 0; } diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index e5869cca5e791..2bbcbb26adb28 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -814,17 +814,19 @@ sr_dis_exit: .endm /** - * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock + * at91_mckx_ps_enable: save MCK settings and switch it to main clock * - * Side effects: overwrites tmp1, tmp2 + * Side effects: overwrites tmp1, tmp2, tmp3 */ .macro at91_mckx_ps_enable #ifdef CONFIG_SOC_SAMA7 ldr pmc, .pmc_base + ldr tmp3, .mck_count - /* There are 4 MCKs we need to handle: MCK1..4 */ + /* Start at MCK1 and go until MCK_count */ mov tmp1, #1 -e_loop: cmp tmp1, #5 +e_loop: + cmp tmp1, tmp3 beq e_done /* Write MCK ID to retrieve the settings. */ @@ -850,7 +852,37 @@ e_save_mck3: b e_ps e_save_mck4: + cmp tmp1, #4 + bne e_save_mck5 str tmp2, .saved_mck4 + b e_ps + +e_save_mck5: + cmp tmp1, #5 + bne e_save_mck6 + str tmp2, .saved_mck5 + b e_ps + +e_save_mck6: + cmp tmp1, #6 + bne e_save_mck7 + str tmp2, .saved_mck6 + b e_ps + +e_save_mck7: + cmp tmp1, #7 + bne e_save_mck8 + str tmp2, .saved_mck7 + b e_ps + +e_save_mck8: + cmp tmp1, #8 + bne e_save_mck9 + str tmp2, .saved_mck8 + b e_ps + +e_save_mck9: + str tmp2, .saved_mck9 e_ps: /* Use CSS=MAINCK and DIV=1. */ @@ -870,17 +902,19 @@ e_done: .endm /** - * at91_mckx_ps_restore: restore MCK1..4 settings + * at91_mckx_ps_restore: restore MCKx settings * * Side effects: overwrites tmp1, tmp2 */ .macro at91_mckx_ps_restore #ifdef CONFIG_SOC_SAMA7 ldr pmc, .pmc_base + ldr tmp2, .mck_count - /* There are 4 MCKs we need to handle: MCK1..4 */ + /* Start from MCK1 and go up to MCK_count */ mov tmp1, #1 -r_loop: cmp tmp1, #5 +r_loop: + cmp tmp1, tmp2 beq r_done r_save_mck1: @@ -902,7 +936,37 @@ r_save_mck3: b r_ps r_save_mck4: + cmp tmp1, #4 + bne r_save_mck5 ldr tmp2, .saved_mck4 + b r_ps + +r_save_mck5: + cmp tmp1, #5 + bne r_save_mck6 + ldr tmp2, .saved_mck5 + b r_ps + +r_save_mck6: + cmp tmp1, #6 + bne r_save_mck7 + ldr tmp2, .saved_mck6 + b r_ps + +r_save_mck7: + cmp tmp1, #7 + bne r_save_mck8 + ldr tmp2, .saved_mck7 + b r_ps + +r_save_mck8: + cmp tmp1, #8 + bne r_save_mck9 + ldr tmp2, .saved_mck8 + b r_ps + +r_save_mck9: + ldr tmp2, .saved_mck9 r_ps: /* Write MCK ID to retrieve the settings. */ @@ -921,6 +985,7 @@ r_ps: wait_mckrdy tmp1 add tmp1, tmp1, #1 + ldr tmp2, .mck_count b r_loop r_done: #endif @@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram) str tmp1, .memtype ldr tmp1, [r0, #PM_DATA_MODE] str tmp1, .pm_mode +#ifdef CONFIG_SOC_SAMA7 + ldr tmp1, [r0, #PM_DATA_PMC_MCK_COUNT] + str tmp1, .mck_count +#endif /* * ldrne below are here to preload their address in the TLB as access @@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram) .word 0 .pmc_version: .word 0 +#ifdef CONFIG_SOC_SAMA7 +.mck_count: + .word 0 +#endif .saved_mckr: .word 0 .saved_pllar: @@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram) .word 0 .saved_mck4: .word 0 +.saved_mck5: + .word 0 +.saved_mck6: + .word 0 +.saved_mck7: + .word 0 +.saved_mck8: + .word 0 +.saved_mck9: + .word 0 #endif ENTRY(at91_pm_suspend_in_sram_sz) From patchwork Mon Feb 10 21:13:13 2025 Content-Type: text/plain; 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Mon, 10 Feb 2025 14:13:47 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 13/15] power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC Date: Mon, 10 Feb 2025 14:13:13 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add sama7d65-pmc compatible string to the list of valid PMC IDs. Signed-off-by: Ryan Wanner --- drivers/power/reset/at91-sama5d2_shdwc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c index edb0df86aff45..0cb7fe9f25a07 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = { { .compatible = "atmel,sama5d2-pmc" }, { .compatible = "microchip,sam9x60-pmc" }, { .compatible = "microchip,sama7g5-pmc" }, + { .compatible = "microchip,sama7d65-pmc" }, { /* Sentinel. */ } }; From patchwork Mon Feb 10 21:13:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 865742 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E2D9253F34; Mon, 10 Feb 2025 21:14:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222062; cv=none; b=rOV0dd9Xj6GtJm2/urUko6cuoUjCDF6O3bOSZ0MjJ50fpfbXh4HlRCj3H5boR+srEK9i1GZBuSkXbNS1CJBKn8yssSKY73BpNPUjQUnLqo+WoMUgbkYPecyOLA7bx6S5nERMg/0sWGX0lApgxRznH35auKLmmxrA2ul8FfZ+V5A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222062; c=relaxed/simple; bh=p8EM3OYRWcrCb8EXs2uauOw4xPx+f4SxoXq7GIVo4uI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BuknczTvLDz6KzrQj2VjUG/ESyJFrKzwh6wRSla/L9AazM45LlFh9Tev0IMcymjmO4YQdn9rlccwq3HC5zrt4+W/KzJElV5Vzefe7zjFBWjkhLdVkpQkQhKC599O2bW05R3YLI1UBN6HUuDwxOMBcq8S7Tx2fpbzij+jhwpVoj0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=G8fnkSwa; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="G8fnkSwa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222060; x=1770758060; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p8EM3OYRWcrCb8EXs2uauOw4xPx+f4SxoXq7GIVo4uI=; b=G8fnkSwamm0x5HVMLJoBfbQkYqt+LrTiuJF9v5ZxJ1rSlCrEjWGM0+0y ATBXrtiMOJauhOHvb41H5hCiqqs64+GoeOeOzfqN5bzjs3D0G/MEJgHwI UsrOsi9hCu1g6X2G5yqausWu/2KNM+KwUWF3NAs8zCTVj11yW88cB1wa3 +dq8+SEq/YLtcktbtGgTSh0PkkrK+Oz8kBowDsYnfBTUU07tXItz4N3g6 DffUxQOkte0W33XGt8jrTmyRZf/H9fQfRqMmAc+Dga2BP8JLvK+GTjj5a pWfjwy9m09YcMjRe+B3EnmgQCmJ7iVMGIPVC81iaOgPOdpSAEWVwtFszP Q==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: GO8bNwHTQJWiQJPTzuOfGg== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027993" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:07 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:47 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:47 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 14/15] ARM: dts: microchip: sama7d65: Add Reset and Shutdown and PM support Date: Mon, 10 Feb 2025 14:13:14 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add support for reset controller, wake up alarm timers, and shutdown controller. Add SRAM, SFR, secumod, UDDRC, and DDR3phy to enable support for low power modes. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 77 +++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 854b30d15dcd4..1d40235bdab0a 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -46,12 +46,42 @@ slow_xtal: clock-slowxtal { }; }; + ns_sram: sram@100000 { + compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x100000 0x20000>; + ranges; + }; + soc { compatible = "simple-bus"; ranges; #address-cells = <1>; #size-cells = <1>; + securam: sram@e0000800 { + compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xe0000800 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe0000800 0x4000>; + no-memory-wc; + }; + + secumod: secumod@e0004000 { + compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; + reg = <0xe0004000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + }; + + sfrbu: sfr@e0008000 { + compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; + reg = <0xe0008000 0x20>; + }; + pioa: pinctrl@e0014000 { compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; reg = <0xe0014000 0x800>; @@ -76,6 +106,31 @@ pmc: clock-controller@e0018000 { clock-names = "td_slck", "md_slck", "main_xtal"; }; + reset_controller: reset-controller@e001d100 { + compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; + reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + + shdwc: poweroff@e001d200 { + compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon"; + reg = <0xe001d200 0x20>; + clocks = <&clk32k 0>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + + rtt: rtc@e001d300 { + compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; + reg = <0xe001d300 0x30>; + interrupts = ; + clocks = <&clk32k 0>; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>; @@ -83,6 +138,18 @@ clk32k: clock-controller@e001d500 { #clock-cells = <1>; }; + gpbr: gpbr@e001d700 { + compatible = "microchip,sama7d65-gpbr", "syscon"; + reg = <0xe001d700 0x48>; + }; + + rtc: rtc@e001d800 { + compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; + reg = <0xe001d800 0x30>; + interrupts = ; + clocks = <&clk32k 1>; + }; + sdmmc1: mmc@e1208000 { compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; reg = <0xe1208000 0x400>; @@ -132,6 +199,16 @@ uart6: serial@200 { }; }; + uddrc: uddrc@e3800000 { + compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; + reg = <0xe3800000 0x4000>; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; + reg = <0xe3804000 0x1000>; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; 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Mon, 10 Feb 2025 14:13:47 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:47 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 15/15] ARM: dts: microchip: add shutdown controller and rtt timer Date: Mon, 10 Feb 2025 14:13:15 -0700 Message-ID: <709f5268da63c123cc4eee9e47875324df81c454.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add shutdown controller and rtt timer to support shutdown and wake up. Signed-off-by: Ryan Wanner --- .../boot/dts/microchip/at91-sama7d65_curiosity.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 0f86360fb733a..d1d0b06fbfc43 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -77,6 +77,11 @@ pinctrl_uart6_default: uart6-default { }; }; +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "disabled"; +}; + &sdmmc1 { bus-width = <4>; pinctrl-names = "default"; @@ -84,6 +89,15 @@ &sdmmc1 { status = "okay"; }; +&shdwc { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + &slow_xtal { clock-frequency = <32768>; };