From patchwork Wed Feb 12 15:43:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 864464 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cc5:0:b0:38f:210b:807b with SMTP id c5csp186244wrt; Wed, 12 Feb 2025 07:44:18 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXpigfICB29Qh7UrKPB5KmW8W0FUt/QOrawv6gAZn/nBYrK7Rvz3B8jG34v4mMAA35pegJwVQ==@linaro.org X-Google-Smtp-Source: AGHT+IHKf1uuAOYddoZDB22b+nycJ2wuS6TjLewrbVUUtU3dXx7ypZPsaPPhypDlAxEDIEKXOHsf X-Received: by 2002:a05:6102:4191:b0:4b6:15fa:566a with SMTP id ada2fe7eead31-4bbf216f8d4mr4212590137.2.1739375058379; Wed, 12 Feb 2025 07:44:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739375058; cv=none; d=google.com; s=arc-20240605; b=Q9/I30Kk1Znt49urWX2gAsECKh0MbCJEoAoCzhe6tQZy5Eofv0Um/rNWBtJJMr0Dz9 ccl5lb+FxecDMI8tp9r156F1KYIZ9zuKYH09IffGgoFT9Zz+iJtFpIXWp/i8f8buLjBs NfgoUSzyUFykKy7fu/55xwg5xis1/4p6kdWmL7VfPFPnrQD9JzNx0zIPPyRNimenWQ9g uxVPKbTQBco3TRpzguNxvI7hyKYUqVLViIpVZ98KvjRs1MoF3omNUL+Ph5VSzFT48y/l sflo3/aSPaxVNU5/5A7R1sp8kofKyb5INqlAtYm+tuqwu84mhH75VVGM/rAujqLNz7rr fC4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UeIZFp/oTPSZTqhQVQuuyB79ED/0E39RbO6UofIGgaE=; fh=lzaa7I3YGCYWkDWyTcVwEb5cG79+nkOCzjzvwF81yJk=; b=e4UNsnzu8tdcrWial4dX1zGx91MqABW5LLLG+SUFQQ2YKzgrtqnMiEOTRFJ4hZWSxz 7vfOTgBpt1/oMNc65hBxBfAsS4/dvYMwXZzB/waZWycTVQkjb2d/yszKyCBE/J6MGtbG Ugmp3Z2lnYBRRHRAP8iuRPxTiHSIGOd4uAPfCWyycwoHy+8dpSDunpTyN8OR06uBVKKI x2jTaufqBK+vLoTMF67cYlDEaqJl5SjRhTDiiq6jcO6UXbBwuEeqHPt9qHDyuGFWNDkk o5uOOgJu2HzlbE3SzqM1VYhqobziC6rmb++RGdKMmyKq8A9+ryZI0mAAqorOS+w7hgyl c+yA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MemEiYgb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-4bbb7f4d386si1863853137.490.2025.02.12.07.44.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Feb 2025 07:44:18 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MemEiYgb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiEtw-0004Oj-NY; Wed, 12 Feb 2025 10:43:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiEtu-0004Nl-53 for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:43:46 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiEtr-0006sK-KN for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:43:45 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-43690d4605dso48146135e9.0 for ; Wed, 12 Feb 2025 07:43:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739375020; x=1739979820; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UeIZFp/oTPSZTqhQVQuuyB79ED/0E39RbO6UofIGgaE=; b=MemEiYgbn7cz9bCXJgmJrLDGqBPFtCKQXZLXvDOeG1eZbz86R2qLw8gdVIZtbRD+pV 2HqnPAEzVLHTyPajI7QdPU7rZwCvnGgOGQsOh4nwXx62NXlS89YH7yEDixXad5BEH6IB E4qgNIzRK9mprO8RoqzmW24l5/oWY3vGt2+rsKK/Zn97bzBOzhz/zstKNzCJxh2XAd/q 3Rqwxvx2uScDCl3or8pDf2tstOlYnJnYvVCngvuRm4aS+aS5fA8uAXM9vuqtTpUqVsEF YQTBOIPDu5kO3WPYEHuLwJ17LVd5ilX83RMXnro8Hfe3YhRGkWz/QU7/1wYC4y76/NuM mmkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739375020; x=1739979820; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UeIZFp/oTPSZTqhQVQuuyB79ED/0E39RbO6UofIGgaE=; b=ICOrSEmD6Kd7e8UeokUrcIgGm3T5caN0GIaaPiPRY0uS0R8ssO+3+V5naJdpbN7dDd hBkRe27x+c3eNpV5rOsRaOGCg/PyE7SrzmHf5QOajxV/Zi0UE9ZR+VBhKf1gHVcwgISu KT/JlL0uF0iX6GsdxovGuwBGkvbch+BgT2tjbP8se8WnKdePFB2CnsQZXZhugHGlpTVr o6ZaIwMXi59jLwcugfYhpEG/DcO4/LB2mobiZaEaXwrQDc1IW/oO4UOqUDgjxSmVQkUO kTzHzJbK3ckDMOlYfSuCvgJJfZxWlDwv7X4DSf83NzMBMHU2QG3x4/lRWlgQRLP7EqDg 4zng== X-Gm-Message-State: AOJu0Ywlv9WrKeEEYq1FGwsrbUa8OiNbW7WtSAHaZUGlMpF3k7kGTMIa fJEFO4F0xzdhd90RItvR+bYhSmF3BF845goBU7q+igRouU+QvtQrdRkcmo+ZtH+3S0AErMcO0gf T/eo= X-Gm-Gg: ASbGncuo9+rJjyay++PyYullOnvin+/CAzzyOJ+LtA4pedsMtf3j/8WgQZ4CMo59eRb w4bIwIa6+BbHJFU6fpaLDMeOws7+dAqyqpPtnTQqW/jXw6T7tJCPK9S9V/hMWN7wlTzYMF70BF+ zw6xc5NsMlvCDJVnfHvJ9iqd9qr+i7M7xUCRIONb7qUVP0j4+v1n1W0ZRxKlJPCo0s9w435bMLH 2uxCU5SsygqgZjyE3xIAW8o+ywFD+qK+ME/+7PbOjNAwPppnBJSKV6js9kJpvBa0IzCn4MhLvS7 uFGQSS5Va+XYhOhnlfmftQJFqUwbRQW5g39xp8isq6wsUjmyb1PMFgRoxmFN0aKM65meDbQ= X-Received: by 2002:a05:600c:4f85:b0:439:4376:cc0 with SMTP id 5b1f17b1804b1-439581ca7fcmr29685005e9.25.1739375020549; Wed, 12 Feb 2025 07:43:40 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd8dee385sm10812262f8f.61.2025.02.12.07.43.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 12 Feb 2025 07:43:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Rob Herring , Igor Mitsyanko , qemu-arm@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/8] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition Date: Wed, 12 Feb 2025 16:43:26 +0100 Message-ID: <20250212154333.28644-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250212154333.28644-1-philmd@linaro.org> References: <20250212154333.28644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The 32 IRQ lines skipped are the GIC internal ones. Use the GIC_INTERNAL definition for clarity. No logical change. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/exynos4210.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index dd0edc81d5c..b6537a2d64a 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -394,7 +394,8 @@ static void exynos4210_init_board_irqs(Exynos4210State *s) } if (irq_id) { qdev_connect_gpio_out(splitter, splitin, - qdev_get_gpio_in(extgicdev, irq_id - 32)); + qdev_get_gpio_in(extgicdev, + irq_id - GIC_INTERNAL)); } } for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { @@ -421,7 +422,8 @@ static void exynos4210_init_board_irqs(Exynos4210State *s) s->irq_table[n] = qdev_get_gpio_in(splitter, 0); qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); qdev_connect_gpio_out(splitter, 1, - qdev_get_gpio_in(extgicdev, irq_id - 32)); + qdev_get_gpio_in(extgicdev, + irq_id - GIC_INTERNAL)); } else { s->irq_table[n] = qdev_get_gpio_in(intcdev, n); } From patchwork Wed Feb 12 15:43:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 864468 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cc5:0:b0:38f:210b:807b with SMTP id c5csp187025wrt; Wed, 12 Feb 2025 07:45:39 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVBV9dMc+jts3NA9t6j0+Dv4zQG/f+SxhgQt4iaR5rxRf2nLgwPkGKO4hSRfo7zvs0VXa0MWw==@linaro.org X-Google-Smtp-Source: AGHT+IFLLGQOZINXfMzACTXhIw00gWdzwNtp0zbe47Y6eMZVmEk/sjqy9AdnaTPNj62blmXzXyNv X-Received: by 2002:a05:6102:e0a:b0:4bb:9b46:3f88 with SMTP id ada2fe7eead31-4bbf2215e60mr4297186137.11.1739375139052; Wed, 12 Feb 2025 07:45:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739375139; cv=none; d=google.com; s=arc-20240605; b=FCPyhIZNCpPH4ENiesNnBG4VuBuGGKDbd4W7auUDe8Q+GP/ASZPvEhC0rS1iWc4YRJ bP4OEMRPTrSW9yRqNdbaGnrL84aUjd8GD0kDHTSAw/+D5Px5dZBc2ylK3ukDybnmJnmj aGS5qMCb0eh2oLigXsG8yDuyN18BYeKF4iZdYroLr6AKRBZ7JlYGXMAgymbB67ZGLMOL q3bpo0PvIbshac9piR3gAuXyVLtFPh/IR4dLbqsxyfPETP0HnE+FqOO0wrqIsVQDVQfT wzNkdUtSvB8BzTRirsb46m25ikhgysdglAzfq08zzeMNTBKJLg11d6kC+dqLkwnaL21v waVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LU07FFTNrNmuJxeXtZj1sROe3UDgZjRzrIqhpiTHeSE=; fh=lzaa7I3YGCYWkDWyTcVwEb5cG79+nkOCzjzvwF81yJk=; b=KwejQQBt3glwYlon/aqItz7yxIz4KLBWFlg5LW25mST4QzdshxhSJhIDT7bn23XpKi iy1WRB+C/ZclkpohwPJ6xe6ZtA1XLxrz1qinVIqGR0CcSNOY7HWw7yBg3nb3DY+ggrN7 nwP0L4yd4JZVE4BH3WN5SthaFCEtzNvF1MEcPRM29LU+scvcDTDSO0QL25RyHrtD2S2F 9RcqQPhxfs1lLlupAG5pHzOFalqYKi0oU8jwFueMWuCQi6kYHJn2qkGQW1pEJY5vQAsw xvBofMi8+tYa2asxrtHJNza/0opd9v11WhKgLhafYKU6HYGHKszci825gktZ1P3yqvGy 09Lg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=akQTDbLx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-4bbc8e4afd8si1621166137.225.2025.02.12.07.45.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Feb 2025 07:45:39 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=akQTDbLx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiEu0-0004PZ-61; Wed, 12 Feb 2025 10:43:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiEtx-0004Op-AO for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:43:49 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiEtv-0006tS-Ne for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:43:48 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4395561ab71so21170125e9.2 for ; Wed, 12 Feb 2025 07:43:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739375025; x=1739979825; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LU07FFTNrNmuJxeXtZj1sROe3UDgZjRzrIqhpiTHeSE=; b=akQTDbLxAjbKTWIfWY+SQwhZAh/ztcYL8vYyOuwDuUkHDxWXea1gpUiIvrWsG4kbGD +xKiU6Tzj/9o0i0wJWsLndfh0X/9htvADotYAZrw6dvqoRSMDD/+H46gw1oGXlD60aA5 rDfOAyTpXkbbQl4712Q/dj6Pqch5aIUzuagD40v56XKQ5oMjmdO4c/Vpjc4xroLu78PN gOPFDmhJ8POoi731JIeNtXrkMx/ajrcOzZidZi8YnDdDliLn9zXka3WqKh7lwdaGZDJL LZ7CG7Z9Eg4CyZR2foLk7tjSoPZqGDKwINqsAcjAavh1lFOaby1ds1QW49XmjeXmx7g/ pFVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739375025; x=1739979825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LU07FFTNrNmuJxeXtZj1sROe3UDgZjRzrIqhpiTHeSE=; b=HVG4p20Atsf4ENJ/2ySINZ3wZpFL/40jpv8juoeOs+HgRshpuLbJZFM+V5wQLLcpps LQJuQVq6W8DLk4fILvulpoxgV1aqvcyvjwsL4VfiIxj+I9YI/qAy8Y73tJy06mYsaKb7 hUiZDp20qxZ1ZEmGRVBjoa1rqgNiX/NMznaU/s3+OTX5qiEyyLPamwKmJkmdsfAD8XFp i5ubSNSC1W1E5J2I+elZLIryFY+rAW6Go6sMTZmiNSnVw0T56FmM+yHPbj/S7b5lz7LT SU0IL5M2MS1qpGR5Z0c11ps2T9QDyGaiJh14SFNz2EBb6+4LQZG7y0LeH7649IfbNV7F Xgiw== X-Gm-Message-State: AOJu0YzxVmhylDs+VC4Zmh2PK7bg39qmxHUVKllqUjXWxsh7wbbo9jOJ 053v5cZ+UGCXRUadNae3zmlDfLcfSGmpMlwWkVkObfz1gAUIxTsuMZU7jSlrZtHFnE2YmlmAfoG uzTo= X-Gm-Gg: ASbGncu0FxhXZR5SPzDdjzkkmbClKqJoVA3PKgcHetiLqcut9gWfT9EDCTPFqklOYeF zP1AOvM52w2LeYnORawTTiXimjFhaGerZwtg9u4h3s6feS1FYw7pJktNCRrBipXJPG4SUdzzghK qt9Z9X5RMT2AocjBVSWv9prYUKxrdmccsKUmUt/XhypmjSaQQJDGnDy72k3ABHy7qLsA2DK6BPZ ZBZ0OHarDgUXYWVEkiPTcCUOsPh4GhUum5bdHZqqTHBKd0SjbWO7vFAtYafm381zbRHb2LxEzED ohYfjKEqr/KqAooj9+8voXnvJI/KmxYRs9z3cL4lTcueXTABoMgJFRrmCT4kArSONzEjPDY= X-Received: by 2002:a5d:6da9:0:b0:38d:d666:5457 with SMTP id ffacd0b85a97d-38dea2cfee0mr3483006f8f.42.1739375025566; Wed, 12 Feb 2025 07:43:45 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4395a1b824dsm22948015e9.34.2025.02.12.07.43.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 12 Feb 2025 07:43:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Rob Herring , Igor Mitsyanko , qemu-arm@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 2/8] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs Date: Wed, 12 Feb 2025 16:43:27 +0100 Message-ID: <20250212154333.28644-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250212154333.28644-1-philmd@linaro.org> References: <20250212154333.28644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/exynos4210.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index b6537a2d64a..b452470598b 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -103,6 +103,8 @@ #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 +#define GIC_EXT_IRQS 64 /* FIXME: verify for this SoC */ + enum ExtGicId { EXT_GIC_ID_MDMA_LCD0 = 66, EXT_GIC_ID_PDMA0, @@ -588,6 +590,8 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) /* Private memory region and Internal GIC */ qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-irq", + GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(&s->a9mpcore); sysbus_realize(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); From patchwork Wed Feb 12 15:43:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 864465 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cc5:0:b0:38f:210b:807b with SMTP id c5csp186259wrt; Wed, 12 Feb 2025 07:44:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWduChgnkEG0GEXrZpOiczfFLueyQr2/F00YblEyGsfQQk9rjcAHl4NyULUBqdtQNAA2iyr2A==@linaro.org X-Google-Smtp-Source: AGHT+IHPOAmxDAGdTkcitwgpf0e57ZjYYx46XR5lh696CzKhQ03oXiridXf11lB+qI9GkbIycRU6 X-Received: by 2002:a05:620a:4807:b0:7bc:db7a:4f78 with SMTP id af79cd13be357-7c068f8a002mr1187960185a.4.1739375059470; Wed, 12 Feb 2025 07:44:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739375059; cv=none; d=google.com; s=arc-20240605; b=F/oeSlyz0MmjK5RYm7izmI7P4AbRWZtS9MXn7/3yySk3AII/UYj0T+GLA/JxROKijh tPa8Kj/x2xwUYPgTQhQErP3NP4BleLNfMK1rUmn+hRtGkDFKJ2gmjFQQWnk9KCy3PDca o63dbuZg0TkhCerzMGWX7r4MR4AT/tA1TeYP6iZZCVk3JYLV1zWI7BnpVVctGLPOpcMb bhEgjgHkGZb2xJcs9ZURCpwLHBNhB5yopthPQbw4ZILVzecj9PkhxyKB3Aq1wynjT8bQ d0d2bpG+w8iPUiYXFxOnGIN04+TsDmOr1n5kUbSAg1lJXQfmGg/ZFEuNYmR7JU9U/xAB qvew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UKvpyBheJZs4xo26Id8y6y+sGte9Qefez9+pLdOdy9I=; fh=lzaa7I3YGCYWkDWyTcVwEb5cG79+nkOCzjzvwF81yJk=; b=F380b/RH5fWqnD+hbM1vFey7Fd6IhmdsTvFXzWgTJiNONVE868yWqGv0P9tAkbLTsq +GMDL01oV+CbxKJfEksuLC1BAhcjS+dJNUiawO4szEE/6hlzgjjnD5CDgiyeYxcos5Sm 1ofTLx3lDODlTpfX4G8fZiSpLdNDWFm0EcCdl55zsdmxq86cKW/MJcXueS+a7uYp+SsX HoqE2fCnKrgLP7PX9sAgzwY6yaOfLX3E3t3tjTx08ap4rkwRYlglt/Lw7ui7+8eTrMGO b2EGSa9IL2JOa2TdssxAUuvvAI4uy8XtYK0I3PEeDE44VLakEYrhWnzjE9cWM30ntpOY eMBw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ialgzR/Z"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7c055f31059si854323085a.488.2025.02.12.07.44.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Feb 2025 07:44:19 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ialgzR/Z"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiEuG-0004XW-IZ; Wed, 12 Feb 2025 10:44:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiEu2-0004Rr-6m for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:43:55 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiEu0-0006uI-L8 for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:43:53 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4394820123dso21816245e9.2 for ; Wed, 12 Feb 2025 07:43:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739375030; x=1739979830; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UKvpyBheJZs4xo26Id8y6y+sGte9Qefez9+pLdOdy9I=; b=ialgzR/Zcd6TcnLT0ox+tvRECh+rmymBU541eZ628aUPhx+0db8oOrsB684bLuvmtG kMbNuPgJ0Qhlca2ldcjL97+P+NcoRU1GwTPSckbi0UzexADUAPtxJvo0qbT4AxoPQisg rzvv+KJP3AafKYHca1LqtiYATlDyiBoUKAhai/z4tHua1ZV5bMf4/APF4ZM5A43uhPTU 9LeG4zc+kpR3SGD6ObsunyWkJznWun38iXUpnQe8Zsh4g9D9SBQqhw+fXXqOiyaXJaq/ 9DsGXGxxC4ImHSKtEbMuT5DIVnQHAmXTsbUgX9pcbjNJ4/Tz//1CXVeYcUOOjff9smWg yR6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739375030; x=1739979830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UKvpyBheJZs4xo26Id8y6y+sGte9Qefez9+pLdOdy9I=; b=mwUIIn4gyJ5H0RCGYfVBQrohY2w7+Ob9pmrzRuPIAdlesmhlvln6zpyBE0sqnSV9Gw VJltmVtgjJ7NrqtyN2NK0i8DU3+kU7GupUpPK8WOWH0CYd107MVNAMcC0YuN6sCgCw5o ajYg0Y5ZDkjm7fVrCunK3X8Zl/BbD4kaI4v9wZ2UVooXX6K8ETpjZC473ivg0u7dPquR b7Y+J9MvYNm46i5Fgj0dfniyMx44P/kA54Li19YNi3U6bfTw9CbXjXnUCkUWB0yXuaA2 IciNadd5F4Sl8CbiuFrl/iyPjA7mmJRP6doHMUuBlsPVp8WhlB4aaVRXuis3PTnzSy52 TzFw== X-Gm-Message-State: AOJu0YyuyL71sN8Q1Xp8mOSSbFf8QGGXvuJDBCiYWgmQSL+G36Ne/s05 nHru1t4BjrXQr/rVKFMV6A2Jzx7UtJYdxOFpn7oI2P2cw1n3VeJO+Ab4Di4h7ogJzzPo7F9690K 6nEA= X-Gm-Gg: ASbGncu7R8mo1i5N9vPt5E77J4/ObsPDdSkEOznF8ZHnEoGLzBftZ5Qxgw8chZDODV0 tRpoig5Gq6L437mCfx6BeFMhCahIw0F2NPcejldEHy+n7lpaMd2awmpgqaOmK3hrF+sviZUH1/9 3eb+Y2U1yEWIZohD4Aos/GopEe0yetdpWctGTgaH59xOcm1Ke4UHUNOg9Wj8K2LKpZc1+Obl/K+ +1v1djP3iSNBeT5uSYFEOfoK515Xl6x6n8Qne3NBUYVuIvO0dTYdeMxyZS+jXnOIWHi8CUm/EGy UJ8O/9UxCDRaistnrIymXRNrea0vDirMVdQI2pbyqrgM8NDOOUvLB8q0aFvao6eF00Uc1s0= X-Received: by 2002:a05:6000:4014:b0:38d:e092:3ced with SMTP id ffacd0b85a97d-38dea251738mr2972459f8f.7.1739375030528; Wed, 12 Feb 2025 07:43:50 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd9c48173sm10137892f8f.37.2025.02.12.07.43.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 12 Feb 2025 07:43:49 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Rob Herring , Igor Mitsyanko , qemu-arm@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 3/8] hw/arm/realview: Specify explicitly the GIC has 64 external IRQs Date: Wed, 12 Feb 2025 16:43:28 +0100 Message-ID: <20250212154333.28644-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250212154333.28644-1-philmd@linaro.org> References: <20250212154333.28644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/realview.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 9900a98f3b8..e50f687227c 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -35,6 +35,8 @@ #define SMP_BOOT_ADDR 0xe0000000 #define SMP_BOOTREG_ADDR 0x10000030 +#define GIC_EXT_IRQS 64 /* Realview PBX-A9 development board */ + /* Board init. */ static struct arm_boot_info realview_binfo = { @@ -185,7 +187,12 @@ static void realview_init(MachineState *machine, sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); if (is_mpcore) { - dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); + if (is_pb) { + dev = qdev_new(TYPE_A9MPCORE_PRIV); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); + } else { + dev = qdev_new("realview_mpcore"); + } qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); @@ -201,7 +208,7 @@ static void realview_init(MachineState *machine, /* For now just create the nIRQ GIC, and ignore the others. */ dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]); } - for (n = 0; n < 64; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } From patchwork Wed Feb 12 15:43:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 864471 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cc5:0:b0:38f:210b:807b with SMTP id c5csp187420wrt; Wed, 12 Feb 2025 07:46:22 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXvqApu+FK2e4OsDyBjk99r5Vx8CM1D3rD2kPUSQXtCtp7Z+rimGXR/VTk4Afbkd1FQyK/9NQ==@linaro.org X-Google-Smtp-Source: AGHT+IHyq9z8kD5CUWBpbOCx7QjoQbnmHuaaNxvtoz0kRgkAJmRLHGkuVc4Sd/NBUxaGMA0M+w8w X-Received: by 2002:a05:620a:4094:b0:7c0:6139:8f78 with SMTP id af79cd13be357-7c06fcceddbmr763946885a.36.1739375182354; Wed, 12 Feb 2025 07:46:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739375182; cv=none; d=google.com; s=arc-20240605; b=Vn1PEVQo1jIP/LM4nFvomQdjlbqd3Emmv7YTFUUdC/GzRX+CDyv0FvDS8/rSMaiUQR +dGbHiMXxrm+lZiSDv3/G4n7yUfsYL5mZZHu79wEeDm0DVCqgiUD1dtSkEKGNQgN3lFV UhveQC1nuTzvsK5j1u8jbDRTfWkD/IIXk4hdz6h+xrzn9shQwwplG+gHfys9aPOYgTh4 T4DhsJ3TfQVsefCdqMITSK2pQzrlmG0Xp3MHsN77E/uYpwP3ndraXrH8Wxmtah27+S/b CW2/eRYZcZ57VT1OcKhmSquXv4jeRnaPZuyATApTDBg6h7Kbxe4R/GolOdh1PJGhB1TF Uo+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mEULPqwUPtpzNSB0Z5/nLsqbWtVDcoNpITYqgf9zX7Q=; fh=lzaa7I3YGCYWkDWyTcVwEb5cG79+nkOCzjzvwF81yJk=; b=LhUGGGa0qFoFLvw8JsCNTlSyJ6OHERWpg+m3x9RnRshDv897o0bsMaMboXPexa1Qi0 UsPodkr33hk3OJJCBA6FMxvb7PqLUtgOxITey8UwDrTwd3yKIQoI+MwXY+M+gj4zX+A+ JxrT4fLZ7M/dNQ6hrP287RKRo/8yMDG+ZqZkHRGY1+GdB8KuTv95rS79KCgKiPo9BVXF GzA+O1M7q3uPw14PpudLXjzRBH7ZKngPQlTIrBOKJ9BlqvKosY7ckFjncddAgHA6WgrU +/JKh2OjsxE5gvYl0RrKiJg+CIP3NHA4RlfxUOpVHTKa0ImLpFphIdbC8YCAwtqeg1Bv 5LUA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P7k3ZPyI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7c0581589c2si797343185a.10.2025.02.12.07.46.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Feb 2025 07:46:22 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P7k3ZPyI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiEuI-0004YU-1f; Wed, 12 Feb 2025 10:44:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiEu7-0004SH-EI for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:43:59 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiEu5-0006vS-Jk for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:43:59 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4394036c0efso25016285e9.2 for ; Wed, 12 Feb 2025 07:43:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739375035; x=1739979835; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mEULPqwUPtpzNSB0Z5/nLsqbWtVDcoNpITYqgf9zX7Q=; b=P7k3ZPyIkKFkLH4dwjWmK9/nwXvJJls5IXb1+24zeRE/ltvtUZO1JvtfS2XaXiqAPq k9CNs1GLJFtfsUEkEZHekY6cdM1eJydveHSUNlIoNCZUZlRw+832wOZW1aBU1GQI0Fds d3TKNUjd6oYDwFjXZmyk2sa9XA7yDjifbPyQ9hrJmL+URH1c/4NpE//fJPuf8Gn+Sb4P knHf+x+BzynCchaI3B9uIWC3CeLlxR95+6vz0sg1xhVqnNjXAZmE1BNB0QwKPZpsLzFN RbiW1W74J54LeBOyZ7sV4TNU3H11KWtkVWbGIUsZ/gSs8/gZBBWiy/MPU7CSsWwJ60ti JSQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739375035; x=1739979835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mEULPqwUPtpzNSB0Z5/nLsqbWtVDcoNpITYqgf9zX7Q=; b=aaYOWg8UhnzTtOGnFs2hp7StJeDCNhGQr6xy4QpQ60Dd7oS3BcIBfZXARFD6b+Gzax QYXOG/NTV1V3HeZ/qnMGKuQpF8I6h8xnpigWJKAsTunFgSJQtVkrRSu+zX3MkSth0Kt+ 0DBQS01cPQ0Ykn4AD5OTU85kesN7JctwKTpBda/X3yXtAUsU82PXuRZMpzAFXcTFogQC U5ihbkaVZOSaBzOfugXNLB4T3WmzvNVDagPWLVcPqYGTdexlQSsogRrMnPJZToK/7pvX J6yyVQ0qIuRWELM8ZgMSZJ9xoUq/IPqq2fU61rgXXRBOTiaNvUw3YgLzYQoMK14Oy4VK O8QA== X-Gm-Message-State: AOJu0Yz9WiZOfwvwwCureJv7DrRHVrBNNZWYCwDySs5v5HvskoXo+3Ox xrxXdoYvw2qNc6EAHuK2APNxSN4734VsjeN6843UiBpyU7AR/cR1r+X12wY0S38W51dlgDcFgZS JoXg= X-Gm-Gg: ASbGncu1QQNaR9ZwFI5ZDl/eUipHWeYmlDCKx+lVIoqkK9rtYWxwzdCzA/dPLpUsXzc Gf4jRllqx1XRnLzWubCOY4mFdRp97uxFEkBIAkghYfAywjo5l/42IxHRtg+qE5Uv5Ou6z1Cm4Hr nOqjIilCYHo6tHwqpdhCKK+jRzs2wYF16k+72zBR1bfLhn9wP/vDhXpDSbupIDa/nhsF44U4p1+ onPX/vcYpQR4kJ6V5lZkXz1tOg6R6OwQ8GHkeNmGjycrgA7lBimvl6QxOy7GqZZI/BBBPVhRR0Z lOAo2j5IyGHYRdefvG/HOjCKIKyAtrJgbUYdkeA5msvkIQGiHrvuAxBQE3Pie5Un2z4fg2c= X-Received: by 2002:a05:600c:34cf:b0:431:3bf9:3ebb with SMTP id 5b1f17b1804b1-439581b2618mr36292205e9.24.1739375035466; Wed, 12 Feb 2025 07:43:55 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38deb4f7bacsm2120986f8f.58.2025.02.12.07.43.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 12 Feb 2025 07:43:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Rob Herring , Igor Mitsyanko , qemu-arm@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 4/8] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL Date: Wed, 12 Feb 2025 16:43:29 +0100 Message-ID: <20250212154333.28644-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250212154333.28644-1-philmd@linaro.org> References: <20250212154333.28644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We already have a definition to distinct GIC internal IRQs versus external ones, use it. No logical changes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/xilinx_zynq.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 8477b828745..18051458945 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -54,8 +54,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) #define FLASH_SIZE (64 * 1024 * 1024) #define FLASH_SECTOR_SIZE (128 * 1024) -#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ - #define MPCORE_PERIPHBASE 0xF8F00000 #define ZYNQ_BOARD_MIDR 0x413FC090 @@ -281,12 +279,12 @@ static void zynq_init(MachineState *machine) pic[n] = qdev_get_gpio_in(dev, n); } - n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0); - n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n); - n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n); + n = zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false, 0); + n = zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false, n); + n = zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, n); - sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); - sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - GIC_INTERNAL]); + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - GIC_INTERNAL]); dev = qdev_new(TYPE_CADENCE_UART); busdev = SYS_BUS_DEVICE(dev); @@ -295,7 +293,7 @@ static void zynq_init(MachineState *machine) qdev_get_clock_out(slcr, "uart0_ref_clk")); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0xE0000000); - sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]); + sysbus_connect_irq(busdev, 0, pic[59 - GIC_INTERNAL]); dev = qdev_new(TYPE_CADENCE_UART); busdev = SYS_BUS_DEVICE(dev); qdev_prop_set_chr(dev, "chardev", serial_hd(1)); @@ -303,15 +301,15 @@ static void zynq_init(MachineState *machine) qdev_get_clock_out(slcr, "uart1_ref_clk")); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0xE0001000); - sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]); + sysbus_connect_irq(busdev, 0, pic[82 - GIC_INTERNAL]); sysbus_create_varargs("cadence_ttc", 0xF8001000, - pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); + pic[42-GIC_INTERNAL], pic[43-GIC_INTERNAL], pic[44-GIC_INTERNAL], NULL); sysbus_create_varargs("cadence_ttc", 0xF8002000, - pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); + pic[69-GIC_INTERNAL], pic[70-GIC_INTERNAL], pic[71-GIC_INTERNAL], NULL); - gem_init(0xE000B000, pic[54 - IRQ_OFFSET]); - gem_init(0xE000C000, pic[77 - IRQ_OFFSET]); + gem_init(0xE000B000, pic[54 - GIC_INTERNAL]); + gem_init(0xE000C000, pic[77 - GIC_INTERNAL]); for (n = 0; n < 2; n++) { int hci_irq = n ? 79 : 56; @@ -330,7 +328,7 @@ static void zynq_init(MachineState *machine) qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - GIC_INTERNAL]); di = drive_get(IF_SD, 0, n); blk = di ? blk_by_legacy_dinfo(di) : NULL; @@ -343,7 +341,7 @@ static void zynq_init(MachineState *machine) dev = qdev_new(TYPE_ZYNQ_XADC); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-GIC_INTERNAL]); dev = qdev_new("pl330"); object_property_set_link(OBJECT(dev), "memory", @@ -363,15 +361,15 @@ static void zynq_init(MachineState *machine) busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0xF8003000); - sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ + sysbus_connect_irq(busdev, 0, pic[45-GIC_INTERNAL]); /* abort irq line */ for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ - sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); + sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - GIC_INTERNAL]); } dev = qdev_new("xlnx.ps7-dev-cfg"); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); - sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); + sysbus_connect_irq(busdev, 0, pic[40 - GIC_INTERNAL]); sysbus_mmio_map(busdev, 0, 0xF8007000); /* From patchwork Wed Feb 12 15:43:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 864470 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cc5:0:b0:38f:210b:807b with SMTP id c5csp187187wrt; Wed, 12 Feb 2025 07:45:57 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUZy6ndRVirXptBGDz6VHkX/h7kj/wY4MR8M7agOJgNazTNB5k7NjAZxcFMj4NfuaQ6QBQa0g==@linaro.org X-Google-Smtp-Source: AGHT+IH/9tSdHK0OkUWqVWRX4XqFOVowmcwW3JKdl5OFJNguhjVuaQS6anoCgiismg3S+1UwJ3Cc X-Received: by 2002:a05:6122:a24:b0:520:5185:1c83 with SMTP id 71dfb90a1353d-52067cc5667mr3634514e0c.11.1739375157407; Wed, 12 Feb 2025 07:45:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739375157; cv=none; d=google.com; s=arc-20240605; b=gvpSc7Yp7iTA526NBNBuMVU9z2ErhTY7FHeLpq/UMB0+k5HPEYIkFWhcbP+VQDuQcX GgIFrwIxlveD8BzYafXuWY7Plsf4WH3st7kUZwdlfSi5HDgF7YMksAza+gNnITlgknmR hvCfCW8LoEQVajKoGVFAHa/hQZspVTYLxSaPvUnBiqGWrxYyotPfHx+foLqkUDbDIZRN 1RtotE4a5YlsMpt7KDM/lrK/s67tr2DOIhPPdlo+Wb+d5GKI4MTfwG3z6yn+PNEVcDJO spcI3OxdrHxyUTf3vI4Y+cK4BxXWHVpm3EB5F20qLC2tw0pAaKoZCG17Ib5aZ3r/2lIA 3p7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZKFgzzj/z0innOIGEpKf0ZON0tQHn0YVUlggdFE5dm8=; fh=lzaa7I3YGCYWkDWyTcVwEb5cG79+nkOCzjzvwF81yJk=; b=WPlatYPzzs4bcrtuOZRLb/W7ywNXVxxG4oF92IXsiVC9++woHjP3mI34v5p2qEfqzV 31rUmuAIW4fyp2KnGpW4S3QvrTQUTu8vhDgj+9WD9d69zo/3ZwzuN19MjxbSeEYPv+/U uXMrlMI5T/8Tnt43cPB9qT0/MPW6fTn79qV2mF9hJytAozYXBIizquN2YP9m03K0vQQT Eiy/F1Iza7U5/qRBLcW4nj7G17DK3noeYF/Lzx34wjwR1zPoq+wvy0Sitp9NloZ4YAp1 E339oLpNpR3ktEe1kfF3hO3eceH7jtOTtKPp49DOtbfdoBKfqxzlYSufFArLliYW7dum 5nGw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=slQiwaCW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 71dfb90a1353d-51f4218f192si2076148e0c.148.2025.02.12.07.45.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Feb 2025 07:45:57 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=slQiwaCW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiEuK-0004e8-4p; Wed, 12 Feb 2025 10:44:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiEuE-0004W7-Pz for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:44:08 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiEuC-0006wW-Ac for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:44:06 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4395817a7f2so7664505e9.1 for ; Wed, 12 Feb 2025 07:44:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739375040; x=1739979840; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZKFgzzj/z0innOIGEpKf0ZON0tQHn0YVUlggdFE5dm8=; b=slQiwaCWvUdLyJOvJFYQuqL8XKe1FwEDtmCRehtMgUhqVnOJC9dqvNA/J2jsO+q0dF uDq1E2u/UfV+lrAg+AElPf27kbc0S+SnXThrLIL2HxI+9t4GdAvOTtvGSmCVRZRP99Dd atHw4UuKAMl+kAp89d0XB1bLeFDrFpIYlx3LaVgnxVhxQGI8T4rQ5TTGiHiUZO6NJihZ NL99KhCoeqwcgbC8yKwWen5KFOYLiimVlzw/3yT3BylDLghkNyB4QXRmTuOknzaD9HMK Q9rhs8a0cVafFRkmkGBogS1grIWCYjuj9bBom6a0sZqalsskdb9SFgJBdDGLKsvaLSYH WTQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739375040; x=1739979840; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZKFgzzj/z0innOIGEpKf0ZON0tQHn0YVUlggdFE5dm8=; b=V0amDbPPqfiH6ngMmhf/9dAqhNQjLEsyNCacM2LVEwcSXY+5kwPJHm5AxcKXUx4uEE 66oU5eunjmlOP34v4I5N/BkGcy60YQsRgHOv6e38HVSF3pexPOigWdrfE6uGLpyw74qa QkJGhIZbc3vc6XVx/VPfj0+0agnPpcXrP9q0xrUG1iEeotVnLctBQNYGCXsCUrKKwoXA entFwpD7got01wkMLu4UotoxHsPcIZKqfK3as8AvuC9lUbDq+uN4+FpRJ2vksrrRvSKu YbTWLd5NLQiMSMRZbhPcue6THMA3xP+JhhI59GHQ71J4/oYfgRMVfuSgSUNJwDK1El3y 0tFQ== X-Gm-Message-State: AOJu0Ywx3dpkR+XaVePJ4kHS27bJuXpzbGicPXYeafjAklnoqRpLoMGo IjsFPEBWV1J1iLqWxANOcgjQ+hIjxvYT9SLbfbBQIDanOMMEJA9TmI0eG4j7cD5tnfXSNmOy2Tg iJd8= X-Gm-Gg: ASbGncskhcTs7VnjQvgiKPzKwewSua0QP3XICLd1xYzaChDqGESFjpp05pBRekHVgtf /+C44zCG2f14sFj8TO/g5RNZiFfw+LAJUJr5F/NpG9CdWzd89RYMgaAkOM9SSV7VEiONv5uqBH9 SLsTezzx/583wHAbcbqrAd+UseFz/Sh5wmBjBYl5qDScYBuU5UJrD9XSL2dRWZhDCpBOpkewZgJ ocwvFpyhrCtiR9hQEGiaKK7W8b9UKide5S39xOaXts255FIY/DsZjyCVvGgaH1vaFIBPfBKhnX/ owTyQ4W8XWq6yE+SbNZlCXAwT9irPH+AaSE5W4ssonqQ3tHB7FCXc+gCnwsBbUpFhjxIg6s= X-Received: by 2002:a05:6000:d83:b0:38d:a879:4778 with SMTP id ffacd0b85a97d-38dea286d93mr3133322f8f.33.1739375040517; Wed, 12 Feb 2025 07:44:00 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4395a04cd53sm23549755e9.6.2025.02.12.07.43.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 12 Feb 2025 07:43:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Rob Herring , Igor Mitsyanko , qemu-arm@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 5/8] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs Date: Wed, 12 Feb 2025 16:43:30 +0100 Message-ID: <20250212154333.28644-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250212154333.28644-1-philmd@linaro.org> References: <20250212154333.28644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Looking at the Zynq 7000 SoC Technical Reference Manual (UG585 v1.14) on Appendix A: Register Details, the mpcore Interrupt Controller Type Register (ICDICTR) has the IT_Lines_Number field read-only with value 0x2, described as: IT_Lines_Number b00010 = the distributor provides 96 interrupts, 64 external interrupt lines. Add a GIC_EXT_IRQS definition (with a comment) to make the number of GIC external IRQs explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/xilinx_zynq.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 18051458945..3d7c4f04974 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -57,6 +57,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) #define MPCORE_PERIPHBASE 0xF8F00000 #define ZYNQ_BOARD_MIDR 0x413FC090 +#define GIC_EXT_IRQS 64 /* Zynq 7000 SoC */ + static const int dma_irqs[8] = { 46, 47, 48, 49, 72, 73, 74, 75 }; @@ -205,7 +207,7 @@ static void zynq_init(MachineState *machine) MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); DeviceState *dev, *slcr; SysBusDevice *busdev; - qemu_irq pic[64]; + qemu_irq pic[GIC_EXT_IRQS]; int n; unsigned int smp_cpus = machine->smp.cpus; @@ -261,6 +263,7 @@ static void zynq_init(MachineState *machine) dev = qdev_new(TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); @@ -275,7 +278,7 @@ static void zynq_init(MachineState *machine) qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); } - for (n = 0; n < 64; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } @@ -458,7 +461,7 @@ static void zynq_machine_class_init(ObjectClass *oc, void *data) }; MachineClass *mc = MACHINE_CLASS(oc); ObjectProperty *prop; - mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; + mc->desc = "Xilinx Zynq 7000 Platform Baseboard for Cortex-A9"; mc->init = zynq_init; mc->max_cpus = ZYNQ_MAX_CPUS; mc->no_sdcard = 1; From patchwork Wed Feb 12 15:43:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 864469 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cc5:0:b0:38f:210b:807b with SMTP id c5csp187179wrt; Wed, 12 Feb 2025 07:45:57 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU0e1Ubx5PC/7q8FD6WEycH0e0I1HX45HEqYDAulYQsgFmqruTGm+zhL2sCQItE7+2Z5DeQ5Q==@linaro.org X-Google-Smtp-Source: AGHT+IF14XG/Cmf1OAizDw5Xqm/RK1FVn0SHodvqP2x8pbk9/xoPINy6HPI+EJxNZHoh0hG/vnvJ X-Received: by 2002:a05:620a:27cf:b0:7bd:bafc:32b0 with SMTP id af79cd13be357-7c06fcde1ccmr648859485a.47.1739375156830; Wed, 12 Feb 2025 07:45:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739375156; cv=none; d=google.com; s=arc-20240605; b=fWhs/JO/7EtQqbaSf0PgKOjswaWrG+rpbn4i54tXY/YzesS+Q798jrfjV8qCyWZD7q 4N/hPgBh0WiKoCbWB7bzKepST1PQ3ABRvuvxAgOSLJQzpp3TN+ZF2mYVQ8r924rMltfW +DWbDqGnEV/wgiV4EP+TKpEyi5C+YpMAPntNroEjn27zT82zOTK/WpTq2uZqwbk/3GVn Q6uz6t+TY2T8tLnhluwVTG88ynAieSq7874ymp93Pmh0SYmeL6YXJJa+mwayz6cJTjDQ 467fK0QOXUAlx2FFnR+sBuiT5aJddiFcIQMw4fPyB8k8sg+UlWPU5+bef1Vr7d0FrW0o WIAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4oliSOJgGRKuXOia3Ki/Ch9S5/flKCg89pdGUC7H+JA=; fh=lzaa7I3YGCYWkDWyTcVwEb5cG79+nkOCzjzvwF81yJk=; b=EgwozkBsSfsGyTAzuTCbK15ZESWqETracoFXP4hDIAfwwCT6byvDXPAQHHpZU+lPNI HG67REAWLIlYn6Ld/uvN6yJu+uDuXGxY5sUJSMi3LEVzPwgOLNKeb2G3ZAhZNbJsW72h N04ai5IcT8uUyzzBWsds36KgmY4r7FZ0IQ1ah/2EN30D7klRFhM928SdicRxc+IzvY77 aCTMX1ZdLts65j3JgYn4NdreH6LKoMs6I61/2Vp/YyY1ggNxalbeaYzGpByxypTZtLAW jMo/MFiAGdlzUpWkO0dxcc1Zg1L5nKKKy0gUHqSMyiq8xmy2CzMZJIUcDagmPrs1TQ4A FINw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=epen3vHf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7c056681c7fsi841291585a.146.2025.02.12.07.45.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Feb 2025 07:45:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=epen3vHf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiEuM-0004gw-LL; Wed, 12 Feb 2025 10:44:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiEuL-0004g9-4H for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:44:13 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiEuF-0006xP-R6 for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:44:12 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-38dcf8009f0so2687824f8f.2 for ; Wed, 12 Feb 2025 07:44:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739375045; x=1739979845; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4oliSOJgGRKuXOia3Ki/Ch9S5/flKCg89pdGUC7H+JA=; b=epen3vHfZRjgsWbgkYYsIDFfE8J9rT9YJzSwSZ5Jtqs1Sd3g9Wq12BegHyNvMnXpGd RRTaGRNVqwfU0GRf4vH4WNvBxz8vPwek4R0HnkWxuhp0X9CBx9Z+vBH5OnHPACBmhfZ+ ywlpTBs76J9MMcDggphHB8qXj1WsuCqsrzpFv0GVc74puVDqYMoQnkNC+xVJsSum/DnH ehql6jsoYSvX1FRILOiLq40bDLb4OqCXRfsQdLaZbTuQcQz28kTmBH3wrzomHIjVkR/5 2KQUoxvqsCO9lf1+fUDXcIRTM26aStAiW4kBcwF2G9vKHaNOzWSMlEkfcr79Rfg6Wvuo 6mhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739375045; x=1739979845; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4oliSOJgGRKuXOia3Ki/Ch9S5/flKCg89pdGUC7H+JA=; b=lB1GzsCLSg7XBQSloTD6uSGeVk5XVgbVj6MhabEMRZmNF7L07ODSZ+s10lye2KaMkZ jglsaAaqqfkUXr5B3MqsIcZsdEWjIZbIrQmqDHrBhyTHHOuxiX52o/YJDcbHilE9Mrck UWKrZJrk4n/l3ySL0/5/ouBrJDtWR9WeuCAHD3XwJe5HElVEMV/jdxNW5XRNv/MaQ3yC 7VKcAGTVtYS5jGxqzGhVG90Z55TqJjzuomDu/7Pu8pbh/T4X1ohfzpS0iGxvWVOTeyeI jEcNQx5/oG+iflpxH0lgvrI9tmIkTfOPSyPsPDoBCaOep3GwGEzsI0ym205E1AaWefKP +zxg== X-Gm-Message-State: AOJu0YxvwLgMJ/DkC09pxo7eoik+P2a0gKnjI8+tsQqM1t0bTQZ+h1/Y JxBhCgu/N/y0kwuSP8Ff+uqdHUyIba7M300PpB5qxcR3d57x/s8zzlHSK+PmoWkwyS/vwL/8JCh kgY4= X-Gm-Gg: ASbGncuw9OUwCyQWGtlQpAxiOiF4Z0G1WLe/XJo0SjnhgTPMcMRdttGGqdDoWAHM+6v v+18L7IAti9hqMn9ObuOjUPPmwBMpRvV7flX/O7kBdDBbo/ohuvgFXOX4woTqGNEXGnNgoPPVwN s3fX+IPYzE8+UZa1M7X7A51jC2SA1nQojjmDXAQIxJeZQ1CCSvBr1KyFWQEGzeDGOSaB0zRNg1n zVWONF/nlzR/d4+52CBfuJX4sAIIoEOO2HFyGulyLDu2l244Stnt5wX9Fw/BpLPU/F9Ia6zKSev hT39DycxuRE8retehgWH2xjLHFS9zwZM/I7PzE7Oh0/vKLuxz+khAbEz6SoqNqHZPEeZtZY= X-Received: by 2002:a5d:47c3:0:b0:38d:de92:adab with SMTP id ffacd0b85a97d-38dea28c762mr2953973f8f.29.1739375045483; Wed, 12 Feb 2025 07:44:05 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f22fe1dffsm328860f8f.98.2025.02.12.07.44.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 12 Feb 2025 07:44:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Rob Herring , Igor Mitsyanko , qemu-arm@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 6/8] hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs Date: Wed, 12 Feb 2025 16:43:31 +0100 Message-ID: <20250212154333.28644-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250212154333.28644-1-philmd@linaro.org> References: <20250212154333.28644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"), and Cortex-15MP to 128 (see commit 528622421eb "hw/cpu/a15mpcore: Correct default value for num-irq"). The Versatile Express board however expects a fixed set of 64 interrupts (see the fixed IRQ length when this board was added in commit 2055283bcc8 ("hw/vexpress: Add model of ARM Versatile Express board"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/vexpress.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index b886d16c023..9676fc770fb 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -51,6 +51,8 @@ #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) +#define GIC_EXT_IRQS 64 /* Versatile Express A9 development board */ + /* Number of virtio transports to create (0..8; limited by * number of available IRQ lines). */ @@ -241,6 +243,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type, */ dev = qdev_new(privdev); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, periphbase); @@ -251,7 +254,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type, * external interrupts starting from 32 (because there * are internal interrupts 0..31). */ - for (n = 0; n < 64; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } @@ -543,7 +546,7 @@ static void vexpress_common_init(MachineState *machine) VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); VEDBoardInfo *daughterboard = vmc->daughterboard; DeviceState *dev, *sysctl, *pl041; - qemu_irq pic[64]; + qemu_irq pic[GIC_EXT_IRQS]; uint32_t sys_id; DriveInfo *dinfo; PFlashCFI01 *pflash0; From patchwork Wed Feb 12 15:43:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 864466 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cc5:0:b0:38f:210b:807b with SMTP id c5csp186291wrt; Wed, 12 Feb 2025 07:44:23 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVdxsc8hxrOwSZzsUwmtxhnp8ROkZ9A7Obnk9ZJlO6dr+YXFBep6zWMC9lZkg1oLsy4jymIig==@linaro.org X-Google-Smtp-Source: AGHT+IGiKeRK2AMMgChYHYWZsKXq+6wG0kpmypn8sOKzJWAdss7Ovd4U8MB3pEcV6nMCWHQRbvOy X-Received: by 2002:a05:620a:198f:b0:7c0:79b6:20c8 with SMTP id af79cd13be357-7c079b622e5mr27492585a.9.1739375062911; Wed, 12 Feb 2025 07:44:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739375062; cv=none; d=google.com; s=arc-20240605; b=McmydXuKLmi5zqBlxAP4XyuIhLMKdm9v4z/kmO5TGYkrZHe4NMr957bbQ7wyTXWp87 8Fs2J6nY9QcijgmUP8D1zsQEDp6KYQm7WZ00KJYpykmZzxw3GQn0MVwmHJbivlUY/H7s vcEiuxlzniPYLFQZdn9byKUlES+IdA9mQzlBADnIcXuXZn0nMrjBlxXjeW3AE2ApiRYk UC4fs9Y2qnD4sT2qSt7L/QQ7h+LOxPgzJc1qVz9srpOkCqtWLVpZ/vqgNlg72k6X1ics gId0n08E+T+bWbIn/mfe+GUMig8RQypqYCpaxh3FEsCops4AjxF67hDDXXNfQcuzUpr8 JNcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7ToV0u5DP1HroTkKU9qlfVC69qypn9I2Owu2OBYKzM4=; fh=lzaa7I3YGCYWkDWyTcVwEb5cG79+nkOCzjzvwF81yJk=; b=WhM68KxYLhTF+/YtXY3FVru1tCtAUSuAM15lFxzQLwKyLdpOiDCMMnmticTN+Qlj8I j2GJcOmP0NY/EhjvnEuYLAeNyiHjHi9IsUrL8hbp0lnF2tTeq6QvZCci68X8ubofV0cV Re1jzbB7xfOvednK2JzNkosfsETIlXNEFL3YIG24gttZrxACgaCki2IKhrTEsUBXoEmE svnJ3srEFDbsezoEp1G4HIrH4eA17qJYoT1dTBpO5QaQ1mLjI5eRIpxPzFRZkw+88BN+ DS6e20hLwBM0j5Tl3v01VWkc6kMqWiSzec//DvxSPf9Atot//3DPe3zP0TJPaZq6bMVn Paiw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ma81nPyh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4717b0539easi91587451cf.621.2025.02.12.07.44.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Feb 2025 07:44:22 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ma81nPyh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiEuP-0004ip-OP; Wed, 12 Feb 2025 10:44:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiEuM-0004h5-Iy for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:44:14 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiEuK-0006yK-Sr for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:44:14 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-38dd0dc21b2so2981266f8f.2 for ; Wed, 12 Feb 2025 07:44:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739375050; x=1739979850; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7ToV0u5DP1HroTkKU9qlfVC69qypn9I2Owu2OBYKzM4=; b=ma81nPyhbvEZsE6X/Ol9x0JxdvtMOqlF/Zyxf2IpT2XW0Mk/ClxoZ38JNHSLzG2GvR x5F28FFJj+Co65ImoH0lZbHg6q+TbgICQCsL2FFJeYRL4K/YsITVCRVwfy1qf5QLVDvF dLeiGcE7TiOAkeQvG3qwduwYupiszTPlM/hCSvax7QTCjS+sKKspX31ZOum4ukqB1Q4G naYYGzO/HVQ0tPkmzuZV2yqAlGfyZCv5sY6xVKs25R9aNKjr9eJfqXDOsAOZlvunIO3q PnvI1p0ne+irUtDv6EfktbZHwIJHjay3MJYy2VBt4G8r1IBz2ZnWMhZsqiouJLfB4eek utjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739375050; x=1739979850; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7ToV0u5DP1HroTkKU9qlfVC69qypn9I2Owu2OBYKzM4=; b=b/VsQ/zR4Mpuzk8+FBPdGRj8KHMyuRxt6q8wFswW1UX7P7qC8f4dpLKoRkurzf8HGf +yPb3S7Ke3RiywXJ2Fifmk+sati1NCI8BF/Sq777EbC8Wn+6yZ5bZW6C0hn6xeU6KHfJ ywAQcPESPbmE3Jvfzgf8Gg6ttWFudcuU+893CPsbeiqjlWCwk0FfBQJr/MoLlj++q29J Hh6Q49qEp2vydejJKnkIsBFSjwPt02HKDvMjLJATxgvbb4Ye0CcScW5q/12XVSoOvh65 /dPMj7ZSQTlTPlVNDORyYGaCA8rpVeLJ/v2ejPLUBUn2hQj1eYR0b3XAWSwVwIpbL8rm qStQ== X-Gm-Message-State: AOJu0Yw0Rg8LeUhzcwB61BHajc4h7/dvbOPo1CgpBEDRkCggIwktXuql w/cxUWhK/hFgLBS3yJ9RAJ8OlouOMLonsY1Ux2CbBU3RAULmvvmMgRxhw4d0zcmEXKsPf48SBJA jq8k= X-Gm-Gg: ASbGncuKchJTD53a+pcWvKVVkjNvGwxKtakUd+a8SgKtyKdpv5T0czbBo0x7e4tuHtr XuwpNCG/yVfgwcntE5jKuGnmJkG0pdWs5umVky7eu2pSscVvb1ZapqNVGKgOatSGp6rRY+bFstI V/uNBYjJqexIACyYZhTbdD9J8VafADjm9EhQaeVt9qK4wJ9XotjelYO1iJtDLOfglip/eRjgAPt wmJiny/gsBXxfFsjBQZdc5ODlRAxWJq1mwjVebFd35Z/pNSKCJt7ehjKnaJCYqpLW9ocuctcobR Jv4ocyT5yBy7pabzW6S0KJ7oxXGlqfO4EyD/2M7hKZJgYmx+HkRY/MtInsHi3N+s51hogZk= X-Received: by 2002:a05:6000:1541:b0:38d:b57e:71e0 with SMTP id ffacd0b85a97d-38dea250f4cmr2560745f8f.4.1739375050418; Wed, 12 Feb 2025 07:44:10 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4395a0558e2sm23185625e9.11.2025.02.12.07.44.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 12 Feb 2025 07:44:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Rob Herring , Igor Mitsyanko , qemu-arm@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 7/8] hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs Date: Wed, 12 Feb 2025 16:43:32 +0100 Message-ID: <20250212154333.28644-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250212154333.28644-1-philmd@linaro.org> References: <20250212154333.28644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"), and Cortex-15MP to 128 (see commit 528622421eb "hw/cpu/a15mpcore: Correct default value for num-irq"). The Caldexa Highbank board however expects a fixed set of 128 interrupts (see the fixed IRQ length when this board was added in commit 2488514cef2 ("arm: SoC model for Calxeda Highbank"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/highbank.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 495704d9726..0f3c207d548 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -45,7 +45,7 @@ #define MVBAR_ADDR 0x200 #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t)) -#define NIRQ_GIC 160 +#define GIC_EXT_IRQS 128 /* EnergyCore ECX-1000 & ECX-2000 */ /* Board init. */ @@ -180,7 +180,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) { DeviceState *dev = NULL; SysBusDevice *busdev; - qemu_irq pic[128]; + qemu_irq pic[GIC_EXT_IRQS]; int n; unsigned int smp_cpus = machine->smp.cpus; qemu_irq cpu_irq[4]; @@ -260,7 +260,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) break; } qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); - qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); @@ -271,7 +271,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]); } - for (n = 0; n < 128; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } From patchwork Wed Feb 12 15:43:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 864467 Delivered-To: patch@linaro.org Received: by 2002:a5d:4cc5:0:b0:38f:210b:807b with SMTP id c5csp187018wrt; Wed, 12 Feb 2025 07:45:38 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXJbtjI+3UUEHQ65kSBJIa3A19HCRxDykQCi1e+QFjHYKho+PYVf2lnZ4IAxL9FA6Xmk2CTeg==@linaro.org X-Google-Smtp-Source: AGHT+IEQe0SlVVr9oIUZE3GfUxw0jjYU57Vxmrwn6iKUzzJKjGzBEmYEjNw0NUkIG9vCPbz/JxTO X-Received: by 2002:a05:6102:50a9:b0:4b2:48ba:9943 with SMTP id ada2fe7eead31-4bbf231076fmr3881778137.24.1739375138300; Wed, 12 Feb 2025 07:45:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739375138; cv=none; d=google.com; s=arc-20240605; b=OhAFb5Zg3+hyYK70VClFTP1dvsTJ5pdUzExeT9jDezf4bW886jFC6G0gz7/m3g74ge X5Rwhcd3RgDs+UicOHLQqqv7dcK4NlR8TFgl7k5h2Cl293Dj8tzgSIjTbwhXHGlGFKd+ vtW/pda6R1fwqXaldZyNlY/8Knjzcg5hTBB2wLXhL8GgsyYWeeB6A+5bIz39wDUx2mix Rxs7TisdPDLkt9IB88cg5eRphhai6vs4htk+8kKYX+7pZXtlZynRSZUmMiIjO20+5kYY 6b1Hpn5TTo28pTHQQC9/3lvQ4QwvoEkkdSudQpIccAJZ6zi7vE8PC+EYJeN9qTyvyFqo 0qLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Mwycz5Xhxtli1uhKd9D+bdo2NY7ikbIMbnIzjX1Fs40=; fh=lzaa7I3YGCYWkDWyTcVwEb5cG79+nkOCzjzvwF81yJk=; b=GjegzV7unfjGdrueDJuNETTTkohpeG+go+CqorToPl9iOCztWYgw+7OE32d5AO0w/7 Elai7iXqFFfFxu7LLVVBJNrI/2T4uavbS7WQiLhnqZRAydCKJ2Nm2PlHC4b9oB+LaRWn GA+knZvxkJyAlCo1m6YSBuGc5n7ivYWuID79+GTt0OmHHBOOdaYnzy8wp1IQVBPYteYe oMUWokhOsOqEHv9lE+jWiuOHlYViEnswXm/XSw+wN2qg2rZRVuVKvtxjRRdEo+3pmSFG CfH4ouhfC187RHZ0l/KGmSVbBaxVMtHYphT9pmTF9x0U6mFc1fAqARbCtqMgqjCWtiZL memg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Kxt/IVvn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-4bbc7cecf1csi1368830137.444.2025.02.12.07.45.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Feb 2025 07:45:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Kxt/IVvn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiEuv-0005Nn-IF; Wed, 12 Feb 2025 10:44:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiEuR-0004pB-HJ for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:44:20 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiEuP-000702-Mr for qemu-devel@nongnu.org; Wed, 12 Feb 2025 10:44:19 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4395f66a639so1935025e9.0 for ; Wed, 12 Feb 2025 07:44:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739375055; x=1739979855; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mwycz5Xhxtli1uhKd9D+bdo2NY7ikbIMbnIzjX1Fs40=; b=Kxt/IVvndSdiupZd40lsqfqr1fHbeRNey2WUM9z8yzwitHSYr8bR4YFDddFbxwkRTm f2HAUZREq9ure5I5tj9Q8gAhE3eg1VdnxQHP1rpj3+AuZ1wxNEyAPU5a2oCz1UdtBJU0 Id45Iaj3al3hTx46LS6WqoPl+CmRxi+MfA3ptWIkB80QoYY4WBRb1xNOAqCheW87D9A8 ++N4sRGQp3EWgf5Gkp3eB9HH5HGdWBsGNBKSRDqjz7gtD5Mca3T7mTvtLIbHfs68Bsls tw8H4KTAbrW/5hPu2CxVzAzt+vf7duzSVajTjcwbqGKf9aDJWljsKFOJbYOqLv2oU+Ny radw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739375055; x=1739979855; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mwycz5Xhxtli1uhKd9D+bdo2NY7ikbIMbnIzjX1Fs40=; b=tPcUQthxOX0ku1XWNsGGGRVW6dvxQDEPiRis9uAtodP8AAkvTrcj7BjYK1fIpzVSWc p9fNzcfnTvqKohn5g/O2Ey/CHVT2apT3h+mmWSFtXxh/Yoov/3+MidEUhZT97hGIeCD6 eUTFPJOYaQo7jmh5cYWGL04PRGf8DT5XdDjVzNgUaPI/JjRzPa+0IrdOKnPlNMsWdC5M wyecz+psO0Pp5oYcn2NQ/76JzA+ToEUkTkcpTwXCqmmvsTr3Bz3POsHQAHySOe7b49VS rXuBGRm9qTI7ezPpfIYgDDwcLo7rLyupzYEehBm83DOTMeT3LQ8Jt0mcbm9Wki1yXh3A S8pQ== X-Gm-Message-State: AOJu0YwxYBykDwxhdniUzuzH2OTxWxOAs2uPWKsIH5uTyiac7VozepS0 ZlAHjswKZS1km8XB2WGk/F1CkZkKL65aAn0a4cBYUdrAQWQaArGC42Qc+18PgZ1ThiZvzpyza/a e+1k= X-Gm-Gg: ASbGnct4j5IgYza60zNd+zb65mx9ouQ9c/2TTRNHIq31NFGS7aJHtA6rDOnMif9bUES W/7KAjLCLGi7/SivkeROPKw6DO/6i/4WaLlwt6a166DtBMt9/aEV6TmQJSOYkEocYcIGdOjN2qI Q70StaQANEcFWLEFtWlRC1vL9D9wrPIWixcgPSGwZxtmZzRBO9RaNN4oH4SAA+WYn4Qn39vngvT try70ywKSAppghvQppLjfW5OlIubaXLgRt4qGLj7s4qdel61K7lFWHCoFE8VewNXX9sN9xNN3yG Q00bbfJwHxAYN/3YwXW/LJ5/+h0BNdkmvVzE+x9a2k/0i7nsSCsiUG4qTo5K4WQ8q7lk1GE= X-Received: by 2002:a05:600c:2d53:b0:439:5a37:8167 with SMTP id 5b1f17b1804b1-4395a37827fmr27759845e9.19.1739375055492; Wed, 12 Feb 2025 07:44:15 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4395a053c58sm23026455e9.13.2025.02.12.07.44.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 12 Feb 2025 07:44:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Rob Herring , Igor Mitsyanko , qemu-arm@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 8/8] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs Date: Wed, 12 Feb 2025 16:43:33 +0100 Message-ID: <20250212154333.28644-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250212154333.28644-1-philmd@linaro.org> References: <20250212154333.28644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Implicit default values are often hard to figure out, better be explicit. Now that all boards explicitly set the number of GIC external IRQs, remove the default values (displaying an error message if it is out of range). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/cpu/a15mpcore.c | 18 ++++++++++++------ hw/cpu/a9mpcore.c | 18 ++++++++++++------ 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index d24ab0a6ab2..676f65a0af4 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -58,6 +58,11 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) bool has_el2 = false; Object *cpuobj; + if (s->num_irq < 32 || s->num_irq > 256) { + error_setg(errp, "Property 'num-irq' must be between 32 and 256"); + return; + } + gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); @@ -146,13 +151,14 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) static const Property a15mp_priv_properties[] = { DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), - /* The Cortex-A15MP may have anything from 0 to 224 external interrupt - * IRQ lines (with another 32 internal). We default to 128+32, which - * is the number provided by the Cortex-A15MP test chip in the - * Versatile Express A15 development board. - * Other boards may differ and should set this property appropriately. + /* + * The Cortex-A15MP may have anything from 0 to 224 external interrupt + * lines, plus always 32 internal IRQs. This property sets the total + * of internal + external, so the valid range is from 32 to 256. + * The board model must set this to whatever the configuration + * used for the CPU on that board or SoC is. */ - DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), + DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 0), }; static void a15mp_priv_class_init(ObjectClass *klass, void *data) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 25416c5032b..1b9f2bef93c 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -56,6 +56,11 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) CPUState *cpu0; Object *cpuobj; + if (s->num_irq < 32 || s->num_irq > 256) { + error_setg(errp, "Property 'num-irq' must be between 32 and 256"); + return; + } + cpu0 = qemu_get_cpu(0); cpuobj = OBJECT(cpu0); if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) { @@ -160,13 +165,14 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) static const Property a9mp_priv_properties[] = { DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), - /* The Cortex-A9MP may have anything from 0 to 224 external interrupt - * IRQ lines (with another 32 internal). We default to 64+32, which - * is the number provided by the Cortex-A9MP test chip in the - * Realview PBX-A9 and Versatile Express A9 development boards. - * Other boards may differ and should set this property appropriately. + /* + * The Cortex-A9MP may have anything from 0 to 224 external interrupt + * lines, plus always 32 internal IRQs. This property sets the total + * of internal + external, so the valid range is from 32 to 256. + * The board model must set this to whatever the configuration + * used for the CPU on that board or SoC is. */ - DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), + DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 0), }; static void a9mp_priv_class_init(ObjectClass *klass, void *data)