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Wed, 19 Feb 2025 14:02:53 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250219140253eusmtrp1c0237ed2985c6b30ee5cdc9466f7ae31~loO2acM2c2416524165eusmtrp1Q; Wed, 19 Feb 2025 14:02:53 +0000 (GMT) X-AuditID: cbfec7f4-c39fa70000004fb9-ec-67b5e48d21d1 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 07.76.19920.D84E5B76; Wed, 19 Feb 2025 14:02:53 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250219140251eusmtip2b10afb40cdb62706fd5ad2842d00f208~loO1GcWVN0084500845eusmtip2i; Wed, 19 Feb 2025 14:02:51 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski , Krzysztof Kozlowski Subject: [PATCH v5 03/21] dt-bindings: firmware: thead,th1520: Add support for firmware node Date: Wed, 19 Feb 2025 15:02:21 +0100 Message-Id: <20250219140239.1378758-4-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250219140239.1378758-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUxTVxiHc+69vbfUFK6FyQlbQkTATB0C44/jdM4t4O4ShW0mMzHBrepd dYMivcXJZvhIy5eUTdRJrFU+JJaPUTb6IVSQCUhlOJCClBmoDnBSxobQ6gZOHOXi5n/POe9z fu95T44Ql1jJIOEhuZJVyKVJIaSIsHTO9b5WNG6WRRonNqEbjgoMmZ9oKfRdSw+GSjt6BMhp N2Fo4NE0iQz3b1FooiWbQINV5ymk6qwnkUvrJFHL72YKzWicAtRv1ZHIXdQBkMWtJlFdxwiF 6h+VYqh8xkygykYrQLkFlwSo76c4NOK8QSBXvwZHuVo/9Ky5kUILgz8Q6NyfrRQyTRULkK1u N1K3nia2BTPTQzkUM+VyEUx7vodiWh6XEUyTdoRiNE03AdNQU0Ayw4PNJHOh6wPmbqENY4yV mYy6rhNjvnkayUxfvU0yX5tqAGNXOaj3JXtEWw6wSYeOsIqNWz8RHcyfGCUO1wQetVc/w7NA pf9x4COEdAy8NFoMvCyhqwAsGMOOA9EiewAczRsA/MIN4JXJEez5iQnLRYov6AEszJldtqYA dI2dEngtko6G9/SlAm8hgM4hYM717CULp0sxWDt/Fvda/vReeH5YT3iZoMPgnXzVEovpt2B1 fxfJ9wuGrdd+XvSFQh96G7zaF8QrK2HX2fElHV9UVOZzuDcf0mYRXOj+kfD6kI6Fxmtr+Bh/ OGkzUTy/ArtPaQieU+A98yzO8zHYpLEt82Y43DNPemNw+lVYb93Ib78Nu/RTy+m+cOiPlfwN fOFJSwnOb4thfq6Et8Pht5qi/5r2VFmW35CB1vIS4gRYrX1hFu0Ls2j/71sG8BoQyKZxyTKW i5azX0Rw0mQuTS6L2J+S3AAWv3f3gs3TCPSTMxFtABOCNgCFeEiAODfTJJOID0jTv2QVKR8r 0pJYrg28LCRCAsUVrTkyCS2TKtnPWfYwq3hexYQ+QVlY/YORUFQRadE5QtV/Ky+knVgROmeV Ns/tCnqvVu2RxoW/kep46K882eDzPdPv/sxp5/bm7fPJY2uNVnHG6cfFhrCCieu+s8PgyJhH +vo49asuyRPDNd3/aOquLn5LrMHQsr28b6E0eE/XpsqtqRtekicMUO+U7AyXs5tXpK4v0+17 uOaXW1zWb+lqv6iIMDtLCUi7X9vlgL82ZHz65JjK3rw+L+aMa21KQOjQTfrDwvaShDtPrzx4 M9UQJVpl7FW8206vk1dq/ZVNhpnL6fFrq+2ZcQs7YjO6ezoHHL417gQ1p9/5z+74VWeMRYm3 9/cenU8zfRWaHT2YuH11+zCxIzGE4A5Ko9bhCk76L9xBYBtNBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUwTdxjH87u73l01yNmi3OoStur+WWahvP5YkJEssktWki06CGxOGz0K jlJzbYkSDW7UroVacDMjXBVwVKaNaBSKFSwMRLC+gFCHo5HWOVxoZ4YIGMm2skKzxP+ePJ/P 8/LHl0RFDoGELC3XsVy5skyKr8HuhIf9W49PO1VJ9YNx8NbDHxHo/Jsn4AX3CAKbB0cE0D/e icAHi7M4vPj0PgFn3F9jcOLcaQJWD13CYZD349D9p5OAcxa/AHq7T+Fw/vgggF3zBhy2D04R 8NJiMwLPzDkxaHd1A2g0twng2O3tcMp/C4NBrwWFRj4WLl93ETA8cRmDtr/6CNj57IQADrcX QEPfSSwngZn99RjBPAsGMeaGaYFg3C9bMOYaP0Uwlmt3AXPFYcaZRxPXcabJ8ykTqB1GmA57 FWNoH0KYun+TmNneX3DG2ukAzHj1Q+ITUZEsi9PodexbJRqtbpv0czlMlskzoSw5NVMmT8nY 9X5ymjQxO2sfW1ZawXKJ2XtkJaaZJ9gBR/zB8fPL6FFgF9cAIUlTqfRMVytRA9aQIuosoE1W KxoFb9ITtUEsWovpfyZq8KgUAvRTY5tgBeBUMv34p+bVOo5qxWh376EVCaXOIvST5Z/xFSCm vqBrTZZVCaPeoX2m6tWtMdQH9HmvB49eSKD7+u9FLpOkkMqhe8ckK21RRBmxBgRRfT3taZxe HUUjerXThtYDin8N8a+hFoA4QByr16pVaq1cplWqtfpylWyvRn0FRELTNbTU4QJNoTnZAEBI MABoEpXGxRirOlWimH3KQ5Usp9nN6ctY7QBIi7x9ApVs2KuJpK5ct1uenpQmT03PTErLTE+R xsfkekeLRZRKqWO/YtkDLPf/HEIKJUcRkIufPilVB9ZOZnP3vhcezLFnGYt31KTG5m4cPbwQ Fj8QxH5IWoNzChf9eIs/mK/Lw3f+3jFpqj+X/94ZxZGK58X8R8degUa48F2xz7K+4dvJHWX2 utthX1eCmEtpp/JKf+hYuC8MLnkUr/gNoYqrlacSfaJtDYXmeKteodgk6f4y11F09076i7qd Hz/aL3f1b33e4zWGQoU3RWut3vpwv7Jte+umaXNG403+8sseR5Ws7+3Ghjc83NLhxT12yR8X s22B4YKeShKG8r/ZWLCuJS8UP780GvjM15ShQgqdF4K7XvSPFYlv2PJ+22yw7d9sazPbUsJ1 M4arR/h1W6SYtkQpfxfltMr/AAD2YAy9AwAA X-CMS-MailID: 20250219140253eucas1p2a137df988b89e84b7e52c45521b5bb06 X-Msg-Generator: CA X-RootMTR: 20250219140253eucas1p2a137df988b89e84b7e52c45521b5bb06 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250219140253eucas1p2a137df988b89e84b7e52c45521b5bb06 References: <20250219140239.1378758-1-m.wilczynski@samsung.com> The kernel communicates with the E902 core through the mailbox transport using AON firmware protocol. Add dt-bindings to document it the dt node. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Michal Wilczynski --- .../bindings/firmware/thead,th1520-aon.yaml | 53 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml diff --git a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml new file mode 100644 index 000000000000..bbc183200400 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/thead,th1520-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 AON (Always-On) Firmware + +description: | + The Always-On (AON) subsystem in the TH1520 SoC is responsible for managing + low-power states, system wakeup events, and power management tasks. It is + designed to operate independently in a dedicated power domain, allowing it to + remain functional even during the SoC's deep sleep states. + + At the heart of the AON subsystem is the E902, a low-power core that executes + firmware responsible for coordinating tasks such as power domain control, + clock management, and system wakeup signaling. Communication between the main + SoC and the AON subsystem is handled through a mailbox interface, which + enables message-based interactions with the AON firmware. + +maintainers: + - Michal Wilczynski + +properties: + compatible: + const: thead,th1520-aon + + mboxes: + maxItems: 1 + + mbox-names: + items: + - const: aon + + "#power-domain-cells": + const: 1 + +required: + - compatible + - mboxes + - mbox-names + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + aon: aon { + compatible = "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + #power-domain-cells = <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index efee40ea589f..0934f9791fe9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20413,6 +20413,7 @@ L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/pdp7/linux.git F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +F: Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml From patchwork Wed Feb 19 14:02:23 2025 Content-Type: text/plain; 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Wed, 19 Feb 2025 14:02:56 +0000 (GMT) X-AuditID: cbfec7f2-b09c370000005155-27-67b5e49043ac Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id FD.42.19654.F84E5B76; Wed, 19 Feb 2025 14:02:55 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250219140254eusmtip2d7608f91caeda22a5cb42989a93fdceb~loO3ipXEQ0084200842eusmtip2-; Wed, 19 Feb 2025 14:02:54 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski , Krzysztof Kozlowski Subject: [PATCH v5 05/21] dt-bindings: power: Add TH1520 SoC power domains Date: Wed, 19 Feb 2025 15:02:23 +0100 Message-Id: <20250219140239.1378758-6-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250219140239.1378758-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xbZRjG851zek7pUjwUtJ+IImQa8QKDzezTLXMzM5xoNLIo7GI2yziU OW5pYdONZCCXsNlyEYHQjpUhAkMqjLaMItBQGN24dKwwboGOJaAWC8hlkGFkUg7T/fe8z/t7 v+d9k4+Pi5pJb/6p+CRWFi+J9ScFRGPXI+tbeVMG6Y6qtJ3o1nA5hgx/qyhU22rFkKbTykN2 mx5Dgw/nSfTLdD+F/mhNI9BQdSmF0rvqSORQ2UnU+qeBQgsKOw8NNF8m0ZKyE6DGpQwSaTsn KFT3UIOhqwsGAlU0NQOUdbGSh+52f4Am7LcI5BhQ4ChL9Qx63NJEofWh6wRSz5kopHfm85BF G4EyTD8Q+32Z+ZFMinE6HATTkb1MMa0rZQRjVE1QjMLYC5iGmoskMz7UQjJXbocx97+zYIyu 4gKToe3CmNx/djDzbfdIJkdfAxhb+jD1qeioYG8UG3vqDCsL2velIObBHS2emCv8eqqyg5cK lNsuATc+pHfBmWktz6VFdDWA1vpPLgHBhl4G0Dg6TnLFEoBjTUrekwlzbiaPa1QB2DZ3A+MK J4BKnYZwUSQdAierNJuUF51JwMybacBV4LQGgz+vleAuypP+ENYXLWyE8PkE/QpMtX/msoX0 e3Dsuo3k4nyhqb0PdyFu9H7YdtebQzzg7ZKpzSx8A0k3qHHX85A2CGDZb9UYN3sQ9q4uE5z2 hDMWPcVpH9hToNjyE+CkYRHndAo0Kixbeg8ct65trobTAbCuOYizD0C9vgJz2ZB2hyOzHtwK 7vD7xmKcs4UwO0vE0a/CQoXyv1BrdePWYgzs+vEvKg/4qZ46RvXUMar/c8sAXgPEbLI8TsrK g+PZs4FySZw8OV4aeDIhrgFsfO+edctiEyidWQg0A4wPzADycX8vYdYFvVQkjJJ8c46VJZyQ JceycjN4gU/4i4XlpkypiJZKktjTLJvIyp50Mb6bdyoWVzSuTzky5f521/v31N268KoSz549 oSMBE1fP8gcLj8vsN31GCTY/O++LMKG6+Kcj3h1R6oCcE6H1fSFJ0p2S06n+EaaU59NyS60H dnsxv88enzfXoL4IZ/i7hwJ0sb0DeQvzh7Gcus9PVr7p0T7uaxoY9CsperklerWm9qtcpRqX NNjmkinxUtO1j6thaeSd84/P8HwmW4rfGKuLodsDQq/FTHhM/1pVb1mL3Lt+LJp4tr/Sy3Ys 2vmROiZ8X35UgTHxxm7N5ZfI1945rF4dzT86K8gP1uGTz6k1D17cbhUfDBoWT0UWfLsSlr1t pbaw22EOXnTeLw85n/DonN+uQ9H9/oQ8RhL8Oi6TS/4Fum8SVk0EAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA02Sa0yTdxjF895bZ8NrqfEdM8N1WWLYVmml7N8NmB82/Qc/6LLJtMZBg6/F UVrTljEWhizc5I6Jl1A6YBs4ZBQntqygLVIIlDnpCqxVBsUh6KpVVgUTN2fX2izx28k5vyfP +XA4GP8sEcc5rNazWrVCJSTX4FeejvnebFi0KBPnK2XA6f0WBZZ/DBTotk2goHVkggC+STMK pleXSdCz9CsF/rR9hQNP59cUKB09RwK/wUcC210LBYK1PgJMDRhJ8LBuBAF9D8tIYBqZo8C5 1VYUfBO04KDdOoCAiqozBHD//D6Y8zlx4J+qxUCFIQaELlkp8NRzHgfN9wcpYA4cJ8CY6WNQ NngC3xYPl6+VUzDg9+Nw+NgKBW2P2nDYb5ijYG3/Lwjs7aoi4aznEglbxj+A8zVjKLzQfhSW mUZR2PBvIly2/0bCenMXAidLvdRuvlyUotXk69lNORqdPlW4XwwkIrEMiCRJMpF461sH3pZI hVvSUg6yqsOfsdotaVminD9cJuxIA+/zxTPDRAlS90I1wuUwdBLjaCgnqpE1HD7dgTCPLyyg 0WAj46nx41EdyzzxVJNR6A7CtF259wwiaQlz4/tWIqIF9Hc4Y7MXRiCM7kCZhdBlMhLE0unM j6eCYc3h4PRrTInvo4jNo99lZs5PktEH8czg0FUsgnDpbYzdHRex+WFkon6eiOLrmPGmxWd9 sDBeamnGGhHa8FxkeC5qQ9AuRMDm6/KUeTqJSKfI0+WrlaJsTV4vEt5M3+hjsxU5eycociAo B3EgDAcTCngVR81KPu+govALVqvJ1OarWJ0DkYZbH8fi1mdrwqNT6zPFyYlScVKyLFEqS94q 3MAjp12H+LRSoWdzWfYIq/3/DuVw40pQY0fRrsr4pr6/lqyZt4pj0gqOVRXQn9ze2d/JQ1+/ VoxImgKpN3JPje1qGlVu31zz3ofrGh0bG4uvE9y9LZtjH1DdK6f3da/OFlt6jLl/O6+adR0L Xt9w8zvTuhzNUtlPLeqbih1yuSEpI+PBgdudKcv7NgX0MXpniBdq2a5qPOTmmlwJRX3398hP qgp4P2hk9nQoBnuN7nuK38dfVmYNtrfPCFQJk1jGi9WXZy6yt3xZzsonZij31qdPDRXdrYJD n+54CXnldDbRuz7Qj7YWupfqgvtny1c2vFG5+6Zg7cUQrPGuTR1IfmR0vTqFyifsvda56z1f KoIn9rjE0pNCXJejECdgWp3iP9GWR4W8AwAA X-CMS-MailID: 20250219140256eucas1p13aa7f19867f88185739552f116ef0fc1 X-Msg-Generator: CA X-RootMTR: 20250219140256eucas1p13aa7f19867f88185739552f116ef0fc1 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250219140256eucas1p13aa7f19867f88185739552f116ef0fc1 References: <20250219140239.1378758-1-m.wilczynski@samsung.com> Add power domain ID's for the TH1520 SoC power domains. Acked-by: Krzysztof Kozlowski Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + .../dt-bindings/power/thead,th1520-power.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 include/dt-bindings/power/thead,th1520-power.h diff --git a/MAINTAINERS b/MAINTAINERS index 3ee5a2f6cdee..781129d60349 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20424,6 +20424,7 @@ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h +F: include/dt-bindings/power/thead,th1520-power.h F: include/linux/firmware/thead/thead,th1520-aon.h RNBD BLOCK DRIVERS diff --git a/include/dt-bindings/power/thead,th1520-power.h b/include/dt-bindings/power/thead,th1520-power.h new file mode 100644 index 000000000000..8395bd1459f3 --- /dev/null +++ b/include/dt-bindings/power/thead,th1520-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#ifndef __DT_BINDINGS_POWER_TH1520_H +#define __DT_BINDINGS_POWER_TH1520_H + +#define TH1520_AUDIO_PD 0 +#define TH1520_VDEC_PD 1 +#define TH1520_NPU_PD 2 +#define TH1520_VENC_PD 3 +#define TH1520_GPU_PD 4 +#define TH1520_DSP0_PD 5 +#define TH1520_DSP1_PD 6 + +#endif From patchwork Wed Feb 19 14:02:24 2025 Content-Type: text/plain; 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Wed, 19 Feb 2025 14:02:57 +0000 (GMT) X-AuditID: cbfec7f2-b11c470000005155-2a-67b5e49136fa Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 40.52.19654.194E5B76; Wed, 19 Feb 2025 14:02:57 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250219140255eusmtip21763dbe52d985cb0683de8ae532326a7~loO4x4nTP0084500845eusmtip2j; Wed, 19 Feb 2025 14:02:55 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [PATCH v5 06/21] pmdomain: thead: Add power-domain driver for TH1520 Date: Wed, 19 Feb 2025 15:02:24 +0100 Message-Id: <20250219140239.1378758-7-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250219140239.1378758-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01SfUxTVxzdfe/1vVJXfVQcV1AnJGpkswLZkpvgBhtze4s6cG5xcV8WfClk BUxr/WAbrUKrsoKAELfyDZ10OARZy1o+Q0WKwHB8WCGhyAyEFWFdQcw2B5v04eZ/5/c759xz fsnl4yIzGcBPTD7GypMlsmBSQDR0/nlrR+6EWRr6e92LqOtOBYbMj/QU+r6lD0OlHX08NDZg wtDQgptEVyd/ptCvLacJ5DAWUyi9s5ZELv0YiTy6MR4abCwi0XxWB0AN8xkkqulwUqh2oRRD 5R4zgQyWRoC05y/zUH/3buQc6yKQa1CHI61+Dfqn2UKhJcc1AhX+1kYh00wuD9lrDqKMtnwi ahPjHtZQzIzLRTDXzz2gmJaHZQRj1TspRmftBUx99XmSGXU0k0zJzf3M3a/sGPODQcVk1HRi zIXFUMbdeptksk3VgBlIv0PFig4Jdh1hZYnHWfnOVw8LEromHmJHv37n5Oy0iVSDuahM4MOH 9Etwqs4JMoGAL6KNAJY5XBQ3PAAwZ/w6jxvmAfxx0ch7Yrl634FzRBWAlWeziGVCRM8AWNMb uYxJOhyOV5V63X60hoCaG6e9ITg9BWDDRBGZCfj8tXQMdGeJlw0EvQWqhzK8CUI6EjpHnRSX 9jxsa/8JX5b70FGwtT+Ak/jCm99MeHPxx5J0c6G3EKRrBNCY58Y47xvQ0J1PcngtnLabVt7c AHsu6ggOp8Bx8xzO4S+gVWdfwRFwtO8vb02c3g5rG3dy69dgwY3viOU1pFfD4VlfrsJqmNdw CefWQnhOK+LUW2GBLuu/0D5jw0oxBmo8s2QOCNI/dYz+qWP0/+eWAbwa+LNKRZKUVYQlsyfE CkmSQpksFcenJNWDxz+7Z8k+ZwHF0x6xDWB8YAOQjwf7CbUqk1QkPCI5lcrKUz6VK2WswgYC +USwv7CiTSMV0VLJMfYzlj3Kyp+wGN8nQI19ImNsBepf8m9Hll88nmp5BYZnazUj4sRLdufl z4tmt62PN9DuNSeG4zDf7HcJ4fvt2hL7NWvamZC7b9la5QkVwRtfeLbprGFvyZ79B6Y23l9U xgVtCX/5ilz4cVp8uqdpe3RTRFhWzIDz2/f0m+MGXbrovblvFpVjCs2p6l2+tbHO3R8E3lqa bFl/crPm3pf+ysqteYc3xDxStfckGc80F6cWrVt8XR16r3zBP/rvTcnP7RksC3tmX0v/ZBjq 7h2yBn0YolvlkFn7u9PqwbaR2E73juzsGd0ByravtfJQ/6LB7wLmX95ZVVin0qtz0Kq4j9ZZ ct5OMh2MwTwhESOqPwKvBBOKBElYCC5XSP4FFw6zbkgEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCKsWRmVeSWpSXmKPExsVy+t/xe7oTn2xNN/j3jM/ixPVFTBZbf89i t1iz9xyTxfwj51gt7l3awmRx5et7Not1Ty+wW7zY28hicW3FXHaL5mPr2SxezrrHZvGx5x6r xeVdc9gsPvceYbTY9rmFzWLtkbvsFuu/zmeyWPhxK4vFkh27GC3aOpexWlw85Wpx994JFouX l3uYLdpm8Vv837OD3eLftY0sFrPf7We32PJmIqvF8bXhFi37p7A4yHm8v9HK7vHm5UsWj8Md X9g99n5bwOKxc9Zddo+enWcYPTat6mTzuHNtD5vHvJOBHve7jzN5bF5S79Gy9hiTR/9fA4/3 +66yefRtWcXocan5OnuAUJSeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJpZ6hsXmslZGpkr6d TUpqTmZZapG+XYJexokn35gKZvhVvH21ha2B8ZNDFyMnh4SAicS619eYQWwhgaWMEjNa0iHi MhLXul+yQNjCEn+udbF1MXIB1bxilLjy6xNYA5uAkcSD5fNZQWwRgcUsEnv3VYIUMQu8ZZS4 PnMjWLewgK/EhtcH2UFsFgFViYYrLWANvAL2Enfv3GWH2CAvsf/gWaChHBycAg4S+y5KQRxk L3Gu7z5UuaDEyZlPwEYyA5U3b53NPIFRYBaS1CwkqQWMTKsYRVJLi3PTc4uN9IoTc4tL89L1 kvNzNzECk8u2Yz+37GBc+eqj3iFGJg7GQ4wSHMxKIrxt9VvShXhTEiurUovy44tKc1KLDzGa Ap09kVlKNDkfmN7ySuINzQxMDU3MLA1MLc2MlcR52a6cTxMSSE8sSc1OTS1ILYLpY+LglGpg WrOyrnprqdzaZx/XNK7mjxHesqBQ2kDRtUayV5pH7I4v11vj50USnbc/rrTSvdL4aPbJnpUK h+Wjv1v65pl1Wiz1UW+eYBF9T2TnftGA3tKdRzcGHitv+zf5sHVXUs1Dp/vnz3XVbK2RS5ip wB60auOmRw5izx9duWlhvX7i3VNqJzzyQuI+TlP2yRWJzHvL0xCaJz1rb4xWwvSH+kcd/BxY L7MxR33t2H0qb/8h5wvTnXfueXE2/pyhdt3JGWm2Dkk5OzT7193dGsfrKMWQZi2kO3H7U4+p fuFcz9NfL5zS1Fx4/tX/pywJ3w7Z9Gz7pc16xsv94ub8e77y73QY/s6dEFtQVZF6TPVEdG6j EktxRqKhFnNRcSIASdnUdrcDAAA= X-CMS-MailID: 20250219140257eucas1p1cc06395993336a6244f6ae0ce2923d71 X-Msg-Generator: CA X-RootMTR: 20250219140257eucas1p1cc06395993336a6244f6ae0ce2923d71 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250219140257eucas1p1cc06395993336a6244f6ae0ce2923d71 References: <20250219140239.1378758-1-m.wilczynski@samsung.com> The T-Head TH1520 SoC contains multiple power islands that can be programmatically turned on and off using the AON (Always-On) protocol and a hardware mailbox [1]. The relevant mailbox driver has already been merged into the mainline kernel in commit 5d4d263e1c6b ("mailbox: Introduce support for T-head TH1520 Mailbox driver"); Introduce a power-domain driver for the TH1520 SoC, which is using AON firmware protocol to communicate with E902 core through the hardware mailbox. This way it can send power on/off commands to the E902 core. The interaction with AUDIO power island e.g trying to turn it OFF proved to crash the firmware running on the E902 core. Introduce the workaround to disable interacting with the power island. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/Makefile | 1 + drivers/pmdomain/thead/Kconfig | 12 ++ drivers/pmdomain/thead/Makefile | 2 + drivers/pmdomain/thead/th1520-pm-domains.c | 209 +++++++++++++++++++++ 6 files changed, 226 insertions(+) create mode 100644 drivers/pmdomain/thead/Kconfig create mode 100644 drivers/pmdomain/thead/Makefile create mode 100644 drivers/pmdomain/thead/th1520-pm-domains.c diff --git a/MAINTAINERS b/MAINTAINERS index 781129d60349..18f0eb293519 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20423,6 +20423,7 @@ F: drivers/firmware/thead,th1520-aon.c F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c +F: drivers/pmdomain/thead/ F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/power/thead,th1520-power.h F: include/linux/firmware/thead/thead,th1520-aon.h diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 23c64851a5b0..91f04ace35d4 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -16,6 +16,7 @@ source "drivers/pmdomain/st/Kconfig" source "drivers/pmdomain/starfive/Kconfig" source "drivers/pmdomain/sunxi/Kconfig" source "drivers/pmdomain/tegra/Kconfig" +source "drivers/pmdomain/thead/Kconfig" source "drivers/pmdomain/ti/Kconfig" source "drivers/pmdomain/xilinx/Kconfig" diff --git a/drivers/pmdomain/Makefile b/drivers/pmdomain/Makefile index a68ece2f4c68..7030f44a49df 100644 --- a/drivers/pmdomain/Makefile +++ b/drivers/pmdomain/Makefile @@ -14,6 +14,7 @@ obj-y += st/ obj-y += starfive/ obj-y += sunxi/ obj-y += tegra/ +obj-y += thead/ obj-y += ti/ obj-y += xilinx/ obj-y += core.o governor.o diff --git a/drivers/pmdomain/thead/Kconfig b/drivers/pmdomain/thead/Kconfig new file mode 100644 index 000000000000..c7a1ac0c61dc --- /dev/null +++ b/drivers/pmdomain/thead/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config TH1520_PM_DOMAINS + tristate "Support TH1520 Power Domains" + depends on TH1520_AON_PROTOCOL || !TH1520_AON_PROTOCOL + select REGMAP_MMIO + help + This driver enables power domain management for the T-HEAD + TH-1520 SoC. On this SoC there are number of power domains, + which can be managed independently. For example GPU, NPU, + and DPU reside in their own power domains which can be + turned on/off. diff --git a/drivers/pmdomain/thead/Makefile b/drivers/pmdomain/thead/Makefile new file mode 100644 index 000000000000..adfdf5479c68 --- /dev/null +++ b/drivers/pmdomain/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_TH1520_PM_DOMAINS) += th1520-pm-domains.o diff --git a/drivers/pmdomain/thead/th1520-pm-domains.c b/drivers/pmdomain/thead/th1520-pm-domains.c new file mode 100644 index 000000000000..7c78cf3955d2 --- /dev/null +++ b/drivers/pmdomain/thead/th1520-pm-domains.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include + +#include + +struct th1520_power_domain { + struct th1520_aon_chan *aon_chan; + struct generic_pm_domain genpd; + u32 rsrc; +}; + +struct th1520_power_info { + const char *name; + u32 rsrc; + bool disabled; +}; + +/* + * The AUDIO power domain is marked as disabled to prevent the driver from + * managing its power state. Direct AON firmware calls to control this power + * island trigger a firmware bug causing system instability. Until this + * firmware issue is resolved, the AUDIO power domain must remain disabled + * to avoid crashes. + */ +static const struct th1520_power_info th1520_pd_ranges[] = { + [TH1520_AUDIO_PD] = {"audio", TH1520_AON_AUDIO_PD, true }, + [TH1520_VDEC_PD] = { "vdec", TH1520_AON_VDEC_PD, false }, + [TH1520_NPU_PD] = { "npu", TH1520_AON_NPU_PD, false }, + [TH1520_VENC_PD] = { "venc", TH1520_AON_VENC_PD, false }, + [TH1520_GPU_PD] = { "gpu", TH1520_AON_GPU_PD, false }, + [TH1520_DSP0_PD] = { "dsp0", TH1520_AON_DSP0_PD, false }, + [TH1520_DSP1_PD] = { "dsp1", TH1520_AON_DSP1_PD, false } +}; + +static inline struct th1520_power_domain * +to_th1520_power_domain(struct generic_pm_domain *genpd) +{ + return container_of(genpd, struct th1520_power_domain, genpd); +} + +static int th1520_pd_power_on(struct generic_pm_domain *domain) +{ + struct th1520_power_domain *pd = to_th1520_power_domain(domain); + + return th1520_aon_power_update(pd->aon_chan, pd->rsrc, true); +} + +static int th1520_pd_power_off(struct generic_pm_domain *domain) +{ + struct th1520_power_domain *pd = to_th1520_power_domain(domain); + + return th1520_aon_power_update(pd->aon_chan, pd->rsrc, false); +} + +static struct generic_pm_domain *th1520_pd_xlate(const struct of_phandle_args *spec, + void *data) +{ + struct generic_pm_domain *domain = ERR_PTR(-ENOENT); + struct genpd_onecell_data *pd_data = data; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(th1520_pd_ranges); i++) { + struct th1520_power_domain *pd; + + if (th1520_pd_ranges[i].disabled) + continue; + + pd = to_th1520_power_domain(pd_data->domains[i]); + if (pd->rsrc == spec->args[0]) { + domain = &pd->genpd; + break; + } + } + + return domain; +} + +static struct th1520_power_domain * +th1520_add_pm_domain(struct device *dev, const struct th1520_power_info *pi) +{ + struct th1520_power_domain *pd; + int ret; + + pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); + if (!pd) + return ERR_PTR(-ENOMEM); + + pd->rsrc = pi->rsrc; + pd->genpd.power_on = th1520_pd_power_on; + pd->genpd.power_off = th1520_pd_power_off; + pd->genpd.name = pi->name; + + ret = pm_genpd_init(&pd->genpd, NULL, true); + if (ret) + return ERR_PTR(ret); + + return pd; +} + +static void th1520_pd_init_all_off(struct generic_pm_domain **domains, + struct device *dev) +{ + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(th1520_pd_ranges); i++) { + struct th1520_power_domain *pd; + + if (th1520_pd_ranges[i].disabled) + continue; + + pd = to_th1520_power_domain(domains[i]); + + ret = th1520_aon_power_update(pd->aon_chan, pd->rsrc, false); + if (ret) + dev_err(dev, + "Failed to initially power down power domain %s\n", + pd->genpd.name); + } +} + +static int th1520_pd_probe(struct platform_device *pdev) +{ + struct generic_pm_domain **domains; + struct genpd_onecell_data *pd_data; + struct th1520_aon_chan *aon_chan; + struct device *dev = &pdev->dev; + int i; + + aon_chan = th1520_aon_init(dev); + if (IS_ERR(aon_chan)) + return dev_err_probe(dev, PTR_ERR(aon_chan), + "Failed to get AON channel\n"); + + platform_set_drvdata(pdev, aon_chan); + + domains = devm_kcalloc(dev, ARRAY_SIZE(th1520_pd_ranges), + sizeof(*domains), GFP_KERNEL); + if (!domains) + return -ENOMEM; + + pd_data = devm_kzalloc(dev, sizeof(*pd_data), GFP_KERNEL); + if (!pd_data) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(th1520_pd_ranges); i++) { + struct th1520_power_domain *pd; + + if (th1520_pd_ranges[i].disabled) + continue; + + pd = th1520_add_pm_domain(dev, &th1520_pd_ranges[i]); + if (IS_ERR(pd)) + return PTR_ERR(pd); + + pd->aon_chan = aon_chan; + domains[i] = &pd->genpd; + dev_dbg(dev, "added power domain %s\n", pd->genpd.name); + } + + pd_data->domains = domains; + pd_data->num_domains = ARRAY_SIZE(th1520_pd_ranges); + pd_data->xlate = th1520_pd_xlate; + + /* + * Initialize all power domains to off to ensure they start in a + * low-power state. This allows device drivers to manage power + * domains by turning them on or off as needed. + */ + th1520_pd_init_all_off(domains, dev); + + return of_genpd_add_provider_onecell(dev->of_node, pd_data); +} + +static void th1520_pd_remove(struct platform_device *pdev) +{ + struct th1520_aon_chan *aon_chan = platform_get_drvdata(pdev); + + th1520_aon_deinit(aon_chan); +} + +static const struct of_device_id th1520_pd_match[] = { + { .compatible = "thead,th1520-aon" }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, th1520_pd_match); + +static struct platform_driver th1520_pd_driver = { + .driver = { + .name = "th1520-pd", + .of_match_table = th1520_pd_match, + }, + .probe = th1520_pd_probe, + .remove = th1520_pd_remove, +}; +module_platform_driver(th1520_pd_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 SoC power domain controller"); +MODULE_LICENSE("GPL"); From patchwork Wed Feb 19 14:02:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 867036 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A558D1F419B for ; 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Wed, 19 Feb 2025 14:02:58 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [PATCH v5 08/21] clk: thead: Add support for custom ops in CCU_GATE_CLK_OPS macro Date: Wed, 19 Feb 2025 15:02:26 +0100 Message-Id: <20250219140239.1378758-9-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250219140239.1378758-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUxTZxTG9957e++lUnapbrxjbsw652YUlBnzJuLGhpobTczmxpwGNxu5 KwQorIUx9yEySgesOGpYDAWsIJOCQwTaDojAqEjBj1ootLBINQIRGNgVcB9MZZSLm/895znP eX/nJC+Ni38mg+l4eSqnkEsTJaSQMHf+fWND4YhJtrHk0quoy1WOIdM/Ogr91GLDkL7DJkDu XiOG+u57SHR+1E6hsZZMAjkNpRTK6qwl0bjOTSKvxi1AjuYSEs3kdwBknlGRqKZjiEK19/UY KvOaCFTR2AyQOvesAPVc2YGG3F0EGndocKTWPY3mLzZS6JGzjkDF99ooZJzUCpC1Zh9StRUS kS+ynoFsip0cHyfYSzmzFNvyx2mCbdINUaym6Rpg66tzSfam8yLJnup+l731nRVjGyoyWFVN J8Z+/3Aj62ntJ9njxmrA9ma5qHfEB4QRsVxi/GecIuyNQ8K49mvn8BTDM5+fdZYTx0BtYB7w oyGzGerOd4E8IKTFjAFA71Q5xhezAPZmVuB8MQOgWa/FH49Yvh0m+EYlgO0FgyRfTAL4V9YZ ypcimXB4u1Iv8DVWMNkEzL6cuUjBmbsLb42UkL7UciYGthSfEPg0wayBD0o7Fxki5k2o0cwS PC8EtrVfX/Bp2o+JhK09wXwkEHYXjSxG8IVIlql4cVfI1Ahha0mOgJ/dDvuqbEt6OZywGile r4TzTXqM18nwtml66bavYJPGuqS3wpu2OdLHxZnXYG1zGG+/BfsLVZTPhkwAHJgK5FcIgCfM J3HeFsEctZhPvwJ/0OT/B7UZzEtQFk7bZ0ABWKV74hjdE8fo/ueeBng1COLSlEkyThku59JD ldIkZZpcFno4OakeLPztq4+ss42gcsIbagEYDSwA0rhkhUidYZSJRbHSI19wiuSPFWmJnNIC nqcJSZCovC1bJmZk0lQugeNSOMXjLkb7BR/Dtv2y8pzKP6p2T9KvyoPzr8MYuomNJprFL6e4 PNvlBOY+Om2fWy9yumIDUmTH2+uetZ254d3vqBrw7i4WvvR72eE7e2PVu4rcssjLWMP+qGWl Bd096FPWo3WxE/FHlY5N69Jz66+uNtjVU2tvBSXYD/oHYWkfBT+Mjtnz9ftHDuSL74Q/8EoD hgfnVIaIZek7T2nT6xyOntX6LfOHtE+N3k19TzC8LxPFjXWGvdDnGYyS926I/2DrljHOFR0x GRI3bln1YULRbw2jxcyP5t3X+6/s3UFsu5D1tvxCf0jqTrEt916ENS/Zv7ynak2e67mRwoFP /lzbJUnLiF6/mSub/KbsSwmhjJNuWocrlNJ/Aa/eXvlKBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xe7pTnmxNN/i5jNPixPVFTBZbf89i t1iz9xyTxfwj51gt7l3awmRx5et7Not1Ty+wW7zY28hicW3FXHaL5mPr2SxezrrHZvGx5x6r xeVdc9gsPvceYbTY9rmFzWLtkbvsFuu/zmeyWPhxK4vFkh27GC3aOpexWlw85Wpx994JFouX l3uYLdpm8Vv837OD3eLftY0sFrPf7We32PJmIqvF8bXhFi37p7A4yHm8v9HK7vHm5UsWj8Md X9g99n5bwOKxc9Zddo+enWcYPTat6mTzuHNtD5vHvJOBHve7jzN5bF5S79Gy9hiTR/9fA4/3 +66yefRtWcXocan5OnuAUJSeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJpZ6hsXmslZGpkr6d TUpqTmZZapG+XYJexsEzq5kLVohWLLu2iKWBcb1gFyMnh4SAicSh9scsXYxcHEICSxklHu14 zwSRkJG41v2SBcIWlvhzrYsNougVo8S0vxfAitgEjCQeLJ/PCmKLCCxmkdi7rxKkiFngLaPE 9ZkbwbqFBaIkGt59YwSxWQRUJf7MPcYMYvMK2Ev09HyB2iAvsf/gWaA4BwengIPEvotSIGEh oJJzffdZIcoFJU7OfAJWzgxU3rx1NvMERoFZSFKzkKQWMDKtYhRJLS3OTc8tNtIrTswtLs1L 10vOz93ECEwv24793LKDceWrj3qHGJk4GA8xSnAwK4nwttVvSRfiTUmsrEotyo8vKs1JLT7E aAp09kRmKdHkfGCCyyuJNzQzMDU0MbM0MLU0M1YS52W7cj5NSCA9sSQ1OzW1ILUIpo+Jg1Oq gWktt+52j0Nuk3RETWtzJtwTNzohnOHu8POyArMb4yl+sTdWh1oLa1dcnLK89OGKposPNvGm 3Pu3PCB4VW+b/9zdX877b1ympXvtc9Myk+W6krG5CbOtNY30dmf2nkkuPf30AOf6gF/nn/75 XCHQmSl8PDPaWHLn9CdOR4+dCVp2abrYejkZFcuynunu25t6V+7oW7Kq/nX3ynSrhZn1R9oi eAtia2yON+u/kNUKLr20r+b5oa2JC2ZJ3OTi2Jr5KMU+LbLfwepH3BnbPZf369i6/p3vtLNg gz4j50eFKUli3nqquq93/m3fu/i07Ot7Lf7O0uazFyY4z7xYqPDA0mf/NBPW4KysmKDonh3p 1kosxRmJhlrMRcWJACbtxqC4AwAA X-CMS-MailID: 20250219140300eucas1p2d776e747555020fd868cf04e55cd70e1 X-Msg-Generator: CA X-RootMTR: 20250219140300eucas1p2d776e747555020fd868cf04e55cd70e1 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250219140300eucas1p2d776e747555020fd868cf04e55cd70e1 References: <20250219140239.1378758-1-m.wilczynski@samsung.com> The IMG Rogue GPU requires three clocks: core, sys, and mem [1]. On the T-HEAD TH1520 SoC, the mem clock gate is marked as "Reserved" in the hardware manual (section 4.4.2.6.1) [2] and cannot be configured. Add a new CCU_GATE_CLK_OPS macro that allows specifying custom clock operations. This enables us to use nop operations for the mem clock, preventing the driver from attempting to enable/disable this reserved clock gate. Link: https://lore.kernel.org/all/2fe3d93f-62ac-4439-ac17-d81137f6410a@imgtec.com [1] Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [2] Signed-off-by: Michal Wilczynski --- drivers/clk/thead/clk-th1520-ap.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index 57972589f120..ea96d007aecd 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -89,6 +89,21 @@ struct ccu_pll { } \ } +#define CCU_GATE_CLK_OPS(_clkid, _struct, _name, _parent, _reg, _gate, _flags, \ + _clk_ops) \ + struct ccu_gate _struct = { \ + .enable = _gate, \ + .common = { \ + .clkid = _clkid, \ + .cfg0 = _reg, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA( \ + _name, \ + _parent, \ + &_clk_ops, \ + _flags), \ + } \ + } + static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) { return container_of(hw, struct ccu_common, hw); @@ -847,6 +862,11 @@ static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, BIT(3), 0); static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2), 0); static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1), 0); +static const struct clk_ops clk_nop_ops = {}; + +static CCU_GATE_CLK_OPS(CLK_GPU_MEM, gpu_mem_clk, "gpu-mem-clk", + video_pll_clk_pd, 0x0, BIT(2), 0, clk_nop_ops); + static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk", video_pll_clk_pd, 0x0, BIT(0), 0); static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd, @@ -1205,6 +1225,12 @@ static int th1520_clk_probe(struct platform_device *pdev) ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw); if (ret) return ret; + } else if (plat_data == &th1520_vo_platdata) { + ret = devm_clk_hw_register(dev, &gpu_mem_clk.common.hw); + if (ret) + return ret; + gpu_mem_clk.common.map = map; + priv->hws[CLK_GPU_MEM] = &gpu_mem_clk.common.hw; } ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); 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Wed, 19 Feb 2025 14:03:02 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250219140302eusmtrp175c9fe4248d58e42f86e1f93a19d0741~loO-OadkE2395223952eusmtrp1V; Wed, 19 Feb 2025 14:03:02 +0000 (GMT) X-AuditID: cbfec7f4-c0df970000004fb9-12-67b5e497c90b Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id C5.86.19920.694E5B76; Wed, 19 Feb 2025 14:03:02 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250219140301eusmtip2639420979e5385099dffb8762ed346a7~loO93-NCx0084500845eusmtip2m; Wed, 19 Feb 2025 14:03:01 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [PATCH v5 10/21] clk: thead: Add GPU clock gate control with CLKGEN reset support Date: Wed, 19 Feb 2025 15:02:28 +0100 Message-Id: <20250219140239.1378758-11-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250219140239.1378758-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUxTVxjGd3q/CqTsUtw4onGRBN2MgDBDzjK3SbKZG80SN5ewETNp9FoQ aF0rjs1uYmhrxSrOIWhxgg0KgXUMbGvpgGpBWsdHoCACo4y5ipSgXceHGQRcy8XN/37nOc9z nvdNDh8TmshofqbkCCuTiLJjyFDc3P5Pd1ypxyTe8nggEjnv63nItKCj0I/N3TxU3tZNoFGX kYf6Z30k+ulhD4Ummk/gaKD6BwoVtNeRyKsbJZFfO0qgPutlEk2faQPIPK0kkaHNTaG62XIe uuo34ajSYgVIfeo6gXp//QC5R5048vZpMaTWvYyeNVkotDRQj6OyJzYKGae+I5DDkIqUtmJ8 +zrGN6iimCmvF2daNTMU0zxXgTONOjfFaBs7AdNQc4pkRgaaSObK3Y+Y3087eMyNyuOM0tDO Y4oWtzC+lnskc9ZYAxhXwX1qtzAtdNsBNjvzKCtLeDc9NKO100AcXojLW9LMgnzg3FAIQviQ 3grHa+uwQhDKF9LVAJq9ZQR3mAGw4akeBF1CehrA+adZzxPGpVuAM1UBOGUykpxpKmCaiwoy SSfBsary5ZdW0Socqu6cWE5g9KNAh+fyciKS3gtPuheJION0LLxpzl9mAb0d3lNNUFzda9B2 uyswIJ8fEtBbeqM5SwS8e8mDBxkLWApMZcs7QLo+FE60tvC47Puwoqie4DgSTjqMK2+uhR3f a3GOpXDM9DfGsQI2ah0r/DYc6Z4ng70Y/QassyZwcgpcaCwkgjKkw+Hg4whuhHB43lyKcbIA atRCzr0BXtCe+a+0u9q8MhgDW2oniXNgve6FZXQvLKP7v7cCYDUgis2V54hZeZKE/TJeLsqR 50rE8fulOQ0g8LM7lhwzFlA16Y+3Ax4f2AHkYzGrBOrjRrFQcED01desTLpPlpvNyu1gDR+P iRLobSqxkBaLjrBZLHuYlT2/5fFDovN5JS1yc+p6f+Z47J8bLZHUUI/PfX413VV11LaxK++9 4QyZZy7us7jRsAfDHmeh3R72cX7ZwWu7r49bxXmKHdJDJTmJ+ji2b7NksCw+MeVm2poPT1q+ KNpzsOPQxTfTS7/Z9On+NFfS0Ot0YoXs6hNS/4s/8Zg61sY661POFWuKOl+NuvJzrcL01x/9 tEU554m4Fn/WtOvh5J0h1859zb85xxJ6Kp5d6Iw9nTyv7VV80it1EbtGwtfmPkpbutj0TnJ/ MjmUB7qUL13KCnM98I1LFFv7kPnziP7YSmtqanRJQX6mf7NAcmyPUgNvrEuv3Fu42r2tuHl+ 563bwh2vaL99a3jREIPLM0SJmzCZXPQv9gOajUgEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xe7rTnmxNN2jep29x4voiJoutv2ex W6zZe47JYv6Rc6wW9y5tYbK48vU9m8W6pxfYLV7sbWSxuLZiLrtF87H1bBYvZ91js/jYc4/V 4vKuOWwWn3uPMFps+9zCZrH2yF12i/Vf5zNZLPy4lcViyY5djBZtnctYLS6ecrW4e+8Ei8XL yz3MFm2z+C3+79nBbvHv2kYWi9nv9rNbbHkzkdXi+Npwi5b9U1gc5Dze32hl93jz8iWLx+GO L+wee78tYPHYOesuu0fPzjOMHptWdbJ53Lm2h81j3slAj/vdx5k8Ni+p92hZe4zJo/+vgcf7 fVfZPPq2rGL0uNR8nT1AKErPpii/tCRVISO/uMRWKdrQwkjP0NJCz8jEUs/Q2DzWyshUSd/O JiU1J7MstUjfLkEv4/CZtawFv3Ur/nV8ZWxgPKHWxcjJISFgIrHl3wHGLkYuDiGBpYwSZy7P Z4ZIyEhc637JAmELS/y51sUGUfSKUWLzoU5WkASbgJHEg+XzwWwRgcUsEnv3VYIUMQu8ZZS4 PnMjWLewQJTE9zfbGEFsFgFVie3bGsAaeAUcJK62vmCH2CAvsf/gWaDNHBycQPF9F6VAwkIC 9hLn+u5DlQtKnJz5BGwkM1B589bZzBMYBWYhSc1CklrAyLSKUSS1tDg3PbfYUK84Mbe4NC9d Lzk/dxMjML1sO/Zz8w7Gea8+6h1iZOJgPMQowcGsJMLbVr8lXYg3JbGyKrUoP76oNCe1+BCj KdDZE5mlRJPzgQkuryTe0MzA1NDEzNLA1NLMWEmc1+3y+TQhgfTEktTs1NSC1CKYPiYOTqkG pnYFu5+Xdzmk3b2ZyxWQdO2hw8JO/nWhqzOPxhyP8+B+nLbi8ea/y/xVOrNuvqhJiPZLP3tx 2+pVp+PONSooZkzZlil7Sc60XuVhGXOc/dmQ7b8VlF31Xv/Zobc3P/GL/hYf26kiSV9jv3Pn ZbyRmK4y/cvewm3v86sFJedzZ8XGfFrwtPEK572yf/ZKT8xTFU6cO5PUeWniA1bPRdGvQqzc Ck6ZKRxr0XJq8/Lb9fh9WM+HvLP6+vN4ZhqLnfLbuqJjlt43x/9vzM6+esbqwqjBf7F0Z/r2 3Auzl0z7MUPG/uHRdqUpNYFzip9fu/az2FM96O6/S9sL5iRcCHy8MYLdYK566u/5R9ecXjsv ukqJpTgj0VCLuag4EQCLbw7buAMAAA== X-CMS-MailID: 20250219140302eucas1p24d9900e424b31661217e3c9182105b3a X-Msg-Generator: CA X-RootMTR: 20250219140302eucas1p24d9900e424b31661217e3c9182105b3a X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250219140302eucas1p24d9900e424b31661217e3c9182105b3a References: <20250219140239.1378758-1-m.wilczynski@samsung.com> The T-HEAD TH1520 has three GPU clocks: core, cfg, and mem. The mem clock gate is marked as "Reserved" in hardware, while core and cfg are configurable. In order for these clock gates to work properly, the CLKGEN reset must be managed in a specific sequence. Move the CLKGEN reset handling to the clock driver since it's fundamentally a clock-related workaround [1]. This ensures that clk_enabled GPU clocks stay physically enabled without external interference from the reset driver. The reset is now deasserted only when both core and cfg clocks are enabled, and asserted when either of them is disabled. The mem clock is configured to use nop operations since it cannot be controlled. Link: https://lore.kernel.org/all/945fb7e913a9c3dcb40697328b7e9842b75fea5c.camel@pengutronix.de [1] Signed-off-by: Michal Wilczynski --- drivers/clk/thead/clk-th1520-ap.c | 87 ++++++++++++++++++++++++++++--- 1 file changed, 81 insertions(+), 6 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index ea96d007aecd..1dfcde867233 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -12,6 +12,7 @@ #include #include #include +#include #define TH1520_PLL_POSTDIV2 GENMASK(26, 24) #define TH1520_PLL_POSTDIV1 GENMASK(22, 20) @@ -862,17 +863,70 @@ static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, BIT(3), 0); static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2), 0); static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1), 0); +static struct reset_control *gpu_reset; +static DEFINE_SPINLOCK(gpu_reset_lock); /* protect GPU reset sequence */ + +static void ccu_gpu_clk_disable(struct clk_hw *hw); +static int ccu_gpu_clk_enable(struct clk_hw *hw); + +static const struct clk_ops ccu_gate_gpu_ops = { + .disable = ccu_gpu_clk_disable, + .enable = ccu_gpu_clk_enable +}; + static const struct clk_ops clk_nop_ops = {}; static CCU_GATE_CLK_OPS(CLK_GPU_MEM, gpu_mem_clk, "gpu-mem-clk", video_pll_clk_pd, 0x0, BIT(2), 0, clk_nop_ops); +static CCU_GATE_CLK_OPS(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", + video_pll_clk_pd, 0x0, BIT(3), 0, ccu_gate_gpu_ops); +static CCU_GATE_CLK_OPS(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", + video_pll_clk_pd, 0x0, BIT(4), 0, ccu_gate_gpu_ops); + +static void ccu_gpu_clk_disable(struct clk_hw *hw) +{ + struct ccu_gate *cg = hw_to_ccu_gate(hw); + unsigned long flags; + + spin_lock_irqsave(&gpu_reset_lock, flags); + + ccu_disable_helper(&cg->common, cg->enable); + + if ((cg == &gpu_core_clk && + !clk_hw_is_enabled(&gpu_cfg_aclk.common.hw)) || + (cg == &gpu_cfg_aclk && + !clk_hw_is_enabled(&gpu_core_clk.common.hw))) + reset_control_assert(gpu_reset); + + spin_unlock_irqrestore(&gpu_reset_lock, flags); +} + +static int ccu_gpu_clk_enable(struct clk_hw *hw) +{ + struct ccu_gate *cg = hw_to_ccu_gate(hw); + unsigned long flags; + int ret; + + spin_lock_irqsave(&gpu_reset_lock, flags); + + ret = ccu_enable_helper(&cg->common, cg->enable); + if (ret) { + spin_unlock_irqrestore(&gpu_reset_lock, flags); + return ret; + } + + if ((cg == &gpu_core_clk && + clk_hw_is_enabled(&gpu_cfg_aclk.common.hw)) || + (cg == &gpu_cfg_aclk && clk_hw_is_enabled(&gpu_core_clk.common.hw))) + ret = reset_control_deassert(gpu_reset); + + spin_unlock_irqrestore(&gpu_reset_lock, flags); + + return ret; +} static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk", video_pll_clk_pd, 0x0, BIT(0), 0); -static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd, - 0x0, BIT(3), 0); -static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", - video_pll_clk_pd, 0x0, BIT(4), 0); static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", video_pll_clk_pd, 0x0, BIT(5), 0); static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", @@ -1046,8 +1100,6 @@ static struct ccu_common *th1520_gate_clks[] = { static struct ccu_common *th1520_vo_gate_clks[] = { &axi4_vo_aclk.common, - &gpu_core_clk.common, - &gpu_cfg_aclk.common, &dpu0_pixelclk.common, &dpu1_pixelclk.common, &dpu_hclk.common, @@ -1150,6 +1202,13 @@ static int th1520_clk_probe(struct platform_device *pdev) if (IS_ERR(map)) return PTR_ERR(map); + if (plat_data == &th1520_vo_platdata) { + gpu_reset = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(gpu_reset)) + return dev_err_probe(dev, PTR_ERR(gpu_reset), + "GPU reset is required for VO clock controller\n"); + } + for (i = 0; i < plat_data->nr_pll_clks; i++) { struct ccu_pll *cp = hw_to_ccu_pll(&plat_data->th1520_pll_clks[i]->hw); @@ -1226,11 +1285,27 @@ static int th1520_clk_probe(struct platform_device *pdev) if (ret) return ret; } else if (plat_data == &th1520_vo_platdata) { + /* GPU clocks need to be treated differently, as MEM clock + * is non-configurable, and the reset needs to be de-asserted + * after enabling CORE and CFG clocks. + */ ret = devm_clk_hw_register(dev, &gpu_mem_clk.common.hw); if (ret) return ret; gpu_mem_clk.common.map = map; priv->hws[CLK_GPU_MEM] = &gpu_mem_clk.common.hw; + + ret = devm_clk_hw_register(dev, &gpu_core_clk.common.hw); + if (ret) + return ret; + gpu_core_clk.common.map = map; + priv->hws[CLK_GPU_CORE] = &gpu_core_clk.common.hw; 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Wed, 19 Feb 2025 14:03:05 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250219140305eusmtrp13a12bb5c0d1dcf0b0f76dcb384c2ab1f~loPBv1Y_F2395223952eusmtrp1Y; Wed, 19 Feb 2025 14:03:05 +0000 (GMT) X-AuditID: cbfec7f2-b09c370000005155-57-67b5e4992752 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 79.86.19920.994E5B76; Wed, 19 Feb 2025 14:03:05 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250219140304eusmtip259883a2a3e0f884864c120997a69f701~loPAbqb8k0642206422eusmtip2L; Wed, 19 Feb 2025 14:03:04 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [PATCH v5 12/21] reset: thead: Add TH1520 reset controller driver Date: Wed, 19 Feb 2025 15:02:30 +0100 Message-Id: <20250219140239.1378758-13-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250219140239.1378758-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Sa1ATVxjl7m52QzS6xAd3aKs1U7QyFRD9cbXKqEPbVWY69VenYqdmYCcg EGxCau1DQQgSTFBK+jCASSktgRYQSDJAgSimhIeGRjDCDESmpFUeEhBxqC1QwtLWf+c753zf +b47l4+L6skQfpIsnZXLJCliUkBY2//s2aH3WqSRdgnquFeKIctfegr91OLEkMHu5CHPHTOG +mZ9JKr+/VcKPWzJJJDbVEKhrPYaEo3qPSSa1nh4qLepmEQzWjtA1plsElXZhyhUM2vA0LfT FgKVNTQBlKP+gYdcXW+gIU8HgUZ7NTjK0a9Fi80NFFpw1xKoaNJGIfNEAQ85qt5F2TYdcWAT 4+tXUczE6CjB3Mx9QjEtT40E06gfohhN4y3A1FWqSWbQ3UwyVzuPMvcvOjCmvuwck13VjjGX 5iMZX+tdksk3VwLmTtY96h3RMcG+BDYl6SNWHhF9QpA4XCI7ZYr6uK/MSGYAQ1ge4PMhvRv2 Dh3PAwK+iDYB2G77g+KKJwD6KjUYV8wAeLtDh+eBwOWO+0N1hB+L6HIAXQMyzjQBYIW7f1kg 6Sg4XG7g+YX1tIqAql8ygb/A6QcAWr3FpN+1jj4C1WNlwI8JOhQ2u6eWsZA+AC3Z9QQXtxna btzG/csGLvGtrhDOEgQ7r3iXLfiSJctShPvnQ7pWAPP77BTXGwNrOy2Aw+vgmMO8wr8Iuws1 K/PT4LDl8cppn8FGjWMFvw4Hnc9Ify5Ob4c1TREcfRDOztsx7u3WwP5HQdwKa+AX1q9xjhbC 3BwR594Kv9Ro/wt1mqwYhxm4OLxIXAZb9M8do3/uGP3/uUaAV4JgVqlIlbKKnTL2dLhCkqpQ yqTh8WmpdWDpX3cvOB43gJKx6fA2gPFBG4B8XLxemHPOLBUJEyRnPmHlaR/IlSmsog28wCfE wcJSm0oqoqWSdDaZZU+x8n9VjB8YkoElt36eECvvie5uGDfN3bqeWBzxUmnWRlwcZuuK2nT5 G1fXgxuWXUElq8f/Vu6JkxHbbMY3yeuqXdWRhs2H0zDv99U1sdYLBv57I/nvfzo7BUWF+5O9 k+pjx+MjsMAPwQbjws23K2Vbk06OW372DuQqdK8UvDyXcMERiulePW1SvVZ9JTiu5/yqi6u0 ppgfu7R34/aW+34LIwIe9X2VGXAp8lD+ybeCnnqeqYTyGGe689qR+PPuM9Frdwy2txoUh7+b Pkjb61YbH4rCq0/s1bqUtrmB+f3X6qe2qQumsYqAfaaNVd6Rs9s7JhtDfUUb0o/uKauoOpRx diRWHD8Tqttd6JWFiQlFomRnGC5XSP4BgygbNkYEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCKsWRmVeSWpSXmKPExsVy+t/xe7ozn2xNN3h5TtbixPVFTBZbf89i t1iz9xyTxfwj51gt7l3awmRx5et7Not1Ty+wW7zY28hicW3FXHaL5mPr2SxezrrHZvGx5x6r xeVdc9gsPvceYbTY9rmFzWLtkbvsFuu/zmeyWPhxK4vFkh27GC3aOpexWlw85Wpx994JFouX l3uYLdpm8Vv837OD3eLftY0sFrPf7We32PJmIqvF8bXhFi37p7A4yHm8v9HK7vHm5UsWj8Md X9g99n5bwOKxc9Zddo+enWcYPTat6mTzuHNtD5vHvJOBHve7jzN5bF5S79Gy9hiTR/9fA4/3 +66yefRtWcXocan5OnuAUJSeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJpZ6hsXmslZGpkr6d TUpqTmZZapG+XYJexoO5eQUrjCquLFnA1sA4X6uLkZNDQsBE4v7dTSxdjFwcQgJLGSWOvdjA BJGQkbjW/ZIFwhaW+HOtiw2i6BWjxIPzS5hBEmwCRhIPls9nBbFFBBazSOzdVwlSxCzwllHi +syNYN3CAl4Sna+WMILYLAKqEnuufQCzeQUcJLa2bIbaIC+x/+BZoKEcHJxA8X0XpUDCQgL2 Euf67rNClAtKnJz5BKycGai8eets5gmMArOQpGYhSS1gZFrFKJJaWpybnltsqFecmFtcmpeu l5yfu4kRmFy2Hfu5eQfjvFcf9Q4xMnEwHmKU4GBWEuFtq9+SLsSbklhZlVqUH19UmpNafIjR FOjsicxSosn5wPSWVxJvaGZgamhiZmlgamlmrCTO63b5fJqQQHpiSWp2ampBahFMHxMHp1QD 08yaixyPD6X5v4tV4XpSaFUjFrlmVbpTqL/T/0It2/suT1R3HTqx/N+XmLO3qvXWKOzd/2ar XJ+nnIHasR69yjlLP/UvsGy33nTg7erqkyt4/Ip1Ppcv9Pt1cUXd0UXVf9fo2onLn5jQY8D7 /z7X1Xf2FwP23pGpcbjJOaHx2M1NKb075y3jOdB25FSSTFcby6GWlPe7kpWLjSs+nhCIeyUy +dUZ521qmT6lybyTTrBKrZq8+em1IIWTPgder3nAfcZpqrpQ5oHuXLPaggMVdxaey5CePXeV qJOkwtSuWwaF02/m2bXOmHPv/bzr5c/99h+Ml36/T0dq4vONb79Lhefdf3h3f6vmjnWLNga8 js1TYinOSDTUYi4qTgQA5yVj6rcDAAA= X-CMS-MailID: 20250219140305eucas1p26317b54727c68cf069458d270e06d962 X-Msg-Generator: CA X-RootMTR: 20250219140305eucas1p26317b54727c68cf069458d270e06d962 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250219140305eucas1p26317b54727c68cf069458d270e06d962 References: <20250219140239.1378758-1-m.wilczynski@samsung.com> Add reset controller driver for the T-HEAD TH1520 SoC that manages hardware reset lines for various subsystems. The driver currently implements support for GPU reset control, with infrastructure in place to extend support for NPU and Watchdog Timer resets in future updates. Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/reset/Kconfig | 10 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-th1520.c | 141 +++++++++++++++++++++++++++++++++++ 4 files changed, 153 insertions(+) create mode 100644 drivers/reset/reset-th1520.c diff --git a/MAINTAINERS b/MAINTAINERS index 819686e98214..e4a0a83b4c11 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20425,6 +20425,7 @@ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: drivers/pmdomain/thead/ +F: drivers/reset/reset-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/power/thead,th1520-power.h F: include/dt-bindings/reset/thead,th1520-reset.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 5b3abb6db248..fa0943c3d1de 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -272,6 +272,16 @@ config RESET_SUNXI help This enables the reset driver for Allwinner SoCs. +config RESET_TH1520 + tristate "T-HEAD 1520 reset controller" + depends on ARCH_THEAD || COMPILE_TEST + select REGMAP_MMIO + help + This driver provides support for the T-HEAD TH1520 SoC reset controller, + which manages hardware reset lines for SoC components such as the GPU. + Enable this option if you need to control hardware resets on TH1520-based + systems. + config RESET_TI_SCI tristate "TI System Control Interface (TI-SCI) reset driver" depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 677c4d1e2632..d6c2774407ae 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o +obj-$(CONFIG_RESET_TH1520) += reset-th1520.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o obj-$(CONFIG_RESET_TI_TPS380X) += reset-tps380x.o diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c new file mode 100644 index 000000000000..d6816c86ba95 --- /dev/null +++ b/drivers/reset/reset-th1520.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include + +#include + + /* register offset in VOSYS_REGMAP */ +#define TH1520_GPU_RST_CFG 0x0 +#define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0) + +/* register values */ +#define TH1520_GPU_SW_GPU_RST BIT(0) +#define TH1520_GPU_SW_CLKGEN_RST BIT(1) + +struct th1520_reset_priv { + struct reset_controller_dev rcdev; + struct regmap *map; +}; + +struct th1520_reset_map { + u32 bit; + u32 reg; +}; + +static const struct th1520_reset_map th1520_resets[] = { + [TH1520_RESET_ID_GPU] = { + .bit = TH1520_GPU_SW_GPU_RST, + .reg = TH1520_GPU_RST_CFG, + }, + [TH1520_RESET_ID_GPU_CLKGEN] = { + .bit = TH1520_GPU_SW_CLKGEN_RST, + .reg = TH1520_GPU_RST_CFG, + } +}; + +static inline struct th1520_reset_priv * +to_th1520_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct th1520_reset_priv, rcdev); +} + +static int th1520_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + const struct th1520_reset_map *reset; + + if (id >= ARRAY_SIZE(th1520_resets)) + return -EINVAL; + + reset = &th1520_resets[id]; + + return regmap_update_bits(priv->map, reset->reg, reset->bit, 0); +} + +static int th1520_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + const struct th1520_reset_map *reset; + + if (id >= ARRAY_SIZE(th1520_resets)) + return -EINVAL; + + reset = &th1520_resets[id]; + + return regmap_update_bits(priv->map, reset->reg, reset->bit, + reset->bit); +} + +static const struct reset_control_ops th1520_reset_ops = { + .assert = th1520_reset_assert, + .deassert = th1520_reset_deassert, +}; + +static const struct regmap_config th1520_reset_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + +static int th1520_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct th1520_reset_priv *priv; + void __iomem *base; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->map = devm_regmap_init_mmio(dev, base, + &th1520_reset_regmap_config); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + /* Initialize GPU resets to asserted state */ + ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, + TH1520_GPU_RST_CFG_MASK, 0); + if (ret) + return ret; + + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.nr_resets = 2; + priv->rcdev.ops = &th1520_reset_ops; + priv->rcdev.of_node = dev->of_node; + + return devm_reset_controller_register(dev, &priv->rcdev); +} + +static const struct of_device_id th1520_reset_match[] = { + { .compatible = "thead,th1520-reset" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, th1520_reset_match); + +static struct platform_driver th1520_reset_driver = { + .driver = { + .name = "th1520-reset", + .of_match_table = th1520_reset_match, + }, + .probe = th1520_reset_probe, +}; +module_platform_driver(th1520_reset_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 SoC reset controller"); +MODULE_LICENSE("GPL"); From patchwork Wed Feb 19 14:02:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 867033 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D88991FDE2A for ; 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Wed, 19 Feb 2025 14:03:06 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski , Krzysztof Kozlowski Subject: [PATCH v5 14/21] dt-bindings: gpu: Add 'resets' property for GPU initialization Date: Wed, 19 Feb 2025 15:02:32 +0100 Message-Id: <20250219140239.1378758-15-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250219140239.1378758-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01SbUxTVxj23Ht776VL9VLYOEPRSbZlM4pOJp4MXQpx5m4//MiybNN92IxL 6UaBtSAfmwijJcKKjglD2rmCYYMh0AzbriCFja+CQjdAgWWlGC3RKh8DikGJbJTbbf57nud9 3vd535ND4+LLZCgtT0rllEnSxHBSSFi6Hzi2nXebZTu+GduKekYuYMi8pKNQnc2BIUOnQ4Bc gyYMXVuYIVHDxO8UumPLJdBwzXkK5XUbSeTRuUhku2em0KzWJUBDzd+SaL6oEyDLvJpE9Z1j FDIuGDBUOWsmUJW1GaD8gh8EaODKa2jM1UMgz5AWR/m6dejvFiuFlod/IpB+uo1CpsliAbLX v43UbSWEZBM7M6qh2EmPh2A7Tnkp1na/gmCbdGMUq23qA2xjbQHJOodbSPa73sPs+Jd2jL1U dZJV13dj7JlHO9iZ1uske9pUC9jBvBHqkPiIcE8clyg/zim3v3pMmFBScU+QoqYzKhwOKge4 yUIQQEPmZXi2zEgVAiEtZmoAnOypInjiBfB+nwHjyTyA7tGuFUKvtlxv2cbr1QBa5iv8pkkA R5bqcN9cktkJb1QbBL5CMKMhoKYrF/gIzhgwePFh+aoriDkC2wo6VzchmOdg11+5hA+LGAks Uffh/IabYNuv/bgvOmBFbx0I5S2BsLfcvWrHVyx5Zj3umw8ZsxCOltoJvncfLMsZ8M8Jgnft JorHG+DVs1q/JxneMM/5PZ/DJq3dj6Oh0/GQ9OXizIvQ2Lydl2Ogc8oJ+JdYC0enAvkV1sKv LWU4L4vgqXwx734elmqL/gt11FgwHrPwzPKo4CuwWffYMbrHjtH9n1sB8FoQwqWpFDJOFZnE pUeopApVWpIs4qNkRSNY+d9Xl+0LVlBzdzaiHWA0aAeQxsODRfknTTKxKE6amcUpkz9UpiVy qnawnibCQ0QX2jQyMSOTpnKfcFwKp/y3itEBoTkYOTxyc++kRP5nQ5A7tn3RYezXJ9AZFjR0 K8pT4tpycI2j6U19Tl2WLvTEnf0W7ccN0eeccfs29i5mX1zyvrfc7SrWS0Ch4qZNkV46J9wQ 5Vz8ufjQwqeFx3daFbGL8rDp19P7kmnXoz/iQ95pSdv9RdRgrOSX4CWlUGoNCDuQotfE775c +PQcLRmfCFNVr9FMRL4ySxWYQyunymPeSIiM659+cmRh/5WDXuYDS9QBb0yRyVQ13ZqZTROJ 6S9IfvPeHo+49pk8/vZA47tbH7izom327wPffyLXmnls/Y/6Z9ZdWnp27+kTRzXzImMGe6uy Y9dTcbuOvnW4JniPbWOHIdueGk6oEqQvbcGVKuk/Rx+UkU4EAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA02Sa0xTdxjGPfeDWbez0uGxbqlpYlyclBa5/Lsw4Avuz1y8JQ4ZI9LosZhR 6npBcCYFKWy2qCMDZa2UIreNDJ2UcjEUFMtVKCBSTSaFbSxb1dkRxgy7wFrIEr+9eZ7f877P h5fG+N8QQvpEro7T5CpyxORG/O7KoC+yet6plPa7XwJDD66iwPm3hQLfujwoqHF7COC714aC +0sBElz7eYICv7qKcOD9upoCxQPXSeC3+EjgeuKkwEKZjwBTN6+QYPG8GwHti0YStLhnKHB9 qQYFtQtOHNR33kRA6blGAkyOpIAZ3xAO/FNlGCi1vAJWuzspsOK9gQPrs14KtD0tJ8BgSxow 9lbgySIYeFhCwad+Pw7vfP4HBV1/2nHYZZmhYFnXKAJbm8+R8JG3m4S24QNw1jyIQke9ARpb BlB48V8pDPRMk/BCWzMC7xU/oPbzP5QkaNR6Hbc1W63VvSPOkIFoiUwOJNExcolsV3zm29Gx 4qjEhGNczok8ThOVmCXJrrA/IU4a6Xy7x0MVIvOkCaFplolhp7sjTchGms80IGzlxGXChIQF 9ddZr9mPr8/h7D9eE7kOPUbYlUAACxkkE83ONdWsBQRMHc66egpCEMY0oOyPq7fIkBHOHGad pqo1CGe2sf2/F61t5THJbIVxFFu/IGJ7b49hoUZhQb1nUhiS+UwS67kwS6zjr7LDX82vRbEg Xuy0Yl8gjOUFy/KCZUfQZkTA6bUqpUork2gVKq0+Vyk5qla1IsGfaR9YdnQitscLkj4EpZE+ hKUxsYBXamhT8nnHFAWnOY36iEafw2n7kNhg7XJM+NpRdfDpcnVHZHHSWFlMnFwaK4/bJd7E 2z01fpzPKBU67mOOO8lp/s+hdJiwEI2/GG48taw8W30G35CaHgFHvMnFhCdzPC2/VqBIc084 Lm0gZ/2fjJrqeb+tvje/uyPdnLqAWgsaXYdvVYwsGz5IUVadmbNiDUtm3/Mf6KwtQ7wiUe0B eXnJUkTRX29Z9JNczPaO1odJm0v3dbdnqvpSbrh37o0Xnt+Ttml/Zd7zdw+uJvTfd52+872b m178rvHlJg3DyGYo/eakOtveLamFdQez3rz2viT8kW2469OOu7aMZDb9mSiR4ft/2inP9JuZ HREgajxScMiUf3nqI1FVhqGStyhyqH8Zu6SFDKy0Nzmc0i+viudKdJ/pPG9sMwm2dtB5Z612 a+8pwxghxrXZCtkOTKNV/Ac2rXuxvAMAAA== X-CMS-MailID: 20250219140309eucas1p2701a4b4bacd3be6e9f20d637d3cefa5c X-Msg-Generator: CA X-RootMTR: 20250219140309eucas1p2701a4b4bacd3be6e9f20d637d3cefa5c X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250219140309eucas1p2701a4b4bacd3be6e9f20d637d3cefa5c References: <20250219140239.1378758-1-m.wilczynski@samsung.com> All IMG Rogue GPUs include a reset line that participates in the power-up sequence. On some SoCs (e.g., T-Head TH1520 and Banana Pi BPI-F3), this reset line is exposed and must be driven explicitly to ensure proper initialization. To support this, add a 'resets' property to the GPU device tree bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Michal Wilczynski --- Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 256e252f8087..bb607d4b1e07 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -37,6 +37,9 @@ properties: power-domains: maxItems: 1 + resets: + maxItems: 1 + required: - compatible - reg From patchwork Wed Feb 19 14:02:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 867032 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2D9D1FFC7C for ; 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Wed, 19 Feb 2025 14:03:11 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [PATCH v5 17/21] drm/imagination: Enable PowerVR driver for RISC-V Date: Wed, 19 Feb 2025 15:02:35 +0100 Message-Id: <20250219140239.1378758-18-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250219140239.1378758-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01SbUxTZxTee+/tvZdi4VqMvGPLiMQRJaMCg+VFlwXmdHfRHxBnSCSZ1Hkp yJe2gG5IkPExlCpDHGaFCrhGa7U0Y6VAB3awQhVYEXTFjM8ZNsGUYfnYJg63loub/57znPOc 5znJoXGxkQygUzOzOXmmND2IFBKmnif20IapZlmY4a9gdGv4Moaan6oodKPDjqE6q12AxoeM GLq3NEeixl/vUGi6o5BADq2aQkU9BhLNqMZJ5FKOC9Bdcy2JFs5aATItFJNIbx2jkGGpDkMN rmYCaVrNAJWeviJAg7270Nj4LQLN3FXiqFTli/5pb6XQM8c3BKr53UIho7NSgGz6BFRsuUDE vMbO3S+hWOfMDMH+ULZIsR1/1BNsm2qMYpVt/YBt0p0m2VFHO8leuh3PTpTbMPZbTQFbrO/B 2IqVMHbu5k8ke86oA+xQ0TAVJz4gfPswl56ay8m3vZMkTPnePI8dNdMnKqdW8FPgc+oM8KIh EwkvDTzBzgAhLWa0AF6YuiLgi0UAG4cLSb5YAPDepBE8l1ic19YaVwG0TX692hAzTrdEHe3B JBMBJ6/Wra7awJQQsKS7EHgKnHkIoGmq1i2naT9mD7xTHuIREMzrsHW5CnhoERMDKy0f8GaB 0NL5I+6hvdz0zcEADy1i1sPbX00RHoy7R4qaa3DPdsjohfDPwREBr30Pni/XrIX2g49sxrWb X4V9VUqCx1lwsnke5/FJ2Ka0reEdcNS+vJoSZ7ZCg3kbT8dC6+LAakrI+MD7s+v5CD7wvOki ztMiWFYq5qeD4ZfKs/+Z2rUmjMcs7CpeEnwBNqleOEb1wjGq/33rAa4D/lyOIkPGKcIzueMS hTRDkZMpk3ycldEE3I/d98w23wrUj1ySLoDRoAtAGg/aICotMMrEosPSTz7l5FkH5TnpnKIL vEITQf6iy5YSmZiRSbO5NI47ysmfdzHaK+AUlt/PRmQnhKlr9tlInaq9uKZa+cb1G8n5R1ra Q60FnZvyy7g3mYf96vzGfb9pXC09JqVvpGakczBuMvc74fbu6QqxTTK4Z3eA9/ShlUPRkeFb jqS8bP9Q07duh6T2rdyB0ePGlwIPhBnM/qERgV71EkHaOUdkTHxcJkg+NmvqHSs64Y1d+9nk yuv+6DNC+NhRuhxRNz+tPnax+kF8lneFbsvmpz3rDAnB786RXL5eH7td+6DXuXFWNDuWp+kN 8tm1+5eJjJ0jwb5VfyfL0vbv1Ubtj6qe2NttShKl2RNj8yIfK7mGGdn7SaM7N29sisoiD56U trQMJaYl0tGUX0iqsySIUKRIw0NwuUL6L0qI9SNHBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEKsWRmVeSWpSXmKPExsVy+t/xe7oLn2xNN/jubXHi+iImi62/Z7Fb rNl7jsli/pFzrBb3Lm1hsrjy9T2bxbqnF9gtXuxtZLG4tmIuu0XzsfVsFi9n3WOz+Nhzj9Xi 8q45bBafe48wWmz73MJmsfbIXXaL9V/nM1ks/LiVxWLJjl2MFm2dy1gtLp5ytbh77wSLxcvL PcwWbbP4Lf7v2cFu8e/aRhaL2e/2s1tseTOR1eL42nCLlv1TWBzkPN7faGX3ePPyJYvH4Y4v 7B57vy1g8dg56y67R8/OM4wem1Z1snncubaHzWPeyUCP+93HmTw2L6n3aFl7jMmj/6+Bx/t9 V9k8+rasYvS41HydPUAoSs+mKL+0JFUhI7+4xFYp2tDCSM/Q0kLPyMRSz9DYPNbKyFRJ384m JTUnsyy1SN8uQS/jwK5PTAW7OComPvnL3MDYzt7FyMkhIWAisf/NSrYuRi4OIYGljBLrX3Sz QiRkJK51v2SBsIUl/lzrgip6xShx59wDsASbgJHEg+XzwRpEBBazSOzdVwlSxCzwllHi+syN QEUcHMIC3hIXurVAalgEVCV2/JrMCBLmFXCQmLjfE2K+vMT+g2eZQcKcQOF9F6VAwkIC9hLn +u6DTecVEJQ4OfMJ2FZmoPLmrbOZJzAKzEKSmoUktYCRaRWjSGppcW56brGhXnFibnFpXrpe cn7uJkZgYtl27OfmHYzzXn3UO8TIxMF4iFGCg1lJhLetfku6EG9KYmVValF+fFFpTmrxIUZT oKsnMkuJJucDU1teSbyhmYGpoYmZpYGppZmxkjiv2+XzaUIC6YklqdmpqQWpRTB9TBycUg1M R98+eb7aM+3BLX6G5Mfzaxp3+B9fIPT+2cOK0ysufNZJ1mEQveeYwNmfuG5TSeEm7+/PZm7d bhaqzub2yuD4/WWsngzXHzyZsaKpR/fBti+zbr4NWao0I+RQaNQHadGcs8XrtA3+s/NbRnMI lbbMOxb1721uz+a++63SRSI+2bnsK803HH2byrshofvvjLL8TQ23Ui522ch8VjnVPOHn4/mS 1/+c+Wpbw39W/nsUdwLvfK3EhJNvc5Kf3PB+sq5IwnmreYeP1o7Xui92Rry8/teB80zC1OCA v4bm5h/0t/px/IlT/2/Nee7Bz1DJ9ed9F20M7Jadu0/VgPVU/Cyzc6UttcmcLBeVS/4sMn9w WomlOCPRUIu5qDgRALnJxLm1AwAA X-CMS-MailID: 20250219140313eucas1p211517932c3cd45ca8c843840ccd42c1e X-Msg-Generator: CA X-RootMTR: 20250219140313eucas1p211517932c3cd45ca8c843840ccd42c1e X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250219140313eucas1p211517932c3cd45ca8c843840ccd42c1e References: <20250219140239.1378758-1-m.wilczynski@samsung.com> Several RISC-V boards feature Imagination GPUs that are compatible with the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi 4A board. This commit adjusts the driver's Kconfig dependencies to allow the PowerVR driver to be compiled on the RISC-V architecture. By enabling compilation on RISC-V, we expand support for these GPUs, providing graphics acceleration capabilities and enhancing hardware compatibility on RISC-V platforms. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imagination/Kconfig index 3bfa2ac212dc..5f218896114c 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -3,7 +3,7 @@ config DRM_POWERVR tristate "Imagination Technologies PowerVR (Series 6 and later) & IMG Graphics" - depends on ARM64 + depends on (ARM64 || RISCV) depends on DRM depends on PM select DRM_EXEC From patchwork Wed Feb 19 14:02:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 867031 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FED8209F3F for ; Wed, 19 Feb 2025 14:03:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 19 Feb 2025 14:03:14 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [PATCH v5 19/21] riscv: dts: thead: Introduce power domain nodes with aon firmware Date: Wed, 19 Feb 2025 15:02:37 +0100 Message-Id: <20250219140239.1378758-20-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250219140239.1378758-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xbZRjG/c45Pac0Fs/KCJ/oQEkgGXGAbi6fcRGIOI8xLui2YBYWVt2x wGhpWhgyJ4NwEWi3wS4yC4zLyCjEjo21TbmUS7kURO4OmIOKWXEUuhEGbCrKpJ5O99/ved7n zfO9ycfHRXrSl58gS2EVMnFSACkgjL1/DO+osRskYRc2KNQ3WY0hw7qGQt+bhzBU0T3EQ7Yx PYZ+Wlsi0bW5EQrNm7MINKEtp1B2bwOJHBobiZbVNh4aby4j0crpboCMKzkk0nXPUKhhrQJD VcsGAtWYmgHKK7jKQ6M/vIdmbH0EcoyrcZSneQE9aTVRaGPiBoFKH7RTSO8s5iGrLgbltF8g IvyYpalcinE6HATTlb9KMeZHlQTTpJmhGHXTj4BprC8gmemJVpK53P8x84vKijE3a04xObpe jDn7dxiz1HaLZM7o6wEzlj1JRYsOCfYcZZMSjrOK0HeOCOJHF3fKezy+7LsywssEa1Qh8OBD ehfML1BhhUDAF9FaAM2DdwlOrAJoLS/CObGyOamrwJ6ujDZ0uFdqAfz1UTHFCSeAPWt9wJUi 6TfgbG0FzzXYSucSMLcnC7gETt8D0GgvI10pL/owrFwt/JcJOhC2Py7muVhIR8DesVqc6/OH 7Z2Dm8zne2z6baO+XGQL7P/OTrgY34xkG0rd8ToBnNZEchwF7a1V7ku94IJV7+aX4cB5NcFx Mpw1PHTvnoRNaqub34bTQ3+Srlqc3g4bmkM5OxJODswRLhvSnnDq/hbuBZ7wnLEE52whzM8T cekgeFF9+r/SIa0R4yIMzHIqisCrmmdO0Txziub/2kqA1wMfNlUplbDKnTI2LUQplipTZZKQ z5OljWDzYw9sWNdMQLuwHGIBGB9YAOTjAVuFeaf0EpHwqDj9BKtIjlOkJrFKC3iJTwT4CKvb cyUiWiJOYY+xrJxVPJ1ifA/fTMy7Zia2wy/wVqdn1N6FBMVf9ojpfar9H11zJJ7tOPJkv1ye GnDwq/qo2A9bVrebymb8w3ZfeXiwpasrXhXdn5MmU4UdLw3e+CBmI3b4fkZrbIJZeiB3cM+l xp9/hzc6VxavD2dQPgqjY0fp19sIw4l1HdVp//a5x6o74ap78quJN3UwZT0ufiDaQ6uVnvNL V6S/Ypt7LcUyFbct0vyWs9xy+1i1VhgeeFtV1/HbN/PV74fDkfK267PyT6Iu+09GBwVXYXe8 nYlvvqjyqmKa0syHpuZDD0wsRt8tMTXPdQ86Tb3vqopijIKW8chdz188E/TZ+eyTD2wl3iG7 Dxu/2Lv4aVtGZgChjBe/HowrlOJ/AHNk9ZJHBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrMKsWRmVeSWpSXmKPExsVy+t/xe7qLn2xNN9jbomhx4voiJoutv2ex W6zZe47JYv6Rc6wW9y5tYbK48vU9m8W6pxfYLV7sbWSxuLZiLrtF87H1bBYvZ91js/jYc4/V 4vKuOWwWn3uPMFps+9zCZrH2yF12i/Vf5zNZLPy4lcViyY5djBZtnctYLS6ecrW4e+8Ei8XL yz3MFm2z+C3+79nBbvHv2kYWi9nv9rNbbHkzkdXi+Npwi5b9U1gc5Dze32hl93jz8iWLx+GO L+wee78tYPHYOesuu0fPzjOMHptWdbJ53Lm2h81j3slAj/vdx5k8Ni+p92hZe4zJo/+vgcf7 fVfZPPq2rGL0uNR8nT1AKErPpii/tCRVISO/uMRWKdrQwkjP0NJCz8jEUs/Q2DzWyshUSd/O JiU1J7MstUjfLkEv4+Jr44KjnBUnFl9gbWD8yt7FyMkhIWAicXH9ASYQW0hgKaPE5ndOEHEZ iWvdL1kgbGGJP9e62LoYuYBqXjFKPDg6BSzBJmAk8WD5fFYQW0RgMYvE3n2VIEXMAm8ZJa7P 3AhWJCwQLfF7/UqwbSwCqhL7v08Ea+AVcJA4dmk5M8QGeYn9B88C2RwcnEDxfRelIA6ylzjX dx+qXFDi5MwnYCOZgcqbt85mnsAoMAtJahaS1AJGplWMIqmlxbnpucWGesWJucWleel6yfm5 mxiBqWXbsZ+bdzDOe/VR7xAjEwfjIUYJDmYlEd62+i3pQrwpiZVVqUX58UWlOanFhxhNgc6e yCwlmpwPTG55JfGGZgamhiZmlgamlmbGSuK8bpfPpwkJpCeWpGanphakFsH0MXFwSjUw2Rbt yNO7fPVcFwczz0/5k3ZrfJdxlOxp/Zu1a6sUx60LBz9MOH7z1dcp/iandoZx521Inqpx9xnP Uo0P/m9CAgo6P4cqTe2TY5z6bHW3toW3zszVVYz7H3mXFYW5Sfj+Yorn3ep1fuLJA04mHRZz Nq0zc705O/92svqfa5aLnpqv6o1/f6HlUGasxoaaSu9Ic9HjxccUFug6bJOeXeDJnBqVofPM k7Pj5tPLe4Jm3eXReS15U3mpsqxzZW/ImoDiT6rarNp5XawBPJfmnXx7/a38XRntrc+Dlkja Sy8wjY2v//R5Tt+xhRa3k3PlpkjOad41cZrY3wmeFkdtpl9LOnlGYXpT1ZITL4TEL+4LVmIp zkg01GIuKk4EAEd0C8K2AwAA X-CMS-MailID: 20250219140315eucas1p10f08d297580edd114f4c487c1fbffa8d X-Msg-Generator: CA X-RootMTR: 20250219140315eucas1p10f08d297580edd114f4c487c1fbffa8d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250219140315eucas1p10f08d297580edd114f4c487c1fbffa8d References: <20250219140239.1378758-1-m.wilczynski@samsung.com> The DRM Imagination GPU requires a power-domain driver. In the T-HEAD TH1520 SoC implements power management capabilities through the E902 core, which can be communicated with through the mailbox, using firmware protocol. Add AON node, which servers as a power-domain controller. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 197df1f32b25..474f31576a1b 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { compatible = "thead,th1520"; @@ -229,6 +230,13 @@ stmmac_axi_config: stmmac-axi-config { snps,blen = <0 0 64 32 0 0 0>; }; + aon: aon { + compatible = "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + #power-domain-cells = <1>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; From patchwork Wed Feb 19 14:02:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 867030 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF07A20F07C for ; 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Wed, 19 Feb 2025 14:03:15 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [PATCH v5 20/21] riscv: dts: thead: Introduce reset controller node Date: Wed, 19 Feb 2025 15:02:38 +0100 Message-Id: <20250219140239.1378758-21-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250219140239.1378758-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Se0xbdRT2d+/tvZeasrtCtl9gKqs644OHZJNfMoOYPfJbwAAxZtFopMKl oJTOlscwKgxoZVAGs25I2XgNhRGRCaVQwiNjHWUb4zkKS1ZGMqYDqwQoyDZB6W6n++873/ed 852THJaUttN+bHJqGq9OlafIaDFl7r8/HPjDbJsipPziDjQwWUugtodGBv3UPUSgKuuQCE2P mQh0Y2WBRj/fHWHQve5jFLI3nGVQXn8zjeaM0zRa1E+L0HjnGRotF1sBMi/n06jJ6mBQ80oV gWoW2yhU19EJkO74jyI0evUAckwPUGhuXE8inXEL+qerg0Eb9l8oVPFnL4NMzpMiZGs6jPJ7 v6MinsULU1oGO+fmKHypwMXg7tVqCluMDgbrLYMAtzQep/EtexeNK6/E4ttFNgK31mXj/KZ+ Apesh+CFngkanzA1AjyWN8nESD8Qv5nApyRn8Org8DhxUvk9A3Vknj16vneYzgEXmELgxUJu N1w6ZaULgZiVcg0A/nUunxEKF4B23U1CKJYBnMk9CR63bFhsHqEeQOtIkaffCWBeYyXhdtFc KJyprxK5BV9OS0Ht5WPAXZDcbwCaZ8/QbpcPFwVbc1YeYYp7Ed5ucYrcWMJFwIVBLSXkPQd7 L14nCwHLem3yPaN+gmUrvFI++8hCblry2ipI93zINYlhpWOVEHr3Q3vxvEjAPnDeZvKcvQNe M+g981Vwpm2JFPCX0KK3efBeeGvoAe3OJbmXYXNnsEC/DYfrKoCbhpw3nPpjq7CCN/zWXEYK tAQW6KSCexc8pS/+L3SowexZDMOHkxN0KdhpfOIY4xPHGP/PrQZkI9jOp2uUCl4TmspnBmnk Sk16qiIoXqVsAZu/fW3D5uoA9fOLQX2AYEEfgCwp85Xosk0KqSRBnvUFr1Z9rE5P4TV9wJ+l ZNsltb1ahZRTyNP4z3j+CK9+rBKsl18O8X16Lr/sd18R+NK+RD9nxaIqOmNntar7cNqEf82l fRF9v3pl7uJuXG5nE/7OfOqN2E8M4/EKn2/ygkOjS/RiJi5XG713tYPcn2UYejpq9Kh99v2v ayMdiUbpHUZS9KoyW8p9fldfjE5ntc6GHbBuhK+l6bCpaR6fcKmcyuU1ouGjpOd9Pixr948s SSt4x3wozDvVMgDH1uLX3wooC3/h0O9JMaVlqutfxYVt616Zi8F7fN/tf6bvrDJgdEts1Dp2 OXqKnbKumsKggKiCqcC4EddSzYU7V/dw2Y7TB3MGH2wLD95tkBgy3vv04NK50LqAitzXbiZm r42HnK+L5C1lpclqGaVJkr/+CqnWyP8F9eu8UEoEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xe7pLnmxNN9jXbGRx4voiJoutv2ex W6zZe47JYv6Rc6wW9y5tYbK48vU9m8W6pxfYLV7sbWSxuLZiLrtF87H1bBYvZ91js/jYc4/V 4vKuOWwWn3uPMFps+9zCZrH2yF12i/Vf5zNZLPy4lcViyY5djBZtnctYLS6ecrW4e+8Ei8XL yz3MFm2z+C3+79nBbvHv2kYWi9nv9rNbbHkzkdXi+Npwi5b9U1gc5Dze32hl93jz8iWLx+GO L+wee78tYPHYOesuu0fPzjOMHptWdbJ53Lm2h81j3slAj/vdx5k8Ni+p92hZe4zJo/+vgcf7 fVfZPPq2rGL0uNR8nT1AKErPpii/tCRVISO/uMRWKdrQwkjP0NJCz8jEUs/Q2DzWyshUSd/O JiU1J7MstUjfLkEvY+aLySwFrzgqVu4/z9bAuIG9i5GTQ0LAROLfzuNMXYxcHEICSxklbl7e wwqRkJG41v2SBcIWlvhzrYsNougVo8SGNf/ButkEjCQeLJ8P1iAisJhFYu++SpAiZoG3jBLX Z24E6xYW8JHY3PCVDcRmEVCVuL/pDVgDr4CDxPszrVAb5CX2HzzL3MXIwcEJFN93UQokLCRg L3Gu7z5UuaDEyZlPwMqZgcqbt85mnsAoMAtJahaS1AJGplWMIqmlxbnpucWGesWJucWleel6 yfm5mxiB6WXbsZ+bdzDOe/VR7xAjEwfjIUYJDmYlEd62+i3pQrwpiZVVqUX58UWlOanFhxhN gc6eyCwlmpwPTHB5JfGGZgamhiZmlgamlmbGSuK8bpfPpwkJpCeWpGanphakFsH0MXFwSjUw xbnrrFVQ7UpZYLdw05XXT5VtJs3MXJD/VTwrsHrn2t6LB361nS5eeU1/UnxgGWN/VRRbLkfm j0flIn7Ocy4K7JLJVGjQmHXXv2jmtm2n2SKcyr7vTEptOtMWGb6fUWV/h+Xvh7Lab/zehfKv Sjscuf1B7dTQpt38j55+PPS7bu9sjW9MUocvLflSf/FHJ//FjdVPQkR+bCl8qS7AJVXN3mzh mcW06Z54RbtBj1ACV/iOt6ZJGc7/JyTz/vn5Z+1/4aq4tb2rxYqKNJI+OFkuazg4l2XyG7Wt Rcf+5yx7uUK6e9rJYwZlHywPnBTlOLtNurki76h31MfSk2VvDR9tXMA6W8y0zWxC3PJWn41n lFiKMxINtZiLihMBlOv5gbgDAAA= X-CMS-MailID: 20250219140316eucas1p29a76023868946f090f261bf78d5103e3 X-Msg-Generator: CA X-RootMTR: 20250219140316eucas1p29a76023868946f090f261bf78d5103e3 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250219140316eucas1p29a76023868946f090f261bf78d5103e3 References: <20250219140239.1378758-1-m.wilczynski@samsung.com> T-HEAD TH1520 SoC requires to put the GPU out of the reset state as part of the power-up sequence. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 474f31576a1b..6b34aab4b455 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "thead,th1520"; @@ -497,6 +498,12 @@ clk: clock-controller@ffef010000 { #clock-cells = <1>; }; + rst: reset-controller@ffef528000 { + compatible = "thead,th1520-reset"; + reg = <0xff 0xef528000 0x0 0x4f>; + #reset-cells = <1>; + }; + clk_vo: clock-controller@ffef528050 { compatible = "thead,th1520-clk-vo"; reg = <0xff 0xef528050 0x0 0xfb0>;