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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54816a55851sm287643e87.27.2025.02.21.07.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:52:05 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 17:52:00 +0200 Subject: [PATCH v3 2/8] dt-bindings: PCI: qcom-ep: describe optional IOMMU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250221-sar2130p-pci-v3-2-61a0fdfb75b4@linaro.org> References: <20250221-sar2130p-pci-v3-0-61a0fdfb75b4@linaro.org> In-Reply-To: <20250221-sar2130p-pci-v3-0-61a0fdfb75b4@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1585; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=8nVGeN+HC+bXQ8NfYsOEnO3Wa1b/eYod1wwftfqnfSc=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnuKEgtI/6KSbLukLpS9h+mZzvpXF9Pff7bFVH4 v5sTu3LsLWJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7ihIAAKCRAU23LtvoBl uPaqD/4w+FLDEY4jeoA7AMqattg5NHR8xblcA04R7vCcEJeQRH+8bnGRcxI4hEDE/omf2smZuIe e+UapEZkBweqQli9YOi1VoDx5+DRVCcKFkRV+MatufpG7N0I8ZBbqGaRVHtUbiFytlM9ZZaz9uS N/T167GeprtM+EuVDsja79i1zGS2TnA7AuB37U2A0BU+woqHkx0VcO+wKXhD2hII9gZFC1x7tPf drF+nkuX3m3trFacyOX5bwbEZ6HGgoBwec0WkyVtd7zYd7hQpKLpFzNCcjJ01EakZzm/ElTaS10 ALgKYpxW6qTt+KJQ3qQP+iuj5nbA7NJU/3BuME+IoHxWqt5KYL/kfZV4b+GqqsFgltJHHU3rx0+ rfw+My+MIb/96Pv6yH0NbkSdfJ5qNvnyKl6RKNBHM+D9ForcQArWm347a7d0pEMEBjKKpUzQThw 1uCzhofZE4vOnwkuyltSyAmGSFWrnvwy3oofppvAtjaa/pGzRmHJbAb/vtEctMlpPvplOxi17SU XMM9lcNrvPAA/wkWT2dSN1ha/aiHlHetkzvyfZzZ38uA19PjXZzbcyL60pDn/xGL9730+HUaRba ODYoTzKjwsQT1aT3YRZ+lLKYe9lKcwiVy8D9eAZ3bxqGsb3SBuR9NbE+WaaKPh4BZ5aqNmSSga2 IGhmaI0eAwnLAJg== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Some of Qualcomm platforms have an IOMMU unit between the PCIe IP and DDR. For example, SA8775P specifies the iommu alththough it is not a part of bindings. Change the schema in order to require the IOMMU for SA8775P and forbid it from being used on SDX55 (SM8450 will be handled in a later patch). This fixes the following warning: pcie-ep@1c10000: Unevaluated properties are not allowed ('iommus' was unexpected) Fixes: 9d3d5e75f31c ("dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC") Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 0c2ca4cfa3b190b3fb204f0d7142370734fb3534..6075361348352bb8d607acecc76189e28b03dc5b 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -75,6 +75,9 @@ properties: - const: doorbell - const: dma + iommus: + maxItems: 1 + reset-gpios: description: GPIO used as PERST# input signal maxItems: 1 @@ -162,6 +165,7 @@ allOf: maxItems: 2 interrupt-names: maxItems: 2 + iommus: false - if: properties: @@ -234,6 +238,8 @@ allOf: interrupt-names: minItems: 3 maxItems: 3 + required: + - iommus unevaluatedProperties: false From patchwork Fri Feb 21 15:52:03 2025 Content-Type: text/plain; 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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54816a55851sm287643e87.27.2025.02.21.07.52.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:52:09 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 17:52:03 +0200 Subject: [PATCH v3 5/8] dt-bindings: PCI: qcom-ep: add SAR2130P compatible Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250221-sar2130p-pci-v3-5-61a0fdfb75b4@linaro.org> References: <20250221-sar2130p-pci-v3-0-61a0fdfb75b4@linaro.org> In-Reply-To: <20250221-sar2130p-pci-v3-0-61a0fdfb75b4@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2475; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=2EB6HQ3Xg729UaJzi6eQwoGHABfEKMGzkAxaHZxQ0PY=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnuKEhIOyO9evi4YM+xJTK2NM4Yj/jKLQrJ9Snz KarRzpLmseJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7ihIQAKCRAU23LtvoBl uIa5D/95JI992C4uMMAmvNAtQO1N1b1d3cIaBQQVRB+Z6u8P4D13JhJcv4BtFqF0hzhQolon93z 9l3Xt0lR2aSvVR/1BELh26VmhYUXIMJJlan2zlWPz5VQ+TucKB+9gdO3gsoJvGcDx/e7p5uhjkC dM89xqHhbhO3Yj7Yuv5wDiYg7RhcQebXG5nrkTRaRK4XJC1+vJhfd2CG0Jq3T2hRXDDUGZqzuXg 5B50dWo/fCPli8sPsFf9Zj/aRFqTZzbMRD3LDu2aSU/YRzKCoUJkwY2q5+IZjoKDyFXn0zsHuf3 7Ei7ogJ+tO4A46l1sGyUNJZrhWnR2jtH1Z1cWOf137KJbT8Y62gbK4hHJtXDlCU0FMN3ApMAIPs Xg980d93pVpCE2ttFBhB4ZkZ13DkG1p8QwE24r7ynV7nRUf9Z8Xy583X3xRiDy5wLHUJFrqydz2 iyob4YM5FqEN317+gQBddC7V5v+XYKfhDMmHk1oRB0rRE2bt1zRmBTVMQknOn762+l1XvfcQYps lKXUmK5gvMjE/QW9Ck+fVLaL6zjaUuk+xxcK2fJpzmkWmBXylrojfbv2clYbpQv+IGDU7xS4S1b pbqm+OUBd+A7zktC5r1T52ZtIEYLmwQrlPQAMjO9H8g1vJ6D1Z48OB4qFpbV6mtuR95cCGJO41X okUVDAdDo5Pgung== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Add support for using the PCI controller in the endpoint mode on the SAR2130P platform. It is impossible to use fallback compatible to any other platform since SAR2130P uses slightly different set of clocks. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 36 ++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 2c1918ca30dcfa8decea684ff6bfe11c602bbc7e..ac3414203d383bbd1a520dc11f317a5da9ca33e4 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - qcom,sa8775p-pcie-ep + - qcom,sar2130p-pcie-ep - qcom,sdx55-pcie-ep - qcom,sm8450-pcie-ep - items: @@ -44,11 +45,11 @@ properties: clocks: minItems: 5 - maxItems: 8 + maxItems: 9 clock-names: minItems: 5 - maxItems: 8 + maxItems: 9 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two @@ -132,6 +133,37 @@ required: allOf: - $ref: pci-ep.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sar2130p-pcie-ep + then: + properties: + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe DDRSS SF TBU clock + - description: PCIe AGGRE NOC AXI clock + - description: PCIe CFG NOC AXI clock + - description: PCIe QMIP AHB clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: ddrss_sf_tbu + - const: aggre_noc_axi + - const: cnoc_sf_axi + - const: qmip_pcie_ahb + - if: properties: compatible: From patchwork Fri Feb 21 15:52:05 2025 Content-Type: text/plain; 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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54816a55851sm287643e87.27.2025.02.21.07.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 07:52:13 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 17:52:05 +0200 Subject: [PATCH v3 7/8] arm64: dts: qcom: sar2130p: add PCIe EP device nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250221-sar2130p-pci-v3-7-61a0fdfb75b4@linaro.org> References: <20250221-sar2130p-pci-v3-0-61a0fdfb75b4@linaro.org> In-Reply-To: <20250221-sar2130p-pci-v3-0-61a0fdfb75b4@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2669; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=b6PLMBw7yyw15o3VEzosQAWxFJYLV5zXvl5ZUGHocbU=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnuKEiLu4pfIYUZYk2R0MP9UobeotuKgNJ4Vvhf 444qj3IgI6JAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7ihIgAKCRAU23LtvoBl uOVzD/4wumWgTSyYzm8guT77vJxWxEvDxLtib6B0StQvn1OelUa5kd2rD9mt7iDV+uuxqVEcu5J QhjoQl99UqfezKsMhYiHN15aeVKVzP4c+ZDss+vog1iokW87cyNooH1Uk3uWoEA0mKeY0pXh8EJ 1Ouf5D16bMD/KaanyXnQzLLy9uvx4hA7cIQIgrvyG6calt+vBYuZhzZ40Z6wzcsVMYQ1rthHEk5 j5mNBXQb5eDQBdNSHJKB2pGMGxGQ5GsKlEodn2d092CeJop68Uni6wkmeycN5z8xLKZQjddi8Fa POLMzqLshMH5iHi477NCBWq4xmi/2xCxRUSmvCHTrQs/dgmQcb/jUTOSHicGmANOPXF9Oz4Mtjs QQwjryHC+bm8MkZOeR0JuP2TDL98czDcyqbsKs6GM7wZVEMOXgl3d1NjwpxuRGi0H3ZNcADhAtL SxpzxUrQ8rm/G0DZEOM+jKDaYecYlTbtrB8auPz1PweNuwpnfCkSoa7yuDltN3nyjU8zvoUm3O+ iprtfdKlHMgK50sk7Tj1WxRvS2pyjn5bZfDNsB3ued59hZV6LKRIMwcFwP0I4s2KKoiDpPN5sHs 0CKDHCzGjo7AeniTpfUqYKbMYvEFbmdmF2Uv5fDTi2slzoSbq4pxOMnR5i7oa4xwfAjD7b6UhZo Af2oEnk+Vto7skg== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On the Qualcomm AR2 Gen1 platform the second PCIe host can be used either as an RC or as an EP device. Add device node for the PCIe EP. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 61 ++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index dd832e6816be85817fd1ecc853f8d4c800826bc4..b45e9e2ae0357bd0c7d719eaf4fc1faa1cf913f2 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1474,6 +1474,67 @@ pcie@0 { }; }; + pcie1_ep: pcie-ep@1c08000 { + compatible = "qcom,sar2130p-pcie-ep"; + reg = <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40200000 0x0 0x1000000>, + <0x0 0x01c0b000 0x0 0x1000>, + <0x0 0x40002000 0x0 0x2000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio", + "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, + <&gcc GCC_QMIP_PCIE_AHB_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre_noc_axi", + "cnoc_sf_axi", + "qmip_pcie_ahb"; + + interrupts = , + , + ; + interrupt-names = "global", + "doorbell", + "dma"; + + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + iommus = <&apps_smmu 0x1e00 0x1>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + num-lanes = <2>; + + status = "disabled"; + }; + pcie1_phy: phy@1c0e000 { compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy"; reg = <0x0 0x01c0e000 0x0 0x2000>;