From patchwork Tue Feb 25 08:48:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Patchwork-Id: 868648 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE25625EFAB; Tue, 25 Feb 2025 08:52:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740473538; cv=none; b=XSet5TneKNpmsl4ALxctSyBcEjMnRqpnpGBMJ+2dp8ObcEU2nw5Yw2rsV9ISPkgBtg6ctOm6afFZi9Zrk1jHizDFiyypi0Q2MbsI2CyAErF1d+gvKdVynMAdzRgqpUZKkUjPQxwqIUvsz7Hqj8C+kOcgDQHx88m3TXU/+63Soxk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740473538; c=relaxed/simple; bh=iztAOqQ4NOYRaMk1P81xiA2ZjauH72u9D2X4LyJ9shQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=IfYT88ymgNxlhRTLRojaQ67jQggQ0Knysfbq8/vaFE7MGmNP3qeQVeaEcZsjw1BJZ4nNvgBCOJps+6KzzPsHR/LCkjP2PseWF4qxKJjKS3qIjQ1IfohEY54eEj5623aLCZwE46Q2XaBJSBfDCffiTckoO6NzZIL/oCte601ZNDU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=aTa3O6NT; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="aTa3O6NT" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51P7VbrL025554; Tue, 25 Feb 2025 09:52:01 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= DEnYecZ9bxA3ogrxmztmDHuaA4UedKniT4I6PXhC3Nc=; b=aTa3O6NTWMizL+0C EUy+HvayBzpe+HSK18Wu6n3TEzupgmkDlmA87/s10q6LoMc0WbivGw1QryO2hOFM PP34OBQu49BvDQghUDFF2WxOcqmzX1aEXK4uVMobNcMPq2koaZ4v6TQBHkkoYNik XNWXlJDzsfxXsm2Zcc8gnW490qFpQ25y+KbA6sCBCgsT41qKGe5wdSKmPKnbtbE6 xmKWdHhPz7utjk8IA1HKN8LMXcErWnFK1xKIm8hRJfk0cVn0iTo47FaXE1etlqWJ eVUBgl6MF1eeomUa7A64zG+qYFcpuzLSU483+3HhSC7trwMitFPXwIDKlQKXvWF0 V1H1fQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 4512spstfk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Feb 2025 09:52:01 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 1D74040059; Tue, 25 Feb 2025 09:50:50 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C563F47A6EA; Tue, 25 Feb 2025 09:48:06 +0100 (CET) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Feb 2025 09:48:06 +0100 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 25 Feb 2025 09:48:00 +0100 Subject: [PATCH 1/9] dt-bindings: pinctrl: stm32: Add HDP includes for stm32mp platforms Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250225-hdp-upstream-v1-1-9d049c65330a@foss.st.com> References: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> In-Reply-To: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-42535 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_03,2025-02-24_02,2024-11-22_01 Each file introduces helpers to choose the signal to monitor through the HDP pin. Signals are different for each platforms: stm32mp13, stm32mp15, stm32mp25. Signed-off-by: Clément Le Goffic --- include/dt-bindings/pinctrl/stm32mp13-hdp.h | 130 +++++++++++++++++++++++++ include/dt-bindings/pinctrl/stm32mp15-hdp.h | 116 ++++++++++++++++++++++ include/dt-bindings/pinctrl/stm32mp25-hdp.h | 144 ++++++++++++++++++++++++++++ 3 files changed, 390 insertions(+) diff --git a/include/dt-bindings/pinctrl/stm32mp13-hdp.h b/include/dt-bindings/pinctrl/stm32mp13-hdp.h new file mode 100644 index 000000000000..a3487e700143 --- /dev/null +++ b/include/dt-bindings/pinctrl/stm32mp13-hdp.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Clément Le Goffic for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP13_HDP_H +#define _DT_BINDINGS_STM32MP13_HDP_H + +/* define a macro for each function a HDP pin can transmit */ +#define HDP0_PWR_PWRWAKE_SYS "0" +#define HDP0_PWR_STOP_FORBIDDEN "1" +#define HDP0_PWR_STDBY_WAKEUP "2" +#define HDP0_PWR_ENCOMP_VDDCORE "3" +#define HDP0_BSEC_OUT_SEC_NIDEN "4" +#define HDP0_AIEC_SYS_WAKEUP "5" +#define HDP0_DDRCTRL_LP_REQ "8" +#define HDP0_PWR_DDR_RET_ENABLE_N "9" +#define HDP0_DTS_CLK_PTAT "10" +#define HDP0_SRAM3CTRL_TAMP_ERASE_ACT "12" +#define HDP0_GPOVAL_0 "15" + +#define HDP1_PWR_SEL_VTH_VDDCPU "0" +#define HDP1_PWR_MPU_RAM_LOWSPEED "1" +#define HDP1_CA7_NAXIERRIRQ "2" +#define HDP1_PWR_OKIN_MR "3" +#define HDP1_BSEC_OUT_SEC_DBGEN "4" +#define HDP1_AIEC_C1_WAKEUP "5" +#define HDP1_RCC_PWRDS_MPU "6" +#define HDP1_DDRCTRL_DFI_CTRLUPD_REQ "8" +#define HDP1_DDRCTRL_CACTIVE_DDRC_ASR "9" +#define HDP1_SRAM3CTRL_HW_ERASE_ACT "12" +#define HDP1_NIC400_S0_BREADY "13" +#define HDP1_GPOVAL_1 "15" + +#define HDP2_PWR_PWRWAKE_MPU "0" +#define HDP2_PWR_MPU_CLOCK_DISABLE_ACK "1" +#define HDP2_CA7_NDBGRESET_I "2" +#define HDP2_BSEC_IN_RSTCORE_N "4" +#define HDP2_BSEC_OUT_SEC_BSC_DIS "5" +#define HDP2_DDRCTRL_DFI_INIT_COMPLETE "8" +#define HDP2_DDRCTRL_PERF_OP_IS_REFRESH "9" +#define HDP2_DDRCTRL_GSKP_DFI_LP_REQ "10" +#define HDP2_SRAM3CTRL_SW_ERASE_ACT "12" +#define HDP2_NIC400_S0_BVALID "13" +#define HDP2_GPOVAL_2 "15" + +#define HDP3_PWR_SEL_VTH_VDDCORE "0" +#define HDP3_PWR_MPU_CLOCK_DISABLE_REQ "1" +#define HDP3_CA7_NPMUIRQ0 "2" +#define HDP3_CA7_NFIQOUT0 "3" +#define HDP3_BSEC_OUT_SEC_DFTLOCK "4" +#define HDP3_BSEC_OUT_SEC_JTAG_DIS "5" +#define HDP3_RCC_PWRDS_SYS "6" +#define HDP3_SRAM3CTRL_TAMP_ERASE_REQ "7" +#define HDP3_DDRCTRL_STAT_DDRC_REG_SELFREF_TYPE0 "8" +#define HDP3_DTS_VALOBUS1_0 "10" +#define HDP3_DTS_VALOBUS2_0 "11" +#define HDP3_TAMP_POTENTIAL_TAMP_ERFCFG "12" +#define HDP3_NIC400_S0_WREADY "13" +#define HDP3_NIC400_S0_RREADY "14" +#define HDP3_GPOVAL_3 "15" + +#define HDP4_PWR_STOP2_ACTIVE "1" +#define HDP4_CA7_NL2RESET_I "2" +#define HDP4_CA7_NPORESET_VARM_I "3" +#define HDP4_BSEC_OUT_SEC_DFTEN "4" +#define HDP4_BSEC_OUT_SEC_DBGSWENABLE "5" +#define HDP4_ETH1_OUT_PMT_INTR_O "6" +#define HDP4_ETH2_OUT_PMT_INTR_O "7" +#define HDP4_DDRCTRL_STAT_DDRC_REG_SELFREF_TYPE1 "8" +#define HDP4_DDRCTRL_CACTIVE_0 "9" +#define HDP4_DTS_VALOBUS1_1 "10" +#define HDP4_DTS_VALOBUS2_1 "11" +#define HDP4_TAMP_NRESET_SRAM_ERCFG "12" +#define HDP4_NIC400_S0_WLAST "13" +#define HDP4_NIC400_S0_RLAST "14" +#define HDP4_GPOVAL_4 "15" + +#define HDP5_CA7_STANDBYWFIL2 "0" +#define HDP5_PWR_VTH_VDDCORE_ACK "1" +#define HDP5_CA7_NCORERESET_I "2" +#define HDP5_CA7_NIRQOUT0 "3" +#define HDP5_BSEC_IN_PWROK "4" +#define HDP5_BSEC_OUT_SEC_DEVICEEN "5" +#define HDP5_ETH1_OUT_LPI_INTR_O "6" +#define HDP5_ETH2_OUT_LPI_INTR_O "7" +#define HDP5_DDRCTRL_CACTIVE_DDRC "8" +#define HDP5_DDRCTRL_WR_CREDIT_CNT "9" +#define HDP5_DTS_VALOBUS1_2 "10" +#define HDP5_DTS_VALOBUS2_2 "11" +#define HDP5_PKA_PKA_ITAMP_OUT "12" +#define HDP5_NIC400_S0_WVALID "13" +#define HDP5_NIC400_S0_RVALID "14" +#define HDP5_GPOVAL_5 "15" + +#define HDP6_CA7_STANDBYWFE0 "0" +#define HDP6_PWR_VTH_VDDCPU_ACK "1" +#define HDP6_CA7_EVENTO "2" +#define HDP6_BSEC_IN_TAMPER_DET "4" +#define HDP6_BSEC_OUT_SEC_SPNIDEN "5" +#define HDP6_ETH1_OUT_MAC_SPEED_O1 "6" +#define HDP6_ETH2_OUT_MAC_SPEED_O1 "7" +#define HDP6_DDRCTRL_CSYSACK_DDRC "8" +#define HDP6_DDRCTRL_LPR_CREDIT_CNT "9" +#define HDP6_DTS_VALOBUS1_3 "10" +#define HDP6_DTS_VALOBUS2_3 "11" +#define HDP6_SAES_TAMPER_OUT "12" +#define HDP6_NIC400_S0_AWREADY "13" +#define HDP6_NIC400_S0_ARREADY "14" +#define HDP6_GPOVAL_6 "15" + +#define HDP7_CA7_STANDBYWFI0 "0" +#define HDP7_PWR_RCC_VCPU_RDY "1" +#define HDP7_CA7_EVENTI "2" +#define HDP7_CA7_DBGACK0 "3" +#define HDP7_BSEC_OUT_FUSE_OK "4" +#define HDP7_BSEC_OUT_SEC_SPIDEN "5" +#define HDP7_ETH1_OUT_MAC_SPEED_O0 "6" +#define HDP7_ETH2_OUT_MAC_SPEED_O0 "7" +#define HDP7_DDRCTRL_CSYSREQ_DDRC "8" +#define HDP7_DDRCTRL_HPR_CREDIT_CNT "9" +#define HDP7_DTS_VALOBUS1_4 "10" +#define HDP7_DTS_VALOBUS2_4 "11" +#define HDP7_RNG_TAMPER_OUT "12" +#define HDP7_NIC400_S0_AWAVALID "13" +#define HDP7_NIC400_S0_ARAVALID "14" +#define HDP7_GPOVAL_7 "15" + +#endif /* _DT_BINDINGS_STM32MP13_HDP_H */ diff --git a/include/dt-bindings/pinctrl/stm32mp15-hdp.h b/include/dt-bindings/pinctrl/stm32mp15-hdp.h new file mode 100644 index 000000000000..ac32cec5a9f6 --- /dev/null +++ b/include/dt-bindings/pinctrl/stm32mp15-hdp.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Clément Le Goffic for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP15_HDP_H +#define _DT_BINDINGS_STM32MP15_HDP_H + +/* define a macro for each function a HDP pin can transmit */ +#define HDP0_PWR_PWRWAKE_SYS "0" +#define HDP0_CM4_SLEEPDEEP "1" +#define HDP0_PWR_STDBY_WKUP "2" +#define HDP0_PWR_ENCOMP_VDDCORE "3" +#define HDP0_BSEC_OUT_SEC_NIDEN "4" +#define HDP0_RCC_CM4_SLEEPDEEP "6" +#define HDP0_GPU_DBG7 "7" +#define HDP0_DDRCTRL_LP_REQ "8" +#define HDP0_PWR_DDR_RET_ENABLE_N "9" +#define HDP0_DTS_CLK_PTAT "10" +#define HDP0_GPOVAL_0 "15" + +#define HDP1_PWR_PWRWAKE_MCU "0" +#define HDP1_CM4_HALTED "1" +#define HDP1_CA7_NAXIERRIRQ "2" +#define HDP1_PWR_OKIN_MR "3" +#define HDP1_BSEC_OUT_SEC_DBGEN "4" +#define HDP1_EXTI_SYS_WAKEUP "5" +#define HDP1_RCC_PWRDS_MPU "6" +#define HDP1_GPU_DBG6 "7" +#define HDP1_DDRCTRL_DFI_CTRLUPD_REQ "8" +#define HDP1_DDRCTRL_CACTIVE_DDRC_ASR "9" +#define HDP1_GPOVAL_1 "15" + +#define HDP2_PWR_PWRWAKE_MPU "0" +#define HDP2_CM4_RXEV "1" +#define HDP2_CA7_NPMUIRQ1 "2" +#define HDP2_CA7_NFIQOUT1 "3" +#define HDP2_BSEC_IN_RSTCORE_N "4" +#define HDP2_EXTI_C2_WAKEUP "5" +#define HDP2_RCC_PWRDS_MCU "6" +#define HDP2_GPU_DBG5 "7" +#define HDP2_DDRCTRL_DFI_INIT_COMPLETE "8" +#define HDP2_DDRCTRL_PERF_OP_IS_REFRESH "9" +#define HDP2_DDRCTRL_GSKP_DFI_LP_REQ "10" +#define HDP2_GPOVAL_2 "15" + +#define HDP3_PWR_SEL_VTH_VDDCORE "0" +#define HDP3_CM4_TXEV "1" +#define HDP3_CA7_NPMUIRQ0 "2" +#define HDP3_CA7_NFIQOUT0 "3" +#define HDP3_BSEC_OUT_SEC_DFTLOCK "4" +#define HDP3_EXTI_C1_WAKEUP "5" +#define HDP3_RCC_PWRDS_SYS "6" +#define HDP3_GPU_DBG4 "7" +#define HDP3_DDRCTRL_STAT_DDRC_REG_SELFREF_TYPE0 "8" +#define HDP3_DDRCTRL_CACTIVE_1 "9" +#define HDP3_DTS_VALOBUS1_0 "10" +#define HDP3_DTS_VALOBUS2_0 "11" +#define HDP3_GPOVAL_3 "15" + +#define HDP4_PWR_PDDS_NOT_CSTBYDIS "0" +#define HDP4_CM4_SLEEPING "1" +#define HDP4_CA7_NRESET1 "2" +#define HDP4_CA7_NIRQOUT1 "3" +#define HDP4_BSEC_OUT_SEC_DFTEN "4" +#define HDP4_BSEC_OUT_SEC_DBGSWENABLE "5" +#define HDP4_ETH_OUT_PMT_INTR_O "6" +#define HDP4_GPU_DBG3 "7" +#define HDP4_DDRCTRL_STAT_DDRC_REG_SELFREF_TYPE1 "8" +#define HDP4_DDRCTRL_CACTIVE_0 "9" +#define HDP4_DTS_VALOBUS1_1 "10" +#define HDP4_DTS_VALOBUS2_1 "11" +#define HDP4_GPOVAL_4 "15" + +#define HDP5_CA7_STANDBYWFIL2 "0" +#define HDP5_PWR_VTH_VDDCORE_ACK "1" +#define HDP5_CA7_NRESET0 "2" +#define HDP5_CA7_NIRQOUT0 "3" +#define HDP5_BSEC_IN_PWROK "4" +#define HDP5_BSEC_OUT_SEC_DEVICEEN "5" +#define HDP5_ETH_OUT_LPI_INTR_O "6" +#define HDP5_GPU_DBG2 "7" +#define HDP5_DDRCTRL_CACTIVE_DDRC "8" +#define HDP5_DDRCTRL_WR_CREDIT_CNT "9" +#define HDP5_DTS_VALOBUS1_2 "10" +#define HDP5_DTS_VALOBUS2_2 "11" +#define HDP5_GPOVAL_5 "15" + +#define HDP6_CA7_STANDBYWFI1 "0" +#define HDP6_CA7_STANDBYWFE1 "1" +#define HDP6_CA7_EVENTO "2" +#define HDP6_CA7_DBGACK1 "3" +#define HDP6_BSEC_OUT_SEC_SPNIDEN "5" +#define HDP6_ETH_OUT_MAC_SPEED_O1 "6" +#define HDP6_GPU_DBG1 "7" +#define HDP6_DDRCTRL_CSYSACK_DDRC "8" +#define HDP6_DDRCTRL_LPR_CREDIT_CNT "9" +#define HDP6_DTS_VALOBUS1_3 "10" +#define HDP6_DTS_VALOBUS2_3 "11" +#define HDP6_GPOVAL_6 "15" + +#define HDP7_CA7_STANDBYWFI0 "0" +#define HDP7_CA7_STANDBYWFE0 "1" +#define HDP7_CA7_DBGACK0 "3" +#define HDP7_BSEC_OUT_FUSE_OK "4" +#define HDP7_BSEC_OUT_SEC_SPIDEN "5" +#define HDP7_ETH_OUT_MAC_SPEED_O0 "6" +#define HDP7_GPU_DBG0 "7" +#define HDP7_DDRCTRL_CSYSREQ_DDRC "8" +#define HDP7_DDRCTRL_HPR_CREDIT_CNT "9" +#define HDP7_DTS_VALOBUS1_4 "10" +#define HDP7_DTS_VALOBUS2_4 "11" +#define HDP7_GPOVAL_7 "15" + +#endif /* _DT_BINDINGS_STM32MP15_HDP_H */ diff --git a/include/dt-bindings/pinctrl/stm32mp25-hdp.h b/include/dt-bindings/pinctrl/stm32mp25-hdp.h new file mode 100644 index 000000000000..bc84042f1605 --- /dev/null +++ b/include/dt-bindings/pinctrl/stm32mp25-hdp.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Clément Le Goffic for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP25_HDP_H +#define _DT_BINDINGS_STM32MP25_HDP_H + +/* define a macro for each function a HDP pin can transmit */ +#define HDP0_PWR_PWRWAKE_SYS "0" +#define HDP0_CPU2_SLEEP_DEEP "1" +#define HDP0_BSEC_OUT_TST_SDR_UNLOCK_OR_DISABLE_SCAN "2" +#define HDP0_BSEC_OUT_NIDENM "3" +#define HDP0_BSEC_OUT_NIDENA "4" +#define HDP0_CPU2_STATE_0 "5" +#define HDP0_RCC_PWRDS_SYS "6" +#define HDP0_GPU_DBG7 "7" +#define HDP0_DDRSS_CSYSREQ_DDRC "8" +#define HDP0_DDRSS_DFI_PHYUPD_REQ "9" +#define HDP0_CPU3_SLEEP_DEEP "10" +#define HDP0_D2_GBL_PER_CLK_BUS_REQ "11" +#define HDP0_PCIE_USB_CXPL_DEBUG_INFO_EI_0 "12" +#define HDP0_PCIE_USB_CXPL_DEBUG_INFO_EI_8 "13" +#define HDP0_D3_STATE_0 "14" +#define HDP0_GPOVAL_0 "15" + +#define HDP1_PWR_PWRWAKE_CPU2 "0" +#define HDP1_CPU2_HALTED "1" +#define HDP1_CPU2_STATE_1 "2" +#define HDP1_BSEC_OUT_DBGENM "3" +#define HDP1_BSEC_OUT_DBGENA "4" +#define HDP1_EXTI1_SYS_WAKEUP "5" +#define HDP1_RCC_PWRDS_CPU2 "6" +#define HDP1_GPU_DBG6 "7" +#define HDP1_DDRSS_CSYSACK_DDRC "8" +#define HDP1_DDRSS_DFI_PHYMSTR_REQ "9" +#define HDP1_CPU3_HALTED "10" +#define HDP1_D2_GBL_PER_DMA_REQ "11" +#define HDP1_PCIE_USB_CXPL_DEBUG_INFO_EI_1 "12" +#define HDP1_PCIE_USB_CXPL_DEBUG_INFO_EI_9 "13" +#define HDP1_D3_STATE_1 "14" +#define HDP1_GPOVAL_1 "15" + +#define HDP2_PWR_PWRWAKE_CPU1 "0" +#define HDP2_CPU2_RXEV "1" +#define HDP2_CPU1_NPMUIRQ1 "2" +#define HDP2_CPU1_NFIQOUT1 "3" +#define HDP2_BSEC_OUT_SHDBGEN "4" +#define HDP2_EXTI1_CPU2_WAKEUP "5" +#define HDP2_RCC_PWRDS_CPU1 "6" +#define HDP2_GPU_DBG5 "7" +#define HDP2_DDRSS_CACTIVE_DDRC "8" +#define HDP2_DDRSS_DFI_LP_REQ "9" +#define HDP2_CPU3_RXEV "10" +#define HDP2_HPDMA1_CLK_BUS_REQ "11" +#define HDP2_PCIE_USB_CXPL_DEBUG_INFO_EI_2 "12" +#define HDP2_PCIE_USB_CXPL_DEBUG_INFO_EI_10 "13" +#define HDP2_D3_STATE_2 "14" +#define HDP2_GPOVAL_2 "15" + +#define HDP3_PWR_SEL_VTH_VDDCPU "0" +#define HDP3_CPU2_TXEV "1" +#define HDP3_CPU1_NPMUIRQ0 "2" +#define HDP3_CPU1_NFIQOUT0 "3" +#define HDP3_BSEC_OUT_DDBGEN "4" +#define HDP3_EXTI1_CPU1_WAKEUP "5" +#define HDP3_CPU3_STATE_0 "6" +#define HDP3_GPU_DBG4 "7" +#define HDP3_DDRSS_MCDCG_EN "8" +#define HDP3_DDRSS_DFI_FREQ_0 "9" +#define HDP3_CPU3_TXEV "10" +#define HDP3_HPDMA2_CLK_BUS_REQ "11" +#define HDP3_PCIE_USB_CXPL_DEBUG_INFO_EI_3 "12" +#define HDP3_PCIE_USB_CXPL_DEBUG_INFO_EI_11 "13" +#define HDP3_D1_STATE_0 "14" +#define HDP3_GPOVAL_3 "15" + +#define HDP4_PWR_SEL_VTH_VDDCORE "0" +#define HDP4_CPU2_SLEEPING "1" +#define HDP4_CPU1_EVENTO "2" +#define HDP4_CPU1_NIRQOUT1 "3" +#define HDP4_BSEC_OUT_SPNIDENA "4" +#define HDP4_EXTI2_D3_WAKEUP "5" +#define HDP4_ETH1_OUT_PMT_INTR_O "6" +#define HDP4_GPU_DBG3 "7" +#define HDP4_DDRSS_DPHYCG_EN "8" +#define HDP4_DDRSS_OBSP0 "9" +#define HDP4_CPU3_SLEEPING "10" +#define HDP4_HPDMA3_CLK_BUS_REQ "11" +#define HDP4_PCIE_USB_CXPL_DEBUG_INFO_EI_4 "12" +#define HDP4_PCIE_USB_CXPL_DEBUG_INFO_EI_12 "13" +#define HDP4_D1_STATE_1 "14" +#define HDP4_GPOVAL_4 "15" + +#define HDP5_CPU1_STANDBY_WFIL2 "0" +#define HDP5_CPU1_NIRQOUT0 "3" +#define HDP5_BSEC_OUT_SPIDENA "4" +#define HDP5_EXTI2_CPU3_WAKEUP "5" +#define HDP5_ETH1_OUT_LPI_INTR_O "6" +#define HDP5_GPU_DBG2 "7" +#define HDP5_DDRCTRL_DFI_INIT_START "8" +#define HDP5_DDRSS_OBSP1 "9" +#define HDP5_CPU3_STATE_1 "10" +#define HDP5_D3_GBL_PER_CLK_BUS_REQ "11" +#define HDP5_PCIE_USB_CXPL_DEBUG_INFO_EI_5 "12" +#define HDP5_PCIE_USB_CXPL_DEBUG_INFO_EI_13 "13" +#define HDP5_D1_STATE_2 "14" +#define HDP5_GPOVAL_5 "15" + +#define HDP6_CPU1_STANDBY_WFI1 "0" +#define HDP6_CPU1_STANDBY_WFE1 "1" +#define HDP6_CPU1_HALTED1 "2" +#define HDP6_CPU1_NAXIERRIRQ "3" +#define HDP6_BSEC_OUT_SPNIDENM "4" +#define HDP6_EXTI2_CPU2_WAKEUP "5" +#define HDP6_ETH2_OUT_PMT_INTR_O "6" +#define HDP6_GPU_DBG1 "7" +#define HDP6_DDRSS_DFI_INIT_COMPLETE "8" +#define HDP6_DDRSS_OBSP2 "9" +#define HDP6_D2_STATE_0 "10" +#define HDP6_D3_GBL_PER_DMA_REQ "11" +#define HDP6_PCIE_USB_CXPL_DEBUG_INFO_EI_6 "12" +#define HDP6_PCIE_USB_CXPL_DEBUG_INFO_EI_14 "13" +#define HDP6_CPU1_STATE_0 "14" +#define HDP6_GPOVAL_6 "15" + +#define HDP7_CPU1_STANDBY_WFI0 "0" +#define HDP7_CPU1_STANDBY_WFE0 "1" +#define HDP7_CPU1_HALTED0 "2" +#define HDP7_BSEC_OUT_SPIDENM "4" +#define HDP7_EXTI2_CPU1__WAKEUP "5" +#define HDP7_ETH2_OUT_LPI_INTR_O "6" +#define HDP7_GPU_DBG0 "7" +#define HDP7_DDRSS_DFI_CTRLUPD_REQ "8" +#define HDP7_DDRSS_OBSP3 "9" +#define HDP7_D2_STATE_1 "10" +#define HDP7_LPDMA1_CLK_BUS_REQ "11" +#define HDP7_PCIE_USB_CXPL_DEBUG_INFO_EI_7 "12" +#define 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'HDP' stands for Hardware Debug Port, it is an hardware block in STMicrolectronics' MPUs that let the user decide which internal SoC's signal to observe. It provides 8 ports and for each port there is up to 16 different signals that can be output. Signals are different for each MPU. Signed-off-by: Clément Le Goffic --- .../bindings/pinctrl/st,stm32-pinctrl-hdp.yaml | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl-hdp.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl-hdp.yaml new file mode 100644 index 000000000000..b6787162faaa --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl-hdp.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) STMicroelectronics 2025. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl-hdp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Hardware Debug Port Mux/Config + +maintainers: + - Clément LE GOFFIC + +description: | + STMicroelectronics's STM32 MPUs integrate a Hardware Debug Port (HDP). + It allows to output internal signals on SoC's GPIO. + +properties: + compatible: + const: st,stm32mp-hdp + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + + properties: + function: + enum: [ "0", "1", "2", "3", "4", "5", "6", "7", + "8", "9", "10", "11", "12", "13", "14", + "15" ] + + pins: + enum: [ hdp0, hdp1, hdp2, hdp3, hdp4, hdp5, hdp6, hdp7 ] + + required: + - function + - pins + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + //Example 1 + pinctrl@54090000 { + compatible = "st,stm32mp-hdp"; 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Tue, 25 Feb 2025 09:50:51 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 386AF47A7A8; Tue, 25 Feb 2025 09:48:08 +0100 (CET) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Feb 2025 09:48:07 +0100 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 25 Feb 2025 09:48:02 +0100 Subject: [PATCH 3/9] pinctrl: stm32: Introduce HDP driver Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250225-hdp-upstream-v1-3-9d049c65330a@foss.st.com> References: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> In-Reply-To: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-42535 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_03,2025-02-24_02,2024-11-22_01 This patch introduce the driver for the Hardware Debug Port available on STM32MP platforms. The HDP allows the observation of internal SoC signals by using multiplexers. Each HDP port can provide up to 16 internal signals (one of them can be software controlled as a GPO) Signed-off-by: Clément Le Goffic --- drivers/pinctrl/stm32/Kconfig | 14 ++ drivers/pinctrl/stm32/Makefile | 1 + drivers/pinctrl/stm32/pinctrl-stm32-hdp.c | 301 ++++++++++++++++++++++++++++++ 3 files changed, 316 insertions(+) diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index 2656d3d3ae40..4b474cfd1f2c 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -57,4 +57,18 @@ config PINCTRL_STM32MP257 depends on OF && HAS_IOMEM default MACH_STM32MP25 select PINCTRL_STM32 + +config PINCTRL_STM32_HDP + tristate "STMicroelectronics STM32 Hardware Debug Port (HDP) pin control" + depends on OF && HAS_IOMEM + default ARM64 || (ARM && CPU_V7) + select PINMUX + select GENERIC_PINCONF + select GPIOLIB + help + The Hardware Debug Port allows the observation of internal signals. + It uses configurable multiplexer to route signals in a dedicated observation register. + This driver also permits the observation of signals on external SoC pins. + It permits the observation of up to 16 signals per HDP line. + endif diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile index 7b17464d8de1..98a1bbc7e16c 100644 --- a/drivers/pinctrl/stm32/Makefile +++ b/drivers/pinctrl/stm32/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o obj-$(CONFIG_PINCTRL_STM32MP135) += pinctrl-stm32mp135.o obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o obj-$(CONFIG_PINCTRL_STM32MP257) += pinctrl-stm32mp257.o +obj-$(CONFIG_PINCTRL_STM32_HDP) += pinctrl-stm32-hdp.o diff --git a/drivers/pinctrl/stm32/pinctrl-stm32-hdp.c b/drivers/pinctrl/stm32/pinctrl-stm32-hdp.c new file mode 100644 index 000000000000..e937d9b9f77a --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32-hdp.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Clément Le Goffic for STMicroelectronics. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" + +#define DRIVER_NAME "stm32_hdp" +#define HDP_CTRL_ENABLE 1 +#define HDP_CTRL_DISABLE 0 +#define NB_FUNCTIONS 16 + +#define HDP_CTRL 0x000 +#define HDP_MUX 0x004 +#define HDP_VAL 0x010 +#define HDP_GPOSET 0x014 +#define HDP_GPOCLR 0x018 +#define HDP_GPOVAL 0x01c +#define HDP_VERR 0x3f4 +#define HDP_IPIDR 0x3f8 +#define HDP_SIDR 0x3fc + +#define HDP_MUX_SHIFT(n) ((n) * 4) +#define HDP_MUX_MASK(n) (GENMASK(3, 0) << HDP_MUX_SHIFT(n)) +#define HDP_MUX_GPOVAL(n) (0xf << HDP_MUX_SHIFT(n)) + +struct stm32_hdp { + struct device *dev; + void __iomem *base; + struct clk *clk; + struct pinctrl_dev *pctl_dev; + struct gpio_chip gpio_chip; + u32 mux_conf; + u32 gposet_conf; +}; + +static const struct pinctrl_pin_desc stm32_hdp_pins[] = { + PINCTRL_PIN(0, "hdp0"), + PINCTRL_PIN(1, "hdp1"), + PINCTRL_PIN(2, "hdp2"), + PINCTRL_PIN(3, "hdp3"), + PINCTRL_PIN(4, "hdp4"), + PINCTRL_PIN(5, "hdp5"), + PINCTRL_PIN(6, "hdp6"), + PINCTRL_PIN(7, "hdp7"), +}; + +static const char * const func_name[] = { + "0", "1", "2", "3", + "4", "5", "6", "7", + "8", "9", "10", "11", + "12", "13", "14", "15", +}; + +static const char * const stm32_hdp_pins_group[] = { + "hdp0", + "hdp1", + "hdp2", + "hdp3", + "hdp4", + "hdp5", + "hdp6", + "hdp7" +}; + +static int stm32_hdp_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) +{ + return GPIO_LINE_DIRECTION_OUT; +} + +static int stm32_hdp_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct stm32_hdp *hdp = gpiochip_get_data(gc); + + if (((hdp->mux_conf & HDP_MUX_MASK(offset))) == HDP_MUX_GPOVAL(offset)) + return !!(readl_relaxed(hdp->base + HDP_GPOVAL) & BIT(offset)); + else + return !!(readl_relaxed(hdp->base + HDP_VAL) & BIT(offset)); +} + +static void stm32_hdp_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) +{ + struct stm32_hdp *hdp = gpiochip_get_data(gc); + + if (value) + writel_relaxed(BIT(offset), hdp->base + HDP_GPOSET); + else + writel_relaxed(BIT(offset), hdp->base + HDP_GPOCLR); +} + +static int stm32_hdp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(stm32_hdp_pins); +} + +static const char *stm32_hdp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return stm32_hdp_pins[selector].name; +} + +static int stm32_hdp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + *pins = &stm32_hdp_pins[selector].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops stm32_hdp_pinctrl_ops = { + .get_groups_count = stm32_hdp_pinctrl_get_groups_count, + .get_group_name = stm32_hdp_pinctrl_get_group_name, + .get_group_pins = stm32_hdp_pinctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static int stm32_hdp_pinmux_get_functions_count(struct pinctrl_dev *pctldev) +{ + return NB_FUNCTIONS; +} + +static const char *stm32_hdp_pinmux_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return func_name[selector]; +} + +static int stm32_hdp_pinmux_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char *const **groups, + unsigned int *num_groups) +{ + *groups = stm32_hdp_pins_group; + *num_groups = ARRAY_SIZE(stm32_hdp_pins_group); + + return 0; +} + +static int stm32_hdp_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, + unsigned int group_selector) +{ + struct stm32_hdp *hdp = pinctrl_dev_get_drvdata(pctldev); + unsigned int pin = stm32_hdp_pins[group_selector].number; + u32 mux; + + mux = readl_relaxed(hdp->base + HDP_MUX); + mux &= ~HDP_MUX_MASK(pin); + mux |= func_selector << HDP_MUX_SHIFT(pin); + + writel_relaxed(mux, hdp->base + HDP_MUX); + hdp->mux_conf = mux; + + return 0; +} + +static const struct pinmux_ops stm32_hdp_pinmux_ops = { + .get_functions_count = stm32_hdp_pinmux_get_functions_count, + .get_function_name = stm32_hdp_pinmux_get_function_name, + .get_function_groups = stm32_hdp_pinmux_get_function_groups, + .set_mux = stm32_hdp_pinmux_set_mux, + .gpio_set_direction = NULL, +}; + +static struct pinctrl_desc stm32_hdp_pdesc = { + .name = DRIVER_NAME, + .pins = stm32_hdp_pins, + .npins = ARRAY_SIZE(stm32_hdp_pins), + .pctlops = &stm32_hdp_pinctrl_ops, + .pmxops = &stm32_hdp_pinmux_ops, + .owner = THIS_MODULE, +}; + +static const struct of_device_id stm32_hdp_of_match[] = { + { + .compatible = "st,stm32mp-hdp" + }, + {} +}; + +static int stm32_hdp_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct stm32_hdp *hdp; + u8 version; + int err; + + hdp = devm_kzalloc(dev, sizeof(*hdp), GFP_KERNEL); + if (!hdp) + return -ENOMEM; + hdp->dev = dev; + + platform_set_drvdata(pdev, hdp); + + hdp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(hdp->base)) + return PTR_ERR(hdp->base); + + hdp->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(hdp->clk)) + return dev_err_probe(dev, PTR_ERR(hdp->clk), "No HDP clock provided\n"); + + err = devm_pinctrl_register_and_init(dev, &stm32_hdp_pdesc, hdp, &hdp->pctl_dev); + if (err) + return dev_err_probe(dev, err, "Failed to register pinctrl\n"); + + err = pinctrl_enable(hdp->pctl_dev); + if (err) + return dev_err_probe(dev, err, "Failed to enable pinctrl\n"); + + hdp->gpio_chip.label = "stm32-hdp"; + hdp->gpio_chip.parent = dev; + hdp->gpio_chip.get_direction = stm32_hdp_gpio_get_direction; + hdp->gpio_chip.get = stm32_hdp_gpio_get; + hdp->gpio_chip.set = stm32_hdp_gpio_set; + hdp->gpio_chip.base = -1; + hdp->gpio_chip.ngpio = ARRAY_SIZE(stm32_hdp_pins); + hdp->gpio_chip.can_sleep = true; + hdp->gpio_chip.names = stm32_hdp_pins_group; + + err = devm_gpiochip_add_data(dev, &hdp->gpio_chip, hdp); + if (err) + return dev_err_probe(dev, err, "Failed to add gpiochip\n"); + + writel_relaxed(HDP_CTRL_ENABLE, hdp->base + HDP_CTRL); + + version = readl_relaxed(hdp->base + HDP_VERR); + dev_dbg(dev, "STM32 HDP version %u.%u initialized\n", version >> 4, version & 0x0f); + + return 0; +} + +static void stm32_hdp_remove(struct platform_device *pdev) +{ + struct stm32_hdp *hdp = platform_get_drvdata(pdev); + + writel_relaxed(HDP_CTRL_DISABLE, hdp->base + HDP_CTRL); +} + +static int stm32_hdp_suspend(struct device *dev) +{ + struct stm32_hdp *hdp = dev_get_drvdata(dev); + + hdp->gposet_conf = readl_relaxed(hdp->base + HDP_GPOSET); + + pinctrl_pm_select_sleep_state(dev); + + clk_disable_unprepare(hdp->clk); + + return 0; +} + +static int stm32_hdp_resume(struct device *dev) +{ + struct stm32_hdp *hdp = dev_get_drvdata(dev); + int err; + + err = clk_prepare_enable(hdp->clk); + if (err) + return dev_err_probe(hdp->dev, err, "Failed to prepare_enable clk"); + + writel_relaxed(HDP_CTRL_ENABLE, hdp->base + HDP_CTRL); + writel_relaxed(hdp->gposet_conf, hdp->base + HDP_GPOSET); + writel_relaxed(hdp->mux_conf, hdp->base + HDP_MUX); + + pinctrl_pm_select_default_state(dev); + + return 0; +} + +DEFINE_SIMPLE_DEV_PM_OPS(stm32_hdp_pm_ops, stm32_hdp_suspend, stm32_hdp_resume); + +static struct platform_driver stm32_hdp_driver = { + .probe = stm32_hdp_probe, + .remove = stm32_hdp_remove, + .driver = { + .name = DRIVER_NAME, + .pm = pm_sleep_ptr(&stm32_hdp_pm_ops), + .of_match_table = stm32_hdp_of_match, + } +}; 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Signed-off-by: Clément Le Goffic --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index efee40ea589f..c277b10cf48b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22425,6 +22425,13 @@ F: drivers/bus/stm32_etzpc.c F: drivers/bus/stm32_firewall.c F: drivers/bus/stm32_rifsc.c +ST STM32 HDP PINCTRL DRIVER +M: Clément Le Goffic +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl-hdp.yaml +F: drivers/pinctrl/stm32/pinctrl-stm32-hdp.c +F: include/dt-bindings/pinctrl/stm32mp*-hdp.h + ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET M: Alain Volmat From patchwork Tue Feb 25 08:48:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Patchwork-Id: 868283 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F17C261364; 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Tue, 25 Feb 2025 09:50:52 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5B81647A7B3; Tue, 25 Feb 2025 09:48:10 +0100 (CET) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Feb 2025 09:48:10 +0100 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 25 Feb 2025 09:48:05 +0100 Subject: [PATCH 6/9] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp15 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250225-hdp-upstream-v1-6-9d049c65330a@foss.st.com> References: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> In-Reply-To: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-42535 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_03,2025-02-24_02,2024-11-22_01 Add the hdp devicetree node for stm32mp15 SoC family Signed-off-by: Clément Le Goffic --- arch/arm/boot/dts/st/stm32mp151.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index b9a87fbe971d..f16307887488 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -270,6 +270,13 @@ dts: thermal@50028000 { status = "disabled"; }; + hdp: pinctrl@5002a000 { + compatible = "st,stm32mp-hdp"; + reg = <0x5002a000 0x400>; + clocks = <&rcc HDP>; + status = "disabled"; + }; + mdma1: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; From patchwork Tue Feb 25 08:48:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Patchwork-Id: 868285 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B022825D55D; Tue, 25 Feb 2025 08:52:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740473536; cv=none; b=IKBjBdG+8FQwnKCaRV7K8JVmwtCgihwzQxwPtNpwx4IxmQTOmPCF4SP/ysEniYsfQYrqFsX7gF4vL5jFtx24b1fLqpgMhyHUZIpeeve32d5q+77I3I2sFwmjXqs4mxG/SskTg/IGO/OQFz5x4rI2begPbrSxvNop4Q8C9irxFdg= ARC-Message-Signature: i=1; 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Tue, 25 Feb 2025 09:50:52 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 183A947A6E0; Tue, 25 Feb 2025 09:48:11 +0100 (CET) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Feb 2025 09:48:10 +0100 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 25 Feb 2025 09:48:06 +0100 Subject: [PATCH 7/9] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp25 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250225-hdp-upstream-v1-7-9d049c65330a@foss.st.com> References: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> In-Reply-To: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-42535 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_03,2025-02-24_02,2024-11-22_01 Add the hdp devicetree node for stm32mp25 SoC family Signed-off-by: Clément Le Goffic --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index f3c6cdfd7008..43aaed4fcf10 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -918,6 +918,13 @@ package_otp@1e8 { }; }; + hdp: pinctrl@44090000 { + compatible = "st,stm32mp-hdp"; + reg = <0x44090000 0x400>; + clocks = <&rcc CK_BUS_HDP>; + status = "disabled"; + }; + rcc: clock-controller@44200000 { compatible = "st,stm32mp25-rcc"; reg = <0x44200000 0x10000>; From patchwork Tue Feb 25 08:48:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Patchwork-Id: 868650 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4949325D537; Tue, 25 Feb 2025 08:52:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740473536; cv=none; b=fMCgOAbIYYvEFHOdelLiIQEVDmIp6Axe2VGB8p5zJstDnZznv6oElxLNScHwAYeGUWHmpHW0ELW124K7jvNhKVGIOHae6CQ2F9hDtH5ch6YM1RHTbUW1+AFEpwNFeaHIY6FFj+EF/uHo7SQOE2pacJV6jXdfcjGstFmjUx1Bagg= ARC-Message-Signature: i=1; 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Tue, 25 Feb 2025 09:50:52 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CCCBD47A7D4; Tue, 25 Feb 2025 09:48:11 +0100 (CET) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Feb 2025 09:48:11 +0100 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 25 Feb 2025 09:48:07 +0100 Subject: [PATCH 8/9] ARM: dts: stm32: add alternate pinmux for HDP pin and add HDP pinctrl node Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250225-hdp-upstream-v1-8-9d049c65330a@foss.st.com> References: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> In-Reply-To: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-42535 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_03,2025-02-24_02,2024-11-22_01 Introduce hdp node to output a user defined value on port hdp2. Add pinctrl nodes to be able to output this signal on one SoC pin. Signed-off-by: Clément Le Goffic --- arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index 95fafc51a1c8..76ff0d6634b4 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -4,6 +4,15 @@ * Author: Ludovic Barre for STMicroelectronics. */ #include +#include + +&hdp { + /omit-if-no-ref/ + hdp2_gpo: hdp2-pins { + function = HDP2_GPOVAL_2; + pins = "hdp2"; + }; +}; &pinctrl { /omit-if-no-ref/ @@ -687,6 +696,23 @@ pins { }; }; + /omit-if-no-ref/ + hdp2_pins_a: hdp2-0 { + pins { + pinmux = ; /* HDP2 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + /omit-if-no-ref/ + hdp2_sleep_pins_a: hdp2-sleep-0 { + pins { + pinmux = ; /* HDP2 */ + }; + }; + /omit-if-no-ref/ i2c1_pins_a: i2c1-0 { pins { From patchwork Tue Feb 25 08:48:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Patchwork-Id: 868646 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE0F0260A44; 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Tue, 25 Feb 2025 09:52:01 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 2B2A440044; Tue, 25 Feb 2025 09:50:55 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 853B447B620; Tue, 25 Feb 2025 09:48:12 +0100 (CET) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Feb 2025 09:48:12 +0100 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 25 Feb 2025 09:48:08 +0100 Subject: [PATCH 9/9] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp157c-dk2 board Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250225-hdp-upstream-v1-9-9d049c65330a@foss.st.com> References: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> In-Reply-To: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-42535 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_03,2025-02-24_02,2024-11-22_01 On the stm32mp157fc-dk2 board, we can observe the hdp GPOVAL function on SoC pin E13 accessible on the pin 5 on the Arduino connector CN13. Add the relevant configuration but keep it disabled as it's used for debug only. Signed-off-by: Clément Le Goffic --- arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts index 5f9c0160a9c4..b183b51f8f50 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -63,6 +63,12 @@ &dsi_out { remote-endpoint = <&panel_in>; }; +&hdp { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdp2_gpo &hdp2_pins_a>; + pinctrl-1 = <&hdp2_sleep_pins_a>; +}; + &i2c1 { touchscreen@38 { compatible = "focaltech,ft6236";