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([49.37.249.43]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-223504c5bddsm13219135ad.140.2025.02.27.04.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 04:36:49 -0800 (PST) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, acpica-devel@lists.linux.dev Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org, james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org, conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com, sunilvl@ventanamicro.com, apatel@ventanamicro.com, Himanshu Chauhan Subject: [RFC PATCH v1 02/10] riscv: Define arch_apei_get_mem_attribute for RISC-V Date: Thu, 27 Feb 2025 18:06:20 +0530 Message-ID: <20250227123628.2931490-3-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227123628.2931490-1-hchauhan@ventanamicro.com> References: <20250227123628.2931490-1-hchauhan@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 ghes_map function uses arch_apei_get_mem_attribute to get the protection bits for a given physical address. These protection bits are then used to map the physical address. Signed-off-by: Himanshu Chauhan --- arch/riscv/include/asm/acpi.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 6e13695120bc..0c599452ef48 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -27,6 +27,26 @@ extern int acpi_disabled; extern int acpi_noirq; extern int acpi_pci_disabled; +#ifdef CONFIG_ACPI_APEI +/* + * acpi_disable_cmcff is used in drivers/acpi/apei/hest.c for disabling + * IA-32 Architecture Corrected Machine Check (CMC) Firmware-First mode + * with a kernel command line parameter "acpi=nocmcoff". But we don't + * have this IA-32 specific feature on ARM64, this definition is only + * for compatibility. + */ +#define acpi_disable_cmcff 1 +static inline pgprot_t arch_apei_get_mem_attribute(phys_addr_t addr) +{ + /* + * Until we have a way to look for EFI memory attributes. + */ + return PAGE_KERNEL; +} +#else /* CONFIG_ACPI_APEI */ +#define acpi_disable_cmcff 0 +#endif /* !CONFIG_ACPI_APEI */ + static inline void disable_acpi(void) { acpi_disabled = 1; From patchwork Thu Feb 27 12:36:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Himanshu Chauhan X-Patchwork-Id: 869000 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1751122D4F3 for ; Thu, 27 Feb 2025 12:36:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740659821; cv=none; b=Dn1dqOMjgCplElKi0ljO7tHPrlmNg5A09otzkYd2/jV2VjRtjTf63jdW84QZ/Edk0PTSM0wn70lBZpz/2Dj0MhwI1VOUGiRbOqlKmta62jtsY2+TXufiqgyXi7O5hNbq+cxf2vEvSvScsZvSIyAKH+lcz92IagbYLICqKEMVwAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740659821; c=relaxed/simple; bh=rGWTzIIeViWhGlD8y9psao/8+qBiPCPjAKNTSslE/48=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mqd0QGras6wXqNl/Ivcx/CJPr+kR+oL4mb9LbxBurXjLcLQPVv1dmax3GzlBM4RP5hyLqoyOiZYkr1bfhgSHq3IkaLO4nMihN/FCPueEzBkiRl9R90hSiMyBOM0vo8EG21KWx6l2H9VPA2prRFcqd1kLygqdgwHzctGc2Ik9OrU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=TqbrQbZB; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="TqbrQbZB" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-2212a930001so21333425ad.0 for ; Thu, 27 Feb 2025 04:36:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1740659819; x=1741264619; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CvAemUtNRi9tUzWy4d/eui/dPAc9laFlbuC1eHj4jHs=; b=TqbrQbZBaYvY5y2YdGx3D0sg+gCI3UW5XBphTHTYm5Cgh5IaLoFi1b6kmPZtkK9ott oFBlbok9irak0WiJ7CBLZdtotOAHfKN66/9y2wmUuyKF4TzfdrgmNLIpwcjW2Lskdsbj xRJAFeyMCsQ5NQYuj8x8G2me+OuBQHyzIwd4Jqn5TWUA/axkd3ipYiM/5T/jXRuod28s M40yFH5ryMwAuFHv2GiiZSGEindR4F6jOXsWRoL101D/+Ce5OwBqhME6rKmt8XUj51Tp S3nCzkxEtNCmkFjYEClVZqZlOs1mTk7MPLpnDk8xdn/kW3NKaYwxZ+CAkkCzx4qV0R5A q8jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740659819; x=1741264619; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CvAemUtNRi9tUzWy4d/eui/dPAc9laFlbuC1eHj4jHs=; b=GUiObY+yyQVQIccdLYGHyCV+Yyz0fHIHTQ3BAFXtswcHZ1FmnXXr+GCJmSMQxEhCxT TU8Q6PFHOU5Wme3bZrYSfTE/lROJu/Skicb1W4WTC38A1sxg0bfY40wDV/Rxmemwr9A1 hpIonPYx/HW0R0/xasdT56becESmJwI7f0OGWBquNHGAPke5iGPP8ERoRoqSeycrreCc ub+WiCSR4EN4ArjuMQwE1LcUkUQRcIXLiykyCdj7z2fXSwwNSVcH0zVcs+h6UekmR97t TDksgjIDIky/1nmAOdMxj/XOl0sN1B6XN/wVDGdNfMFUxtTx8JcLOUs7gKH5XFNmJHeW zlsA== X-Forwarded-Encrypted: i=1; AJvYcCXrQskYJPkzBeIKlrhNku/BY7Zp4dcqpVwjsmp+Cszeo91Zj/LTYqbv7xon7oQkdmaEI/EExq3vYBAK@vger.kernel.org X-Gm-Message-State: AOJu0YzTDosb5w/+muPayhMTspBaoK6pH4A++D6j9lNRODASuGrNkcr4 KutbUeq4nCRdI6jd4OVBe3n9HaTbaAQL2bL8jmbOWr2mp38dY1bVaQWiaQaSRXQ= X-Gm-Gg: ASbGncsHAT0A+NTriZVtTcwGD0fVBUTWNqEmhKnT7Kc5nSZ6+EcOELnnKBl0f7Nfp6d U5HrrFeV2YAQ0O54sW6+Z4jPqR+Q9uZHe3IgBrZfkeRZ9qooply77siqs9oI8Lk5qhNu2ApwjW8 hVy/c+ohLvbaIcC7yDiQ5S1LkPO2KpHEoubT+6/ah/4nWEXqnjbz+l4BBlJ2LkgWcb+Mz7LCVtC GzUCHvvdJTw4TuzhvLxAWB9fCHVc4AUkScZZq7/yUQO/3VbkJoJW5UYzQIg46Lh2PoGoVAkXgaf VUnEobeAzw9fn0hG7rYnxgLxl842ON52ZiHa X-Google-Smtp-Source: AGHT+IFYVtprbH9evLqNClf+RfnxGHGySs3bbzOLOoRiAZRk+G2rF8ng8rvkLS2SHiGq2QScEJQDTw== X-Received: by 2002:a17:903:228d:b0:21f:1bd:efd4 with SMTP id d9443c01a7336-221a0ed7e4cmr423165445ad.19.1740659819428; Thu, 27 Feb 2025 04:36:59 -0800 (PST) Received: from ventana-bhyve.. ([49.37.249.43]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-223504c5bddsm13219135ad.140.2025.02.27.04.36.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 04:36:59 -0800 (PST) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, acpica-devel@lists.linux.dev Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org, james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org, conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com, sunilvl@ventanamicro.com, apatel@ventanamicro.com, Himanshu Chauhan Subject: [RFC PATCH v1 04/10] riscv: Add fixmap indices for GHES IRQ and SSE contexts Date: Thu, 27 Feb 2025 18:06:22 +0530 Message-ID: <20250227123628.2931490-5-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227123628.2931490-1-hchauhan@ventanamicro.com> References: <20250227123628.2931490-1-hchauhan@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 GHES error handling requires fixmap entries for IRQ notifications. Add fixmap indices for IRQ, SSE Low and High priority notifications. Signed-off-by: Himanshu Chauhan --- arch/riscv/include/asm/fixmap.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h index 0a55099bb734..fa3a0ec0c55c 100644 --- a/arch/riscv/include/asm/fixmap.h +++ b/arch/riscv/include/asm/fixmap.h @@ -38,6 +38,14 @@ enum fixed_addresses { FIX_TEXT_POKE0, FIX_EARLYCON_MEM_BASE, +#ifdef CONFIG_ACPI_APEI_GHES + /* Used for GHES mapping from assorted contexts */ + FIX_APEI_GHES_IRQ, +#ifdef CONFIG_RISCV_SSE + FIX_APEI_GHES_SSE_LOW_PRIORITY, + FIX_APEI_GHES_SSE_HIGH_PRIORITY, +#endif /* CONFIG_RISCV_SSE */ +#endif /* CONFIG_ACPI_APEI_GHES */ __end_of_permanent_fixed_addresses, /* * Temporary boot-time mappings, used by early_ioremap(), From patchwork Thu Feb 27 12:36:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Himanshu Chauhan X-Patchwork-Id: 868999 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B93F323237A for ; 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([49.37.249.43]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-223504c5bddsm13219135ad.140.2025.02.27.04.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 04:37:09 -0800 (PST) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, acpica-devel@lists.linux.dev Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org, james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org, conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com, sunilvl@ventanamicro.com, apatel@ventanamicro.com, Himanshu Chauhan Subject: [RFC PATCH v1 06/10] riscv: Add functions to register ghes having SSE notification Date: Thu, 27 Feb 2025 18:06:24 +0530 Message-ID: <20250227123628.2931490-7-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227123628.2931490-1-hchauhan@ventanamicro.com> References: <20250227123628.2931490-1-hchauhan@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add functions to register the ghes entries which have SSE as notification type. The vector inside the ghes is the SSE event ID that should be registered. Signed-off-by: Himanshu Chauhan --- drivers/firmware/riscv/riscv_sse.c | 147 +++++++++++++++++++++++++++++ include/linux/riscv_sse.h | 15 +++ 2 files changed, 162 insertions(+) diff --git a/drivers/firmware/riscv/riscv_sse.c b/drivers/firmware/riscv/riscv_sse.c index c165e32cc9a5..511db9ad7a9e 100644 --- a/drivers/firmware/riscv/riscv_sse.c +++ b/drivers/firmware/riscv/riscv_sse.c @@ -5,6 +5,8 @@ #define pr_fmt(fmt) "sse: " fmt +#include +#include #include #include #include @@ -689,3 +691,148 @@ static int __init sse_init(void) return ret; } arch_initcall(sse_init); + +struct sse_ghes_callback { + struct list_head head; + struct ghes *ghes; + sse_event_handler *callback; +}; + +struct sse_ghes_event_data { + struct list_head head; + u32 event_num; + struct list_head callback_list; + struct sse_event *event; +}; + +static DEFINE_SPINLOCK(sse_ghes_event_list_lock); +static LIST_HEAD(sse_ghes_event_list); + +static int sse_ghes_handler(u32 event_num, void *arg, struct pt_regs *regs) +{ + struct sse_ghes_event_data *ev_data = arg; + struct sse_ghes_callback *cb = NULL; + + list_for_each_entry(cb, &ev_data->callback_list, head) { + if (cb && cb->ghes && cb->callback) { + cb->callback(ev_data->event_num, cb->ghes, regs); + } + } + + return 0; +} + +int sse_register_ghes(struct ghes *ghes, sse_event_handler *lo_cb, + sse_event_handler *hi_cb) +{ + struct sse_ghes_event_data *ev_data, *evd; + struct sse_ghes_callback *cb; + u32 ev_num; + int err; + + if (!sse_available) + return -EOPNOTSUPP; + if (!ghes || !lo_cb || !hi_cb) + return -EINVAL; + + ev_num = ghes->generic->notify.vector; + + ev_data = NULL; + spin_lock(&sse_ghes_event_list_lock); + list_for_each_entry(evd, &sse_ghes_event_list, head) { + if (evd->event_num == ev_num) { + ev_data = evd; + break; + } + } + spin_unlock(&sse_ghes_event_list_lock); + + if (!ev_data) { + ev_data = kzalloc(sizeof(*ev_data), GFP_KERNEL); + if (!ev_data) + return -ENOMEM; + + INIT_LIST_HEAD(&ev_data->head); + ev_data->event_num = ev_num; + + INIT_LIST_HEAD(&ev_data->callback_list); + + ev_data->event = sse_event_register(ev_num, ev_num, + sse_ghes_handler, ev_data); + if (IS_ERR(ev_data->event)) { + pr_err("%s: Couldn't register event 0x%x\n", __func__, ev_num); + kfree(ev_data); + return -ENOMEM; + } + + err = sse_event_enable(ev_data->event); + if (err) { + pr_err("%s: Couldn't enable event 0x%x\n", __func__, ev_num); + sse_event_unregister(ev_data->event); + kfree(ev_data); + return err; + } + + spin_lock(&sse_ghes_event_list_lock); + list_add_tail(&ev_data->head, &sse_ghes_event_list); + spin_unlock(&sse_ghes_event_list_lock); + } + + list_for_each_entry(cb, &ev_data->callback_list, head) { + if (cb->ghes == ghes) + return -EALREADY; + } + + cb = kzalloc(sizeof(*cb), GFP_KERNEL); + if (!cb) + return -ENOMEM; + INIT_LIST_HEAD(&cb->head); + cb->ghes = ghes; + cb->callback = lo_cb; + list_add_tail(&cb->head, &ev_data->callback_list); + + return 0; +} + +int sse_unregister_ghes(struct ghes *ghes) +{ + struct sse_ghes_event_data *ev_data, *tmp; + struct sse_ghes_callback *cb; + int free_ev_data = 0; + + if (!ghes) + return -EINVAL; + + spin_lock(&sse_ghes_event_list_lock); + + list_for_each_entry_safe(ev_data, tmp, &sse_ghes_event_list, head) { + list_for_each_entry(cb, &ev_data->callback_list, head) { + if (cb->ghes != ghes) + continue; + + list_del(&cb->head); + kfree(cb); + break; + } + + if (list_empty(&ev_data->callback_list)) + free_ev_data = 1; + + if (free_ev_data) { + spin_unlock(&sse_ghes_event_list_lock); + + sse_event_disable(ev_data->event); + sse_event_unregister(ev_data->event); + ev_data->event = NULL; + + spin_lock(&sse_ghes_event_list_lock); + + list_del(&ev_data->head); + kfree(ev_data); + } + } + + spin_unlock(&sse_ghes_event_list_lock); + + return 0; +} diff --git a/include/linux/riscv_sse.h b/include/linux/riscv_sse.h index c73184074b8c..16700677f1e8 100644 --- a/include/linux/riscv_sse.h +++ b/include/linux/riscv_sse.h @@ -12,6 +12,8 @@ struct sse_event; struct pt_regs; +struct ghes; + typedef int (sse_event_handler)(u32 event_num, void *arg, struct pt_regs *regs); #ifdef CONFIG_RISCV_SSE @@ -27,6 +29,9 @@ int sse_event_enable(struct sse_event *sse_evt); void sse_event_disable(struct sse_event *sse_evt); +int sse_register_ghes(struct ghes *ghes, sse_event_handler *lo_cb, + sse_event_handler *hi_cb); +int sse_unregister_ghes(struct ghes *ghes); #else static inline struct sse_event *sse_event_register(u32 event_num, u32 priority, sse_event_handler *handler, @@ -50,6 +55,16 @@ static inline int sse_event_enable(struct sse_event *sse_evt) static inline void sse_event_disable(struct sse_event *sse_evt) {} +static inline int sse_register_ghes(struct ghes *ghes, sse_event_handler *lo_cb, + sse_event_handler *hi_cb) +{ + return -EOPNOTSUPP; +} + +static inline int sse_unregister_ghes(struct ghes *ghes) +{ + return -EOPNOTSUPP; +} #endif From patchwork Thu Feb 27 12:36:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Himanshu Chauhan X-Patchwork-Id: 868998 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 897B4233158 for ; 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([49.37.249.43]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-223504c5bddsm13219135ad.140.2025.02.27.04.37.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 04:37:19 -0800 (PST) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, acpica-devel@lists.linux.dev Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org, james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org, conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com, sunilvl@ventanamicro.com, apatel@ventanamicro.com, Himanshu Chauhan Subject: [RFC PATCH v1 08/10] riscv: Introduce HEST SSE notification handlers Date: Thu, 27 Feb 2025 18:06:26 +0530 Message-ID: <20250227123628.2931490-9-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227123628.2931490-1-hchauhan@ventanamicro.com> References: <20250227123628.2931490-1-hchauhan@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 - Functions to register a ghes entry with SSE - Add Handlers for low/high priority events - Call ghes common handler to handle an error event Signed-off-by: Himanshu Chauhan --- drivers/acpi/apei/ghes.c | 100 ++++++++++++++++++++++++++++++++++----- 1 file changed, 89 insertions(+), 11 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 8a1029163799..59abb89d3547 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -17,6 +17,7 @@ * Author: Huang Ying */ +#include #include #include #include @@ -97,6 +98,11 @@ #define FIX_APEI_GHES_SDEI_CRITICAL __end_of_fixed_addresses #endif +#ifndef CONFIG_RISCV_SSE +#define FIX_APEI_GHES_SSE_LOW_PRIORITY __end_of_fixed_addresses +#define FIX_APEI_GHES_SSE_HIGH_PRIORITY __end_of_fixed_addresses +#endif + static ATOMIC_NOTIFIER_HEAD(ghes_report_chain); static inline bool is_hest_type_generic_v2(struct ghes *ghes) @@ -1405,6 +1411,63 @@ static int apei_sdei_unregister_ghes(struct ghes *ghes) return sdei_unregister_ghes(ghes); } +#if defined(CONFIG_ACPI_APEI_SSE) +/* SSE Handlers */ +static int __ghes_sse_callback(struct ghes *ghes, + enum fixed_addresses fixmap_idx) +{ + if (!ghes_in_nmi_queue_one_entry(ghes, fixmap_idx)) { + irq_work_queue(&ghes_proc_irq_work); + + return 0; + } + + return -ENOENT; +} + +/* Low priority */ +static int ghes_sse_lo_callback(u32 event_num, void *arg, struct pt_regs *regs) +{ + static DEFINE_RAW_SPINLOCK(ghes_notify_lock_sse_lo); + struct ghes *ghes = arg; + int err; + + raw_spin_lock(&ghes_notify_lock_sse_lo); + err = __ghes_sse_callback(ghes, FIX_APEI_GHES_SSE_LOW_PRIORITY); + raw_spin_unlock(&ghes_notify_lock_sse_lo); + + return err; +} + +/* High priority */ +static int ghes_sse_hi_callback(u32 event_num, void *arg, struct pt_regs *regs) +{ + static DEFINE_RAW_SPINLOCK(ghes_notify_lock_sse_hi); + struct ghes *ghes = arg; + int err; + + raw_spin_lock(&ghes_notify_lock_sse_hi); + err = __ghes_sse_callback(ghes, FIX_APEI_GHES_SSE_HIGH_PRIORITY); + raw_spin_unlock(&ghes_notify_lock_sse_hi); + + return err; +} + +static int apei_sse_register_ghes(struct ghes *ghes) +{ + return sse_register_ghes(ghes, ghes_sse_lo_callback, + ghes_sse_hi_callback); +} + +static int apei_sse_unregister_ghes(struct ghes *ghes) +{ + return sse_unregister_ghes(ghes); +} +#else /* CONFIG_ACPI_APEI_SSE */ +static int apei_sse_register_ghes(struct ghes *ghes) { return -ENOTSUPP; } +static int apei_sse_unregister_ghes(struct ghes *ghes) { return -ENOTSUPP; } +#endif + static int ghes_probe(struct platform_device *ghes_dev) { struct acpi_hest_generic *generic; @@ -1451,6 +1514,15 @@ static int ghes_probe(struct platform_device *ghes_dev) pr_warn(GHES_PFX "Generic hardware error source: %d notified via local interrupt is not supported!\n", generic->header.source_id); goto err; + case ACPI_HEST_NOTIFY_SSE: + if (!IS_ENABLED(CONFIG_ACPI_APEI_SSE)) { + pr_warn(GHES_PFX "Generic hardware error source: %d " + "notified via SSE is not supported\n", + generic->header.source_id); + rc = -ENOTSUPP; + goto err; + } + break; default: pr_warn(FW_WARN GHES_PFX "Unknown notification type: %u for generic hardware error source: %d\n", generic->notify.type, generic->header.source_id); @@ -1514,6 +1586,18 @@ static int ghes_probe(struct platform_device *ghes_dev) if (rc) goto err; break; + + case ACPI_HEST_NOTIFY_SSE: + rc = apei_sse_register_ghes(ghes); + if (rc) { + pr_err(GHES_PFX "Failed to register for SSE notification" + " on vector %d\n", + generic->notify.vector); + goto err; + } + pr_err(GHES_PFX "Registered SSE notification on vector %d\n", + generic->notify.vector); + break; default: BUG(); } @@ -1543,7 +1627,6 @@ static int ghes_probe(struct platform_device *ghes_dev) static void ghes_remove(struct platform_device *ghes_dev) { - int rc; struct ghes *ghes; struct acpi_hest_generic *generic; @@ -1577,16 +1660,11 @@ static void ghes_remove(struct platform_device *ghes_dev) ghes_nmi_remove(ghes); break; case ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED: - rc = apei_sdei_unregister_ghes(ghes); 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([49.37.249.43]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-223504c5bddsm13219135ad.140.2025.02.27.04.37.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 04:37:30 -0800 (PST) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, acpica-devel@lists.linux.dev Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org, james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org, conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com, sunilvl@ventanamicro.com, apatel@ventanamicro.com, Himanshu Chauhan Subject: [RFC PATCH v1 10/10] riscv: Enable APEI and NMI safe cmpxchg options required for RAS Date: Thu, 27 Feb 2025 18:06:28 +0530 Message-ID: <20250227123628.2931490-11-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227123628.2931490-1-hchauhan@ventanamicro.com> References: <20250227123628.2931490-1-hchauhan@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable the APEI option so that APEI GHES options are visible. Enable SAFE_CMPXCHG option required for GHES error handling. Signed-off-by: Himanshu Chauhan --- arch/riscv/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7612c52e9b1e..baf97a4f6830 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -54,6 +54,7 @@ config RISCV select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UBSAN select ARCH_HAS_VDSO_TIME_DATA + select ARCH_HAVE_NMI_SAFE_CMPXCHG select ARCH_KEEP_MEMBLOCK if ACPI select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX @@ -175,6 +176,7 @@ config RISCV select HAVE_MOVE_PUD select HAVE_PAGE_SIZE_4KB select HAVE_PCI + select HAVE_ACPI_APEI if ACPI select HAVE_PERF_EVENTS select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP