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Fri, 28 Feb 2025 00:40:30 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43b7a27aa85sm48096605e9.28.2025.02.28.00.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 00:40:30 -0800 (PST) From: Neil Armstrong Date: Fri, 28 Feb 2025 09:40:25 +0100 Subject: [PATCH v4 1/2] arm64: dts: qcom: sm8650: switch to interrupt-cells 4 to add PPI partitions Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250228-topic-sm8650-pmu-ppi-partition-v4-1-78cffd35c73d@linaro.org> References: <20250228-topic-sm8650-pmu-ppi-partition-v4-0-78cffd35c73d@linaro.org> In-Reply-To: <20250228-topic-sm8650-pmu-ppi-partition-v4-0-78cffd35c73d@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The ARM PMUs shares the same per-cpu (PPI) interrupt, so we need to switch to interrupt-cells = <4> in the GIC node to allow adding an interrupt partition map phandle as the 4th cell value for GIC_PPI interrupts. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 542 +++++++++++++++++------------------ 1 file changed, 271 insertions(+), 271 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index de960bcaf3ccf6e2be47bf63a02effbfb75241bf..982579d0af4684f07d5620e03d0cba20e58acd2e 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -1417,17 +1417,17 @@ opp-3302400000 { pmu-a520 { compatible = "arm,cortex-a520-pmu"; - interrupts = ; + interrupts = ; }; pmu-a720 { compatible = "arm,cortex-a720-pmu"; - interrupts = ; + interrupts = ; }; pmu-x4 { compatible = "arm,cortex-x4-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -1805,7 +1805,7 @@ ipcc: mailbox@406000 { compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; reg = <0 0x00406000 0 0x1000>; - interrupts = ; + interrupts = ; interrupt-controller; #interrupt-cells = <3>; @@ -1816,18 +1816,18 @@ gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00800000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; dma-channels = <12>; dma-channel-mask = <0x3f>; @@ -1863,7 +1863,7 @@ i2c8: i2c@880000 { compatible = "qcom,geni-i2c"; reg = <0 0x00880000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; @@ -1900,7 +1900,7 @@ spi8: spi@880000 { compatible = "qcom,geni-spi"; reg = <0 0x00880000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; @@ -1937,7 +1937,7 @@ i2c9: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0 0x00884000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; @@ -1974,7 +1974,7 @@ spi9: spi@884000 { compatible = "qcom,geni-spi"; reg = <0 0x00884000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; @@ -2011,7 +2011,7 @@ i2c10: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; @@ -2048,7 +2048,7 @@ spi10: spi@888000 { compatible = "qcom,geni-spi"; reg = <0 0x00888000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; @@ -2085,7 +2085,7 @@ i2c11: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; @@ -2122,7 +2122,7 @@ spi11: spi@88c000 { compatible = "qcom,geni-spi"; reg = <0 0x0088c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; @@ -2159,7 +2159,7 @@ i2c12: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; clock-names = "se"; @@ -2196,7 +2196,7 @@ spi12: spi@890000 { compatible = "qcom,geni-spi"; reg = <0 0x00890000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; clock-names = "se"; @@ -2233,7 +2233,7 @@ i2c13: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; @@ -2270,7 +2270,7 @@ spi13: spi@894000 { compatible = "qcom,geni-spi"; reg = <0 0x00894000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; @@ -2307,7 +2307,7 @@ uart14: serial@898000 { compatible = "qcom,geni-uart"; reg = <0 0x00898000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; @@ -2333,7 +2333,7 @@ uart15: serial@89c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x0089c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; clock-names = "se"; @@ -2373,7 +2373,7 @@ i2c_hub_0: i2c@980000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00980000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2404,7 +2404,7 @@ i2c_hub_1: i2c@984000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00984000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2435,7 +2435,7 @@ i2c_hub_2: i2c@988000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00988000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2466,7 +2466,7 @@ i2c_hub_3: i2c@98c000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x0098c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2497,7 +2497,7 @@ i2c_hub_4: i2c@990000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00990000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2528,7 +2528,7 @@ i2c_hub_5: i2c@994000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00994000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2559,7 +2559,7 @@ i2c_hub_6: i2c@998000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00998000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2590,7 +2590,7 @@ i2c_hub_7: i2c@99c000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x0099c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2621,7 +2621,7 @@ i2c_hub_8: i2c@9a0000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x009a0000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2652,7 +2652,7 @@ i2c_hub_9: i2c@9a4000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x009a4000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2684,18 +2684,18 @@ gpi_dma1: dma-controller@a00000 { compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00a00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; dma-channels = <12>; dma-channel-mask = <0xc>; @@ -2734,7 +2734,7 @@ i2c0: i2c@a80000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a80000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; @@ -2771,7 +2771,7 @@ spi0: spi@a80000 { compatible = "qcom,geni-spi"; reg = <0 0x00a80000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; @@ -2808,7 +2808,7 @@ i2c1: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; @@ -2845,7 +2845,7 @@ spi1: spi@a84000 { compatible = "qcom,geni-spi"; reg = <0 0x00a84000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; @@ -2882,7 +2882,7 @@ i2c2: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; @@ -2919,7 +2919,7 @@ spi2: spi@a88000 { compatible = "qcom,geni-spi"; reg = <0 0x00a88000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; @@ -2956,7 +2956,7 @@ i2c3: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; @@ -2993,7 +2993,7 @@ spi3: spi@a8c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a8c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; @@ -3030,7 +3030,7 @@ i2c4: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a90000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; @@ -3067,7 +3067,7 @@ spi4: spi@a90000 { compatible = "qcom,geni-spi"; reg = <0 0x00a90000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; @@ -3104,7 +3104,7 @@ i2c5: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; @@ -3141,7 +3141,7 @@ spi5: spi@a94000 { compatible = "qcom,geni-spi"; reg = <0 0x00a94000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; @@ -3178,7 +3178,7 @@ i2c6: i2c@a98000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a98000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; @@ -3215,7 +3215,7 @@ spi6: spi@a98000 { compatible = "qcom,geni-spi"; reg = <0 0x00a98000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; @@ -3252,7 +3252,7 @@ i2c7: i2c@a9c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a9c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; @@ -3289,7 +3289,7 @@ spi7: spi@a9c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a9c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; @@ -3409,15 +3409,15 @@ pcie0: pcie@1c00000 { <0 0x60100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; - interrupts = , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -3462,10 +3462,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, iommu-map = <0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; @@ -3584,15 +3584,15 @@ pcie1: pcie@1c08000 { "atu", "config"; - interrupts = , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -3642,10 +3642,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, iommu-map = <0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; @@ -3763,7 +3763,7 @@ cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x28000>; - interrupts = ; + interrupts = ; #dma-cells = <1>; @@ -3815,7 +3815,7 @@ ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0 0x01d84000 0 0x3000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -3936,7 +3936,7 @@ gpu: gpu@3d00000 { "cx_mem", "cx_dbgc"; - interrupts = ; + interrupts = ; iommus = <&adreno_smmu 0 0x0>, <&adreno_smmu 1 0x0>; @@ -4035,8 +4035,8 @@ gmu: gmu@3d6a000 { <0x0 0x0b280000 0x0 0x10000>; reg-names = "gmu", "rscc", "gmu_pdc"; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_AHB_CLK>, @@ -4099,32 +4099,32 @@ adreno_smmu: iommu@3da0000 { reg = <0x0 0x03da0000 0x0 0x40000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, @@ -4149,8 +4149,8 @@ ipa: ipa@3f40000 { "ipa-shared", "gsi"; - interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", @@ -4182,7 +4182,7 @@ remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8650-mpss-pas"; reg = <0x0 0x04080000 0x0 0x10000>; - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, @@ -4399,7 +4399,7 @@ lpass_wsa2macro: codec@6aa0000 { swr3: soundwire@6ab0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ab0000 0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&lpass_wsa2macro>; clock-names = "iface"; label = "WSA2"; @@ -4446,7 +4446,7 @@ lpass_rxmacro: codec@6ac0000 { swr1: soundwire@6ad0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ad0000 0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&lpass_rxmacro>; clock-names = "iface"; label = "RX"; @@ -4510,7 +4510,7 @@ lpass_wsamacro: codec@6b00000 { swr0: soundwire@6b10000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06b10000 0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&lpass_wsamacro>; clock-names = "iface"; label = "WSA"; @@ -4540,8 +4540,8 @@ swr0: soundwire@6b10000 { swr2: soundwire@6d30000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06d30000 0 0x10000>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "core", "wakeup"; clocks = <&lpass_txmacro>; clock-names = "iface"; @@ -4732,8 +4732,8 @@ sdhc_2: mmc@8804000 { compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hc_irq", "pwr_irq"; @@ -4807,7 +4807,7 @@ videocc: clock-controller@aaf0000 { cci0: cci@ac15000 { compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; reg = <0 0x0ac15000 0 0x1000>; - interrupts = ; + interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -4840,7 +4840,7 @@ cci0_i2c1: i2c-bus@1 { cci1: cci@ac16000 { compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; reg = <0 0x0ac16000 0 0x1000>; - interrupts = ; + interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -4873,7 +4873,7 @@ cci1_i2c1: i2c-bus@1 { cci2: cci@ac17000 { compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; reg = <0 0x0ac17000 0 0x1000>; - interrupts = ; + interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -4921,7 +4921,7 @@ mdss: display-subsystem@ae00000 { reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; - interrupts = ; + interrupts = ; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, @@ -5390,8 +5390,8 @@ usb_1: usb@a6f8800 { compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&pdc 15 IRQ_TYPE_EDGE_RISING>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; @@ -5440,7 +5440,7 @@ usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; + interrupts = ; iommus = <&apps_smmu 0x40 0>; @@ -5504,8 +5504,8 @@ tsens0: thermal-sensor@c228000 { reg = <0 0x0c228000 0 0x1000>, /* TM */ <0 0x0c222000 0 0x1000>; /* SROT */ - interrupts = , - ; + interrupts = , + ; interrupt-names = "uplow", "critical"; @@ -5519,8 +5519,8 @@ tsens1: thermal-sensor@c229000 { reg = <0 0x0c229000 0 0x1000>, /* TM */ <0 0x0c223000 0 0x1000>; /* SROT */ - interrupts = , - ; + interrupts = , + ; interrupt-names = "uplow", "critical"; @@ -5534,8 +5534,8 @@ tsens2: thermal-sensor@c22a000 { reg = <0 0x0c22a000 0 0x1000>, /* TM */ <0 0x0c224000 0 0x1000>; /* SROT */ - interrupts = , - ; + interrupts = , + ; interrupt-names = "uplow", "critical"; @@ -5593,7 +5593,7 @@ tlmm: pinctrl@f100000 { compatible = "qcom,sm8650-tlmm"; reg = <0 0x0f100000 0 0x300000>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <2>; @@ -6469,103 +6469,103 @@ apps_smmu: iommu@15000000 { compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; #iommu-cells = <2>; #global-interrupts = <1>; @@ -6578,9 +6578,9 @@ intc: interrupt-controller@17100000 { reg = <0 0x17100000 0 0x10000>, /* GICD */ <0 0x17180000 0 0x200000>; /* GICR * 8 */ - interrupts = ; + interrupts = ; - #interrupt-cells = <3>; + #interrupt-cells = <4>; interrupt-controller; #redistributor-regions = <1>; @@ -6611,8 +6611,8 @@ frame@17421000 { reg = <0x17421000 0x1000>, <0x17422000 0x1000>; - interrupts = , - ; + interrupts = , + ; frame-number = <0>; }; @@ -6620,7 +6620,7 @@ frame@17421000 { frame@17423000 { reg = <0x17423000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <1>; @@ -6630,7 +6630,7 @@ frame@17423000 { frame@17425000 { reg = <0x17425000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <2>; @@ -6640,7 +6640,7 @@ frame@17425000 { frame@17427000 { reg = <0x17427000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <3>; @@ -6650,7 +6650,7 @@ frame@17427000 { frame@17429000 { reg = <0x17429000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <4>; @@ -6660,7 +6660,7 @@ frame@17429000 { frame@1742b000 { reg = <0x1742b000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <5>; @@ -6670,7 +6670,7 @@ frame@1742b000 { frame@1742d000 { reg = <0x1742d000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <6>; @@ -6688,9 +6688,9 @@ apps_rsc: rsc@17a00000 { "drv-1", "drv-2"; - interrupts = , - , - ; + interrupts = , + , + ; power-domains = <&cluster_pd>; @@ -6808,10 +6808,10 @@ cpufreq_hw: cpufreq@17d91000 { "freq-domain2", "freq-domain3"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2", @@ -6828,7 +6828,7 @@ pmu@24091000 { compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x24091000 0 0x1000>; - interrupts = ; + interrupts = ; interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -6880,7 +6880,7 @@ pmu@240b7400 { compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x240b7400 0 0x600>; - interrupts = ; + interrupts = ; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -6940,7 +6940,7 @@ system-cache-controller@25000000 { "llcc_broadcast_base", "llcc_broadcast_and_base"; - interrupts = ; + interrupts = ; }; nsp_noc: interconnect@320c0000 { @@ -6956,7 +6956,7 @@ remoteproc_cdsp: remoteproc@32300000 { compatible = "qcom,sm8650-cdsp-pas"; reg = <0x0 0x32300000 0x0 0x10000>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -7956,9 +7956,9 @@ modem3-critical { timer { compatible = "arm,armv8-timer"; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper interrupt partition maps and use the 4th interrupt cell to pass the partition phandle for each ARM PMU node. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 982579d0af4684f07d5620e03d0cba20e58acd2e..512a5a4c77951d6336082c8e0d94eb69f29d67c7 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -1417,17 +1417,17 @@ opp-3302400000 { pmu-a520 { compatible = "arm,cortex-a520-pmu"; - interrupts = ; + interrupts = ; }; pmu-a720 { compatible = "arm,cortex-a720-pmu"; - interrupts = ; + interrupts = ; }; pmu-x4 { compatible = "arm,cortex-x4-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -6590,6 +6590,20 @@ intc: interrupt-controller@17100000 { #size-cells = <2>; ranges; + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>; + }; + + ppi_cluster2: interrupt-partition-2 { + affinity = <&cpu7>; + }; + }; + gic_its: msi-controller@17140000 { compatible = "arm,gic-v3-its"; reg = <0 0x17140000 0 0x20000>;