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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/21] hw/arm/smmu-common: Remove the repeated ttb field Date: Fri, 7 Mar 2025 15:06:48 +0000 Message-ID: <20250307150708.3222813-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: JianChunfu SMMUTransCfg->ttb is never used in QEMU, TT base address can be accessed by SMMUTransCfg->tt[i]->ttb. Signed-off-by: JianChunfu Reviewed-by: Eric Auger Message-id: 20250221031034.69822-1-jansef.jian@hj-micro.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index d1a4a64551d..e5ad55bbae7 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -110,7 +110,6 @@ typedef struct SMMUTransCfg { /* Used by stage-1 only. */ bool aa64; /* arch64 or aarch32 translation table */ bool record_faults; /* record fault events */ - uint64_t ttb; /* TT base address */ uint8_t oas; /* output address width */ uint8_t tbi; /* Top Byte Ignore */ int asid; From patchwork Fri Mar 7 15:06:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871197 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp811096wri; Fri, 7 Mar 2025 07:12:43 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXldtrBVfuARFzmgRlC6A2i3VT7sQ5cBegEdDxFLTJzA0eomh4wsvON7FC3d34gBRlo4btQCA==@linaro.org X-Google-Smtp-Source: AGHT+IGdQ3sTMcxe5Icx2gD9i2Sol2yamLpVCh0m/y94EL1ToqQ8UAF/KfuxI7vFZXFBLRMHkvDf X-Received: by 2002:a05:6102:2927:b0:4c1:83c4:8562 with SMTP id ada2fe7eead31-4c30a619ce9mr2372536137.13.1741360363150; Fri, 07 Mar 2025 07:12:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360363; cv=none; d=google.com; s=arc-20240605; b=PoqpqWBL5KO3dW8UcxPu5KK9WK8nDSiRTzHSfRMRCe5Hp5rDqb7TxQEfLiQckphYnI A7K5Fab1FkCoidL/nyjjBnQJzVYZJqIw77EjfpqwjrO1v1qabVLdvKfrrDQeNcuZhGbZ tXHVnMbzUvGTU3EMqwGiOePQWLG2wmG9ONlkOycKgJXjmP4MbTbHtW0QFr6P+ehK7Kiv 5ObnRKgG31nXSIaiKI/XnrSvTd3kyGziwp4/RNPVM2ENnEB55ojBztHrXiXgsAuwCwMo t9MDYQiJFiJ3h1XRJc9rzsGnn2HSz64lD5TJPQ17mOXppAQ9s3RnR+H8VuOUoVhT74Qp O6tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dJa7xFMSJ9Cj8sAYI9y1hV/NskVbtE4S9vRHsNQbdj8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=hf1nUpgCpgGfYlKKxib9y/Gs5OZJzPTt+8/OFy7IsyURn8mrYF5vEv9i5JTkGY9Hlp 49B9yKL46Ruclz6k1gkiQCaVrpncCIVquNfJ7jkEL+gS4qWgVEe9R5SCHAZeTfRhpoDd sXRw08o/y5ufCBqjArEDVKw+kfbcjZ562us9BZfJ8qMqbmY2cRbM3uDi0bP/OSqNRmyp RYGtAC7jbbGslLJspLfRMl44rJAKei6AjfQdNFYw3J4QsFGONFlS+H0uHat3k/t0yLtg aC4G9elBN5k3onCZNeXXxfcBYkTKAbWMBehDiNVunOAYSQjwxlruLxDnMJdPGes14pE+ 6cHw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XSrxlXKZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/21] hw/gpio: npcm7xx: fixup out-of-bounds access Date: Fri, 7 Mar 2025 15:06:49 +0000 Message-ID: <20250307150708.3222813-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Patrick Venture The reg isn't validated to be a possible register before it's dereferenced for one case. The mmio space registered for the gpio device is 4KiB but there aren't that many registers in the struct. Cc: qemu-stable@nongnu.org Fixes: 526dbbe0874 ("hw/gpio: Add GPIO model for Nuvoton NPCM7xx") Signed-off-by: Patrick Venture Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250226024603.493148-1-venture@google.com Signed-off-by: Peter Maydell --- hw/gpio/npcm7xx_gpio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c index 23e67424c9f..2916056fae6 100644 --- a/hw/gpio/npcm7xx_gpio.c +++ b/hw/gpio/npcm7xx_gpio.c @@ -220,8 +220,6 @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v, return; } - diff = s->regs[reg] ^ value; - switch (reg) { case NPCM7XX_GPIO_TLOCK1: case NPCM7XX_GPIO_TLOCK2: @@ -242,6 +240,7 @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v, case NPCM7XX_GPIO_PU: case NPCM7XX_GPIO_PD: case NPCM7XX_GPIO_IEM: + diff = s->regs[reg] ^ value; s->regs[reg] = value; npcm7xx_gpio_update_pins(s, diff); break; From patchwork Fri Mar 7 15:06:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871200 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp811208wri; Fri, 7 Mar 2025 07:12:56 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU/eQPcw2dwk94y8N0yJQJbLVmDlXcPP8umkkzrU+MPfhK4tIJbjySJ4NhTGTpTRqYFcVlcwQ==@linaro.org X-Google-Smtp-Source: AGHT+IE6Y3B1ZW50YCpb+19Q4tQhq6mFQvh5wNfeVDkNeWfeuEua/rOaLcVJz42tDjKQZeEvXxM3 X-Received: by 2002:a67:e7cb:0:b0:4bb:9b46:3f87 with SMTP id ada2fe7eead31-4c30a559894mr2298555137.6.1741360376052; Fri, 07 Mar 2025 07:12:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360376; cv=none; d=google.com; s=arc-20240605; b=CiwA8eGvYP+o8W6owxVmCrMGy93VdTmlRCP9mxSGq5uZGRcbjLdGyRc83d2osBte+K FWl1/rwEsW2nGo/BRs9hCpHySJgOWpYM7AovCYvHl/q8WuWY0iOyqQq9gi6Y/QkcdEIn xd/oY6KdNIEGjtxLayMMiWcEifsofRq8FptQwFkRkndcaVLxtuNu7N+i3njZIhUXvTAi yN4Q5jUiOLm9PKL3pNJMBh/BqCQSbURvRjOHzUZxDRAISZPvzguNQnh1LVtzE/LW7b0t tYhnhDjSDuG8vOt214JIpwlEena5aeQz1d3y8pADhSOqHzJGmdgyrj3Or6cSnV2f3y4H VRvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rIwmQF35hYwgON9JLC3NfuNYRtNZnkx/8hFBCdAWebE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=TtXDlV+SYRmkzdCHMMRGYvKEAe00PpYUqnGOob2YIDhpJIurLYnBOVk7s/9htujFhH LmKNhRpk9dBpnzwjeyJgxITVBuuIOnOQ5oRyODEefOWSNtyrZnmt+xA2F1UVF0S7oVEt 1Y0jiI2WZnPfHEdlnUCummnQ+jopNQAKoIB8YQTgjm473kKEG4Dl4Ru3XQKzNqFmJBni cDi0QD48XcXeO4sGptu1Dk7lA2kxNZfHSn72LlRxs763rLJ0LPR1SdL+74BXcUtX0Nkh lEEVg1Hlp+EMEDxHqrZIj1Z3ZnAwilnZMRJIACiZRvRXJCo2lAXjcAhLAJ76MMAE2kQm vqkQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yj5J8pAr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/21] tests/functional/test_arm_sx1: Check whether the serial console is working Date: Fri, 7 Mar 2025 15:06:50 +0000 Message-ID: <20250307150708.3222813-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Thomas Huth The kernel that is used in the sx1 test prints the usual Linux log onto the serial console, but this test currently ignores it. To make sure that the serial device is working properly, let's check for some strings in the output here. While we're at it, also add the test to the corresponding section in the MAINTAINERS file. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250226104833.1176253-1-thuth@redhat.com Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + tests/functional/test_arm_sx1.py | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 5df6020ed54..699cf59e0b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2010,6 +2010,7 @@ S: Maintained F: hw/*/omap* F: include/hw/arm/omap.h F: docs/system/arm/sx1.rst +F: tests/functional/test_arm_sx1.py IPack M: Alberto Garcia diff --git a/tests/functional/test_arm_sx1.py b/tests/functional/test_arm_sx1.py index 4dd1e1859fa..25800b388c9 100755 --- a/tests/functional/test_arm_sx1.py +++ b/tests/functional/test_arm_sx1.py @@ -43,7 +43,8 @@ def test_arm_sx1_initrd(self): self.vm.add_args('-append', f'kunit.enable=0 rdinit=/sbin/init {self.CONSOLE_ARGS}') self.vm.add_args('-no-reboot') self.launch_kernel(zimage_path, - initrd=initrd_path) + initrd=initrd_path, + wait_for='Boot successful') self.vm.wait(timeout=120) def test_arm_sx1_sd(self): @@ -54,7 +55,7 @@ def test_arm_sx1_sd(self): self.vm.add_args('-no-reboot') self.vm.add_args('-snapshot') self.vm.add_args('-drive', f'format=raw,if=sd,file={sd_fs_path}') - self.launch_kernel(zimage_path) + self.launch_kernel(zimage_path, wait_for='Boot successful') self.vm.wait(timeout=120) def test_arm_sx1_flash(self): @@ -65,7 +66,7 @@ def test_arm_sx1_flash(self): self.vm.add_args('-no-reboot') self.vm.add_args('-snapshot') self.vm.add_args('-drive', f'format=raw,if=pflash,file={flash_path}') - self.launch_kernel(zimage_path) + self.launch_kernel(zimage_path, wait_for='Boot successful') self.vm.wait(timeout=120) if __name__ == '__main__': From patchwork Fri Mar 7 15:06:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871188 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp809301wri; Fri, 7 Mar 2025 07:09:33 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUQ4qo3Gxb7EXoQFuVvb9kr55rjeUGDErQph1I/sYmaRvhLlV5kiUkkJleDaW+v59o53mrTeQ==@linaro.org X-Google-Smtp-Source: AGHT+IEtwaq10cwTqydwTSkVo2yhCJjIy+dihdAWzH03u0rY9t6lfZ5rMYgGxpnsqV3vLPFujsl3 X-Received: by 2002:a05:620a:8017:b0:7c3:dc24:ce9d with SMTP id af79cd13be357-7c4e1676833mr644656285a.7.1741360173340; Fri, 07 Mar 2025 07:09:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360173; cv=none; d=google.com; s=arc-20240605; b=Ptd59JaT82t6kvkffP9pikP2KsiBTEXB8Ttpx+PM+X4GxiL0KAbuqVv/JmoCG3iHNr MIFLmotS3jxT46guLa/0SNztS4MniGLjrGzVVHIWOdZqM8Yku2pB1t+ImBTvYFU+WVEr bJF1+JwABvt4XEC23QOEQPrFHp1Q9hODloZKNi03iO06P+khV66AmmptysAgzoxsaOjR RHTtJFn+lhkUGOJp8wbdmm1mHVXKUAR/nq8b8zpgBUkRTXXxdmTpOKy/+Iebw9jP3kUO QZq6MKGZzIRI5wk0v0eRcGozahhD0/1NnP/96QO1WFH3ZcCYqR/J6cHcAgOJ2zwWuOFP TsJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aSWu7SERkDl4TrKpc52a/rImNAR7H05Ny8NJ0H5vIQY=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=QHRU+YPJ5hAtmltN4283lmMygadrPrl+c7lIsO6bbENXqFXFZoe9g9y94Hrdk/kL1p f0wXd1liSTjmwre5WrEHQS2Z/vQouzwCMse8cNsgs422cLsgpfvBgmZ3wdU0o1/FMUsD TSiOCNC+oBL9HCZ7a1xlraiTAncn6jW7B5biKZiCbItI4SlqRm9kDKxBqVA1WB9KTdiQ bLnFRYalXrAMngG/2GAg6rGD2/K9tVFV2eJSw7/xEXNNLO9b+PEq43K+QQvkm1cs+Aot A+cznq2z5A3CWiFimOP+uIX7KQbTAg7S2j6LmG0V9YgzP3W9y5GR8fsmEOuEjlzseENL DMaA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uCABt+86; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/21] target/arm: Apply correct timer offset when calculating deadlines Date: Fri, 7 Mar 2025 15:06:51 +0000 Message-ID: <20250307150708.3222813-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we are calculating timer deadlines, the correct definition of whether or not to apply an offset to the physical count is described in the Arm ARM DDI4087 rev L.a section D12.2.4.1. This is different from when the offset should be applied for a direct read of the counter sysreg. We got this right for the EL1 physical timer and for the EL1 virtual timer, but got all the rest wrong: they should be using a zero offset always. Factor the offset calculation out into a function that has a comment documenting exactly which offset it is calculating and which gets the HYP, SEC, and HYPVIRT cases right. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 20250204125009.2281315-2-peter.maydell@linaro.org --- target/arm/helper.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 71dead7241b..7f341d753cd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2460,6 +2460,32 @@ static uint64_t gt_phys_cnt_offset(CPUARMState *env) return gt_phys_raw_cnt_offset(env); } +static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) +{ + /* + * Return the timer offset to use for indirect accesses to the timer. + * This is the Offset value as defined in D12.2.4.1 "Operation of the + * CompareValue views of the timers". + * + * The condition here is not always the same as the condition for + * whether to apply an offset register when doing a direct read of + * the counter sysreg; those conditions are described in the + * access pseudocode for each counter register. + */ + switch (timeridx) { + case GTIMER_PHYS: + return gt_phys_raw_cnt_offset(env); + case GTIMER_VIRT: + return env->cp15.cntvoff_el2; + case GTIMER_HYP: + case GTIMER_SEC: + case GTIMER_HYPVIRT: + return 0; + default: + g_assert_not_reached(); + } +} + static void gt_recalc_timer(ARMCPU *cpu, int timeridx) { ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; @@ -2469,8 +2495,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) * Timer enabled: calculate and set current ISTATUS, irq, and * reset timer to when ISTATUS next has to change */ - uint64_t offset = timeridx == GTIMER_VIRT ? - cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env); + uint64_t offset = gt_indirect_access_timer_offset(&cpu->env, timeridx); uint64_t count = gt_get_countervalue(&cpu->env); /* Note that this must be unsigned 64 bit arithmetic: */ int istatus = count - offset >= gt->cval; From patchwork Fri Mar 7 15:06:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871185 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp808751wri; Fri, 7 Mar 2025 07:08:29 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWqN1aTVQ8Q446vVDzFRmzS2hYgoKObsVu4vO47CaNtY71xiaeIQbJz4UAh+xtKGHNM7/N5Eg==@linaro.org X-Google-Smtp-Source: AGHT+IHS4OQ1N3S8vytWRPGfD43x4z92JGrGBtDnR/FRtBegpCBnH7GujcH604UPIf02awi4yPaW X-Received: by 2002:a05:6122:8297:b0:51b:a11f:cbdb with SMTP id 71dfb90a1353d-523e4172c0amr3004903e0c.4.1741360107863; Fri, 07 Mar 2025 07:08:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360107; cv=none; d=google.com; s=arc-20240605; b=TS+9eM53OZ7Au5stKEA7jAH1IgLJuJmXUM1pIxBgTitWcxPQxNQjNiUvoqH3SJDejK 6JwxYeOIMepbLkacPjNUvIsOpy61GxiEKZqoPoYdBFCBITm50dpKrW77zZssIO+f/H/9 baO0xW0TtFBvu0HpJCwwvwKsyxNv/CzbcAX+9eal+zcnu7X1PvWTLq32maip0f6YGrlF FXvIyhvl1kIZOAhWWhQpTsN9/HPjOa+IGjv9ZiTh4mFkxgpUchBRS9G51HmfEE4xkHA9 nyURRUnPl9KRWpqHoZfmY12Cd/JRYGitIdQU3atIM9JQLAzfJukDqeti6IlMeV6yXq6t kndQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=li357AJWMFZ6xWx4JegFBm32HWxf9f0kQo9Ln4K3jaE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=UEp7n98bVAZbRfXuWoCHK27Mpa+jqevjW1c7QJCNNFVdyFwrUTvPD11df9PFs+BiHF PaHrZ5BDEFHy1fKI6+y0etpZzImogpAVfQwJQsnHorP+g6S1tcl55WbU0QRTGecOH6EM OaRyT88L30xHETjubWsGc5Ngn95vKbNIGsRVcq2IwJW+jaNL4W1vMJhRsfmoRFBIqdEH TmkaWLNIujhxHfFsP0bkWNguk7PSW/XdNXMHSoou2ZlVi+8rM6ZJ4O3Mg9A/Plyy+OSI s+Fn+lS7j+m3ghVipi8pSn38qDC1e/O/Orjedgq5EFD01HrgtY9zNlgTAEvogGzR6sC2 ++lg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rAFbZoZD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/21] target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer Date: Fri, 7 Mar 2025 15:06:52 +0000 Message-ID: <20250307150708.3222813-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The CNTVOFF_EL2 offset register should only be applied for accessses to CNTVCT_EL0 and for the EL1 virtual timer (CNTV_*). We were incorrectly applying it for the EL2 virtual timer (CNTHV_*). Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 20250204125009.2281315-3-peter.maydell@linaro.org --- target/arm/helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7f341d753cd..5729b313f84 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2604,7 +2604,6 @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, switch (timeridx) { case GTIMER_VIRT: - case GTIMER_HYPVIRT: offset = gt_virt_cnt_offset(env); break; case GTIMER_PHYS: @@ -2624,7 +2623,6 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, switch (timeridx) { case GTIMER_VIRT: - case GTIMER_HYPVIRT: offset = gt_virt_cnt_offset(env); break; case GTIMER_PHYS: From patchwork Fri Mar 7 15:06:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871199 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp811176wri; Fri, 7 Mar 2025 07:12:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXbEAI9Le6ifPqYQGsyGaC1OV0HD0fu7j+g5qzNqIFTfpaxnj/vQxBDdCX/5cRdLKyOL/2kRQ==@linaro.org X-Google-Smtp-Source: AGHT+IFNIyMRy5gJ5pg+zzKKAZtr8lNim27usWdAK4NVV8hiEX1aQ6TBl7mGOspR/y7a8f+tZDVv X-Received: by 2002:a05:6122:1d45:b0:520:5a87:66eb with SMTP id 71dfb90a1353d-523e413acc8mr2845314e0c.3.1741360370900; Fri, 07 Mar 2025 07:12:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360370; cv=none; d=google.com; s=arc-20240605; b=IZ26XZ/Yx8PFPm6qUai9HgrZRspPhTbkRQy6uaWIgyrArlgDMJtNHDO3soM69HhoiC pRTQZqJcQPPVdPjSjQAfQT+jusui1MbOKTPM3GMJ0NQx92nBOkyah2xaCGvbEdevIzoX Ubt09ZMooC9rOkDFhI+Z82Zfx3FQXpkz58tirmXJeoYZr98PbcIgptELo0J24zV40d5W xpwrAJOGOa6zzPxDz0fLOctwkha8gBBVBE6rpCqX3sbHtZvT42I8xKY+2ZFxlYtOKQ0G ClA8I7G657Ip9jSVFzGXbJXScmXW72eKHAPYiyB8Q2OmRco96o9UXWS3CPFNUbpqpbKc niQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VbVylxx7Oy35uID6Gb8pD3yEbXq+7FDTy6cITNgisqM=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=J0RcYxphftCy9TGdkspotx+t1uyo6JzaFaU2ct2H2MnS9LcIvmMsLx6PNPs4ZIQXId Sz+isNj02peblcuWTJb/2DHPpDyb1qdscJN/hVQL+Alu1F97tszd/NVH9Pz0UkLlVXU8 1hP1XLcz1h7Yqb4mfrXm4e77SSoE6MBPR3XrvA21Mf8MC3yvKh+OHHB96+e4MqojzO61 1aeaKSflQtGIRRuz5npImNR5y4oyI75JAPu/rGlT3qm/hqNaPH6qIag+REgc5Z17564y dwaDZmh4Me5hIY8w3OrrTGImNTohG5dg988lQvkuVTZd8zMPcR75NBXplQIAVNfTMHIu /1bw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dx8rS4Hi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/21] target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled Date: Fri, 7 Mar 2025 15:06:53 +0000 Message-ID: <20250307150708.3222813-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we added Secure EL2 support, we missed that this needs an update to the access code for the EL3 physical timer registers. These are supposed to UNDEF from Secure EL1 when Secure EL2 is enabled. (Note for stable backporting: for backports to branches where CP_ACCESS_UNDEFINED is not defined, the old name to use instead is CP_ACCESS_TRAP_UNCATEGORIZED.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 20250204125009.2281315-4-peter.maydell@linaro.org --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5729b313f84..5b6de446ace 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2387,6 +2387,9 @@ static CPAccessResult gt_stimer_access(CPUARMState *env, if (!arm_is_secure(env)) { return CP_ACCESS_UNDEFINED; } + if (arm_is_el2_enabled(env)) { + return CP_ACCESS_UNDEFINED; + } if (!(env->cp15.scr_el3 & SCR_ST)) { return CP_ACCESS_TRAP_EL3; } From patchwork Fri Mar 7 15:06:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871189 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp809519wri; Fri, 7 Mar 2025 07:09:54 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWdU6vTFHBsAHFiM+gbfMbYlU6pPYaZEeQfF09L8BYImRd8vKIBIfjHubD37y4VNwVqWYaN9A==@linaro.org X-Google-Smtp-Source: AGHT+IFbcrPOZrmRQlqvmtlx98/f3AGzaQjwdu6/FL4skcLeHMrJEHFr4Z74Qf98waaPB6zsG5S7 X-Received: by 2002:a0c:fc46:0:b0:6e8:fee2:aadf with SMTP id 6a1803df08f44-6e9006752ebmr34427616d6.31.1741360194566; Fri, 07 Mar 2025 07:09:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360194; cv=none; d=google.com; s=arc-20240605; b=MH/kQrsFqb79V7W9aE8s8zQJSIQkYYVAHoZPBLBD+FRgv4LrcTsiSg3475XLDOEUGO KDxWVU8v9HbPZNxz92Rq8UNLk4aXPaclTCIdNLG4v1XYjfzUshqTjuKucrJyvJp/13VI YQuqCpB6xDv8j7S8Q0MujiXlymny8V0lRig1MlOBGyBOumlI4WqPrtB2fA0u12+JCjYr lMP3C3m+nNlaWgFIRi37VEH/LHQUwyJS8bwBe0DYxo91m2pqqd/mmFB/aq3VwMmvW666 pCBT6HkdHefHsj9iRIuRQIrgve+3C1n/h3X9pJGcHv28gBiiaXmZhrytGd7y9sIvhunD Di9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=h3NyAbjZw6t/Yl0m428z8/u6iBTIpIakfmeyR5Ut3i0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=aJBIibuSZ+V2/zlWoxmQCLk72jFbz5cWQEtUlY+9COgUMGdkjRpyo+frVVMveairjl MDHKNr3Ow3pyn5TuZVtgKH37Uz0JvAcupJG87y4NKDMJQ7h1LiLREbsFjTkl/6wBOfJe 9hnjAgGAdyBnBWh0kY9GpIzys3dZzOygXI+NXqyNB+7vUDOSLTEv6XCafEA4nS7YG33n hlhB8lYqNvj4MrCfizPH2gTVO2hDu8PnYFWVZxSLQ/bbSMqXCvtoqwNOIpil8WVNrFzp XeIXplZ2bumFC0DnNEkaFqzP1c9YJbOPUF+qwJdDcQyK6bOXTdMq0wayFduWeOucUBkw khLg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WWU9FYpn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/21] target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses Date: Fri, 7 Mar 2025 15:06:54 +0000 Message-ID: <20250307150708.3222813-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently we handle CNTV_TVAL_EL02 by calling gt_tval_read() for the EL1 virt timer. This is almost correct, but the underlying CNTV_TVAL_EL0 register behaves slightly differently. CNTV_TVAL_EL02 always applies the CNTVOFF_EL2 offset; CNTV_TVAL_EL0 doesn't do so if we're at EL2 and HCR_EL2.E2H is 1. We were getting this wrong, because we ended up in gt_virt_cnt_offset() and did the E2H check. Factor out the tval read/write calculation from the selection of the offset, so that we can special case gt_virt_tval_read() and gt_virt_tval_write() to unconditionally pass CNTVOFF_EL2. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 20250204125009.2281315-5-peter.maydell@linaro.org --- target/arm/helper.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5b6de446ace..acf77793c79 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2600,6 +2600,12 @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, gt_recalc_timer(env_archcpu(env), timeridx); } +static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset) +{ + return (uint32_t)(env->cp15.c14_timer[timeridx].cval - + (gt_get_countervalue(env) - offset)); +} + static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx) { @@ -2614,8 +2620,16 @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, break; } - return (uint32_t)(env->cp15.c14_timer[timeridx].cval - - (gt_get_countervalue(env) - offset)); + return do_tval_read(env, timeridx, offset); +} + +static void do_tval_write(CPUARMState *env, int timeridx, uint64_t value, + uint64_t offset) +{ + trace_arm_gt_tval_write(timeridx, value); + env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + + sextract64(value, 0, 32); + gt_recalc_timer(env_archcpu(env), timeridx); } static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2632,11 +2646,7 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, offset = gt_phys_cnt_offset(env); break; } - - trace_arm_gt_tval_write(timeridx, value); - env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + - sextract64(value, 0, 32); - gt_recalc_timer(env_archcpu(env), timeridx); + do_tval_write(env, timeridx, value, offset); } static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2768,13 +2778,21 @@ static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) { - return gt_tval_read(env, ri, GTIMER_VIRT); + /* + * This is CNTV_TVAL_EL02; unlike the underlying CNTV_TVAL_EL0 + * we always apply CNTVOFF_EL2. Special case that here rather + * than going into the generic gt_tval_read() and then having + * to re-detect that it's this register. + * Note that the accessfn/perms mean we know we're at EL2 or EL3 here. + */ + return do_tval_read(env, GTIMER_VIRT, env->cp15.cntvoff_el2); } static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - gt_tval_write(env, ri, GTIMER_VIRT, value); + /* Similarly for writes to CNTV_TVAL_EL02 */ + do_tval_write(env, GTIMER_VIRT, value, env->cp15.cntvoff_el2); } static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Fri Mar 7 15:06:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871187 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp809191wri; Fri, 7 Mar 2025 07:09:22 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXKUamywHPX+dUVdM2MXx0EjmBV3Sw+jJykAw7XxbCIxF58Tz/eKGLSUZSFpZwclkBf4CuuWw==@linaro.org X-Google-Smtp-Source: AGHT+IH2+Xc1w9V6PscpHwN9hQXv456J45df6ywP7tkdlgQu0zZRP7uUdsJGP4uGo7Q1QJfZSVQa X-Received: by 2002:a05:6122:2005:b0:520:6773:e5ea with SMTP id 71dfb90a1353d-523e411fa7dmr2952930e0c.7.1741360161232; Fri, 07 Mar 2025 07:09:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360161; cv=none; d=google.com; s=arc-20240605; b=OXTjDmOeqbUZoqCG5/G8P780sQ6zVkY5ou5pgviCS+KowC5x7F1EuqPRTh0P4f9+L/ /M1+4NDfsbhCQRN/eVi34xnTQP4Hjsi2WDQPdqPHkb6acyh/+v/cnNscBVBSguJGFasU +A15rq1YjneulswkaD+LvgIMf3E9Oafth/VXkQ2X6Db5AFsn8ZUNq4OugV6EgfSrdlYZ 87AkT+nXuz6pq/PotY0X6GZtiRIU2MrTmQOu5Fwcaz2+O+QRZt16W6fd3WYsMVK2gfTM l6a3eivjEhaFURH0qbLqeCKtovzKRZi6Vqy2PqSG3x+iA/o6j5vDkgjcFn+EQmm57nG6 KfHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Tjmv83nAHErAC/ciev0XLUkQWxcsHmZ1ReYlvJi0IGY=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=M0Upy7lpgq1LLw3/87TjZEWLg3OSmDxhfxAXezDv6vBF6zpNUp/7TY5oh7TpEhMvfm 6SZhcebqTsERwhRjDC1ANdr1JxUOubI5C+g9CogLo8NqRGOcGBYPytISISSdIuny/wbq yvPeawT/6Oth2IBn9JtJ/i6aGPAtxFSCpRaluv+5R8opeYLz9csVkgL/sZNaRQ8jNFnr c5ULm3/ceAqWBzO0mOXGlZGF1aU6vcREO3eD5VTwkWciPeNyJEXZIN8V/TzwEjzGB8WK F+f5aSMkd7Nn1X7dmiLam1+9trok9CZ/+VTFFDhw3vj9ibVqNtU/l28j8Hze9R8H+uFd 31Lg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Guu0Ak6N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/21] target/arm: Refactor handling of timer offset for direct register accesses Date: Fri, 7 Mar 2025 15:06:55 +0000 Message-ID: <20250307150708.3222813-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When reading or writing the timer registers, sometimes we need to apply one of the timer offsets. Specifically, this happens for direct reads of the counter registers CNTPCT_EL0 and CNTVCT_EL0 (and their self-synchronized variants CNTVCTSS_EL0 and CNTPCTSS_EL0). It also applies for direct reads and writes of the CNT*_TVAL_EL* registers that provide the 32-bit downcounting view of each timer. We currently do this with duplicated code in gt_tval_read() and gt_tval_write() and a special-case in gt_virt_cnt_read() and gt_cnt_read(). Refactor this so that we handle it all in a single function gt_direct_access_timer_offset(), to parallel how we handle the offset for indirect accesses. The call in the WFIT helper previously to gt_virt_cnt_offset() is now to gt_direct_access_timer_offset(); this is the correct behaviour, but it's not immediately obvious that it shouldn't be considered an indirect access, so we add an explanatory comment. This commit should make no behavioural changes. (Cc to stable because the following bugfix commit will depend on this one.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 20250204125009.2281315-6-peter.maydell@linaro.org --- target/arm/internals.h | 5 +- target/arm/helper.c | 103 +++++++++++++++++++------------------ target/arm/tcg/op_helper.c | 8 ++- 3 files changed, 62 insertions(+), 54 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a6ff228f9fd..bb962389192 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1819,9 +1819,10 @@ int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type); uint64_t gt_get_countervalue(CPUARMState *env); /* * Return the currently applicable offset between the system counter - * and CNTVCT_EL0 (this will be either 0 or the value of CNTVOFF_EL2). + * and the counter for the specified timer, as used for direct register + * accesses. */ -uint64_t gt_virt_cnt_offset(CPUARMState *env); +uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx); /* * Return mask of ARMMMUIdxBit values corresponding to an "invalidate diff --git a/target/arm/helper.c b/target/arm/helper.c index acf77793c79..54147d97611 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2455,14 +2455,6 @@ static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env) return 0; } -static uint64_t gt_phys_cnt_offset(CPUARMState *env) -{ - if (arm_current_el(env) >= 2) { - return 0; - } - return gt_phys_raw_cnt_offset(env); -} - static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) { /* @@ -2489,6 +2481,52 @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) } } +uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx) +{ + /* + * Return the timer offset to use for direct accesses to the + * counter registers CNTPCT and CNTVCT, and for direct accesses + * to the CNT*_TVAL registers. + * + * This isn't exactly the same as the indirect-access offset, + * because here we also care about what EL the register access + * is being made from. + * + * This corresponds to the access pseudocode for the registers. + */ + uint64_t hcr; + + switch (timeridx) { + case GTIMER_PHYS: + if (arm_current_el(env) >= 2) { + return 0; + } + return gt_phys_raw_cnt_offset(env); + case GTIMER_VIRT: + switch (arm_current_el(env)) { + case 2: + hcr = arm_hcr_el2_eff(env); + if (hcr & HCR_E2H) { + return 0; + } + break; + case 0: + hcr = arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { + return 0; + } + break; + } + return env->cp15.cntvoff_el2; + case GTIMER_HYP: + case GTIMER_SEC: + case GTIMER_HYPVIRT: + return 0; + default: + g_assert_not_reached(); + } +} + static void gt_recalc_timer(ARMCPU *cpu, int timeridx) { ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; @@ -2561,34 +2599,14 @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { - return gt_get_countervalue(env) - gt_phys_cnt_offset(env); -} - -uint64_t gt_virt_cnt_offset(CPUARMState *env) -{ - uint64_t hcr; - - switch (arm_current_el(env)) { - case 2: - hcr = arm_hcr_el2_eff(env); - if (hcr & HCR_E2H) { - return 0; - } - break; - case 0: - hcr = arm_hcr_el2_eff(env); - if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { - return 0; - } - break; - } - - return env->cp15.cntvoff_el2; + uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_PHYS); + return gt_get_countervalue(env) - offset; } static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { - return gt_get_countervalue(env) - gt_virt_cnt_offset(env); + uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT); + return gt_get_countervalue(env) - offset; } static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2609,16 +2627,7 @@ static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset) static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx) { - uint64_t offset = 0; - - switch (timeridx) { - case GTIMER_VIRT: - offset = gt_virt_cnt_offset(env); - break; - case GTIMER_PHYS: - offset = gt_phys_cnt_offset(env); - break; - } + uint64_t offset = gt_direct_access_timer_offset(env, timeridx); return do_tval_read(env, timeridx, offset); } @@ -2636,16 +2645,8 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx, uint64_t value) { - uint64_t offset = 0; + uint64_t offset = gt_direct_access_timer_offset(env, timeridx); - switch (timeridx) { - case GTIMER_VIRT: - offset = gt_virt_cnt_offset(env); - break; - case GTIMER_PHYS: - offset = gt_phys_cnt_offset(env); - break; - } do_tval_write(env, timeridx, value, offset); } diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 02c375d196d..30786fd1ff4 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -427,7 +427,13 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout) int target_el = check_wfx_trap(env, false, &excp); /* The WFIT should time out when CNTVCT_EL0 >= the specified value. */ uint64_t cntval = gt_get_countervalue(env); - uint64_t offset = gt_virt_cnt_offset(env); + /* + * We want the value that we would get if we read CNTVCT_EL0 from + * the current exception level, so the direct_access offset, not + * the indirect_access one. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/21] target/arm: Implement SEL2 physical and virtual timers Date: Fri, 7 Mar 2025 15:06:56 +0000 Message-ID: <20250307150708.3222813-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Alex Bennée When FEAT_SEL2 was implemented the SEL2 timers were missed. This shows up when building the latest Hafnium with SPMC_AT_EL=2. The actual implementation utilises the same logic as the rest of the timers so all we need to do is: - define the timers and their access functions - conditionally add the correct system registers - create a new accessfn as the rules are subtly different to the existing secure timer Fixes: e9152ee91c (target/arm: add ARMv8.4-SEL2 system registers) Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell Message-id: 20250204125009.2281315-7-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org Cc: Andrei Homescu Cc: Arve Hjønnevåg Cc: Rémi Denis-Courmont [PMM: CP_ACCESS_TRAP_UNCATEGORIZED -> CP_ACCESS_UNDEFINED; offset logic now in gt_{indirect,direct}_access_timer_offset() ] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/bsa.h | 2 + target/arm/cpu.h | 2 + target/arm/gtimer.h | 4 +- target/arm/cpu.c | 4 ++ target/arm/helper.c | 163 +++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 174 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h index 8eaab603c03..13ed2d2ac19 100644 --- a/include/hw/arm/bsa.h +++ b/include/hw/arm/bsa.h @@ -22,6 +22,8 @@ #define QEMU_ARM_BSA_H /* These are architectural INTID values */ +#define ARCH_TIMER_S_EL2_VIRT_IRQ 19 +#define ARCH_TIMER_S_EL2_IRQ 20 #define VIRTUAL_PMU_IRQ 23 #define ARCH_GIC_MAINT_IRQ 25 #define ARCH_TIMER_NS_EL2_IRQ 26 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 215845c7e25..8f52380c88c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1171,6 +1171,8 @@ void arm_gt_vtimer_cb(void *opaque); void arm_gt_htimer_cb(void *opaque); void arm_gt_stimer_cb(void *opaque); void arm_gt_hvtimer_cb(void *opaque); +void arm_gt_sel2timer_cb(void *opaque); +void arm_gt_sel2vtimer_cb(void *opaque); unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h index b992941bef1..0e89b8e58d0 100644 --- a/target/arm/gtimer.h +++ b/target/arm/gtimer.h @@ -15,7 +15,9 @@ enum { GTIMER_HYP = 2, GTIMER_SEC = 3, GTIMER_HYPVIRT = 4, -#define NUM_GTIMERS 5 + GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */ + GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */ +#define NUM_GTIMERS 7 }; #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 948defa3f5d..cacbbc615a2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2069,6 +2069,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) arm_gt_stimer_cb, cpu); cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, arm_gt_hvtimer_cb, cpu); + cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_sel2timer_cb, cpu); + cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_sel2vtimer_cb, cpu); } #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 54147d97611..407efe9427c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2404,6 +2404,45 @@ static CPAccessResult gt_stimer_access(CPUARMState *env, } } +static CPAccessResult gt_sel2timer_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* + * The AArch64 register view of the secure EL2 timers are mostly + * accessible from EL3 and EL2 although can also be trapped to EL2 + * from EL1 depending on nested virt config. + */ + switch (arm_current_el(env)) { + case 0: /* UNDEFINED */ + return CP_ACCESS_UNDEFINED; + case 1: + if (!arm_is_secure(env)) { + /* UNDEFINED */ + return CP_ACCESS_UNDEFINED; + } else if (arm_hcr_el2_eff(env) & HCR_NV) { + /* Aarch64.SystemAccessTrap(EL2, 0x18) */ + return CP_ACCESS_TRAP_EL2; + } + /* UNDEFINED */ + return CP_ACCESS_UNDEFINED; + case 2: + if (!arm_is_secure(env)) { + /* UNDEFINED */ + return CP_ACCESS_UNDEFINED; + } + return CP_ACCESS_OK; + case 3: + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_OK; + } else { + return CP_ACCESS_UNDEFINED; + } + default: + g_assert_not_reached(); + } +} + uint64_t gt_get_countervalue(CPUARMState *env) { ARMCPU *cpu = env_archcpu(env); @@ -2475,6 +2514,8 @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) case GTIMER_HYP: case GTIMER_SEC: case GTIMER_HYPVIRT: + case GTIMER_S_EL2_PHYS: + case GTIMER_S_EL2_VIRT: return 0; default: g_assert_not_reached(); @@ -2521,6 +2562,8 @@ uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx) case GTIMER_HYP: case GTIMER_SEC: case GTIMER_HYPVIRT: + case GTIMER_S_EL2_PHYS: + case GTIMER_S_EL2_VIRT: return 0; default: g_assert_not_reached(); @@ -2953,6 +2996,62 @@ static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_SEC, value); } +static void gt_sec_pel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_S_EL2_PHYS); +} + +static void gt_sec_pel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_S_EL2_PHYS, value); +} + +static uint64_t gt_sec_pel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_S_EL2_PHYS); +} + +static void gt_sec_pel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_S_EL2_PHYS, value); +} + +static void gt_sec_pel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_S_EL2_PHYS, value); +} + +static void gt_sec_vel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_S_EL2_VIRT); +} + +static void gt_sec_vel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_S_EL2_VIRT, value); +} + +static uint64_t gt_sec_vel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_S_EL2_VIRT); +} + +static void gt_sec_vel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_S_EL2_VIRT, value); +} + +static void gt_sec_vel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_S_EL2_VIRT, value); +} + static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) { gt_timer_reset(env, ri, GTIMER_HYPVIRT); @@ -3009,6 +3108,20 @@ void arm_gt_stimer_cb(void *opaque) gt_recalc_timer(cpu, GTIMER_SEC); } +void arm_gt_sel2timer_cb(void *opaque) +{ + ARMCPU *cpu = opaque; + + gt_recalc_timer(cpu, GTIMER_S_EL2_PHYS); +} + +void arm_gt_sel2vtimer_cb(void *opaque) +{ + ARMCPU *cpu = opaque; + + gt_recalc_timer(cpu, GTIMER_S_EL2_VIRT); +} + void arm_gt_hvtimer_cb(void *opaque) { ARMCPU *cpu = opaque; @@ -5733,6 +5846,56 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = { .access = PL2_RW, .accessfn = sel2_access, .nv2_redirect_offset = 0x48, .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, +#ifndef CONFIG_USER_ONLY + /* Secure EL2 Physical Timer */ + { .name = "CNTHPS_TVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 0, + .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .readfn = gt_sec_pel2_tval_read, + .writefn = gt_sec_pel2_tval_write, + .resetfn = gt_sec_pel2_timer_reset, + }, + { .name = "CNTHPS_CTL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 1, + .type = ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].ctl), + .resetvalue = 0, + .writefn = gt_sec_pel2_ctl_write, .raw_writefn = raw_write, + }, + { .name = "CNTHPS_CVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 2, + .type = ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].cval), + .writefn = gt_sec_pel2_cval_write, .raw_writefn = raw_write, + }, + /* Secure EL2 Virtual Timer */ + { .name = "CNTHVS_TVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 0, + .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .readfn = gt_sec_vel2_tval_read, + .writefn = gt_sec_vel2_tval_write, + .resetfn = gt_sec_vel2_timer_reset, + }, + { .name = "CNTHVS_CTL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 1, + .type = ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].ctl), + .resetvalue = 0, + .writefn = gt_sec_vel2_ctl_write, .raw_writefn = raw_write, + }, + { .name = "CNTHVS_CVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 2, + .type = ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].cval), + .writefn = gt_sec_vel2_cval_write, .raw_writefn = raw_write, + }, +#endif }; static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Fri Mar 7 15:06:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871195 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp810394wri; Fri, 7 Mar 2025 07:11:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWBNt1vgbaHb+6OsS0cpXfWQW+PNBWgjUT8P9xUuKlehEMERQRuhV8x/aZkLjBl4Tu4u/tbpw==@linaro.org X-Google-Smtp-Source: AGHT+IECBWpI1F57J13HNVqEPQPNxF1LJkHkTqypWrUqlDhThzYOFTTOmk81GsDC5UdTyjsgLRFu X-Received: by 2002:a05:6214:212b:b0:6e8:ff23:66d6 with SMTP id 6a1803df08f44-6e9005aef8emr42014426d6.9.1741360279657; Fri, 07 Mar 2025 07:11:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360279; cv=none; d=google.com; s=arc-20240605; b=CfGt7bJRlt8mexPy1Yc/7+2giarO4puSINJjlh8z+3dLHyGxPezkiP2oJccDKqMGLu bk/2nJIhfmX8ZdJjzOb2LG/yvzVaSoKZulErajJlzsBb2adGxckrJdtA55owR/RRDNHB 0mbjxo2jiENETZkCpUCSGLu38UeHuE3yaiLfjOrA8sjRkozSyZC5VM086Cv5wW7Q8tQW NKuV2bYzD9iA0Njh08u+WifvtCQ4poIEwBMr+s7D02JBqy2F2sjhnCtG6FyCkXTNalMt jmV9jZTYdlt1dbIV4e7vfOzHXP7t5GdmYxDhk0EmPgNBshKdp79JUqtQL6QV2Crh4Q8z c59w== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/21] target/arm: Document the architectural names of our GTIMERs Date: Fri, 7 Mar 2025 15:06:57 +0000 Message-ID: <20250307150708.3222813-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Alex Bennée As we are about to add more physical and virtual timers let's make it clear what each timer does. Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell Message-id: 20250204125009.2281315-8-peter.maydell@linaro.org [PMM: Add timer register name prefix to each comment] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/gtimer.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h index 0e89b8e58d0..d49c63cbf87 100644 --- a/target/arm/gtimer.h +++ b/target/arm/gtimer.h @@ -10,11 +10,11 @@ #define TARGET_ARM_GTIMER_H enum { - GTIMER_PHYS = 0, - GTIMER_VIRT = 1, - GTIMER_HYP = 2, - GTIMER_SEC = 3, - GTIMER_HYPVIRT = 4, + GTIMER_PHYS = 0, /* CNTP_* ; EL1 physical timer */ + GTIMER_VIRT = 1, /* CNTV_* ; EL1 virtual timer */ + GTIMER_HYP = 2, /* CNTHP_* ; EL2 physical timer */ + GTIMER_SEC = 3, /* CNTPS_* ; EL3 physical timer */ + GTIMER_HYPVIRT = 4, /* CNTHV_* ; EL2 virtual timer ; only if FEAT_VHE */ GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */ GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */ #define NUM_GTIMERS 7 From patchwork Fri Mar 7 15:06:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871186 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp809157wri; Fri, 7 Mar 2025 07:09:17 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU5FMXVDT248CQxOtzr+jNkw6qdVa0ii3qbhZ7C3w650lgqutEL1jUNLJYu7omY9AeBbpGS9w==@linaro.org X-Google-Smtp-Source: AGHT+IE8iO5yaI/tdXFw5Q6EsU7THygLafE/c+zx9VBp1t5D1MbIonZX/7Jf+tSTTxguauSLYYOC X-Received: by 2002:a05:6122:3092:b0:523:dd87:fe86 with SMTP id 71dfb90a1353d-523e42144bemr3035405e0c.6.1741360156986; Fri, 07 Mar 2025 07:09:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360156; cv=none; d=google.com; s=arc-20240605; b=JtUydtHc68G6YFRgHWKqe/dtvLqj+Sr2/ZgnC94uDcAeDA6vhZ6HYd22vLY6hxExol uAFW3L9qeZhnXsBqLeGTJ+xkU/CofQphF7qZeOg5i2aHsS1YXT7ThrB0v/TlfUCEetxN vy2OY7nF8RrTBOYiAjykrmMTgGM1FCGlewXk41wuYpuEY8btwY0c4zEWpetPJYB+rvQV 8cAz9XtNpNK1jkG7GqJ12tIDTpJAxK7Y2bjvpeO0tCV9KfAzI2RAZFtts9S77fXGyKZ2 GtUnAc6pgLR+CxtvfqDVtS7J6rU3NaawSo64SUsJgE0o4AUZmkL9A55tiv2av+L/88iT 9HGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=POedfr8OIoRc4zd6hYJv4201L8L1FVmVr4GGYLpisj8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=dpMl7ToBzFIdHl1lO229Hnj7wicWzut8jeaHqatd61sRAK2HPWQ1+UMudfeXDIvvJg i4X7qRS3MoC04PruNOR8H5cWfNB64ZnHBMAY1NZiHz8TU8d/s808MRNHUNG58kyDLPUv 8gqbBgPQYwKt3t5Do0LN+m+fK673RX7dQjD/L2xqIOHJx980kbOuVkb9cj2+ieevy0Gg YwyAcIiHl/oh77wcxqE/5fpjN3UeqDbCD0yrH4o4Las2/k3cEOk69bVDbauCkUucjRYw TkDIPR+ghSwGrTcphUKvM7qlHnqZl1z2gQURGAantF1Lomvkm5jrVsFc5PRkFGsBi6FZ Dw4A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="kNBWhgy/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/21] hw/arm: enable secure EL2 timers for virt machine Date: Fri, 7 Mar 2025 15:06:58 +0000 Message-ID: <20250307150708.3222813-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Alex Bennée Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell Message-id: 20250204125009.2281315-9-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 904c698b140..a96452f17a4 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -882,6 +882,8 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, + [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ, + [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ, }; for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { From patchwork Fri Mar 7 15:06:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871191 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp809896wri; Fri, 7 Mar 2025 07:10:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV9y7wXPp7Om7ZoIml6FEeOIOodHeKZ/v1euwT1WN6/jJz4ju4IBtbz430+RRpdRsyxaqJTfQ==@linaro.org X-Google-Smtp-Source: AGHT+IHZA706+6sPcNdqXHP6egPOuvMRaE0o/I8X0oscZ6cE4EoV9y8Z+gRUtjRg5sBhUcFzowCE X-Received: by 2002:a05:620a:4808:b0:7c0:a3bd:a788 with SMTP id af79cd13be357-7c4e6104e2cmr650888885a.25.1741360232396; Fri, 07 Mar 2025 07:10:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360232; cv=none; d=google.com; s=arc-20240605; b=VBYRMhEBNZWuHAc9IM47mrl3qOFSeqnNEKy+3sTIhf5t/ff1Iuz4FKS9MNGisCRhK4 meH1SUF6bzDpAArY/W/XxoxQqawP/ygBVPvbpcCzj0vPTvtOGEdB9kovr8siuNvs2Cnv vn0fSsmPcSJrK1maozr4JnOeqPbmo+ExTQRnc47rgYIgeQe+TaMfBc4bdQOt4aEKl0zR TdbrzbW8LY3MKgCUFfqp4AmuifEsbsmddT7Tr1OztF0nuakvuiPfYR79F1OjZJPassQ3 rzsS7NBCWkxed2MYZRIF0X2zI084n0ygya6SvW3oouYzB2qLQ2x4dsfKyvmmYzzWqI55 dMCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=l5tIzE5Flt/Mk2PuwQMT4yx2y90XXlNLNl3RYwyZsjU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=b9iodkYfZMfcTUId1aUfIzL69WyHXk1g1F5Hnb4x8DUxuaRRjx764GJHkNQT2/8Jr+ gHplYu3xm/eq1aqkMWLLo+KYA8lr2Vjk0XdZWd5mFKJhd+t10r80b8MTZyiVuR+1HQTP bFcpm4dGK3aSnl08iYlhCdlZyBiGc6bAHixNpgYQZ22SyFXm6XAXD4jdUEI+zVfzfr1u VwcP2r2mZ+fV4W1gLiooYwaE0r+VDK1E4ePJXrcCR323pv4CI16+6l6p/qqy1rHOY60M sjn4ANurpwTt4pIKa7JRqa3VbLK7vc3dInBaD9aoRSqpyuWb9E1QC8X6do4tR0rbhqtz wiSQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NyynZ3z4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/21] hw/arm: enable secure EL2 timers for sbsa machine Date: Fri, 7 Mar 2025 15:06:59 +0000 Message-ID: <20250307150708.3222813-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Alex Bennée Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell Message-id: 20250204125009.2281315-10-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index e720de30641..aa09d7a0917 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -484,6 +484,8 @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, + [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ, + [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ, }; for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { From patchwork Fri Mar 7 15:07:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871194 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp809950wri; Fri, 7 Mar 2025 07:10:37 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVbLFdGyB+gxVrHovS20B8iYNbuJCAnNFvzuD5aKcoGWPWLYhnxD+wH1ePugd7cajk352nx/w==@linaro.org X-Google-Smtp-Source: AGHT+IFwO6EWkOLeg8JI3bxb5Hw5b+Hw4IPRcZe5goQ/gLTi4DNTQ0pONoA3K7H+6YfBFu2E8FUO X-Received: by 2002:a05:6102:578f:b0:4bb:e8c5:b168 with SMTP id ada2fe7eead31-4c30a5ec050mr2474031137.10.1741360237224; Fri, 07 Mar 2025 07:10:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360237; cv=none; d=google.com; s=arc-20240605; b=YvEWgsao7w3xELPiFte4vQ1Nb8FSfoWUzxIwUDDzqUGZsjKbBfAUS4sW4fHEz2UZaJ PpkdIBIqqv2Mu83m5/5jbAD25+Npsk7ytN2Pbv/QObWCES6M0pTkE7ECKkymxo09d9kM QeSjnWfcsvua6P64HR5rL9wxhX1aVBr+X6pJnv4iGtGStAlPBRTfSZeLtfkZDA1RYoQq zr7j30r+dROh/3e0leaD4rMc1vQKH50Pf8F7m0WIb01xlXjGyj0RQs8fujRxSg/3uRc9 jZ470Bp2t6weFC58lNwYXYtOXVUwtAzxgKtkbrOgsugGFu1pzAjsAbh0sBm4YjmgTlxL vg9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sPQzlaT0o0OQv6YSIoANGooc60IYlGPPa8yEd55FTZY=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=R5EjvvqGA6H6g4smrZ6AL76mT+8+X2QVjjTVbl1opdHYGbS+q/tJzsKwB3th8/ZYKu OAC1IRasEUbnjiJ9D5ceOKmijg20RCIh/gHk+vYuFtgI+Yu12OxdkWCCCXLzZ/YqeQJU /PwsL/H5nFgUeD0hd39o1wwWBHTseO0XN/xZINKqOkVTjO9um/DwZgFgSKyWM4EnRMJW poRuroaIPsUb8nN7K2Y6n+jWV6Fqgl8t5onxeM0kLAXPQK+PaubbQur8fCWnV5zmtTdO ZGA+oqNgnnln2EbzMf6N/AxEzEmXpC7nrWH0Xhpl4h9L0c29d1B/OvDZavcOIgD+6Jhv T89A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tEQ2plXs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/21] target/arm: Correct LDRD atomicity and fault behaviour Date: Fri, 7 Mar 2025 15:07:00 +0000 Message-ID: <20250307150708.3222813-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Our LDRD implementation is wrong in two respects: * if the address is 4-aligned and the load crosses a page boundary and the second load faults and the first load was to the base register (as in cases like "ldrd r2, r3, [r2]", then we must not update the base register before taking the fault * if the address is 8-aligned the access must be a 64-bit single-copy atomic access, not two 32-bit accesses Rewrite the handling of the loads in LDRD to use a single tcg_gen_qemu_ld_i64() and split the result into the destination registers. This allows us to get the atomicity requirements right, and also implicitly means that we won't update the base register too early for the page-crossing case. Note that because we no longer increment 'addr' by 4 in the course of performing the LDRD we must change the adjustment value we pass to op_addr_ri_post() and op_addr_rr_post(): it no longer needs to subtract 4 to get the correct value to use if doing base register writeback. STRD has the same problem with not getting the atomicity right; we will deal with that in the following commit. Cc: qemu-stable@nongnu.org Reported-by: Stu Grossman Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20250227142746.1698904-2-peter.maydell@linaro.org --- target/arm/tcg/translate.c | 70 +++++++++++++++++++++++++------------- 1 file changed, 46 insertions(+), 24 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index d8225b77c8c..93772da39a4 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -5003,10 +5003,49 @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, return true; } +static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2) +{ + /* + * LDRD is required to be an atomic 64-bit access if the + * address is 8-aligned, two atomic 32-bit accesses if + * it's only 4-aligned, and to give an alignment fault + * if it's not 4-aligned. This is MO_ALIGN_4 | MO_ATOM_SUBALIGN. + * Rt is always the word from the lower address, and Rt2 the + * data from the higher address, regardless of endianness. + * So (like gen_load_exclusive) we avoid gen_aa32_ld_i64() + * so we don't get its SCTLR_B check, and instead do a 64-bit access + * using MO_BE if appropriate and then split the two halves. + * + * For M-profile, and for A-profile before LPAE, the 64-bit + * atomicity is not required. We could model that using + * the looser MO_ATOM_IFALIGN_PAIR, but providing a higher + * level of atomicity than required is harmless (we would not + * currently generate better code for IFALIGN_PAIR here). + * + * This also gives us the correct behaviour of not updating + * rt if the load of rt2 faults; this is required for cases + * like "ldrd r2, r3, [r2]" where rt is also the base register. + */ + int mem_idx = get_mem_index(s); + MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data; + TCGv taddr = gen_aa32_addr(s, addr, opc); + TCGv_i64 t64 = tcg_temp_new_i64(); + TCGv_i32 tmp = tcg_temp_new_i32(); + TCGv_i32 tmp2 = tcg_temp_new_i32(); + + tcg_gen_qemu_ld_i64(t64, taddr, mem_idx, opc); + if (s->be_data == MO_BE) { + tcg_gen_extr_i64_i32(tmp2, tmp, t64); + } else { + tcg_gen_extr_i64_i32(tmp, tmp2, t64); + } + store_reg(s, rt, tmp); + store_reg(s, rt2, tmp2); +} + static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) { - int mem_idx = get_mem_index(s); - TCGv_i32 addr, tmp; + TCGv_i32 addr; if (!ENABLE_ARCH_5TE) { return false; @@ -5017,18 +5056,10 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) } addr = op_addr_rr_pre(s, a); - tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); - store_reg(s, a->rt, tmp); - - tcg_gen_addi_i32(addr, addr, 4); - - tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); - store_reg(s, a->rt + 1, tmp); + do_ldrd_load(s, addr, a->rt, a->rt + 1); /* LDRD w/ base writeback is undefined if the registers overlap. */ - op_addr_rr_post(s, a, addr, -4); + op_addr_rr_post(s, a, addr, 0); return true; } @@ -5152,23 +5183,14 @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) { - int mem_idx = get_mem_index(s); - TCGv_i32 addr, tmp; + TCGv_i32 addr; addr = op_addr_ri_pre(s, a); - tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); - store_reg(s, a->rt, tmp); - - tcg_gen_addi_i32(addr, addr, 4); - - tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); - store_reg(s, rt2, tmp); + do_ldrd_load(s, addr, a->rt, rt2); /* LDRD w/ base writeback is undefined if the registers overlap. */ - op_addr_ri_post(s, a, addr, -4); + op_addr_ri_post(s, a, addr, 0); return true; } From patchwork Fri Mar 7 15:07:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871193 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp809949wri; Fri, 7 Mar 2025 07:10:37 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVC2sxt3LkKA1ejMY7DqNDwUsJEk/wnIfSt1MAPHe8i2JlRbmi8/t7vB5+IyH2RcUqbaXiQLA==@linaro.org X-Google-Smtp-Source: AGHT+IFru3EmTXL1krkTKcEOFNYRqBZAyKvZhHMgXv8B54QmhwdOxoSn/hes3/lZRb6cSwOd53Z5 X-Received: by 2002:ac8:59d0:0:b0:471:ef27:a313 with SMTP id d75a77b69052e-476109bbc16mr52179201cf.23.1741360237195; Fri, 07 Mar 2025 07:10:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360237; cv=none; d=google.com; s=arc-20240605; b=OiozBIvQTkj3wl1tr5pE4W7+jF1/OtHH/jV+/NF3x51JDSRNbzPm++98SXqT0tPcmt vKsTIp3QxjbijNsFpujBqiEefnS4/hI5scGDx+dAuKw1+xsfcOPQ1OCsm+OvH0WBC+69 4yujuYc/nq2k6KDNkeF7bJdqL/KubqswCjcMVRbabLRcvhXW3y63u6JXRPnRLCNgo+O4 jRq3tOlyr6ErGNwYngigRaG4U/q0ovOjFkdeNoC+dB/+4r/lxSf4Tg7uuRuTVasNPa0a TOHKmgNJkjieEEJTNgESbcMiu4uAOA2tZwuDjTjf3jGbnVa0y9icg6H+BnZisfWtOSM8 JF7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=saDmTi5qBVoivSppj4pMAPptghWgJB1RwsIGgVuCH9w=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=P1ZtoXowX7rY6SkK1km0c5j82KbZOML1WwqKCBdj1Y4I3wNHbWT+eJ/0n9i18FCNBB BJw1FdeXN7pq18Jhrtc7CL1DhfRjCXaRBh9peg227IZoSWX1oOzkhOw8W62rxydUsTSs EczfQE9P53dqNRpCQpPyk5Bj7QNILKfzfvo8FlTmiEZctzg1sPDIHOttvEjYEMHCh5H6 o4pmnzaafruHe12yb4ZOGk9+UoPUw/TPwGJBZb8VTB0rxs/pvJpIvuQKq1B3F5bXAB8a I7aLKBQpb3gqR0d3K8PKL8vpGZOIM89Ur9tCQ0pTV/iSKxEwnP3yOf+Vgmb0aZL1vy90 yOkw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xa6cvBcf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/21] target/arm: Correct STRD atomicity Date: Fri, 7 Mar 2025 15:07:01 +0000 Message-ID: <20250307150708.3222813-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Our STRD implementation doesn't correctly implement the requirement: * if the address is 8-aligned the access must be a 64-bit single-copy atomic access, not two 32-bit accesses Rewrite the handling of STRD to use a single tcg_gen_qemu_st_i64() of a value produced by concatenating the two 32 bit source registers. This allows us to get the atomicity right. As with the LDRD change, now that we don't update 'addr' in the course of performing the store we need to adjust the offset we pass to op_addr_ri_post() and op_addr_rr_post(). Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20250227142746.1698904-3-peter.maydell@linaro.org --- target/arm/tcg/translate.c | 59 +++++++++++++++++++++++++------------- 1 file changed, 39 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 93772da39a4..404a254678a 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -5063,10 +5063,42 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) return true; } +static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2) +{ + /* + * STRD is required to be an atomic 64-bit access if the + * address is 8-aligned, two atomic 32-bit accesses if + * it's only 4-aligned, and to give an alignment fault + * if it's not 4-aligned. + * Rt is always the word from the lower address, and Rt2 the + * data from the higher address, regardless of endianness. + * So (like gen_store_exclusive) we avoid gen_aa32_ld_i64() + * so we don't get its SCTLR_B check, and instead do a 64-bit access + * using MO_BE if appropriate, using a value constructed + * by putting the two halves together in the right order. + * + * As with LDRD, the 64-bit atomicity is not required for + * M-profile, or for A-profile before LPAE, and we provide + * the higher guarantee always for simplicity. + */ + int mem_idx = get_mem_index(s); + MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data; + TCGv taddr = gen_aa32_addr(s, addr, opc); + TCGv_i32 t1 = load_reg(s, rt); + TCGv_i32 t2 = load_reg(s, rt2); + TCGv_i64 t64 = tcg_temp_new_i64(); + + if (s->be_data == MO_BE) { + tcg_gen_concat_i32_i64(t64, t2, t1); + } else { + tcg_gen_concat_i32_i64(t64, t1, t2); + } + tcg_gen_qemu_st_i64(t64, taddr, mem_idx, opc); +} + static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) { - int mem_idx = get_mem_index(s); - TCGv_i32 addr, tmp; + TCGv_i32 addr; if (!ENABLE_ARCH_5TE) { return false; @@ -5077,15 +5109,9 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) } addr = op_addr_rr_pre(s, a); - tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); + do_strd_store(s, addr, a->rt, a->rt + 1); - tcg_gen_addi_i32(addr, addr, 4); - - tmp = load_reg(s, a->rt + 1); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); - - op_addr_rr_post(s, a, addr, -4); + op_addr_rr_post(s, a, addr, 0); return true; } @@ -5213,20 +5239,13 @@ static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) { - int mem_idx = get_mem_index(s); - TCGv_i32 addr, tmp; + TCGv_i32 addr; addr = op_addr_ri_pre(s, a); - tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); + do_strd_store(s, addr, a->rt, rt2); - tcg_gen_addi_i32(addr, addr, 4); - - tmp = load_reg(s, rt2); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); - - op_addr_ri_post(s, a, addr, -4); + op_addr_ri_post(s, a, addr, 0); return true; } From patchwork Fri Mar 7 15:07:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871203 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp811947wri; Fri, 7 Mar 2025 07:14:21 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV+gDPyaTbCpmNyW3xbyxhfZ1vh486B6GYiabhE82KXJzyX2tY7zcpKmrqopOk4PZWiR1uKWQ==@linaro.org X-Google-Smtp-Source: AGHT+IFvW1nLoIxI2tBCNM90EtpeM7zehrpxqK9GD0ZUAxRmL0h/VJoSRdqNHQ9LLgI03mRvPReN X-Received: by 2002:a05:622a:454:b0:474:f369:8ddb with SMTP id d75a77b69052e-4761194bd9dmr45351781cf.35.1741360461372; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/21] target/arm: Drop unused address_offset from op_addr_{rr, ri}_post() Date: Fri, 7 Mar 2025 15:07:02 +0000 Message-ID: <20250307150708.3222813-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All the callers of op_addr_rr_post() and op_addr_ri_post() now pass in zero for the address_offset, so we can remove that argument. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250227142746.1698904-4-peter.maydell@linaro.org --- target/arm/tcg/translate.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 404a254678a..d2800181388 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -4941,7 +4941,7 @@ static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a) } static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a, - TCGv_i32 addr, int address_offset) + TCGv_i32 addr) { if (!a->p) { TCGv_i32 ofs = load_reg(s, a->rm); @@ -4954,7 +4954,6 @@ static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a, } else if (!a->w) { return; } - tcg_gen_addi_i32(addr, addr, address_offset); store_reg(s, a->rn, addr); } @@ -4974,7 +4973,7 @@ static bool op_load_rr(DisasContext *s, arg_ldst_rr *a, * Perform base writeback before the loaded value to * ensure correct behavior with overlapping index registers. */ - op_addr_rr_post(s, a, addr, 0); + op_addr_rr_post(s, a, addr); store_reg_from_load(s, a->rt, tmp); return true; } @@ -4999,7 +4998,7 @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); - op_addr_rr_post(s, a, addr, 0); + op_addr_rr_post(s, a, addr); return true; } @@ -5059,7 +5058,7 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) do_ldrd_load(s, addr, a->rt, a->rt + 1); /* LDRD w/ base writeback is undefined if the registers overlap. */ - op_addr_rr_post(s, a, addr, 0); + op_addr_rr_post(s, a, addr); return true; } @@ -5111,7 +5110,7 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) do_strd_store(s, addr, a->rt, a->rt + 1); - op_addr_rr_post(s, a, addr, 0); + op_addr_rr_post(s, a, addr); return true; } @@ -5147,13 +5146,14 @@ static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a) } static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a, - TCGv_i32 addr, int address_offset) + TCGv_i32 addr) { + int address_offset = 0; if (!a->p) { if (a->u) { - address_offset += a->imm; + address_offset = a->imm; } else { - address_offset -= a->imm; + address_offset = -a->imm; } } else if (!a->w) { return; @@ -5178,7 +5178,7 @@ static bool op_load_ri(DisasContext *s, arg_ldst_ri *a, * Perform base writeback before the loaded value to * ensure correct behavior with overlapping index registers. */ - op_addr_ri_post(s, a, addr, 0); + op_addr_ri_post(s, a, addr); store_reg_from_load(s, a->rt, tmp); return true; } @@ -5203,7 +5203,7 @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); - op_addr_ri_post(s, a, addr, 0); + op_addr_ri_post(s, a, addr); return true; } @@ -5216,7 +5216,7 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) do_ldrd_load(s, addr, a->rt, rt2); /* LDRD w/ base writeback is undefined if the registers overlap. */ - op_addr_ri_post(s, a, addr, 0); + op_addr_ri_post(s, a, addr); return true; } @@ -5245,7 +5245,7 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) do_strd_store(s, addr, a->rt, rt2); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/21] target/arm: Make dummy debug registers RAZ, not NOP Date: Fri, 7 Mar 2025 15:07:03 +0000 Message-ID: <20250307150708.3222813-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In debug_helper.c we provide a few dummy versions of debug registers: * DBGVCR (AArch32 only): enable bits for vector-catch debug events * MDCCINT_EL1: interrupt enable bits for the DCC debug communications channel * DBGVCR32_EL2: the AArch64 accessor for the state in DBGVCR We implemented these only to stop Linux crashing on startup, but we chose to implement them as ARM_CP_NOP. This worked for Linux where it only cares about trying to write to these registers, but is very confusing behaviour for anything that wants to read the registers (perhaps for context state switches), because the destination register will be left with whatever random value it happened to have before the read. Model these registers instead as RAZ. Fixes: 5e8b12ffbb8c68 ("target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0") Fixes: 5dbdc4342f479d ("target-arm: Implement dummy MDCCINT_EL1") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2708 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20250228162424.1917269-1-peter.maydell@linaro.org --- target/arm/debug_helper.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 36bffde74e9..a9a619ba6b1 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -1037,7 +1037,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { { .name = "DBGVCR", .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, .access = PL1_RW, .accessfn = access_tda, - .type = ARM_CP_NOP }, + .type = ARM_CP_CONST, .resetvalue = 0 }, /* * Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Channel but Linux may try to access this register. The 32-bit @@ -1046,7 +1046,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, .access = PL1_RW, .accessfn = access_tdcc, - .type = ARM_CP_NOP }, + .type = ARM_CP_CONST, .resetvalue = 0 }, /* * Dummy DBGCLAIM registers. * "The architecture does not define any functionality for the CLAIM tag bits.", @@ -1075,7 +1075,8 @@ static const ARMCPRegInfo debug_aa32_el1_reginfo[] = { { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, .access = PL2_RW, .accessfn = access_dbgvcr32, - .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, + .type = ARM_CP_CONST | ARM_CP_EL3_NO_EL2_KEEP, + .resetvalue = 0 }, }; static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { From patchwork Fri Mar 7 15:07:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871204 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp811985wri; Fri, 7 Mar 2025 07:14:25 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUh4fgQ+z3ilpetheqhBrytd9os1Bkv30CC5YJ4h7vxIuBQnLjkrtjH2jk74yFfFwbiQZBKiw==@linaro.org X-Google-Smtp-Source: AGHT+IHW4u2FNf09vgR/aVg+RlpD1UV7jK73NYCxHgBnp1r6XxsgHo0VxOLWhZkDkZbhYAe/o+DJ X-Received: by 2002:a05:6102:2d09:b0:4bb:e1c9:80c6 with SMTP id ada2fe7eead31-4c30a344411mr2990827137.0.1741360465187; Fri, 07 Mar 2025 07:14:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360465; cv=none; d=google.com; s=arc-20240605; b=VuWYkVesrsyOoyR/WdEKlFBpRtubV35Osio1UjEb1191iMplWioEKsjRolG5PR1aa2 YYACrptiLR5MnQCoV+7ZXYOOvQ29Ke69su+tYjYS3Oviz1qlchE+QB1GQ028S13LlSP/ z2/kk7+XcVRi895eEUPe5tMR0ZsIJFxlwAVGf6rzbcULo7c5ASzbjI4ic7bKVGOcdFSw 1i7XAi3qrSC+AJ+Nn+bZHEWNhmC5XCmTB+3gGM8/3yBah2oOE3pJr3M/0ixP5R7n1rnQ NRFtgkwZ+P6LFur4QpueejjJUZowh58DVuGz8POtCsYeYCDQ1vnMAopYGtGhqew3TZEl 67YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cZx+EJrwSEPWcdmfK70Ab9fdIcmzEh488cpidIw4fLI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=XsIWKwV3zuRL78NpFMRwUO2OlhooVbDJLN6Cen9eTNLYYZT/kPLTtFsCtE+ATATKSx IpEWSTUC6B+IZeJn/HVr4q2ajvansZvCRWKv/+lJVMYbLYH5EJzEpRBHHDujsaHAWwd1 pFGDqFPhEDXanBewUv1RdyN5dX3YnOCCg+7hsGlQfwht7opDFM9doIqNM0RS4E3Lun1Q PVZWUA6LYDndGhKXuXDRr+uKpqEtri0ZJ9Z0uREi55H9X9E2UX2bOQgPuKuuNPKbqIMW ISuTxh4bO9w28YP8Xe1YF83rpFz68cgbhq9xW3hl8euV59RdDeoqaTROPB7L9382S9sn Ue5g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s3p1s0At; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/21] util/qemu-timer.c: Don't warp timer from timerlist_rearm() Date: Fri, 7 Mar 2025 15:07:04 +0000 Message-ID: <20250307150708.3222813-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently we call icount_start_warp_timer() from timerlist_rearm(). This produces incorrect behaviour, because timerlist_rearm() is called, for instance, when a timer callback modifies its timer. We cannot decide here to warp the timer forwards to the next timer deadline merely because all_cpu_threads_idle() is true, because the timer callback we were called from (or some other callback later in the list of callbacks being invoked) may be about to raise a CPU interrupt and move a CPU from idle to ready. The only valid place to choose to warp the timer forward is from the main loop, when we know we have no outstanding IO or timer callbacks that might be about to wake up a CPU. For Arm guests, this bug was mostly latent until the refactoring commit f6fc36deef6abc ("target/arm/helper: Implement CNTHCTL_EL2.CNT[VP]MASK"), which exposed it because it refactored a timer callback so that it happened to call timer_mod() first and raise the interrupt second, when it had previously raised the interrupt first and called timer_mod() afterwards. This call seems to have originally derived from the pre-record-and-replay icount code, which (as of e.g. commit db1a49726c3c in 2010) in this location did a call to qemu_notify_event(), necessary to get the icount code in the vCPU round-robin thread to stop and recalculate the icount deadline when a timer was reprogrammed from the IO thread. In current QEMU, everything is done on the vCPU thread when we are in icount mode, so there's no need to try to notify another thread here. I suspect that the other reason why this call was doing icount timer warping is that it pre-dates commit efab87cf79077a from 2015, which added a call to icount_start_warp_timer() to main_loop_wait(). Once the call in timerlist_rearm() has been removed, if the timer callbacks don't cause any CPU to be woken up then we will end up calling icount_start_warp_timer() from main_loop_wait() when the rr main loop code calls rr_wait_io_event(). Remove the incorrect call from timerlist_rearm(). Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2703 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Tested-by: Alex Bennée Message-id: 20250210135804.3526943-1-peter.maydell@linaro.org --- util/qemu-timer.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/util/qemu-timer.c b/util/qemu-timer.c index 3243d2c515c..788466fe22f 100644 --- a/util/qemu-timer.c +++ b/util/qemu-timer.c @@ -409,10 +409,6 @@ static bool timer_mod_ns_locked(QEMUTimerList *timer_list, static void timerlist_rearm(QEMUTimerList *timer_list) { - /* Interrupt execution to force deadline recalculation. */ - if (icount_enabled() && timer_list->clock->type == QEMU_CLOCK_VIRTUAL) { - icount_start_warp_timer(); - } timerlist_notify(timer_list); } From patchwork Fri Mar 7 15:07:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871190 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp809822wri; Fri, 7 Mar 2025 07:10:23 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXkG5O9zl686y+SMyJb4RVmAH49d3mrbGTgh0opyPbBlzY0lY/hl57Gg/fFhk6cwvrtqXd+qg==@linaro.org X-Google-Smtp-Source: AGHT+IHtmEt0+1MxXuBa/SFmVcr2jMJ52Iv361USjnMvV+qwMnSMedZ0JbGyq9sxvoAjaQE3xLH5 X-Received: by 2002:ac8:5a96:0:b0:474:fb5b:30b with SMTP id d75a77b69052e-476109be1c9mr47397131cf.27.1741360107749; Fri, 07 Mar 2025 07:08:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360107; cv=none; d=google.com; s=arc-20240605; b=IXk1SgfmWVQdGlccVsdCeMhobRO7QoiTe7xY4ovsFnxdj4ZqEm5fcdIk1EeXUTHQKV Pb9UM4VEs2r9xNQmjQhhj/Egvf/DzWDrYonp0kOFw2ebufbKEYGKLCi5NeInE24+4vQL x1GZBf9gUfcitcT8WFtQ4t8xgd+awMiwwpVlMNXPWCYguZ218nIva5OJbkJ3EF4XV8Ys rckLrBpdexAN6JxSrjE06bAkIsAtXOkKvtmxM1whs+k2dUaP8Mdd1JjNL+fB4kAk8ATN 5BlLNJCE8gB3P7pd74cqW7seNhNjAWsZTzILbrjY6l8dFRn5+eo2Quenn2BXndP2og7K mp5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nTp52Om52JlzEKvgvtGomRWuf+tAauGk1Wv9ixJOvzU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=bpTVnpnDpN7P5u1nQRxbrb1kRK4ODIaKi0xwmeS84ag4LJSo3Z+RWOnTLtPUe/QwnW lBwjF6yraXyJJIwUVLR0zLpjGVN507135cIoPXkSAyBb21tfTDMiqomvd4BNjjPQGFfK 6VcPtAGkW2iT1llOwh28g36zHtdIWSbst6OXHhGbv8H8FvYh2I27vp55r0TlLHir+cf9 /wcdS4qyj8Cf0hb4iv8zU83Zf+Rh3JKy0TBiLTGZRwqRW6z+6Ia1e1FsOqh1tS3WXyMR cg0FXEm9b/9mzhAShFHYZWZeTR/owjh+fGBccucCNe7rhelRjegdZC7Hgjac/TkjGXK5 dWnA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Gwd/K5B4"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/21] include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN Date: Fri, 7 Mar 2025 15:07:05 +0000 Message-ID: <20250307150708.3222813-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Expand the example in the comment documenting MO_ATOM_SUBALIGN, to be clearer about the atomicity guarantees it represents. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20250228103222.1838913-1-peter.maydell@linaro.org --- include/exec/memop.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index acdb40a9b3b..407a47d82c7 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -91,8 +91,12 @@ typedef enum MemOp { * Depending on alignment, one or both will be single-copy atomic. * This is the atomicity e.g. of Arm FEAT_LSE2 LDP. * MO_ATOM_SUBALIGN: the operation is single-copy atomic by parts - * by the alignment. E.g. if the address is 0 mod 4, then each - * 4-byte subobject is single-copy atomic. + * by the alignment. E.g. if an 8-byte value is accessed at an + * address which is 0 mod 8, then the whole 8-byte access is + * single-copy atomic; otherwise, if it is accessed at 0 mod 4 + * then each 4-byte subobject is single-copy atomic; otherwise + * if it is accessed at 0 mod 2 then the four 2-byte subobjects + * are single-copy atomic. * This is the atomicity e.g. of IBM Power. * MO_ATOM_NONE: the operation has no atomicity requirements. * From patchwork Fri Mar 7 15:07:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871201 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp811254wri; Fri, 7 Mar 2025 07:13:03 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUBZctZ2ifsOQ0/7UfWEqCacJbsX51PHxOHHPcrzpswNL9eVoCEP1YjFaVqiE12GiaXRpiFig==@linaro.org X-Google-Smtp-Source: AGHT+IGJGoJm6A8rbKS6rhjPVXaCKJrMF2rJaD9GE/AYimBNajRFqGMiYa/JJdoDxKdtQYwbDjWI X-Received: by 2002:a05:6122:1d9f:b0:516:230b:eec with SMTP id 71dfb90a1353d-523e4076cf3mr3062430e0c.5.1741360383039; Fri, 07 Mar 2025 07:13:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360383; cv=none; d=google.com; s=arc-20240605; b=iMKnV2n+s4RG2q11UPjOiIyP6F3RHpGR+Z35vl16sSsbm6x2UXxkcuZ2FBdtz3R/TP yqmP8vasPEsQz+mEbY0bbrHNOkpNNNMo3A0QmMqluUhZd8ZQgufTKaX1u1ySkC61aK1v Bbq9ncyP4p9bF+BEtVtoCPbpFTLb0v7YbuvnyqJrPWUqz0n656kiNRFAID032LbKpQc7 OHEmg5AoXUYNgQWm3PbQ7uRaFcweMAu9cd//nESif8uK6H5xb5znXcSEHnJhoz3KJD/X 0JlMMvoMFfOZ1ZEZfx0Mm12a6F5KbO8cTd+i+sEb33txOwnVa/sUdyeqgxkGdj0TSRc5 pIkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xyxLh5BLcDl2AJdz4+J0eOXFTj1L4hj69KVc/wA423Q=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=DrRRlSJiuQ5r4TUl/vl/xglWh1/LzkmlCrkn3hFDR0ef103xzgg/ybsTVscsj7TUHY ihdD+JaGWqDMMRwoAdS8yIObX7ACOdM+GEGqFIIW8JWYtqRER4hVmvB7cjlUAPRjUPSk +1CqzyD5ZsS3Fiu+oRbqZp218Yl/zqXW7ujHBEkkGccZ53U1zJfPgYUUk6d6lvxOpgzy Uo+ubR24zqrMgLJfxt7SaS1oANNhNQCrfCJs2dENitS45Iw3vBYthBaQ+dfCwIBnNmoB GnFbruTg+mgpp167SgTwcUnLY/3Ms25/fcM2wc1yLlYXxx3h2EvbX14zQfhz5OQJtTKo h/Og==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w4wWq9ee; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/21] hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper Date: Fri, 7 Mar 2025 15:07:06 +0000 Message-ID: <20250307150708.3222813-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: JianChunfu Use a similar terminology smmu_hash_remove_by_sid_range() as the one being used for other hash table matching functions since smmuv3_invalidate_ste() name is not self explanatory, and introduce a helper that invokes the g_hash_table_foreach_remove. No functional change intended. Signed-off-by: JianChunfu Reviewed-by: Eric Auger Message-id: 20250228031438.3916-1-jansef.jian@hj-micro.com Signed-off-by: Peter Maydell --- hw/arm/smmu-internal.h | 5 ----- include/hw/arm/smmu-common.h | 6 ++++++ hw/arm/smmu-common.c | 21 +++++++++++++++++++++ hw/arm/smmuv3.c | 19 ++----------------- hw/arm/trace-events | 3 ++- 5 files changed, 31 insertions(+), 23 deletions(-) diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index 843bebb185d..d143d296f34 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -141,9 +141,4 @@ typedef struct SMMUIOTLBPageInvInfo { uint64_t mask; } SMMUIOTLBPageInvInfo; -typedef struct SMMUSIDRange { - uint32_t start; - uint32_t end; -} SMMUSIDRange; - #endif diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index e5ad55bbae7..e5e2d09294d 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -142,6 +142,11 @@ typedef struct SMMUIOTLBKey { uint8_t level; } SMMUIOTLBKey; +typedef struct SMMUSIDRange { + uint32_t start; + uint32_t end; +} SMMUSIDRange; + struct SMMUState { /* */ SysBusDevice dev; @@ -219,6 +224,7 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl); void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg, uint64_t num_pages, uint8_t ttl); +void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range); /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 8c1b407b824..6e720e1b9a0 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -225,6 +225,27 @@ static gboolean smmu_hash_remove_by_vmid_ipa(gpointer key, gpointer value, ((entry->iova & ~info->mask) == info->iova); } +static gboolean +smmu_hash_remove_by_sid_range(gpointer key, gpointer value, gpointer user_data) +{ + SMMUDevice *sdev = (SMMUDevice *)key; + uint32_t sid = smmu_get_sid(sdev); + SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data; + + if (sid < sid_range->start || sid > sid_range->end) { + return false; + } + trace_smmu_config_cache_inv(sid); + return true; +} + +void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range) +{ + trace_smmu_configs_inv_sid_range(sid_range.start, sid_range.end); + g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sid_range, + &sid_range); +} + void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index b40acbe0245..1a96287ba9d 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -903,7 +903,7 @@ static void smmuv3_flush_config(SMMUDevice *sdev) SMMUv3State *s = sdev->smmu; SMMUState *bc = &s->smmu_state; - trace_smmuv3_config_cache_inv(smmu_get_sid(sdev)); + trace_smmu_config_cache_inv(smmu_get_sid(sdev)); g_hash_table_remove(bc->configs, sdev); } @@ -1277,20 +1277,6 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage) } } -static gboolean -smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data) -{ - SMMUDevice *sdev = (SMMUDevice *)key; - uint32_t sid = smmu_get_sid(sdev); - SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data; - - if (sid < sid_range->start || sid > sid_range->end) { - return false; - } - trace_smmuv3_config_cache_inv(sid); - return true; -} - static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUState *bs = ARM_SMMU(s); @@ -1373,8 +1359,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) sid_range.end = sid_range.start + mask; trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end); - g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste, - &sid_range); + smmu_configs_inv_sid_range(bs, sid_range); break; } case SMMU_CMD_CFGI_CD: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f49cae1656e..f3386bd7ae1 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -22,6 +22,8 @@ smmu_iotlb_inv_asid_vmid(int asid, int vmid) "IOTLB invalidate asid=%d vmid=%d" smmu_iotlb_inv_vmid(int vmid) "IOTLB invalidate vmid=%d" smmu_iotlb_inv_vmid_s1(int vmid) "IOTLB invalidate vmid=%d" smmu_iotlb_inv_iova(int asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64 +smmu_configs_inv_sid_range(uint32_t start, uint32_t end) "Config cache INV SID range from 0x%x to 0x%x" +smmu_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x" smmu_inv_notifiers_mr(const char *name) "iommu mr=%s" smmu_iotlb_lookup_hit(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" smmu_iotlb_lookup_miss(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" @@ -59,7 +61,6 @@ smmuv3_cmdq_tlbi_nh(int vmid) "vmid=%d" smmuv3_cmdq_tlbi_nsnh(void) "" smmuv3_cmdq_tlbi_nh_asid(int asid) "asid=%d" smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=%d" -smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" stage=%d" From patchwork Fri Mar 7 15:07:07 2025 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/21] target/rx: Set exception vector base to 0xffffff80 Date: Fri, 7 Mar 2025 15:07:07 +0000 Message-ID: <20250307150708.3222813-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Keith Packard The documentation says the vector is at 0xffffff80, instead of the previous value of 0xffffffc0. That value must have been a bug because the standard vector values (20, 21, 23, 25, 30) were all past the end of the array. Signed-off-by: Keith Packard Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/rx/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/rx/helper.c b/target/rx/helper.c index 7f28e729891..e8aabf40ffb 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -88,7 +88,7 @@ void rx_cpu_do_interrupt(CPUState *cs) cpu_stl_data(env, env->isp, env->pc); if (vec < 0x100) { - env->pc = cpu_ldl_data(env, 0xffffffc0 + vec * 4); + env->pc = cpu_ldl_data(env, 0xffffff80 + vec * 4); } else { env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4); } From patchwork Fri Mar 7 15:07:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 871196 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp811067wri; Fri, 7 Mar 2025 07:12:39 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXeEVe8M7E3Z5g5zKX5R7/DQmyjAmL9Rw6o3s4YF42gOFoplbpYbLcjhL02i9P6rAT7ktZxPg==@linaro.org X-Google-Smtp-Source: AGHT+IHrG5AKYs+68a3SfpgkdHckhWeCUUXv0EtFsVe4DXBJUft39RMkg4R2RSEb0N57lrG8EOIM X-Received: by 2002:a05:6122:2005:b0:520:6773:e5ea with SMTP id 71dfb90a1353d-523e411fa7dmr2982914e0c.7.1741360358756; Fri, 07 Mar 2025 07:12:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741360358; cv=none; d=google.com; s=arc-20240605; b=QvM4X+YsdlkR2WBnczXYbHF3QqJcAiQ6rQ12e/3bprbFs4nAuNtUXgmXl380SyPnhk toIEedNevhDTCG6Bx87SJEcTAZal8W6EIWT1q6+obj2G+C5c2Fkf+wksJtANybpvD5+f XH5MINZg8EqAF6cqE0WnT7lgamWvoq9pNVa2PumWd4hRKT5TpQKIb+6PKJhsYt+41Vhp nLCTD5PvD7pPh4UjlPzGpNs2N1vJtA+QLpzk16mBXGgACwU4JriDRwNpEkLtTZVlDXba CVPXJx3r54TmnfJ4ruI1TpBeWoX1E9M024GrItEXCTMFUFIbnCkCMC6Qd28Fa2kNLUJw wnQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Od4b3d3rOr7fMBRm5KIcutZc76QQ9AX8573/i1gjMqU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=ikmZdGxj2V4rQxKwFzJQdeCrczkaAayHm1/TSmqg18e6RfY/Z3HPQXx+y15QLZ65Xk Y9/5PmLbZMVmF9HP22ZDYRT5WzzFCHNwNVBrGk3Z1N+w2+4CFpvQ5SNsVv3xaH2CzXye uHLlPn81PyWCHicrVl1xhrxya9rWLrTHrDGkH22eLTZts66uPU+bS16ADc7nEwWnkRGg 2yDegYSYfXucS40LPvn4ZFscvl2Jq9m6MlcgFTipps+h3y+s3XQj6ElqJLH/4hdI4oS6 kBsAw5cJ1X9flnzipsrK1bajcP79gUH7tFs49CA2+RrWVdqfzlDuDfHKCVa9Tz4d4j5L +0dg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gYun6AsM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1031fdsm5443627f8f.89.2025.03.07.07.07.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 07:07:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/21] target/rx: Remove TCG_CALL_NO_WG from helpers which write env Date: Fri, 7 Mar 2025 15:07:08 +0000 Message-ID: <20250307150708.3222813-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307150708.3222813-1-peter.maydell@linaro.org> References: <20250307150708.3222813-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Keith Packard Functions which modify TCG globals must not be marked TCG_CALL_NO_WG, as that tells the optimizer that TCG global values already loaded in machine registers are still valid, and so any changes which these helpers make to the CPU state may be ignored. The target/rx code chooses to put (among other things) all the PSW bits and also ACC into globals, so the NO_WG flag on various functions that touch the PSW or ACC is incorrect and must be removed. This includes all the floating point helper functions, because update_fpsw() will update PSW Z and S. Signed-off-by: Keith Packard [PMM: Clarified commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/rx/helper.h | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target/rx/helper.h b/target/rx/helper.h index ebb47394744..8cc38b0cb71 100644 --- a/target/rx/helper.h +++ b/target/rx/helper.h @@ -4,27 +4,27 @@ DEF_HELPER_1(raise_privilege_violation, noreturn, env) DEF_HELPER_1(wait, noreturn, env) DEF_HELPER_2(rxint, noreturn, env, i32) DEF_HELPER_1(rxbrk, noreturn, env) -DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fsub, TCG_CALL_NO_WG, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_2(ftoi, TCG_CALL_NO_WG, i32, env, f32) -DEF_HELPER_FLAGS_2(round, TCG_CALL_NO_WG, i32, env, f32) -DEF_HELPER_FLAGS_2(itof, TCG_CALL_NO_WG, f32, env, i32) +DEF_HELPER_3(fadd, f32, env, f32, f32) +DEF_HELPER_3(fsub, f32, env, f32, f32) +DEF_HELPER_3(fmul, f32, env, f32, f32) +DEF_HELPER_3(fdiv, f32, env, f32, f32) +DEF_HELPER_3(fcmp, void, env, f32, f32) +DEF_HELPER_2(ftoi, i32, env, f32) +DEF_HELPER_2(round, i32, env, f32) +DEF_HELPER_2(itof, f32, env, i32) DEF_HELPER_2(set_fpsw, void, env, i32) -DEF_HELPER_FLAGS_2(racw, TCG_CALL_NO_WG, void, env, i32) -DEF_HELPER_FLAGS_2(set_psw_rte, TCG_CALL_NO_WG, void, env, i32) -DEF_HELPER_FLAGS_2(set_psw, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_2(racw, void, env, i32) +DEF_HELPER_2(set_psw_rte, void, env, i32) +DEF_HELPER_2(set_psw, void, env, i32) DEF_HELPER_1(pack_psw, i32, env) -DEF_HELPER_FLAGS_3(div, TCG_CALL_NO_WG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) -DEF_HELPER_FLAGS_1(scmpu, TCG_CALL_NO_WG, void, env) +DEF_HELPER_3(div, i32, env, i32, i32) +DEF_HELPER_3(divu, i32, env, i32, i32) +DEF_HELPER_1(scmpu, void, env) DEF_HELPER_1(smovu, void, env) DEF_HELPER_1(smovf, void, env) DEF_HELPER_1(smovb, void, env) DEF_HELPER_2(sstr, void, env, i32) -DEF_HELPER_FLAGS_2(swhile, TCG_CALL_NO_WG, void, env, i32) -DEF_HELPER_FLAGS_2(suntil, TCG_CALL_NO_WG, void, env, i32) -DEF_HELPER_FLAGS_2(rmpa, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_2(swhile, void, env, i32) +DEF_HELPER_2(suntil, void, env, i32) +DEF_HELPER_2(rmpa, void, env, i32) DEF_HELPER_1(satr, void, env)